Three-dimensional semiconductor chip including a memory die bonded to both sides of a support die and method of manufacturing the same

Abstract

The present invention discloses a support die, which includes a complementary metal oxide semiconductor (CMOS) device, a front support die bonding pad electrically connected to a first subset of peripheral circuits, and a backside bonding structure electrically connected to a second subset of peripheral circuits. A first memory die including a three-dimensional array of first memory elements is bonded to the support die. A first memory die bonding pad of the first memory die is bonded to the front support die bonding pad. A second memory die including a three-dimensional array of second memory elements is bonded to the support die. A second memory die bonding pad of the second memory die is bonded to the backside bonding structure.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent application serial number 16 / 255,413, filed on January 23, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular, to a three-dimensional memory chip including a memory die bonded to both sides of a support die and a method of manufacturing the same. Background Art

[0004] A three-dimensional vertical NAND string with one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Support circuits are used to perform write, read, and erase operations of the memory cells in the vertical NAND string. Typically, a complementary metal oxide semiconductor (CMOS) device is formed on the same substrate as the three-dimensional memory device. Summary of the invention

[0005] According to one embodiment of the present disclosure, a bonding assembly is provided, which includes: a support die, the support die including peripheral circuits, a front support die bonding pad electrically connected to a first subset of the peripheral circuits, and a back-side bonding structure electrically connected to a second subset of the peripheral circuits; a first memory die, the first memory die including a first three-dimensional array of memory elements and a first memory die bonding pad bonded to the front support die bonding pad; and a second memory die, the second memory die including a second three-dimensional array of memory elements and a second memory die bonding pad bonded to the back-side bonding structure.

[0006] According to another embodiment of the present disclosure, a method for forming a bonding assembly is provided, the method comprising: providing a support die comprising a complementary metal oxide semiconductor (CMOS) device and a front support die bonding pad electrically connected to a first subset of peripheral circuits; bonding a first memory die comprising a three-dimensional array of first memory elements to the support die, wherein a first memory die bonding pad of the first memory die is bonded to the front support die bonding pad; forming a backside bonding structure electrically connected to a second subset of peripheral circuits through a semiconductor substrate of the support die; and bonding a second memory die comprising a second three-dimensional array of memory elements to the support die, wherein a second memory die bonding pad of the second memory die is bonded to the backside bonding structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic vertical cross-sectional view of an exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers according to an embodiment of the present disclosure.

[0008] Figure 2A is a schematic vertical cross-sectional view of an exemplary structure after forming a stepped terrace and a backward stepped dielectric material portion according to an embodiment of the present disclosure.

[0009] Figure 2B yes Figure 2A A top view of an exemplary structure of FIG. The vertical plane A-A' is Figure 2A The plane of the section.

[0010] Figure 3A is a schematic vertical cross-sectional view of an exemplary structure after forming a storage opening and a support opening according to an embodiment of the present disclosure.

[0011] Figure 3B yes Figure 3A A top view of an exemplary structure of FIG. The vertical plane A-A' is Figure 3A The plane of the section.

[0012] 4A to 4H are sequential schematic vertical cross-sectional views of a memory opening within an exemplary structure during formation of a memory stack structure, an optional dielectric core, and a drain region therein according to an embodiment of the present disclosure.

[0013] Figure 5 is a schematic vertical cross-sectional view of an exemplary structure after forming a memory stack structure and a support pillar structure according to an embodiment of the present disclosure.

[0014] Fig. 6A is a schematic vertical cross-sectional view of an exemplary structure after forming backside trenches according to an embodiment of the present disclosure.

[0015] Figure 6B yes Fig. 6A A partial perspective top view of an exemplary structure of FIG. The vertical plane A-A' is Fig. 6A A schematic vertical cross-sectional view of a plane.

[0016] Figure 7 is a schematic vertical cross-sectional view of an exemplary structure after forming a backside recess according to an embodiment of the present disclosure.

[0017] FIG. 8A to FIG. 8D are sequential vertical cross-sectional views of regions of an exemplary structure during formation of a conductive layer according to an embodiment of the present disclosure.

[0018] Fig. 9 yes Fig.8D Schematic vertical cross-sectional view of an exemplary structure at a processing step of .

[0019] Fig. 10A is a schematic vertical cross-sectional view of an exemplary structure after removal of deposited conductive material from within the backside trenches according to an embodiment of the present disclosure.

[0020] Fig. 10B yes Fig. 10A A top view of an exemplary structure of FIG.

[0021] Fig.11A is a schematic vertical cross-sectional view of an exemplary structure after forming insulating spacers and source contact structures within each backside trench according to an embodiment of the present disclosure.

[0022] Fig. 11B yes Fig.11A Magnified view of a region of an exemplary structure.

[0023] Fig. 12A is a schematic vertical cross-sectional view of an exemplary structure after forming a contact-level dielectric material layer and a contact via structure according to an embodiment of the present disclosure.

[0024] Fig. 12B yes Fig. 12A A top view of an exemplary structure of FIG. The vertical plane A-A' is Fig. 12A A schematic vertical cross-sectional view of a plane.

[0025] Fig.13A is a schematic vertical cross-sectional view of an exemplary structure after forming a first-level dielectric material layer and a first-level metal interconnect structure according to an embodiment of the present disclosure.

[0026] Fig. 13B yes Fig.13A A top view of an exemplary structure of FIG. The vertical plane A-A' is Fig.13AA schematic vertical cross-sectional view of a plane.

[0027] Fig.14A is a schematic vertical cross-sectional view of an exemplary structure after forming a pad connection via structure and a memory die bonding pad according to an embodiment of the present disclosure.

[0028] Fig. 14B yes Fig.14A A top view of a region of an exemplary structure.

[0029] Fig. 14C yes Fig.14A and Fig. 14B A top view of a larger area of ​​an exemplary structure.

[0030] Fig.15A is a vertical cross-sectional view of a support die after forming a front support die bond pad according to an embodiment of the present disclosure.

[0031] Fig. 15B is a plan view of a first configuration of peripheral circuits in a support die according to an embodiment of the present disclosure.

[0032] Fig. 15C is a plan view of a second configuration of peripheral circuits in a support die according to an embodiment of the present disclosure.

[0033] Fig.16 is a vertical cross-sectional view of a bonded assembly of a support die and a first memory die according to an embodiment of the present disclosure.

[0034] Fig.17 is a vertical cross-sectional view of a bonded assembly after thinning the support die according to an embodiment of the present disclosure.

[0035] Fig.18 is a vertical cross-sectional view of a bonded assembly after forming tubular insulating spacers and through-substrate via structures according to an embodiment of the present disclosure.

[0036] Fig.19 is a vertical cross-sectional view of a bonded assembly after forming a backside support die bond pad according to an embodiment of the present disclosure.

[0037] Fig. 20A is a schematic vertical cross-sectional view of a second memory die according to an embodiment of the present disclosure.

[0038] Fig. 20B yes Fig. 20A FIG. 1 is a top view of a second memory die.

[0039] Fig.21A is a vertical cross-sectional view of a joined assembly of a support die, a first memory die, and a second memory die according to an embodiment of the present disclosure.

[0040] Fig.21B is a vertical cross-sectional view of another configuration of a joined assembly of a support die, a first memory die, and a second memory die according to an embodiment of the present disclosure.

[0041] Fig. 22 After forming the external bonding pads, solder structures and bonding wires according to an embodiment of the present disclosure Fig.21A or Fig.21B A vertical cross-sectional view of a first configuration of a joining assembly.

[0042] Fig.23 After forming the external bonding pads, solder structures and bonding wires according to an embodiment of the present disclosure Fig.21A or Fig.21B A vertical cross-sectional view of a second configuration of the engagement assembly.

[0043] Fig.24 After forming the external bonding pads, solder structures and bonding wires according to an embodiment of the present disclosure Fig.21A or Fig.21B A vertical cross-sectional view of a third configuration of the engagement assembly. DETAILED DESCRIPTION

[0044] A three-dimensional memory chip may include a memory die including a vertical NAND string. The support circuit is used to perform write, read and erase operations of the memory cells in the vertical NAND string. Typically, a complementary metal oxide semiconductor (CMOS) device is formed on the same substrate as the three-dimensional memory device. However, the degradation of the peripheral circuit caused by the incidental thermal cycle and hydrogen diffusion during the manufacture of the three-dimensional memory device constrains the performance of the support circuit including the peripheral circuit. In addition, due to the constraints of the etching process for patterning the alternating stack, the number of word lines in the alternating stack of the insulating layer and the word line is limited. Therefore, in a three-dimensional memory device in which the support circuit is formed on the same substrate and the memory device, the total number of word lines that can be stacked vertically is limited. The embodiments of the present disclosure relate to a three-dimensional memory chip having a memory die bonded to both sides of the support die and a method for manufacturing the same, and various aspects thereof are described below. The embodiments of the present disclosure can be used to form various structures, including a multi-level memory structure, and non-limiting examples thereof include semiconductor devices, such as a three-dimensional monomer memory array device including a plurality of NAND memory strings.

[0045] The accompanying drawings are not drawn to scale. Multiple instances of elements can be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of elements. Serial numbers such as "first", "second" and "third" are only used to identify similar elements, and different serial numbers can be used throughout the specification and claims of the present disclosure. The same figure numerals represent the same element or similar elements. Unless otherwise specified, elements with the same figure numerals are assumed to have the same composition. Unless otherwise specified, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. As used herein, a first element positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, a "prototype" structure or "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0046] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. Additionally, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0047] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolith" refers to the layers of each level of the array being deposited directly on the layers of each underlying level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167, entitled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory levels before bonding, but since the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. The three-dimensional memory devices of various embodiments of the present disclosure include monolithic three-dimensional NAND string memory devices and may be manufactured using the various embodiments described herein.

[0048] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or "chip") or multiple semiconductor chips that are bonded together, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. When the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. Each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming.

[0049] refer to Figure 1 , shows an exemplary structure according to an embodiment of the present disclosure, which can be used, for example, to manufacture a device structure including a vertical NAND memory device. The exemplary structure includes a substrate (9, 10) which can be a semiconductor substrate. The substrate can include a substrate semiconductor layer 9 and an optional semiconductor material layer 10. The substrate semiconductor layer 9 can be a semiconductor wafer or semiconductor material layer, and can include at least one elemental semiconductor material (e.g., a single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0050] As used herein, "semiconductor material" refers to a semiconductor material having a -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m, and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 5 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state) (i.e., having a conductivity greater than 1.0×10 5 S / m) of a semiconductor material. A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 5 S / m in the range of 1000 Å / s. A semiconductor material having an electrical dopant (i.e., a p-type dopant and / or an n-type dopant) with a conductivity in the range of 1000 Å / s. An "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0051] A stack of alternating multiple first material layers (which may be insulating layers 32) and second material layers (which may be sacrificial material layers 42) may be formed above the top surface of the substrate (9, 10). As used herein, "material layer" refers to a layer including a material throughout its entirety. As used herein, alternating multiple first elements and second elements refer to a structure in which instances of the first element and instances of the second element are alternating. Each instance of a first element that is not an end element of the alternating multiple elements is adjacent to two instances of the second element on both sides, and each instance of a second element that is not an end element of the alternating multiple elements is adjacent to two instances of the first element on both ends. The first element may always have the same thickness, or may have different thicknesses. The second element may always have the same thickness, or may have different thicknesses. The alternating multiple first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, instances of the first element and instances of the second element may form a unit that is repeated periodically within the alternating multiple elements.

[0052] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32, and each second material layer may be a sacrificial material layer. In this case, the stack may include alternating multiple insulating layers 32 and sacrificial material layers 42, and constitute a prototype stack including alternating layers of insulating layers 32 and sacrificial material layers 42.

[0053] The alternating plurality of stacks are referred to herein as alternating stacks (32, 42). In one embodiment, the alternating stacks (32, 42) may include an insulating layer 32 composed of a first material and a sacrificial material layer 42 composed of a second material, the second material being different from the material of the insulating layer 32. The first material of the insulating layer 32 may be at least one insulating material. Therefore, each insulating layer 32 may be an insulating material layer. Insulating materials that may be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) commonly referred to as high dielectric constant (high-k) dielectric oxides and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

[0054] The second material of sacrificial material layer 42 is a sacrificial material that is selectively removable with respect to the first material of insulating layer 32. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0055] The sacrificial material layer 42 may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer including silicon nitride or a semiconductor material including at least one of silicon and germanium.

[0056] In one embodiment, insulating layer 32 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0057] The sacrificial material layer 42 may be appropriately patterned so that a conductive material portion subsequently formed by replacing the sacrificial material layer 42 may be used as a conductive electrode, such as a control gate electrode of a subsequently formed single three-dimensional NAND string memory device. The sacrificial material layer 42 may include a portion having a stripe shape extending substantially parallel to the top surface of the substrate (9, 10).

[0058] The thickness of the insulating layer 32 and the sacrificial material layer 42 can be in the range of 20nm to 50nm, but smaller and larger thicknesses can be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the pair of insulating layers 32 and sacrificial material layers (e.g., control gate electrodes or sacrificial material layers) 42 can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. The top gate electrode and the bottom gate electrode in the stack can be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a uniform thickness that is substantially constant within each corresponding sacrificial material layer 42.

[0059] Although the description of the present disclosure uses an embodiment in which the spacer material layer is a sacrificial material layer 42 that is subsequently replaced by a conductive layer, in other embodiments, the sacrificial material layer is formed as a conductive layer. In this case, the step of replacing the spacer material layer with a conductive layer can be omitted.

[0060] Optionally, an insulating capping layer 70 may be formed over the alternating stack (32, 42). The insulating capping layer 70 includes a dielectric material different from the material of the sacrificial material layer 42. In one embodiment, the insulating capping layer 70 may include a dielectric material that may be used for the insulating layer 32 as described above. The insulating capping layer 70 may have a greater thickness than each insulating layer 32. The insulating capping layer 70 may be deposited by, for example, chemical vapor deposition. In one embodiment, the insulating capping layer 70 may be a silicon oxide layer.

[0061] refer to Figure 2A and Figure 2B, forming a stepped surface at a peripheral region of the alternating stack (32, 42), which is referred to herein as a platform region. As used herein, "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface, and adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, and a portion of the alternating stack (32, 42) is removed from the volume by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0062] The platform area is formed in the stair area 300, which is located adjacent to the memory array area 100. The stepped cavity may have various stepped surfaces so that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the cavity depth by one or more levels, and the second type of etching process laterally expanding the area to be vertically etched in a subsequent etching process of the first type. As used herein, a "level" of a structure including an alternating plurality is defined as the relative position of a pair of first material layers and a second material layer within the structure.

[0063] Each sacrificial material layer 42 except the topmost sacrificial material layer 42 in the alternating stack (32, 42) extends laterally further than any overlying sacrificial material layer 42 in the alternating stack (32, 42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32, 42) that extend continuously from the bottommost layer in the alternating stack (32, 42) to the topmost layer in the alternating stack (32, 42).

[0064] Each vertical step of the stepped surface may have a height of one or more pairs of insulating layers 32 and sacrificial material layers. In one embodiment, each vertical step may have a height of a single pair of insulating layers 32 and sacrificial material layers 42. In another embodiment, multiple "columns" of stairs may be formed along the first horizontal direction hd1, so that each vertical step has a height of multiple pairs of insulating layers 32 and sacrificial material layers 42, and the number of columns may be at least the number of the multiple pairs. Each column of stairs may be vertically offset from each other, so that each of the sacrificial material layers 42 has a physically exposed top surface in the corresponding column of stairs. In an exemplary example, two columns of stairs are formed for each block of the memory stack structure to be subsequently formed, so that one column of stairs provides a physically exposed top surface for odd-numbered sacrificial material layers 42 (as counted from the bottom) and the other column of stairs provides a physically exposed top surface for even-numbered sacrificial material layers (as counted from the bottom). Configurations using three, four, or more columns of stairs may also be used, in which a corresponding set of vertical offsets are formed along the physically exposed surface of the sacrificial material layer 42. Each sacrificial material layer 42 has a greater lateral extent than any overlying sacrificial material layer 42 along at least one direction, such that each physically exposed surface of any sacrificial material layer 42 has no overhang. In one embodiment, the vertical steps within each column of stairs may be arranged along a first horizontal direction hd1, and the columns of stairs may be arranged along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1 may be perpendicular to a boundary between the memory array region 100 and the staircase region 300.

[0065] A backward stepped dielectric material portion 65 (i.e., an insulating filling material portion) may be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material (such as silicon oxide) may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from above the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the backward stepped dielectric material portion 65. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the backward stepped dielectric material portion 65, the silicon oxide of the backward stepped dielectric material portion 65 may be doped with a dopant or may not be doped with a dopant, such as B, P, and / or F.

[0066] Optionally, a drain select level isolation structure 72 may be formed through the insulating cap layer 70 and a subset of the sacrificial material layer 42 positioned at the drain select level. The drain select level isolation structure 72 may be formed, for example, by forming a drain select level isolation trench and filling the drain select level isolation trench with a dielectric material such as silicon oxide. Excess portions of the dielectric material may be removed from above the top surface of the insulating cap layer 70.

[0067] refer to Figure 3A and Figure 3B A photolithographic material stack (not shown) including at least a photoresist layer may be formed over the insulating cap layer 70 and the backward stepped dielectric material portion 65 and may be photolithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the staircase region 300. The pattern in the photolithographic material stack may be transferred through the insulating cap layer 70 or the backward stepped dielectric material portion 65 and through the alternating stack (32, 42) by at least one anisotropic etch using the patterned photolithographic material stack as an etch mask. Portions of the alternating stack (32, 42) below the openings in the patterned photolithographic material stack are etched to form memory openings 49 and support openings 19. As used herein, a "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed therein. As used herein, a "support opening" refers to a structure in which a support structure (such as a support column structure) that mechanically supports other elements is subsequently formed. Memory opening 49 is formed through insulating capping layer 70 and the entirety of alternating stacks (32, 42) in memory array region 100. Support opening 19 is formed through rearward stepped dielectric material portion 65 and portions of alternating stacks (32, 42) below the stepped surface in staircase region 300.

[0068] The memory opening 49 extends through the entirety of the alternating stack (32, 42). The support opening 19 extends through a subset of the layers within the alternating stack (32, 42). The chemistry of the anisotropic etching process used to etch the material through the alternating stack (32, 42) can be alternating to optimize the etching of the first material and the second material in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of the memory opening 49 and the support opening 19 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0069] The memory openings 49 and the support openings 19 may extend from the top surface of the alternating stack (32, 42) to at least a horizontal plane including the topmost surface of the semiconductor material layer 10. In one embodiment, after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each memory opening 49 and each support opening 19, an overetching of the semiconductor material layer 10 may be optionally performed. The overetching may be performed before or after removing the photolithographic material stack. In other words, the recessed surface of the semiconductor material layer 10 may be vertically offset from the unrecessed top surface of the semiconductor material layer 10 by a recessed depth. The recessed depth may be in the range of, for example, 1 nm to 50 nm, but smaller and larger recessed depths may also be used. Overetching (as shown) is optional and may be omitted. If overetching is not performed, the bottom surfaces of the memory openings 49 and the support openings 19 may be coplanar with the topmost surface of the semiconductor material layer 10 (not shown).

[0070] Each of the memory opening 49 and the support opening 19 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings 49 may be formed in the memory array area 100. A two-dimensional array of support openings 19 may be formed in the staircase area 300. The substrate semiconductor layer 9 and the semiconductor material layer 10 together constitute a substrate (9, 10), which may be a semiconductor substrate. Alternatively, the semiconductor material layer 10 may be omitted, and the memory opening 49 and the support opening 19 may extend to the top surface of the substrate semiconductor layer 9.

[0071] 4A to 4H shows the structural changes in the storage opening 49, which is Figure 3A and Figure 3B The same structural changes occur simultaneously in each of the other storage openings 49 and each support opening 19.

[0072] refer to Figure 4A , showing Figure 3A and Figure 3B Memory opening 49 in an exemplary device structure of . Memory opening 49 extends through insulating cap layer 70, alternating stack (32, 42), and optionally into an upper portion of semiconductor material layer 10. In this processing step, each support opening 19 may extend through the backward stepped dielectric material portion 65, a subset of the layers in the alternating stack (32, 42), and optionally through an upper portion of semiconductor material layer 10. The bottom surface of each memory opening may be recessed to a depth in the range of 0 nm to 30 nm relative to the top surface of semiconductor material layer 10, although greater recess depths may also be used. Optionally, sacrificial material layer 42 may be partially laterally recessed, for example by isotropic etching, to form a lateral recess (not shown).

[0073] refer to Figure 4B , an optional pedestal channel portion (e.g., epitaxial pedestal) 11 may be formed at the bottom portion of each memory opening 49 and each support opening 19, for example, by selective epitaxy. Each pedestal channel portion 11 includes a single crystalline semiconductor material epitaxially aligned with the single crystalline semiconductor material of the semiconductor material layer 10. In one embodiment, the pedestal channel portion 11 may be doped with an electrical dopant of the same conductivity type as the semiconductor material layer 10. In one embodiment, the top surface of each pedestal channel portion 11 may be formed above a horizontal plane including the top surface of the sacrificial material layer 42. In this case, at least one source select gate electrode may be subsequently formed by replacing each sacrificial material layer 42 positioned below the horizontal plane including the top surface of the pedestal channel portion 11 with a corresponding conductive material layer. The pedestal channel portion 11 may be a portion of a transistor channel extending between a source region to be subsequently formed in the substrate (9, 10) and a drain region to be subsequently formed in an upper portion of the memory opening 49. A memory cavity 49' is present in the unfilled portion of the memory opening 49 above the pedestal channel portion 11. In one embodiment, the base channel portion 11 may include single crystal silicon. In one embodiment, the base channel portion 11 may have a doping of a first conductivity type, which is the same conductivity type as the semiconductor material layer 10 that the base channel portion contacts. If there is no semiconductor material layer 10, the base channel portion 11 may be formed directly on the substrate semiconductor layer 9, which may have a doping of the first conductivity type.

[0074] refer to Figure 4C A layer stack including a blocking dielectric layer 52 , a charge storage layer 54 , a tunneling dielectric 56 and an optional first semiconductor channel layer 601 may be sequentially deposited in the memory opening 49 .

[0075] The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may be essentially composed of at least one metal element and oxygen, or may be essentially composed of at least one metal element, oxygen and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride).

[0076] Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer may be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source atomized chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer may be in the range of 1 nm to 20 nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 may include a plurality of dielectric metal oxide layers having different material compositions.

[0077] Alternatively or in addition, the blocking dielectric layer 52 may include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer 52 may include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 may be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound may be in the range of 1 nm to 20 nm, but smaller and larger thicknesses may also be used. Alternatively, the blocking dielectric layer 52 may be omitted, and the backside blocking dielectric layer may be formed after forming a backside recess on the surface of the memory film to be formed subsequently.

[0078] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material, such as doped polysilicon or a metallic material, which is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer 42 within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer.

[0079] In another embodiment, the sacrificial material layer 42 may be laterally recessed relative to the sidewalls of the insulating layer 32, and a combination of a deposition process and anisotropic etching process may be used to form the charge storage layer 54 into a plurality of vertically spaced memory material portions. Although the description in the present disclosure uses an embodiment in which the charge storage layer 54 is a single continuous layer, in other embodiments, the charge storage layer 54 is replaced with a plurality of vertically spaced memory material portions (which may be charge trapping material portions or electrically isolated conductive material portions).

[0080] The charge storage layer 54 may be formed as a single charge storage layer of uniform composition, or may include a stack of multiple charge storage layers. The multiple charge storage layers (if used) may include multiple spaced-apart floating gate material layers, which contain conductive materials (e.g., metals such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium and alloys thereof, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide or combinations thereof) and / or semiconductor materials (e.g., polycrystalline or amorphous semiconductor materials including at least one element semiconductor element or at least one compound semiconductor material). Alternatively or in addition, the charge storage layer 54 may include an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the charge storage layer 54 may include conductive nanoparticles, such as metal nanoparticles, which may be, for example, ruthenium nanoparticles. The charge storage layer 54 may be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of charge storage layer 54 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0081] The tunneling dielectric 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicate, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used.

[0082] The optional first semiconductor channel layer 601 includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 includes amorphous silicon or polycrystalline silicon. The first semiconductor channel layer 601 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer 601 can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The memory cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 601).

[0083] refer to Figure 4D , the optional first semiconductor channel layer 601, the tunneling dielectric 56, the charge storage layer 54, the blocking dielectric layer 52 are anisotropically etched in sequence using at least one anisotropic etching process. Portions of the first semiconductor channel layer 601, the tunneling dielectric 56, the charge storage layer 54, and the blocking dielectric layer 52 positioned above the top surface of the insulating cap layer 70 may be removed by at least one anisotropic etching process. In addition, horizontal portions of the first semiconductor channel layer 601, the tunneling dielectric 56, the charge storage layer 54, and the blocking dielectric layer 52 at the bottom of each memory cavity 49' may be removed to form openings in the remaining portions thereof. Each of the first semiconductor channel layer 601, the tunneling dielectric 56, the charge storage layer 54, and the blocking dielectric layer 52 may be etched by a corresponding anisotropic etching process using a corresponding etching chemistry, which may be the same or different for the various material layers.

[0084] Each remaining portion of the first semiconductor channel layer 601 may have a tubular configuration. The charge storage layer 54 may include a charge trapping material or a floating gate material. In one embodiment, each charge storage layer 54 may include a vertical stack of charge storage regions that store charge when programmed. In one embodiment, the charge storage layer 54 may be a charge storage layer in which each portion adjacent to the sacrificial material layer 42 constitutes a charge storage region.

[0085] The surface of the base channel portion 11 (or the surface of the semiconductor material layer 10 in the case where the base channel portion 11 is not used) can be physically exposed below the opening through the first semiconductor channel layer 601, the tunneling dielectric 56, the charge storage layer 54 and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' can be vertically recessed, so that the recessed semiconductor surface below the memory cavity 49' is vertically offset from the topmost surface of the base channel portion 11 (or the semiconductor material layer 10 in the case where the base channel portion 11 is not used) by a recessed distance. The tunneling dielectric 56 is positioned above the charge storage layer 54. The blocking dielectric layer 52, the charge storage layer 54 and the tunneling dielectric 56 in the memory opening 49 constitute a memory film 50, which includes a plurality of charge storage regions (including the charge storage layer 54), which are insulated from surrounding materials by the blocking dielectric layer 52 and the tunneling dielectric 56. In one embodiment, the first semiconductor channel layer 601 , the tunneling dielectric 56 , the charge storage layer 54 , and the blocking dielectric layer 52 may have vertically coincident sidewalls.

[0086] refer to Figure 4E , the second semiconductor channel layer 602 can be deposited directly on the semiconductor surface of the base channel portion 11 or on the semiconductor material layer 10 (if the base channel portion 11 is omitted), and directly deposited on the first semiconductor channel layer 601. The second semiconductor channel layer 602 includes a semiconductor material, such as at least one element semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer 602 includes amorphous silicon or polycrystalline silicon. The second semiconductor channel layer 602 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer 602 can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The second semiconductor channel layer 602 can partially fill the memory cavity 49' in each memory opening, or can completely fill the cavity in each memory opening.

[0087] The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as semiconductor channel materials. In other words, the semiconductor channel material is a collection of all semiconductor materials in the first semiconductor channel layer 601 and the second semiconductor channel layer 602.

[0088] refer to Figure 4FIn the case where the memory cavity 49' in each memory opening is not completely filled with the second semiconductor channel layer 602, a dielectric core layer 62L may be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer 62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L may be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD) or by a self-planarization deposition process such as spin coating.

[0089] refer to Figure 4G , the horizontal portion of the dielectric core layer 62L may be removed, for example, by recess etching from above the top surface of the insulating cap layer 70. Each remaining portion of the dielectric core layer 62L constitutes the dielectric core 62. In addition, the horizontal portion of the second semiconductor channel layer 602 positioned above the top surface of the insulating cap layer 70 may be removed by a planarization process that may use recess etching or chemical mechanical planarization (CMP). Each remaining portion of the second semiconductor channel layer 602 may be positioned entirely within the memory opening 49 or entirely within the support opening 19.

[0090] Each adjacent pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can together form a vertical semiconductor channel 60, and when the vertical NAND device including the vertical semiconductor channel 60 is turned on, current can flow through the vertical semiconductor channel. The tunneling dielectric 56 is surrounded by the charge storage layer 54 and laterally surrounds a portion of the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, charge storage layers 54 and tunneling dielectrics 56 together constitute a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the backside recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0091] refer to Figure 4H , the top surface of each dielectric core 62 may be further recessed into each memory opening, for example by recess etching to a depth positioned between the top surface of the insulating cap layer 70 and the bottom surface of the insulating cap layer 70. Drain regions 63 may be formed by depositing a doped semiconductor material in each recessed region above the dielectric core 62. The drain regions 63 may have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the drain regions 63 may be between 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm3 The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material may be removed from above the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP) or recess etching, to form the drain region 63.

[0092] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel, a tunnel dielectric, a plurality of memory elements including a portion of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening filling structure 58. Each combination of the base channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure.

[0093] refer to Figure 5 , shows an exemplary structure after forming a memory opening filling structure 58 and a support pillar structure 20 in the memory opening 49 and the support opening 19, respectively. Figure 4A and Figure 4B An instance of memory opening fill structure 58 is formed within each memory opening 49 of the structure. Figure 4A and Figure 4B An instance of a support column structure 20 is formed within each support opening 19 of the structure.

[0094] Each memory stack structure 55 includes a vertical semiconductor channel 60, which may include a plurality of semiconductor channel layers (601, 602) and a memory film 50. The memory film 50 may include a tunneling dielectric 56 laterally surrounding the vertical semiconductor channel 60 and a vertical stack of charge storage regions laterally surrounding the tunneling dielectric 56 (including a charge storage layer 54) and an optional blocking dielectric layer 52. Although the description in the present disclosure uses the illustrated configuration for the memory stack structure, the methods of the various embodiments of the present disclosure may be applied to alternative memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60.

[0095] refer to Fig. 6A and Figure 6B, a lower contact level dielectric layer 73 may be formed over the alternating stack (32, 42) of insulating layers 32 and sacrificial material layers 42 and over the memory stack structure 55 and the support pillar structure 20. The lower contact level dielectric layer 73 includes a dielectric material different from the dielectric material of the sacrificial material layer 42. For example, the lower contact level dielectric layer 73 may include silicon oxide. The lower contact level dielectric layer 73 may have a thickness in the range of 50 nm to 500 nm, but smaller and larger thicknesses may also be used.

[0096] A photoresist layer (not shown) may be applied over the lower contact level dielectric layer 73 and photolithographically patterned to form openings in the areas between the clusters of the memory stack structure 55. The pattern in the photoresist layer may be transferred through the lower contact level dielectric layer 73, the alternating stacks (32, 42) and / or the back stepped dielectric material portions 65 using anisotropic etching to form backside trenches 79 extending vertically from at least the top surface of the lower contact level dielectric layer 73 to the top surface of the substrate (9, 10) and extending laterally through the memory array region 100 and the staircase region 300.

[0097] In one embodiment, the backside trenches 79 may extend laterally along a first horizontal direction hd1, and may be spaced laterally from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The memory stack structures 55 may be arranged in rows extending along the first horizontal direction hd1. The drain selection level isolation structure 72 may extend laterally along the first horizontal direction hd1. Each backside trench 79 may have a uniform width that is constant along the longitudinal direction (i.e., along the first horizontal direction hd1). Each drain selection level isolation structure 72 may have a uniform vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1, which does not change with translation along the first horizontal direction hd1. The multi-row memory stack structures 55 may be positioned between an adjacent pair of backside trenches 79 and drain selection level isolation structures 72, or between an adjacent pair of drain selection level isolation structures 72. In one embodiment, the backside trenches 79 may include a source contact opening, and a source contact structure may then be formed in the source contact opening. The photoresist layer may be removed, for example, by ashing.

[0098] refer to Figure 7 and Fig. 8A An etchant may be introduced into the backside trench 79 , for example, using an etching process, the etchant selectively etching the second material of the sacrificial material layer 42 relative to the first material of the insulating layer 32 . Fig. 9A shows a region of the exemplary structure of Figure 8. The backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The second material of the sacrificial material layer 42 can be removed selectively to the first material of the insulating layer 32, the material of the backward stepped dielectric material portion 65, the semiconductor material of the semiconductor material layer 10, and the outermost material of the memory film 50. In one embodiment, the sacrificial material layer 42 may include silicon nitride, and the materials of the insulating layer 32 and the backward stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxide.

[0099] The etching process for selectively removing the second material from the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in a vapor phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process in which the exemplary structure is immersed in a wet etching tank including phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art. When the backside recess 43 exists within the volume previously occupied by the sacrificial material layer 42, the support pillar structure 20, the rear stepped dielectric material portion 65, and the memory stack structure 55 provide structural support.

[0100] Each back side recess 43 may be a laterally extending cavity, the lateral dimension of which is greater than the vertical extent of the cavity. In other words, the lateral dimension of each back side recess 43 may be greater than the height of the back side recess 43. Multiple back side recesses 43 may be formed in the volume of the second material from which the sacrificial material layer 42 is removed. The memory opening in which the memory stack structure 55 is formed is referred to herein as the front side opening or the front side cavity, in contrast to the back side recess 43. In one embodiment, the memory array area 100 includes a monomer three-dimensional NAND string array having a plurality of device levels disposed above the substrate (9, 10). In this case, each back side recess 43 may define a space for accommodating a corresponding word line of the monomer three-dimensional NAND string array.

[0101] Each of the plurality of backside recesses 43 may extend substantially parallel to the top surface of the substrate (9, 10). The backside recess 43 may be vertically bounded by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each backside recess 43 may have a uniform height throughout.

[0102] The optional base channel portion 11 and the physically exposed surface portion of the semiconductor material layer 10 can be converted into a dielectric material portion by thermal conversion and / or plasma conversion of the semiconductor material into a dielectric material. For example, thermal conversion and / or plasma conversion can be used to convert the surface portion of each base channel portion 11 into a tubular dielectric spacer 115, and each physically exposed surface portion of the semiconductor material layer 10 into a planar dielectric portion 616. In one embodiment, each tubular dielectric spacer 115 can be topologically homeomorphic to a torus, i.e., roughly annular. As used herein, if the shape of the element can be continuously stretched without destroying the hole or forming a new hole into the shape of the torus, the element is topologically homeomorphic to the torus. The tubular dielectric spacer 115 includes a dielectric material that includes the same semiconductor element as the base channel portion 11, and additionally includes at least one non-metallic element such as oxygen and / or nitrogen, so that the material of the tubular dielectric spacer 115 is a dielectric material. In one embodiment, tubular dielectric spacer 115 may include a dielectric oxide, dielectric nitride, or dielectric oxynitride of the semiconductor material of base channel portion 11. Likewise, each planar dielectric portion 616 includes a dielectric material that includes the same semiconductor elements as the semiconductor material layer and additionally includes at least one non-metallic element such as oxygen and / or nitrogen, such that the material of planar dielectric portion 616 is a dielectric material. In one embodiment, planar dielectric portion 616 may include a dielectric oxide, dielectric nitride, or dielectric oxynitride of the semiconductor material of semiconductor material layer 10.

[0103] refer to Figure 8B , a backside blocking dielectric layer 44 may be optionally formed. The backside blocking dielectric layer 44, if present, comprises a dielectric material that serves as a control gate dielectric for a control gate subsequently formed in the backside recess 43. In the case where a blocking dielectric layer 52 is present within each memory opening, the backside blocking dielectric layer 44 is optional. In the case where the blocking dielectric layer 52 is omitted, the backside blocking dielectric layer 44 is present.

[0104] The backside blocking dielectric layer 44 may be formed in the backside recess 43 and on the sidewalls of the backside trench 79. The backside blocking dielectric layer 44 may be formed directly on the horizontal surface of the insulating layer 32 in the backside recess 43 and on the sidewalls of the memory stack structure 55. If the backside blocking dielectric layer 44 is formed, it is optional to form the tubular dielectric spacer 115 and the planar dielectric portion 616 before forming the backside blocking dielectric layer 44. In one embodiment, the backside blocking dielectric layer 44 may be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer 44 may be substantially composed of aluminum oxide. The thickness of the backside blocking dielectric layer 44 may be in the range of 1nm to 15nm, such as 2nm to 6nm, but smaller and larger thicknesses may also be used.

[0105] The dielectric material of the backside blocking dielectric layer 44 may be a dielectric metal oxide (such as aluminum oxide), a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, a dielectric oxide of a combination of aluminum and at least one transition metal element and / or at least one lanthanide element. Alternatively or in addition, the backside blocking dielectric layer 44 may include a silicon oxide layer. The backside blocking dielectric layer 44 may be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer 44 is formed on the sidewalls of the backside trench 79, the horizontal surface and sidewalls of the insulating layer 32, the portion of the sidewall surface of the memory stack structure 55 that is physically exposed to the backside recess 43, and the top surface of the planar dielectric portion 616. A backside cavity 79' exists in the portion of each backside trench 79 that is not filled with the backside blocking dielectric layer 44.

[0106] refer to Figure 8C , a metal barrier layer 46A may be deposited in the backside recess 43. The metal barrier layer 46A includes a conductive metal material that may serve as a diffusion barrier and / or adhesion promoting layer for a metal fill material to be subsequently deposited. The metal barrier layer 46A may include a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may include a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer 46A may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer 46A may be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, although smaller and larger thicknesses may also be used. In one embodiment, the metal barrier layer 46A may consist essentially of a conductive metal nitride such as TiN.

[0107] refer to Fig.8D and Fig. 9, the metal filling material is deposited in the plurality of backside recesses 43, on the sidewalls of at least one backside trench 79, and above the top surface of the lower contact level dielectric layer 73 to form a metal filling material layer 46B. The metal filling material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal filling material layer 46B may be substantially composed of at least one elemental metal. The at least one elemental metal of the metal filling material layer 46B may be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal filling material layer 46B may be substantially composed of a single elemental metal. In one embodiment, a fluorine-containing precursor gas (such as WF6) may be used to deposit the metal filling material layer 46B. In one embodiment, the metal filling material layer 46B may be a tungsten layer including residual level fluorine atoms as impurities. The metal filling material layer 46B is spaced apart from the insulating layer 32 and the memory stack structure 55 by the metal barrier layer 46A, which is a metal barrier layer that blocks fluorine atoms from diffusing therethrough.

[0108] A plurality of conductive layers 46 may be formed in the plurality of backside recesses 43, and a continuous conductive material layer 46L may be formed on the sidewalls of each backside trench 79 and over the lower contact level dielectric layer 73. Each conductive layer 46 includes a portion of a metal barrier layer 46A and a portion of a metal fill material layer 46B positioned between a pair of vertically adjacent dielectric material layers such as a pair of insulating layers 32. The continuous conductive material layer 46L includes a continuous portion of the metal barrier layer 46A and a continuous portion of the metal fill material layer 46B positioned in the backside trench 79 or over the lower contact level dielectric layer 73.

[0109] Each sacrificial material layer 42 may be replaced by a conductive layer 46. A backside cavity 79' exists in a portion of each backside trench 79 that is not filled with the backside blocking dielectric layer 44 and the continuous conductive material layer 46L. A tubular dielectric spacer 115 laterally surrounds the base channel portion 11. When the conductive layer 46 is formed, the bottommost conductive layer 46 laterally surrounds each tubular dielectric spacer 115.

[0110] refer to Fig. 10A and Fig. 10B , the deposited metal material of the continuous conductive material layer 46L is etched back from the sidewalls of each backside trench 79 and from above the lower contact level dielectric layer 73, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metal material in the backside recess 43 constitutes a conductive layer 46. Each conductive layer 46 can be a conductive line structure. Therefore, the sacrificial material layer 42 is replaced by the conductive layer 46.

[0111] Each conductive layer 46 may be used as a combination of a plurality of control gate electrodes positioned at the same level and a word line electrically interconnecting (i.e., electrically connecting) the plurality of control gate electrodes positioned at the same level. The plurality of control gate electrodes within each conductive layer 46 are control gate electrodes for a vertical memory device including the memory stack structure 55. In other words, each conductive layer 46 may be a word line used as a common control gate electrode for a plurality of vertical memory devices.

[0112] In one embodiment, the removal of the continuous conductive material layer 46L may be selective to the material of the backside blocking dielectric layer 44. In this case, a horizontal portion of the backside blocking dielectric layer 44 may be present at the bottom of each backside trench 79. In another embodiment, the removal of the continuous conductive material layer 46L may not be selective to the material of the backside blocking dielectric layer 44, or the backside blocking dielectric layer 44 may not be used. The planar dielectric portion 616 may be removed during the removal of the continuous conductive material layer 46L. A backside cavity 79' is present within each backside trench 79.

[0113] refer to Fig.11A and Fig. 11B , an insulating material layer may be formed in the backside trench 79 and above the lower contact level dielectric layer 73 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organic silicate glass, or a combination thereof. In one embodiment, the insulating material layer may include silicon oxide. The insulating material layer may be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer may be in the range of 1.5 nm to 60 nm, but smaller and larger thicknesses may also be used.

[0114] If backside blocking dielectric layer 44 is present, the insulating material layer may be formed directly on the surface of backside blocking dielectric layer 44 and directly on the sidewalls of conductive layer 46. If backside blocking dielectric layer 44 is not used, the insulating material layer may be formed directly on the sidewalls of insulating layer 32 and directly on the sidewalls of conductive layer 46.

[0115] Anisotropic etching is performed to remove horizontal portions of the insulating material layer from above the lower contact level dielectric layer 73 and at the bottom of each backside trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A backside cavity 79' exists within the volume surrounded by each insulating spacer 74. The top surface of the semiconductor material layer 10 may be physically exposed at the bottom of each backside trench 79.

[0116] Source regions 61 may be formed at a surface portion of the semiconductor material layer 10 beneath each backside cavity 79' by implanting electrical dopants into the physically exposed surface portion of the semiconductor material layer 10. Each source region 61 is formed in a surface portion of the substrate (9, 10) that is located beneath a corresponding opening through the insulating spacer 74. Due to the spreading of the implanted dopant atoms during the implantation process and the lateral diffusion of the implanted dopant atoms during the subsequent activation annealing process, each source region 61 may have a lateral extent that is greater than the lateral extent of the opening through the insulating spacer 74.

[0117] The upper portion of the semiconductor material layer 10 extending between the source region 61 and the plurality of base channel portions 11 constitutes a horizontal semiconductor channel 59 for a plurality of field effect transistors. The horizontal semiconductor channel 59 is connected to a plurality of vertical semiconductor channels 60 through the corresponding base channel portions 11. The horizontal semiconductor channel 59 contacts the source region 61 and the plurality of base channel portions 11. The bottommost conductive layer 46 provided when forming the conductive layer 46 within the alternating stack (32, 46) may include a select gate electrode for the field effect transistor. Each source region 61 is formed in the upper portion of the substrate (9, 10). The semiconductor channel (59, 11, 60) extends between each source region 61 and a corresponding set of drain regions 63. The semiconductor channel (59, 11, 60) includes the vertical semiconductor channel 60 of the memory stack structure 55.

[0118] The source contact structure 76 may be formed in each backside cavity 79'. Each contact via structure 76 may fill a corresponding cavity 79'. The contact via structure 76 may be formed by depositing at least one conductive material in the remaining unfilled volume of the backside trench 79 (i.e., the backside cavity 79'). For example, the at least one conductive material may include a conductive liner 76A and a conductive filling material portion 76B. The conductive liner 76A may include a conductive metal liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner 76A may be in the range of 3nm to 30nm, but smaller and larger thicknesses may also be used. The conductive filling material portion 76B may include a metal or a metal alloy. For example, the conductive filling material portion 76B may include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

[0119] The lower contact level dielectric layer 73 overlying the alternating stack (32, 46) can be used as a stop layer to planarize the at least one conductive material. If a chemical mechanical planarization (CMP) process is used, the lower contact level dielectric layer 73 can be used as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in the backside trench 79 constitutes a source contact structure 76.

[0120] The source contact structure 76 extends through the alternating stack (32, 46) and contacts the top surface of the source region 61. The source contact structure 76 may contact the sidewalls of the backside blocking dielectric layer 44 if a backside blocking dielectric layer 44 is used.

[0121] refer to Fig. 12A and Fig. 12B , a layer contact via structure 86 may be formed to pass through the lower contact level dielectric layer 73 and the backward stepped dielectric material portion 65 to reach the top surface of the corresponding conductive layer in the conductive layer 46 in the stair region. The layer contact via structure 86 includes a word line contact via structure that contacts a subset of the conductive layer 46 used as a word line. In one embodiment, the top surface of the layer contact via structure 86 may be coplanar with the top surface of the lower contact level dielectric layer 73.

[0122] An intermediate contact level dielectric layer 181 may be deposited over the lower contact level dielectric layer 73. The intermediate contact level dielectric layer 181 includes a dielectric material, such as silicon oxide. Line trenches may be formed through the intermediate contact level dielectric layer 181 over the layer contact via structures 86. The line trenches in the intermediate contact level dielectric layer 181 may be filled with at least one conductive material to form contact connection line structures 182 that contact the top surface of the corresponding underlying layer contact via structures in the layer contact via structures 86.

[0123] Alternatively, an intermediate contact level dielectric layer 181 may be formed above the lower contact level dielectric layer 73 before forming the layer contact via structure 86, and an integrated line and via cavity may be formed through the intermediate contact level dielectric layer 181 and the lower contact level dielectric layer 73. Each integrated line and via cavity may include a combined volume for the layer contact via structure 86 and the contact connection line structure 182. The integrated line and via cavity is filled with at least one conductive material to form an integrated line and via structure. Each integrated line and via structure may include a combination of the layer contact via structure 86 and the contact connection line structure 182.

[0124] An upper contact level dielectric layer 183 may be formed over the middle contact level dielectric layer 181. The upper contact level dielectric layer 183 includes a dielectric material, such as silicon oxide. A contact via cavity extending through the upper contact level dielectric layer 183, optionally through the middle contact level dielectric layer 181, and optionally through the lower contact level dielectric layer 73 may be formed, for example, by applying a photoresist layer (not shown) over the upper contact level dielectric layer 183 and patterning it, and by an anisotropic etching process that transfers the pattern in the photoresist layer through the upper contact level dielectric layer 183, the middle contact level dielectric layer 181, and the lower contact level dielectric layer 73. The contact via cavity may be formed over the memory opening fill structure 58, the source contact structure 76, and the contact connection line structure 182, which may serve as an etch stop structure during the formation of the contact via cavity. The photoresist layer may be removed, for example, by ashing.

[0125] Optionally, a linear pattern may be formed in the upper region of a subset of the contact via cavities. For example, a photoresist layer (not shown) may be applied above the upper contact level dielectric layer 183 and may be photolithographically patterned to form a linear opening covering the subset of the contact via cavities. The pattern in the photoresist layer may be transferred to the upper region of the upper contact level dielectric layer 183 by an anisotropic etching process. An integrated line and via cavity may be formed through the upper contact level dielectric layer 183. In one embodiment, an integrated line and via cavity may be formed above the source contact structure 76 and the contact connection line structure 182. A cylindrical via cavity may be formed in the memory array region, the cylindrical via cavity comprising a vertical sidewall extending from the top surface of the upper contact level dielectric layer 183 to the top surface of the corresponding drain region in the drain region 63. The photoresist layer may then be removed, for example, by ashing.

[0126] At least one conductive material may be deposited in the integrated line and via cavities and the cylindrical via cavities. Various contact via structures (88, 184, 186) may be formed through the upper contact level dielectric layer 183, the middle contact level dielectric layer 181, and the lower contact level dielectric layer 73. The contact via structures (88, 184, 186) may include a drain contact via structure 88 that extends through the upper contact level dielectric layer 183, the middle contact level dielectric layer 181, and the lower contact level dielectric layer 73 and contacts the top surface of the corresponding drain region in the drain region 63. Each drain contact via structure 88 may have a cylindrical shape, i.e., a shape having a horizontal cross-sectional area that does not vary with translation along the vertical direction. The contact via structures (88, 184, 186) may also include a word line connection contact via structure 186 formed on a top surface of a corresponding one of the contact connection line structures 182. Each word line connection contact via structure 186 may extend through the upper contact level dielectric layer 183. In addition, the contact via structures (88, 184, 186) may also include a source connection contact via structure 184 formed on a top surface of a corresponding one of the source contact structures 76. Each source connection contact via structure 184 may extend through the upper contact level dielectric layer 183 and the intermediate contact level dielectric layer 181. In one embodiment, each of the word line connection contact via structure 186 and the source connection contact via structure 184 may be an integrated line and via structure including a corresponding via portion and a corresponding line portion. In one embodiment, the line portion of each source connection contact via structure 184 may extend laterally along a first horizontal direction hd1 along a major portion (i.e., greater than 50%) of the entire length of the underlying source contact structure 76. A source connection contact via structure 184 may be formed over each source contact structure 76 and may be electrically connected to each source contact structure.

[0127] refer to Fig.13A and Fig. 13B , a first via level dielectric layer 110 may be deposited over the upper contact level dielectric layer 183. The first via level dielectric layer 110 includes a dielectric material such as undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the first via level dielectric layer 110 may be in the range of 50 nm to 300 nm, although lesser and greater thicknesses may also be used.

[0128] For example, a via cavity is formed through the first via level dielectric layer 110 by applying a photoresist layer (not shown) over the first via level dielectric layer 110 and patterning it, and by anisotropically etching unmasked portions of the first via level dielectric layer 110. The photoresist layer may then be removed. Conductive material may be deposited in the via cavity to form various first via structures (118, 114, 116). The first through-hole structure (118, 114, 116) may include: a bit line connection through-hole structure 118, which is formed on the top surface of the corresponding drain contact through-hole structure in the drain contact through-hole structure 88; a first source connection through-hole structure 114, which is formed on the top surface of the corresponding source connection contact through-hole structure in the source connection contact through-hole structure 184; and a first word line connection through-hole structure 116, which is formed on the top surface of the corresponding word line connection contact through-hole structure in the word line connection contact through-hole structure 186.

[0129] A first line-level dielectric layer 120 may be deposited over the first via-level dielectric layer 110. The first line-level dielectric layer 120 includes a dielectric material such as undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the first line-level dielectric layer 120 may be in the range of 50 nm to 300 nm, although lesser and greater thicknesses may also be used.

[0130] For example, a line cavity is formed through the first line level dielectric layer 120 by applying a photoresist layer (not shown) over the first line level dielectric layer 120 and patterning it, and by anisotropically etching the unmasked portion of the first line level dielectric layer 120. The photoresist layer may then be removed. Conductive material may be deposited in the line cavity to form various first line structures (128, 124, 126). The first line structures (128, 124, 126) may include: a bit line 128 formed on a top surface of a corresponding bit line connection via structure in the bit line connection via structures 118; a first source connection line structure 124 formed on a top surface of a corresponding first source connection via structure in the first source connection via structures 114; and a first word line connection line structure 126 formed on a top surface of a corresponding first word line connection via structure in the first word line connection via structures 116.

[0131] In one embodiment, the bit lines 128 may extend laterally along the second horizontal direction hd2 and may be laterally spaced apart at a uniform pitch (referred to herein as a bit line pitch) along the first horizontal direction hd1. The first source connection line structure 124 and the first word line connection line structure 126 may extend laterally along the first horizontal direction hd1 and may be formed in the staircase region 300. Each source region 61 may be electrically connected to a corresponding set of at least one first source connection line structure 124 through a corresponding source contact structure 76 and a corresponding at least one first source connection via structure 114.

[0132] refer to FIG. 14A to FIG. 14C , a second via level dielectric layer 130 may be deposited over the upper contact level dielectric layer 183. The second via level dielectric layer 130 includes a dielectric material such as undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the second via level dielectric layer 130 may be in the range of 50 nm to 300 nm, although lesser and greater thicknesses may also be used.

[0133] For example, a via cavity is formed through the second via level dielectric layer 130 by applying a photoresist layer (not shown) over the second via level dielectric layer 130 and patterning it, and by anisotropically etching an unmasked portion of the second via level dielectric layer 130. The photoresist layer may then be removed. A conductive material may be deposited in the via cavity to form a second via structure (134, 136). The second via structure (134, 136) may include: a second source connection via structure 134 formed on a corresponding first source connection line structure in the first source connection line structures 124; a second word line connection via structure 136 formed on a corresponding word line connection line structure in the word line connection line structures 126; and a bit line connection via structure (not shown) formed on a top surface of a corresponding bit line in the bit line 128.

[0134] The memory side pad level dielectric layer 140 may be deposited over the second via level dielectric layer 130. The memory side pad level dielectric layer 140 includes a dielectric material such as undoped silicate glass, doped silicate glass, or organosilicate glass. The thickness of the memory side pad level dielectric layer 140 may be in the range of 50 nm to 300 nm, although smaller and larger thicknesses may also be used.

[0135] For example, a pad cavity is formed through the memory side pad level dielectric layer 140 by applying a photoresist layer (not shown) over the memory side pad level dielectric layer 140 and patterning it, and by anisotropically etching the unmasked portion of the memory side pad level dielectric layer 140. The photoresist layer may then be removed. The pad cavity may have a rectangular shape and may be arranged in a rectangular periodic array, or may have a non-rectangular shape, such as an "H-shape", and may be arranged in a periodic array that may or may not be a rectangular array.

[0136] Conductive material may be deposited in the pad cavity to form various memory die bonding pads 144. The memory die bonding pads 144 may include: a source network memory die bonding pad 144A formed on a top surface of a corresponding second source connection via structure in the second source connection via structure 134; a word line connection memory die bonding pad 144B formed on a top surface of a corresponding second word line connection via structure in the second word line connection via structure 136; and a bit line connection memory die bonding pad 144C formed on a top surface of a corresponding bit line connection via structure in the bit line connection via structure. An array of source network memory die bonding pads 144A may be formed in a first area RA overlying the memory array region 100. The array of source network memory die bonding pads 144A may be formed as a first periodic two-dimensional array and may be used as a component of a power distribution network for supplying power to the source region 61. An array of word line connection memory die bonding pads 144B may be formed in a second area RB covering the staircase area 300. The array of word line connection memory die bonding pads 144B may be formed as a second periodic two-dimensional array. Each word line connection memory die bonding pad 144B may be electrically connected to a corresponding conductive layer in the conductive layer 46. An array of bit line connection memory die bonding pads 144C may be formed in a third area RC, which is laterally offset from the first area RA and the second area RB. Each bit line connection memory die bonding pad 144C may be connected to a corresponding bit line 128 and a corresponding subset of the drain region 63.

[0137] FIG. 14A to FIG. 14CThe exemplary structure shown includes a memory die 900. In general, the memory die 900 may include an alternating stack of insulating layers 32 and conductive layers 46 positioned above a substrate (9, 10), a memory stack structure 55 extending through the alternating stack (32, 46), wherein each of the memory stack structures 55 includes a memory film 50 and a vertical semiconductor channel 60, a source region 61 positioned on or in the substrate (9, 10), a source contact structure 76 extending vertically through the alternating stack (32, 46) and contacting the source region 61, and an array of memory die bond pads (i.e., source network memory die bond pads 144A) electrically connected to the source contact structure 76 through a subset of memory-side metal interconnect structures, the source contact structure may include a source connection contact via structure 184, a first source connection via structure 114, a first source connection line structure 124, and a second source connection via structure 134.

[0138] A plurality of memory dies 900 may be provided. Each of the memory dies 900 may include an alternating stack of insulating layers 32 and word lines, the word lines including a subset of conductive layers 46. The alternating stacks (32, 46) have a stepped surface in which the subset of conductive layers 46 has a lateral extent that increases with the distance from the bonding surface of the memory die 900 including the memory die bonding pads 144. The memory stack structures 55 extend vertically through the alternating stacks (32, 46). Each of the memory stack structures 55 includes a corresponding vertical semiconductor channel 60 and a corresponding group of vertically stacked memory elements positioned at the level of the conductive layer 46. Each group of vertically stacked memory elements may include a portion of the charge storage layer 54 positioned at the level of the conductive layer 46. The word line contact via structure (which is a subset of the layer contact via structure 86 that contacts the subset of the conductive layer 46 used as a word line) may contact a corresponding word line in the word lines. Each of the word line contact via structures extends vertically from a corresponding one of the word lines toward the bonding surface of the memory die 900 .

[0139] refer to FIG. 15A to FIG. 15C, a support die 700 including various semiconductor devices 710 is provided. The semiconductor device 710 includes a peripheral circuit 730 for operating a three-dimensional memory array in a memory die 900. The peripheral circuit 730 may include: a word line driver 734 that drives the word lines (including the conductive layer 46) of the three-dimensional memory array within the memory die 900; a bit line driver 736 that drives the bit lines 128 in the memory die 900; a word line decoder circuit that decodes the address of the conductive layer 46; a bit line decoder circuit that decodes the address of the bit line 128; a sense amplifier 732 circuit that senses the state of the memory element within the memory stack structure 55 in the memory die 900; a source power supply circuit that provides power to the source region 61 of the memory die 900; a data buffer and / or latch; or any other semiconductor circuit that can be used to operate the array of memory stack structures 58 in the memory die 900.

[0140] The support die 700 may include a support die substrate 708, which may include a support die semiconductor layer 706. The support die semiconductor layer 706 may include at least one elemental semiconductor material (e.g., a single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0141] Shallow trench isolation structures 720 may be provided in the surface region of the support die semiconductor layer 706 to provide electrical isolation from the semiconductor devices of the peripheral circuit 730. Various semiconductor devices 710 may include field effect transistors, which include corresponding transistor active regions 742 (i.e., source regions and drain regions), channels 746, and gate structures 750. The field effect transistors may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758. For example, the semiconductor device 710 may include: a word line driver 734 for electrically biasing a word line of the memory die 900, the word line including the conductive layer 46; and a source power supply field effect transistor, which generates power to be supplied to the source region 61 of the memory die 900.

[0142] A dielectric material layer is formed over the semiconductor device 710, which is referred to herein as a support chip dielectric layer 760. Optionally, a dielectric liner 762 (such as a silicon nitride liner) may be formed to apply mechanical stress to the various field effect transistors and / or to prevent hydrogen or impurities from diffusing from the support chip dielectric layer 760 into the semiconductor device 710. A support chip metal interconnect structure 780 is formed within the support chip dielectric layer 760. The support chip metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes contacting corresponding source and drain nodes of a device or gate electrode contact), interconnect level metal line structures 784, interconnect level metal via structures 786, and front support die bonding pads 788. The front support die bonding pads 788 are configured to cooperate with the memory die bonding pads 144 to provide a conductive path between the memory die 900 and the support die 700.

[0143] In one embodiment, the semiconductor device 710 of the support die 700 may include a complementary metal oxide semiconductor (CMOS) device. In one embodiment, the peripheral circuit 730 may include a peripheral circuit 730 configured to drive a plurality of memory dies 900. In one embodiment, the front support die bond pad 788 may be electrically connected to a first subset 731A of the peripheral circuits 730, which is configured to drive a first instance of the memory die 900. The second subset 731B of the peripheral circuits 730 may be configured to drive a second instance of the memory die 900. The intersection (i.e., the common subset) of the first subset 731A of the peripheral circuits 730 and the second subset 731B of the peripheral circuits 730 includes a third subset 731C of the peripheral circuits 730, which is configured to be electrically connected to an electrical node within the first instance of the memory die 900 and an electrical node within the second instance of the memory die 900.

[0144] In one embodiment, the peripheral circuit 730 may include a sense amplifier 732 and a first switchable electrical connection circuit 733. The first switchable electrical connection circuit 733 may be configured to connect the sense amplifier 732 to a set of nodes selected from a set of first bit lines 128 positioned within a first instance of a memory die 900 to be subsequently bonded to the support die 700 and a set of second bit lines 128 positioned within a second instance of a memory die 900 to be subsequently bonded to the support die 700.

[0145] In one embodiment, peripheral circuit 730 includes word line driver 734 and second switchable electrical connection circuit 735. Second switchable electrical connection circuit 735 is configured to connect word line driver 734 to a set of nodes selected from a set of first word lines (including a subset of conductive layer 46) positioned within a first instance of memory die 900 to be subsequently bonded to support die 700 and a set of second word lines (including a subset of conductive layer 46) positioned within a second instance of memory die 900 to be subsequently bonded to support die 700.

[0146] In one embodiment, the peripheral circuit 730 includes a bit line driver 736 and a third switchable electrical connection circuit 737. The third switchable electrical connection circuit 737 is configured to connect the bit line driver 736 to a set of nodes selected from a set of first bit lines 128 positioned within a first instance of a memory die 900 to be subsequently bonded to the support die 700 and a set of second bit lines 128 positioned within a second instance of a memory die 900 to be subsequently bonded to the support die 700.

[0147] In one embodiment, the peripheral circuit 730 includes a source power supply circuit 738 configured to drive a first source line (including a combination of source region 61, source contact structure 76, source connection contact via structure 184, first source connection via structure 114, first source connection line structure 124, and second source connection via structure 134) in a first instance of the memory die 900 and a second source line in a second instance of the memory die 900. The support die 700 may include a source power distribution network including a subset of the metal interconnect structure 780 and connected to the source power supply circuit and a subset of the front support die bond pads 788, and to a subset of the backside bond structures to be formed subsequently.

[0148] A separate driving circuit may be used in place of any combination of a driving circuit and a switchable electrical connection circuit. For example, a combination of a first sense amplifier 732A and a second sense amplifier 732B may be used in place of the combination of a sense amplifier 732 and a first switchable electrical connection circuit 733. In this case, the first sense amplifier 732A may be connected to a set of first bit lines 128 positioned within a first instance of a memory die 900 to be subsequently bonded to the support die 700, and the second sense amplifier 732B may be connected to a set of second bit lines 128 positioned within a second instance of a memory die 900 to be subsequently bonded to the support die 700.

[0149] In one embodiment, the peripheral circuit 730 includes: a first bit line driver 736A, which can be subsequently connected to a first bit line 128 within a first instance of the memory die 900 through a first subset of the front support die bonding pads 788 and a first subset of the first memory die bonding pads 144 (such as bit line connection memory die bonding pads 144C); and a second bit line driver 736B, which can be subsequently connected to a second bit line 128 within a second instance of the memory die 900 through a first subset of back side bonding structures to be subsequently formed on the support die 700 and through a first subset of the second memory die bonding pads (such as bit line connection memory die bonding pads 144C).

[0150] In one embodiment, the peripheral circuit 730 includes: a first word line driver 734A, which can be subsequently connected to a first word line (including a subset of conductive layer 46) within a first instance of the memory die 900 through a second subset of the front support die bonding pads 788 and a second subset of the first memory die bonding pads 144 (such as word line connection memory die bonding pads 144B); and a second word line driver 734B, which can be subsequently connected to a second word line (including a subset of conductive layer 46) within a second instance of the memory die 900 through a second subset of back side bonding structures to be subsequently formed on the support die 700 and through a second subset of the second memory die bonding pads (such as word line connection memory die bonding pads 144B).

[0151] refer to Fig.16 , a bonded assembly of the support die 700 and a first instance of the memory die 900 may be formed. The first instance of the memory die 900 is referred to herein as the first memory die 900A. The memory die bond pad 144 of the first memory die 900A is referred to herein as the first memory die bond pad 144. The first memory die bond pad 144 of the first memory die 900A may be bonded to the front support die bond pad 788 of the support die 700 via metal-to-metal bonding or by a solder ball array (not shown).

[0152] refer to Fig.17 , the support die semiconductor layer 706 may be thinned from the back side, for example by grinding, to provide a thinned support die semiconductor layer 709, which is a semiconductor material layer. The thinned support die semiconductor layer 709 may have a thickness in the range of 1 nm to 100 nm, such as 3 nm to 30 nm, although smaller and larger thicknesses may also be used.

[0153] refer to Fig.18, a backside insulating layer 714 may be deposited on the backside surface of the thinned support die semiconductor layer 709. The backside insulating layer 714 includes a dielectric material (such as silicon oxide) and may have a thickness in the range of 30nm to 1,000nm, although smaller and larger thicknesses may also be used. A photoresist layer (not shown) may be applied over the backside of the thinned support die semiconductor layer 709 and photolithographically patterned to form openings therein. The openings in the photoresist layer may be formed directly above the corresponding support chip metal interconnect structures in the support chip metal interconnect structures 780.

[0154] An anisotropic etching process may be performed using the photoresist layer as an etching mask layer to etch through the thinned support die semiconductor layer 709 to the surface of the corresponding support chip metal interconnect structure in the support chip metal interconnect structure 780. A through-substrate via cavity is formed through the backside insulating layer 714 and the thinned support die semiconductor layer 709. The photoresist layer may then be removed, for example, by ashing. An insulating liner layer may be deposited in the through-substrate via cavity and above the backside insulating layer 714. A horizontal portion of the insulating liner layer may be removed from above the backside insulating layer 714 by an anisotropic etching process. Each remaining tubular portion of the insulating liner layer constitutes a tubular insulating spacer 711. The tubular insulating spacer 711 includes a dielectric material such as silicon oxide and may have a lateral thickness in the range of 10 nm to 300 nm between the inner sidewall and the outer sidewall. At least one conductive material, such as a combination of a metal liner (eg, TiN) and a metal fill material (eg, W), may be deposited in the remaining volume of the through substrate via cavity to form a through substrate via structure 712 .

[0155] refer to Fig.19 , the backside support die bonding pad 716 may optionally be formed directly on a corresponding through substrate via structure in the through substrate via structure 712. In the case where the backside support die bonding pad 716 is formed, the backside support die bonding pad 716 may have a mirror image pattern of the pattern of the front support die bonding pad 788. Each combination of the through substrate via structure 712 and the backside support die bonding pad 716 constitutes a backside bonding structure (712, 716). Each of the backside bonding structures (712, 716) may include: a through substrate via structure 712, which extends through the semiconductor substrate of the support die 700 (including the support die substrate 708) and is laterally electrically insulated from the semiconductor substrate by the tubular insulating spacer 711; and a backside support die bonding pad 716, which contacts the through substrate via structure 712 and is subsequently bonded to the memory die bonding pad 144 of the second memory die.

[0156] In the absence of forming a backside support die bond pad 716, each backside bonding structure may include and / or may consist of a through substrate via structure 712 that extends through the semiconductor substrate (including the support die substrate 708) of the support die 700. The through substrate via structure 712 is laterally electrically insulated from the semiconductor substrate by the tubular insulating spacer 711 and subsequently bonded to the memory die bond pad 144 of the second memory die. In one embodiment, the backside bonding structure is electrically connected to the second subset 731B of the peripheral circuit 730 through the semiconductor substrate (including the support die substrate 708) of the support die 700.

[0157] refer to Fig. 20A and Fig. 20B , showing a second example of the memory die 900 of the present disclosure, which is referred to herein as the second memory die 900B. The memory die bonding pads of the second memory die 900B are referred to herein as the second memory die bonding pads 244. The second memory die bonding pads 244 may include: a second source network memory die bonding pad 244A, which is formed on the top surface of the corresponding second source connection via structure in the second source connection via structure 134; a second word line connection memory die bonding pad 244B, which is formed on the top surface of the corresponding second word line connection via structure in the second word line connection via structure 136; and a second bit line connection memory die bonding pad 244C, which is formed on the top surface of the corresponding bit line connection via structure in the bit line connection via structure. An array of the second source network memory die bonding pads 244A may be formed in a first area RA overlying the memory array region 100. The array of second source network memory die bonding pads 244A may be formed as a first periodic two-dimensional array and may be used as a component of a power distribution network for supplying power to source region 61. The array of second word line connection memory die bonding pads 244B may be formed in a second area RB covering staircase region 300. The array of second word line connection memory die bonding pads 244B may be formed as a second periodic two-dimensional array. Each second word line connection memory die bonding pad 244B may be electrically connected to a corresponding conductive layer in conductive layer 46. The array of second bit line connection memory die bonding pads 244C may be formed in a third area RC, which is laterally offset from the first area RA and the second area RB. Each second bit line connection memory die bonding pad 244C may be connected to a corresponding bit line 128 and a corresponding subset of drain region 63.

[0158] refer to Fig.21A and Fig.21B , the second memory die 900B may be Fig.19The second memory die bonding pad 244 is bonded to the back side bonding structure {(712, 716) or 712} of the support die 700. In the presence of the back side support die bonding pad 716, a Fig.21A The configuration shown, in which the second memory die bond pad 244 is bonded to the backside support die bond pad 716. Without the backside support bond pad 716, a Fig.21B A configuration in which the second memory die bond pad 244 is bonded to the through substrate via structure 712.

[0159] In one embodiment, the first memory die bond pad 144 can be bonded to the front support die bond pad 788 by metal-to-metal bonding, and the second memory die bond pad 244 can be bonded to the backside bond structure {(712, 716) or 712} by metal-to-metal bonding. Alternatively, the first memory die bond pad 144 can be bonded to the front support die bond pad 788 by a front side solder ball array, and / or the second memory die bond pad 244 can be bonded to the backside bond structure {(712, 716) or 712} by a backside solder ball array.

[0160] Each of the first memory die 900A and the second memory die 900B includes an alternating stack of insulating layers 32 and word lines (including a subset of conductive layers 46). Each alternating stack (32, 46) has a stepped surface, wherein the subset of conductive layers 46 has a lateral extent that increases with distance from the support die 700. Each of the first memory die 900A and the second memory die 900B includes a memory stack structure 55 that extends vertically through the alternating stack (32, 46) and includes a respective vertical semiconductor channel 60 and a respective set of vertically stacked memory elements (including portions of the charge storage layer 54) positioned at the level of the conductive layers 46. The word line contact via structure (which is a subset of the layer contact via structure 86) can contact a respective one of the word lines (which is a subset of the conductive layers 46) and can extend from the respective one of the word lines toward the support die 700.

[0161] refer to Figure 22 to Figure 24, external bonding pads (718, 722, 918, 922), solder structures (724, 924) and bonding wires (726, 926) may be formed on at least one of the support die 700, the first memory die 900A and the second memory die 900B. The external bonding pads (718, 722, 918, 922) may include a copper plate and / or an underlay bonding material (UBM) stack. The solder structures (724, 924) may include a solder material such as a tin-silver alloy. The solder structures (724, 924) may be formed on corresponding external bonding pads in the external bonding pads (718, 722, 918, 922).

[0162] Fig. 22 A first configuration is shown in which the external bonding pads (718, 722), solder structures 724, and bonding wires 726 are formed only on the support die 700. In this case, the external bonding pads (718, 722) may include: a front side external bonding pad 718 formed on a front side surface of the support die 700 facing the first memory die 900A; and a back side external bonding pad 722 formed on a back side surface of the support die 700 facing the second memory die 900B. The lateral extent of the support die 700 may be greater than the lateral extent of the first memory die 900A and / or the lateral extent of the second memory die 900B to allow the external bonding pads (718, 722) to be placed on the support die 700.

[0163] Fig.23 A second configuration is shown in which external bonding pads (918, 922), solder structures 924, and bonding wires 926 are formed only on at least one of the first memory die 900A and the second memory die 900B. In this case, the external bonding pads (918, 922) may include: a front side external bonding pad 918 formed on a distal surface of the first memory die 900A that is not in contact with the support die 700; and / or a rear side external bonding pad 922 formed on a distal surface of the second memory die 900B that is not in contact with the support die 700. The lateral extent of the support die 700 may be the same as, less than, or greater than the lateral extent of the first memory die 900A and / or the lateral extent of the second memory die 900B.

[0164] Fig.24 A third configuration is shown in which external bond pads (718, 722, 918, 922), solder structures (724, 924), and bond wires (726, 926) are formed on the support die 700 and on at least one of the first memory die 900A and the second memory die 900B.

[0165] With reference to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a bonding assembly (700, 900A, 900B) is provided, which includes: a support die 700, which includes a peripheral circuit 730, a front support die bonding pad 788 electrically connected to a first subset 731A of the peripheral circuit 730, and a backside bonding structure {(712, 716) or 712} electrically connected to a second subset 731B of the peripheral circuit 730; a first memory die 900A, which includes a first memory element three-dimensional array and a first memory die bonding pad 144 bonded to the front support die bonding pad 788; and a second memory die 900B, which includes a second memory element three-dimensional array and a second memory die bonding pad 244 bonded to the backside bonding structure {(712, 716) or 712}.

[0166] In one embodiment, the conductive path (including a subset of the support chip metal interconnect structure 780) extends through the support die 700 between a corresponding pair of front support chip bonding pads 788 and the backside bonding structure {(712, 716) or 712}. In one embodiment, the conductive path is connected to a node of one of the peripheral circuits 730 in the support die 700.

[0167] In one embodiment, the intersection of the first subset 731A of peripheral circuits 730 and the second subset 731B of peripheral circuits 730 includes a third subset 731C of peripheral circuits 730 that is electrically connected to electrical nodes within the first memory die 900A and electrical nodes within the second memory die 900B.

[0168] In one embodiment, the peripheral circuit 730 includes a sense amplifier 732 and a first switchable electrical connection circuit 733, wherein the first switchable electrical connection circuit 733 is configured to connect the sense amplifier 732 to a set of nodes selected from a set of first bit lines 128 positioned within the first memory die 900A and a set of second bit lines 128 positioned within the second memory die 900B.

[0169] In one embodiment, the peripheral circuit 730 includes a word line driver 734 and a second switchable electrical connection circuit 735, wherein the second switchable electrical connection circuit 735 is configured to connect the word line driver 734 to a set of nodes selected from a set of first word lines (including a subset of the conductive layer 46) positioned within the first memory tube core 900A and a set of second word lines (including a subset of the conductive layer 46) positioned within the second memory tube core 900B.

[0170] In one embodiment, the peripheral circuit 730 includes: a first bit line driver 736A connected to a first bit line 128 within a first memory die 900A via a first subset of front support die bond pads 788 and a first subset of first memory die bond pads 144; a second bit line driver 736B connected to a second bit line 128 within a second memory die 900B via a first subset of backside bond structures {(712, 716) or 712} and a first subset of second memory die bond pads 244; A first word line driver 734A, which is connected to the first word line (including a subset of the conductive layer 46) within the first memory die 900A through a second subset of the front support die bonding pads 788 and a second subset of the first memory die bonding pads 144; and a second word line driver 734B, which is connected to the second word line (including a subset of the conductive layer 46) within the second memory die 900B through a second subset of the back side bonding structures {(712, 716) or 712} and a second subset of the second memory die bonding pads 244.

[0171] In one embodiment, the peripheral circuit 730 includes a source power circuit 738, which is configured to drive a first source line in the first memory tube core 900A (including a combination of the source region 61, the source contact structure 76, the source connection contact through-hole structure 184, the first source connection through-hole structure 114, the first source connection line structure 124 and the second source connection through-hole structure 134) and a second source line in the second memory tube core 900B; and the support tube core 700 includes a source power distribution network, which includes a subset of metal interconnect structures (i.e., the support tube core metal interconnect structure 780) and is connected to the source power circuit 738, a subset of the front support tube core bonding pads 788, and a subset of the back side bonding structures {(712, 716) or 712}.

[0172] In one embodiment, the bonding assembly includes: external bonding pads (718, 722) positioned on the support die 700; and a solder structure 724 positioned on the external bonding pads (718, 722).

[0173] In one embodiment, the bonding assembly includes: an external bonding pad (918, 922) positioned on at least one of the first memory die 900A and the second memory die 900B; and a solder structure 924 positioned on the external bonding pad (918, 922).

[0174] In one embodiment, one of the backside bonding structures 712 includes a through substrate via structure 712 that extends through a semiconductor substrate of the support die 700 (such as a thinned support die semiconductor layer 709), is laterally electrically insulated from the semiconductor substrate by a tubular insulating spacer 711, and is electrically connected to the semiconductor substrate. Fig.21B One of the second memory die bond pads 244 is shown in contact.

[0175] In one embodiment, one of the back side bonding structures (712, 716) includes: a through substrate via structure 712, which extends through a semiconductor substrate of a support die 700 (such as a thinned support die semiconductor layer 709) and is laterally electrically insulated from the semiconductor substrate by a tubular insulating spacer 711; and a back side support die bonding pad 716, which contacts the through substrate via structure 712 and is bonded to one of the second memory die bonding pads 244.

[0176] At least some components of the peripheral circuit 730 in the support die 700 may be shared by the first memory die 900A and the second memory die 900B. The bonding of multiple memory dies (900A, 900B) to the support die 700 may provide efficient utilization of resources in the support die 700 and provide enhanced performance for a bonded memory chip including the support die 700, the first memory die 900A and the second memory die 900B. By providing memory dies on both sides of the support die, a reduction in the device area of ​​the support die may be avoided. The area of ​​the support die may be comparable to the area of ​​the first memory die or the second memory die.

[0177] Although specific preferred embodiments have been mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the claims. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the claims may be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A joint assembly comprising: a support die including peripheral circuitry, a front support die bond pad electrically connected to a first subset of the peripheral circuitry, and a backside bond structure electrically connected to a second subset of the peripheral circuitry; a first memory die comprising a first three-dimensional array of memory elements and a first memory die bond pad bonded to the front support die bond pad; and a second memory die comprising a second three-dimensional array of memory elements and second memory die bond pads bonded to the backside bonding structure; wherein the first memory die bond pad is bonded to the front support die bond pad by metal-to-metal bonding; and The second memory die bond pad is bonded to the backside bonding structure by metal-to-metal bonding. 2 . The bonded assembly of claim 1 , wherein a conductive path extends through the support die between one of the front support die bond pads and one of the backside bond structures.

3. The bonded assembly of claim 2, wherein the conductive path is connected to a node of one of the peripheral circuits in the support die.

4. The joined assembly of claim 1 , wherein the intersection of the first subset of the peripheral circuits and the second subset of the peripheral circuits comprises a third subset of the peripheral circuits electrically connected to an electrical node within the first memory die and an electrical node within the second memory die.

5. The bonded assembly of claim 1 , wherein the peripheral circuit comprises a sense amplifier and a first switchable electrical connection circuit, wherein the first switchable electrical connection circuit is configured to connect the sense amplifier to a set of nodes selected from: a set of first bit lines positioned within said first memory die; and A set of second bit lines is positioned within the second memory die.

6. The bonded assembly of claim 5, wherein the peripheral circuit comprises a word line driver and a second switchable electrical connection circuit, wherein the second switchable electrical connection circuit is configured to connect the word line driver to a set of nodes selected from: a first set of word lines positioned within the first memory die; and A set of second word lines is positioned within the second memory die.

7. The bonding assembly of claim 1, wherein the peripheral circuit comprises: a first bit line driver connected to a first bit line within the first memory die through a first subset of the front support die bond pads and a first subset of the first memory die bond pads; a second bit line driver connected to a second bit line within the second memory die through a first subset of the backside bonding structures and a first subset of the second memory die bond pads; a first word line driver connected to a first word line within the first memory die through a second subset of the front support die bond pads and a second subset of the first memory die bond pads; and A second word line driver is connected to a second word line within the second memory die through a second subset of the backside bonding structures and a second subset of the second memory die bond pads.

8. The joint assembly of claim 1, wherein: The peripheral circuit includes a source power circuit configured to drive a first source line in the first memory die and a second source line in the second memory die; and The support die includes a source power distribution network including a subset of metal interconnect structures and connected to the source power circuit, a subset of the front support die bond pads, and a subset of the backside bond structures.

9. The engagement assembly of claim 1, further comprising: an external bonding pad positioned on the support die; and A solder structure is positioned on the external bond pad.

10. The engagement assembly of claim 1, further comprising: an external bonding pad positioned on at least one of the first memory die and the second memory die; and A solder structure is positioned on the external bond pad.

11. The bonding assembly of claim 1 , wherein one of the backside bonding structures comprises a through substrate via structure extending through a semiconductor substrate supporting the die, being laterally electrically insulated from the semiconductor substrate by a tubular insulating spacer, and contacting one of the second memory die bonding pads.

12. The joint assembly of claim 1, wherein one of the back-side joint structures comprises: a through substrate via structure extending through the semiconductor substrate supporting the die and laterally electrically insulated from the semiconductor substrate by tubular insulating spacers; and A backside support die bond pad is in contact with the through substrate via structure and is bonded to one of the second memory die bond pads.

13. The bonded assembly of claim 1 , wherein each of the first memory die and the second memory die comprises: an alternating stack of insulating layers and conductive layers forming word lines, the alternating stack having a stepped surface wherein a subset of the conductive layers have a lateral extent that increases with distance from the support die; a memory stack structure extending vertically through the alternating stack and comprising respective vertical semiconductor channels and a respective set of vertically stacked memory elements positioned at the level of the conductive layer; and A word line contact via structure contacts a corresponding one of the word lines and extends from the corresponding one of the word lines toward the support die.

14. A joint assembly comprising: a support die including peripheral circuitry, a front support die bond pad electrically connected to a first subset of the peripheral circuitry, and a backside bond structure electrically connected to a second subset of the peripheral circuitry; a first memory die comprising a first three-dimensional array of memory elements and a first memory die bond pad bonded to the front support die bond pad; and a second memory die comprising a second three-dimensional array of memory elements and second memory die bond pads bonded to the backside bonding structure; The peripheral circuit comprises: a first bit line driver connected to a first bit line within the first memory die through a first subset of the front support die bond pads and a first subset of the first memory die bond pads; a second bit line driver connected to a second bit line within the second memory die through a first subset of the backside bonding structures and a first subset of the second memory die bond pads; a first word line driver connected to a first word line within the first memory die through a second subset of the front support die bond pads and a second subset of the first memory die bond pads; and A second word line driver is connected to a second word line within the second memory die through a second subset of the backside bonding structures and a second subset of the second memory die bond pads.

15. A joint assembly comprising: a support die including peripheral circuitry, a front support die bond pad electrically connected to a first subset of the peripheral circuitry, and a backside bond structure electrically connected to a second subset of the peripheral circuitry; a first memory die comprising a first three-dimensional array of memory elements and a first memory die bond pad bonded to the front support die bond pad; and a second memory die comprising a second three-dimensional array of memory elements and second memory die bond pads bonded to the backside bonding structure; in The peripheral circuit includes a source power circuit configured to drive a first source line in the first memory die and a second source line in the second memory die; and The support die includes a source power distribution network including a subset of metal interconnect structures and connected to the source power circuit, a subset of the front support die bond pads, and a subset of the backside bond structures.

16. A method for forming a joint assembly, the method comprising: providing a support die including a complementary metal oxide semiconductor (CMOS) device and a front support die bond pad electrically connected to a first subset of peripheral circuits; bonding a first memory die including a first three-dimensional array of memory elements to the support die, wherein a first memory die bond pad of the first memory die is bonded to the front support die bond pad; forming a backside bonding structure electrically connected to a second subset of the peripheral circuits through the semiconductor substrate of the support die; as well as A second memory die including a second three dimensional array of memory elements is bonded to the support die, wherein a second memory die bond pad of the second memory die is bonded to the backside bonding structure.

17. The method of claim 16, wherein the intersection of the first subset of the peripheral circuits and the second subset of the peripheral circuits comprises a third subset of the peripheral circuits, the third subset of the peripheral circuits being electrically connected to an electrical node within the first memory die and an electrical node within the second memory die.

18. The method according to claim 16, further comprising: forming external bonding pads positioned on the support die; as well as A solder structure is formed on the external bond pad.

19. The method according to claim 16, further comprising: forming external bond pads positioned on at least one of the first memory die and the second memory die; as well as A solder structure is formed on the external bond pad.

20. The method of claim 16, wherein: One of the backside bonding structures comprises a through substrate via structure extending through the semiconductor substrate supporting the die and laterally electrically insulated from the semiconductor substrate by a tubular insulating spacer; and The method includes bonding one of the second memory die bond pads to the through substrate via structure.

21. The method of claim 16, wherein: One of the backside bonding structures comprises a through substrate via structure extending through the semiconductor substrate of the support die and laterally electrically insulated from the semiconductor substrate by a tubular insulating spacer, and a backside support die bonding pad in contact with the through substrate via structure; and The method includes bonding the backside support die bond pad to one of the second memory die bond pads.

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