Bonded assembly including a memory die bonded to an integrated peripheral and system die and method of making the same

Abstract

A bonding assembly includes a memory die bonded to a support die. The memory die includes at least one three-dimensional memory element array, a memory die dielectric material layer, and a memory die bonding pad. The support die includes: at least one peripheral circuit, the at least one peripheral circuit includes a complementary metal oxide semiconductor (CMOS) device and is configured to generate control signals for the at least one three-dimensional memory element array and receive sensing signals therefrom; and a functional module, the functional module is configured to provide functions unrelated to the operation of the at least one three-dimensional memory element array. The functional module may include an error correction code (ECC) module, a memory module configured to interact with an external processor module located outside the memory die, a microprocessor unit module, a wireless communication module, and / or a system-level controller module.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent application serial number 16 / 269,301 filed on February 6, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular, to integrated peripheral and system dies bonded to memory dies and methods of manufacturing the same. Background Art

[0004] A three-dimensional semiconductor device including a three-dimensional vertical NAND string with one bit per cell is disclosed in an article by T. Endoh et al. entitled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one embodiment of the present disclosure, a bonding assembly is provided, the bonding assembly comprising: a first memory die, the first memory die comprising: at least one first three-dimensional memory element array; a first memory die metal interconnect structure, the first memory die metal interconnect structure formed in the first memory die dielectric material layer; and a first memory die bonding pad, the first memory die bonding pad is located on the first memory die dielectric material layer or formed in the first memory die dielectric material layer and is electrically connected to a corresponding node of the at least one first three-dimensional memory element array; and a first support die, the first support die comprising: at least one first peripheral circuit, the at least A first peripheral circuit includes a complementary metal oxide semiconductor (CMOS) device and is configured to generate control signals for the at least one first three-dimensional memory element array and receive sensing signals from the at least one first three-dimensional memory element array; and a first functional module, the first functional module is configured to provide functions unrelated to the operation of the at least one first three-dimensional memory element array; wherein the first support die includes a first support die bonding pad, the first support die bonding pad is located on the first support die dielectric material layer or formed in the first support die dielectric material layer, is electrically connected to the corresponding node of the at least one first peripheral circuit, and is bonded to the first memory die bonding pad.

[0006] According to another embodiment of the present disclosure, a method for forming a bonding assembly is provided, the method comprising: providing a first memory die, the first memory die comprising: at least one first three-dimensional memory element array; a first memory die metal interconnect structure, the first memory die metal interconnect structure formed in the first memory die dielectric material layer; and a first memory die bonding pad, the first memory die bonding pad being located on the first memory die dielectric material layer or formed in the first memory die dielectric material layer and electrically connected to a corresponding node of the at least one first three-dimensional memory element array; providing a first support die, the first support die comprising: at least one first peripheral circuit, the at least one first The peripheral circuit includes a complementary metal oxide semiconductor (CMOS) device and is configured to generate control signals for the at least one first three-dimensional memory element array and receive sensing signals from the at least one first three-dimensional memory element array; and a first functional module, which is configured to provide functions unrelated to the operation of the at least one first three-dimensional memory element array; wherein the first support die includes a first support die bonding pad, which is located on the first support die dielectric material layer or formed in the first support die dielectric material layer and is electrically connected to the corresponding node of the at least one first peripheral circuit; and the first support die bonding pad is bonded to the first memory die bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a vertical cross-sectional view of an exemplary structure after forming a source-side dielectric material layer and a doped semiconductor layer on a semiconductor substrate according to an embodiment of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a first layer of alternate stacking of first insulating layers and first spacer material layers according to an embodiment of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of an exemplary structure after patterning a first level staircase region, a first stepped dielectric material portion, and an interlayer dielectric layer according to an embodiment of the present disclosure.

[0010] Figure 4A is a vertical cross-sectional view of an exemplary structure after forming a first layer memory opening and a first layer support opening according to an embodiment of the present disclosure.

[0011] Figure 4B yes Figure 4A Horizontal cross-sectional view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Figure 4A A plane of a vertical section.

[0012] Figure 5is a vertical cross-sectional view of an exemplary structure after forming various sacrificial fill structures according to an embodiment of the present disclosure.

[0013] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming a second layer alternating stack of second insulating layers and second spacer material layers, a second stepped surface, and a second stepped dielectric material portion according to an embodiment of the present disclosure.

[0014] Fig. 7A is a vertical cross-sectional view of an exemplary structure after forming a second layer memory opening and a second layer support opening according to an embodiment of the present disclosure.

[0015] Figure 7B is along Fig. 7A The horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Fig. 7A A plane of a vertical section.

[0016] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming an inter-layer memory opening and an inter-layer support opening according to an embodiment of the present disclosure.

[0017] 9A to 9D Sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure according to an embodiment of the present disclosure are shown.

[0018] Fig.10 is a vertical cross-sectional view of an exemplary structure after forming a memory opening filling structure and a support pillar structure according to an embodiment of the present disclosure.

[0019] Fig.11A is a vertical cross-sectional view of an exemplary structure after forming a post cavity according to an embodiment of the present disclosure.

[0020] Fig. 11B is along Fig.11A The horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Fig.11A A plane of a vertical section.

[0021] Fig.12 is a vertical cross-sectional view of an exemplary structure after forming a dielectric pillar structure according to an embodiment of the present disclosure.

[0022] Fig.13A is a vertical cross-sectional view of an exemplary structure after forming a first contact level dielectric layer and backside trenches according to an embodiment of the present disclosure.

[0023] Fig. 13B is along Fig.13AThe horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Fig.13A A plane of a vertical section.

[0024] Fig.14 is a vertical cross-sectional view of an exemplary structure after forming a backside recess according to an embodiment of the present disclosure.

[0025] Fig.15A is a vertical cross-sectional view of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0026] Fig. 15B is along Fig.15A The horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Fig.15A A plane of a vertical section.

[0027] Fig.16A is a vertical cross-sectional view of an exemplary structure after forming a backside trench fill structure in the backside trench according to an embodiment of the present disclosure.

[0028] Fig. 16B is along Fig.16A The horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Fig.16A A plane of a vertical section.

[0029] Fig. 16C is along Fig. 16B A vertical cross-sectional view of an exemplary structure taken along a vertical plane CC'.

[0030] Fig.17A is a vertical cross-sectional view of an exemplary structure after forming a second contact level dielectric layer and various contact via structures according to an embodiment of the present disclosure.

[0031] Fig. 17B is along Fig.17A A horizontal cross-sectional view of an exemplary structure taken along a vertical plane BB'. The hinged vertical plane AA' corresponds to Fig.17A A plane of a vertical section.

[0032] Fig.18 is a vertical cross-sectional view of an exemplary structure after forming a first line-level metal interconnect structure according to an embodiment of the present disclosure.

[0033] Fig.19A is a vertical cross-sectional view of an exemplary structure after forming a memory die dielectric material layer and a memory die bond pad according to an embodiment of the present disclosure.

[0034] Fig.19BYes Fig.19A Layout of a memory die of an exemplary structure.

[0035] Fig. 20A is a vertical cross-sectional view of a support die according to an embodiment of the present disclosure.

[0036] Fig. 20B yes Fig. 20A The layout of the supporting die.

[0037] Fig.21 According to the embodiment of the present disclosure, by bonding Fig.19A and Fig.19B Memory die and Fig. 20A and Fig. 20B A vertical cross-sectional view of a first exemplary bonding assembly formed of a support die.

[0038] Fig. 22 is a vertical cross-sectional view of a first exemplary bonded assembly after forming a through substrate via structure and a backside bond pad according to an embodiment of the present disclosure.

[0039] Fig.23 is a vertical cross-sectional view of a first exemplary bonded assembly after removal of a substrate of a memory die according to an embodiment of the present disclosure.

[0040] Fig.24 is a vertical cross-sectional view of a first exemplary bonded assembly after attaching a second support die and a second memory die according to an embodiment of the present disclosure.

[0041] Fig.25 is a vertical cross-sectional view of a first exemplary bonded assembly after attaching an additional support die and an additional memory die according to an embodiment of the present disclosure.

[0042] Fig.26 is a vertical cross-sectional view of a first exemplary bonded assembly including a system function die according to an embodiment of the present disclosure.

[0043] Fig. 27 is a vertical cross-sectional view of a second exemplary engagement assembly according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0044] As described above, embodiments of the present disclosure relate to integrated memory and system chips including three-dimensional memory arrays and functional device elements and methods of manufacturing the same, various aspects of which are described in detail herein.

[0045] The accompanying drawings are not drawn to scale. Multiple instances of elements can be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of elements. Serial numbers such as "first", "second" and "third" are only used to identify similar elements, and different serial numbers can be used throughout the specification and claims of this disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. As used herein, a first element "on" a second element can be located on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, a "prototype" structure or "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0046] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0047] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0048] As used herein, a "memory level" or "memory array level" refers to a level corresponding to a common area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) and a second horizontal plane, wherein the first horizontal plane includes the topmost surface of the array of memory elements and the second horizontal plane includes the bottommost surface of the array of memory elements. As used herein, a "through-stacked" element refers to an element that extends vertically through a memory level.

[0049] As used herein, "semiconductor material" refers to a semiconductor material having a -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m, and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 5 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state) (i.e., having a conductivity greater than 1.0×10 5 S / m) of a semiconductor material. A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 5 S / m in the range of 1000 s / m. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Therefore, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. Doped semiconductor materials can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that includes at least one metal element. All conductivity measurements are performed under standard conditions.

[0050] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory levels before bonding, but since the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. The substrate may include integrated circuits manufactured thereon, such as driver circuits for memory devices.

[0051] Various three-dimensional memory devices of the present disclosure include single three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein. Single three-dimensional NAND strings are positioned in a single three-dimensional NAND string array located above a substrate. At least one memory cell in a first device level of the three-dimensional array of NAND strings is located above another memory cell in a second device level of the three-dimensional array of NAND strings.

[0052] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded therein, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of planes therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0053] See also Figure 1, shows an exemplary structure including an in-process memory die. As used herein, a memory die is a semiconductor die that includes an array of memory elements. Thus, an in-process memory die is a structure that is subsequently modified to form a memory die.

[0054] The exemplary structure includes a carrier substrate 908 including a carrier substrate layer 909. The carrier substrate 908 may include a commercially available semiconductor wafer, such as a single crystal silicon wafer. A source side dielectric material layer 910 is formed over the carrier substrate layer 909. The source side dielectric material layer 910 includes a dielectric material, such as silicon oxide. The maximum thickness of the source side dielectric material layer 910 may be in the range of 200 nm to 3,000 nm, although smaller and larger thicknesses may also be used.

[0055] An optional metal plate layer 6 and a source semiconductor layer 10 may be formed in the source side dielectric material layer 910. The optional metal plate layer 6 (if present) provides a highly conductive conductive path for current flowing into, along and / or out of the source semiconductor layer 10. The optional metal plate layer 6 includes a conductive material such as a metal or a heavily doped semiconductor material. The optional metal plate layer 6 may, for example, include a tungsten layer having a thickness in the range of 3nm to 100nm, but smaller and larger thicknesses may also be used. A metal nitride layer (not shown) may be provided on top of the metal plate layer 6 as a diffusion barrier. The metal plate layer 6 may be used as part of a source line in a completed die. The thickness of the metal plate layer 6 may be in the range of 20nm to 200nm, but smaller and larger thicknesses may also be used.

[0056] The source semiconductor layer 10 is a doped semiconductor layer having a doping of a conductivity type opposite to the conductivity type of the vertical semiconductor channel to be formed later. For example, if the vertical semiconductor channel to be formed later has a doping of a first conductivity type, the source semiconductor layer 10 may have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is a p-type, the second conductivity type is an n-type, and vice versa. The atomic concentration of the second conductivity type dopant in the source semiconductor layer 10 may be 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 The thickness of the source semiconductor layer 10 may be in the range of 100 nm to 600 nm, but smaller and larger atomic concentrations may also be used.

[0057] The source semiconductor layer 10 and the metal plate layer 6 may be patterned so that the source semiconductor layer 10 and the metal plate layer 6 extend over at least a portion of the memory array region 100 (where a memory stack structure will be formed later) and over the staircase region 300 (where a stepped surface of a conductive layer embodying a word line will be formed later). A through-hole interconnection region 400 may be provided around the memory array region 100 and the staircase region 300. In one embodiment, the top surface of the source semiconductor layer 10 may be coplanar with the top surface of the source-side dielectric material layer 910.

[0058] See also Figure 2 , an alternating stack of first material layers and second material layers may subsequently be formed. Each first material layer may include a first material, and each second material layer may include a second material different from the first material. Where at least another alternating stack of material layers is subsequently formed above the alternating stack of the first material layers and the second material layers, the alternating stack is referred to herein as a first layer alternating stack. A level of the first layer alternating stack is referred to herein as a first layer level, and a level of the alternating stack to be subsequently formed immediately above the first layer level is referred to herein as a second layer level, and so on.

[0059] The first layer of alternating stacking may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by other layers. Although the present disclosure is described using an embodiment in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby avoiding the need to perform a replacement process) are explicitly considered herein.

[0060] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. Alternating multiple first insulating layers 132 and first sacrificial material layers 142 may be formed over the source semiconductor layer 10. As used herein, "sacrificial material" refers to a material that is removed during subsequent processing steps.

[0061] As used herein, the alternating stacking of the first element and the second element refers to a structure in which an instance of the first element and an instance of the second element are alternating. Each instance of the first element that is not an end element of the alternating plurality of elements adjoins two instances of the second element on both sides, and each instance of the second element that is not an end element of the alternating plurality of elements adjoins two instances of the first element on both ends. The first element may have the same thickness therein, or may have different thicknesses. The second element may have the same thickness therein, or may have different thicknesses. The alternating plurality of first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, an instance of the first element and an instance of the second element may form a unit that is periodically repeated within the alternating plurality of elements.

[0062] The first layer alternating stack (132, 142) may include a first insulating layer 132 composed of a first material, and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0063] The second material of the first sacrificial material layer 142 may be a sacrificial material that is selectively removable with respect to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0064] The first sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer including silicon nitride.

[0065] In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0066] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 pair can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each first sacrificial material layer 142 in the first layer alternating stack (132, 142) can have a uniform thickness that is substantially constant within each corresponding first sacrificial material layer 142.

[0067] A first insulating capping layer 170 may then be formed over the first alternating stack (132, 142). The first insulating capping layer 170 may include a dielectric material, which may be any dielectric material that may be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 includes the same dielectric material as the first insulating layer 132. The thickness of the first insulating capping layer 170 may be in the range of 20 nm to 300 nm, although lesser and greater thicknesses may also be used.

[0068] See also Figure 3 , the first insulating cap layer 170 and the first layer may be alternately stacked (132, 142) and patterned to form a first stepped surface in the staircase region 300. The staircase region 300 may include a corresponding first stepped region and a second stepped region, in which a first stepped surface is formed, and in the second stepped region, an additional stepped surface is subsequently formed in a second layer structure (which will subsequently be formed above the first layer structure) and / or an additional layer structure. The first stepped surface may be formed, for example, by forming a mask layer having an opening therein, etching a cavity within the level of the first insulating cap layer 170 and iteratively extending the etching region, and vertically recessing the cavity by etching each first insulating layer 132 and first sacrificial material layer 142 pair directly below the bottom surface of the etching cavity positioned in the etching region. In one embodiment, the top surface of the first sacrificial material layer 142 may be physically exposed at the first stepped surface. The cavity covering the first stepped surface is referred to herein as a first stepped cavity.

[0069] A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the dielectric fill material filling the area overlying the first stepped surface constitutes a first stepped dielectric material portion 165. As used herein, a "stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. The first layer of alternating stacks (132, 142) and the first backward stepped dielectric material portion 165 together constitute a first layer structure, which is a process structure that is subsequently modified.

[0070] An interlayer dielectric layer 180 may be optionally deposited over the first layer structure (132, 142, 170, 165). The interlayer dielectric layer 180 comprises a dielectric material, such as silicon oxide. In one embodiment, the interlayer dielectric layer 180 may comprise a doped silicate glass having a greater etching rate than the material of the first insulating layer 132 (which may comprise undoped silicate glass). For example, the interlayer dielectric layer 180 may comprise phosphosilicate glass. The thickness of the interlayer dielectric layer 180 may be in the range of 30 nm to 300 nm, but smaller and larger thicknesses may also be used.

[0071] See also Figure 4A and Figure 4B , various first layer openings (149, 129) can be formed to pass through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the source semiconductor layer 10. A photoresist layer (not shown) can be applied over the interlayer dielectric layer 180 and can be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer can be transferred through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the source semiconductor layer 10 by a first anisotropic etching process to form various first layer openings (149, 129) simultaneously (i.e., during the first isotropic etching process). The various first layer openings (149, 129) may include a first layer memory opening 149 and a first layer support opening 129. In Figure 4B The location of the step S in the first alternating stack (132, 142) is shown by dashed lines.

[0072] The first layer memory openings 149 may be openings formed in the memory array region 100 through each layer within the first alternating stack (132, 142) and may subsequently be used to form a memory stack structure therein. The first layer memory openings 149 may be formed as clusters of first layer memory openings 149 that may be laterally spaced apart along the second horizontal direction hd2. Each cluster of first layer memory openings 149 may be formed as a two-dimensional array of first layer memory openings 149.

[0073] The first layer support openings 129 are openings formed in the stair region 300. A subset of the first layer support openings 129 formed through the first stepped dielectric material portion 165 may be formed through corresponding horizontal surfaces of the first stepped surface.

[0074] In one embodiment, the first anisotropic etching process may include an initial step in which the material of the first layer alternating stack (132, 142) may be etched simultaneously with the material of the first stepped dielectric material portion 165. The chemistry of the initial etching step may be alternating to optimize the etching of the first material and the second material in the first layer alternating stack (132, 142) while providing an average etching rate comparable to the material of the first stepped dielectric material portion 165. The first anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various first layer openings (149, 129) may be substantially vertical, or may be tapered. In one embodiment, the end portion of the anisotropic etching process may include an over-etching step that etches into the upper portion of the source semiconductor layer 10. The photoresist layer may then be removed, for example, by ashing.

[0075] Optionally, the first layer memory opening 149 and the first layer support opening 129 at the level of the interlayer dielectric layer 180 can be laterally expanded by isotropic etching. In this case, the interlayer dielectric layer 180 can include a dielectric material (such as borosilicate glass) having a greater etching rate in dilute hydrofluoric acid than the first insulating layer 132 (which may include undoped silicate glass). Isotropic etching (such as wet etching using HF) can be used to expand the lateral size of the first layer memory opening 149 at the level of the interlayer dielectric layer 180. The portion of the first layer memory opening 149 located at the level of the interlayer dielectric layer 180 can be optionally widened to provide a larger landing pad for the second layer memory opening that will be subsequently formed through the second layer alternating stack (subsequently formed before forming the second layer memory opening).

[0076] See also Figure 5, a sacrificial first layer opening filling portion (148, 128) may be formed in various first layer openings (149, 129). For example, a sacrificial first layer filling material may be simultaneously deposited in each of the first layer openings (149, 129). The sacrificial first layer filling material includes a material that can be selectively removed from the material of the first insulating layer 132 and the first sacrificial material layer 142.

[0077] In one embodiment, the sacrificial first layer fill material may include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0078] In another embodiment, the sacrificial first layer fill material may include a silicon oxide material having a higher etch rate than the materials of the first insulating layer 132, the first insulating capping layer 170, and the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than the etch rate of dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densifying in an annealing process) in 100:1 diluted hydrofluoric acid. In this case, a thin etch stop liner (such as a silicon nitride layer with a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by a non-conformal deposition or a conformal deposition method.

[0079] In yet another embodiment, the sacrificial first layer fill material may include amorphous silicon or a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently selectively removed for the material of the first alternating stack (132, 142).

[0080] Portions of the deposited sacrificial material may be removed from above the topmost layer of the first layer alternating stack (132, 142), such as from above the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may be recessed to the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 may be used as an etch stop layer or a planarization stop layer.

[0081] The remaining portions of the sacrificial first layer filling material include sacrificial first layer opening filling portions (148, 128). Specifically, each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial first layer memory opening filling portion 148. Each remaining portion of the sacrificial material in the first layer support opening 129 constitutes a sacrificial first layer support opening filling portion 128. The various sacrificial first layer opening filling portions (148, 128) can be formed simultaneously, i.e., formed during the same set of processes, including a deposition process that deposits the sacrificial first layer filling material and a planarization process that removes the first layer deposition process from above the first alternating stack (132, 142), such as from above the top surface of the interlayer dielectric layer 180. The top surface of the sacrificial first layer opening filling portion (148, 128) can be coplanar with the top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer opening filling portions (148, 128) may or may not include a cavity therein.

[0082] See also Figure 6 , a second layer structure may be formed above the first layer structure (132, 142, 170, 148). The second layer structure may include additional alternating stacks of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack (232, 242) of material layers may then be formed on the top surface of the first alternating stack (132, 142). The second alternating stack (232, 242) may include alternating multiple third material layers and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0083] In one embodiment, the third material layer may be a second insulating layer 232, and the fourth material layer may be a second spacer material layer providing a vertical spacing between each vertically adjacent pair of second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be a second insulating layer 232 and a second sacrificial material layer 242, respectively. The third material of the second insulating layer 232 may be at least one insulating material. The fourth material of the second sacrificial material layer 242 may be a sacrificial material that may be selectively removed for the third material of the second insulating layer 232. The second sacrificial material layer 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 may then be replaced with a conductive electrode, which may be used as, for example, a control gate electrode of a vertical NAND device.

[0084] In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second alternating stack (232, 242) may include alternating multiple second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0085] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that may be used for the second insulating layer 232 may be any material that may be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that may be selectively removed with respect to the third material of the second insulating layer 232. The sacrificial material that may be used for the second sacrificial material layer 242 may be any material that may be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

[0086] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 can be in the range of 20 nm to 50 nm, but smaller and larger thicknesses can be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and the second sacrificial material layer 242 pair can be in the range of 2 to 1,024, and typically in the range of 8 to 256, but more repetitions can also be used. In one embodiment, each second sacrificial material layer 242 in the second alternating stack (232, 242) can have a uniform thickness that is substantially constant within each respective second sacrificial material layer 242.

[0087] The second stepped surface in the second stepped region can be formed in the staircase region 300 using the same set of processing steps as the processing steps used to form the first stepped surface in the first stepped region, wherein the pattern of at least one mask layer is appropriately adjusted. A second stepped dielectric material portion 265 can be formed over the second stepped surface in the staircase region 300.

[0088] A second insulating capping layer 270 may then be formed over the second alternating stack (232, 242). The second insulating capping layer 270 comprises a dielectric material that is different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating capping layer 270 may include silicon oxide. In one embodiment, the first sacrificial material layer and the second sacrificial material layer (142, 242) may include silicon nitride.

[0089] Generally speaking, at least one alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed above the source semiconductor layer 10, and at least one stepped dielectric material portion (165, 265) can be formed above the staircase area on at least one alternating stack (132, 142, 232, 242).

[0090] Optionally, a drain select level isolation structure 72 may be formed through a subset of the layers in the upper portion of the second layer alternating stack (232, 242). The second sacrificial material layer 242 cut by the drain select level isolation structure 72 corresponds to the level at which the drain select level conductive layer is subsequently formed. The drain select level isolation structure 72 includes a dielectric material, such as silicon oxide. The drain select level isolation structure 72 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The combination of the second alternating stack (232, 242), the second stepped dielectric material portion 265, the second insulating cap layer 270, and the optional drain select level isolation structure 72 together constitute the second layer structure (232, 242, 265, 270, 72).

[0091] See also Fig. 7A and Figure 7B , various second layer openings (249, 229) can be formed through the second layer structure (232, 242, 265, 270, 72). A photoresist layer (not shown) can be applied over the second insulating cap layer 270 and can be photolithographically patterned to form various openings therethrough. The pattern of the openings can be the same as the pattern of the various first layer openings (149, 129), which is the same as the sacrificial first layer opening filling portion (148, 128). Therefore, the photoresist layer can be patterned using a photolithographic mask used to pattern the first layer openings (149, 129).

[0092] The pattern of the openings in the photoresist layer can be transferred through the second layer structure (232, 242, 265, 270, 72) by a second anisotropic etching process to simultaneously (i.e., during the second anisotropic etching process) form various second layer openings (249, 229). The various second layer openings (249, 229) can include second layer memory openings 249 and second layer support openings 229.

[0093] The second layer memory opening 249 may be formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening filling portions 148. The second layer support opening 229 may be formed directly on the top surface of a corresponding one of the sacrificial first layer support opening filling portions 128. In addition, each second layer support opening 229 may be formed to pass through a horizontal surface within the second stepped surfaces, which include the inter-facial surfaces between the second alternating stacks (232, 242) and the second stepped dielectric material portion 265. Figure 7B The positions of the steps S in the first layer of alternating stacking (132, 142) and the second layer of alternating stacking (232, 242) are shown by dotted lines.

[0094] The second anisotropic etching process may include an etching step in which the material of the second layer alternating stack (232, 242) is etched simultaneously with the material of the second stepped dielectric material portion 265. The chemistry of the etching steps may be alternating to optimize the etching of the material in the second layer alternating stack (232, 242) while providing an average etching rate comparable to the material of the second stepped dielectric material portion 265. The second anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various second layer openings (249, 229) may be substantially vertical, or may be tapered. The bottom perimeter of each second layer opening (249, 229) may be laterally offset, and / or may be completely positioned within the perimeter of the top surface of the underlying sacrificial first layer opening fill portion (148, 128). The photoresist layer may then be removed, for example, by ashing.

[0095] See also Figure 8 , the sacrificial first layer filling material of the sacrificial first layer opening filling portion (148, 128) can be removed using an etching process that selectively etches the sacrificial first layer filling material with respect to the materials of the first and second insulating layers (132, 232), the first and second sacrificial material layers (142, 242), the first and second insulating capping layers (170, 270), and the interlayer dielectric layer 180. A memory opening 49 (also referred to as an interlayer memory opening 49) is formed in each combination of a second layer memory opening 249 and a volume from which the sacrificial first layer memory opening filling portion 148 is removed. A support opening 19 (also referred to as an interlayer support opening 19) is formed in each combination of a second layer support opening 229 and a volume from which the sacrificial first layer support opening filling portion 128 is removed.

[0096] 9A to 9D Sequential cross-sectional views of memory opening 49 during formation of a memory opening fill structure are provided. The same structural changes occur in each of memory opening 49 and support opening 19.

[0097] See also Fig.9A , a base channel portion 11 can be formed at the bottom of each memory opening 49 and at the bottom of each support opening 19 by a selective semiconductor material deposition process. Doped semiconductor material having a first conductivity type of doping can be selectively grown from the physically exposed surface of the source semiconductor layer 10, while the growth of the doped semiconductor material from the dielectric surface is suppressed during the selective semiconductor material deposition process. Semiconductor precursor gas, dopant gas including dopant atoms of the first conductivity type, and etchant can flow simultaneously or alternately into a processing chamber including the exemplary structure. The periphery of the top surface of each base channel portion 11 can contact the sidewall of the first insulating layer 132, which covers and contacts the bottommost first sacrificial material layer 142. The atomic concentration of the first conductivity type dopant in the base channel portion 11 can be in the range of 1.0×1014 / cm3 to 1.0×1018 / cm3, but smaller and larger dopant atomic concentrations can also be used. A pn ​​junction can be formed at each interface between the source semiconductor layer 10 and the base channel portion 11.

[0098] See also Fig. 9B , a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1nm to 20nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may be used to block the stored charge from leaking to the control gate electrode dielectric material portion. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. Alternatively or additionally, the blocking dielectric layer 52 may include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0099] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coincident sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layer (142, 242) can be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 can be in the range of 2nm to 20nm, although smaller and larger thicknesses can also be used.

[0100] The tunneling dielectric layer 56 includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2nm to 20nm, but smaller and larger thicknesses may also be used. The stack of the blocking dielectric layer 52, the charge storage layer 54, and the tunneling dielectric layer 56 constitutes a memory film 50 that stores a memory bit.

[0101] The semiconductor channel material layer 60L includes a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may have uniform doping. In one embodiment, the semiconductor channel material layer 60L has a p-type doping, wherein the p-type dopant (such as boron atoms) is present at 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 For example, 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 In one embodiment, the semiconductor channel material layer 60L includes boron-doped amorphous silicon or boron-doped polysilicon and / or consists essentially of boron-doped amorphous silicon or boron-doped polysilicon. In another embodiment, the semiconductor channel material layer 60L has an n-type doping, wherein the n-type dopant (such as phosphorus atoms or arsenic atoms) is present at an atomic concentration of 1.0×10 15 / cm 3 to 1.0×10 19 / cm 3 For example, 1.0×10 16 / cm 3 to 1.0×10 18 / cm 3 The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2 nm to 10 nm, but smaller and larger thicknesses may also be used. The cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0102] See also Fig. 9C , in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organic silicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)), or deposited by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the second insulating cap layer 270 can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0103] See also Fig.9D, a doped semiconductor material may be deposited in a cavity overlying the dielectric core 62. The doped semiconductor material has a doping of a conductivity type opposite to the doping conductivity type of the semiconductor channel material layer 60L. Thus, the doped semiconductor material has an n-type doping. Portions of the deposited doped semiconductor material, the semiconductor channel material layer 60L, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 overlying the horizontal plane (which includes the top surface of the second insulating cap layer 270) may be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0104] Each remaining portion of the n-doped semiconductor material constitutes a drain region 63. The dopant concentration of the drain region 63 may be in the range of 5.0×1019 / cm3 to 2.0×1021 / cm3, although lesser and greater dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.

[0105] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each group of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the backside recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time of more than 24 hours.

[0106] Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunnel dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening filling structure 58. The source semiconductor layer 10, the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265, 72), the interlayer dielectric layer 180, and the memory opening filling structure 58 together constitute a memory hierarchical component.

[0107] See also Fig.10, shows an exemplary structure after forming the memory opening filling structure 58. The support pillar structures 20 are formed in the support openings 19 at the same time as the memory opening filling structure 58 is formed. Each support pillar structure 20 may have the same set of components as the memory opening filling structure 58.

[0108] See also Fig.11A and Fig. 11B A first contact level dielectric layer 280 may be formed over the second layer structure (232, 242, 270, 265, 72). The first contact level dielectric layer 280 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the first contact level dielectric layer 280 may include undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be used.

[0109] A photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be photolithographically patterned to form discrete openings in the memory array region 100 in areas where the memory opening fill structures 58 are not present. Anisotropic etching may be performed to form vertical interconnect region cavities 585 having substantially vertical sidewalls extending through the first contact level dielectric layer 280, and the second layer structures (232, 242, 270, 265, 72) and the first layer structures (132, 142, 170, 165) may be formed below the openings in the photoresist layer. The top surface of the source side dielectric material layer 910 may be physically exposed at the bottom of each vertical interconnect region cavity 585. The photoresist layer may be removed, for example, by ashing.

[0110] refer to Fig.12 , a dielectric material such as silicon oxide may be deposited in the vertical interconnect region cavity 585 by a conformal deposition process such as low pressure chemical vapor deposition or a self-planarization deposition process such as spin coating. Excess portions of the deposited dielectric material may be removed from above the top surface of the first contact level dielectric layer 280 by a planarization process. The remaining portion of the dielectric material in the vertical interconnect region cavity 585 constitutes the interconnect region dielectric filling material portion 584.

[0111] refer to Fig.13A and Fig. 13BA photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be photolithographically patterned to form elongated openings that extend along the first horizontal direction hd1 between the clusters of memory opening fill structures 58. Backside trenches 79 may be formed by transferring the pattern in the photoresist layer through the first contact level dielectric layer 280, the second layer structures (232, 242, 270, 265, 72), and the first layer structures (132, 142, 170, 165) and into the process source semiconductor layer 10. Portions of the first contact level dielectric layer 280, the second layer structures (232, 242, 270, 265, 72), the first layer structures (132, 142, 170, 165), and the source semiconductor layer 10 below the openings in the photoresist layer may be removed to form the backside trenches 79. In one embodiment, backside trenches 79 may be formed between clusters of memory stack structures 55. Clusters of memory stack structures 55 may be laterally spaced apart along a second horizontal direction hd2 by backside trenches 79. Although it is desirable that backside trenches 79 be formed with completely straight sidewalls, backside trenches 79 are typically formed with local width variations and non-straight surfaces due to various effects, including local variations in process parameters (such as local variations in gas flow, pressure, electric fields, etc.) and variations in charge density within the exemplary structure due to local layout variations of conductive features within the exemplary structure.

[0112] See also Fig.14 , the sacrificial material layer (142, 242) can be selectively removed with respect to the insulating layer (132, 232), the first and second insulating capping layers (170, 270), the first contact level dielectric layer 280, and the source semiconductor layer 10. For example, an etchant that selectively etches the material of the sacrificial material layer (142, 242) with respect to the material of the insulating layer (132, 232), the first and second insulating capping layers 170, 270, the stepped dielectric material portion (165, 265), and the material of the outermost layer of the memory film 50 can be introduced into the backside trench 79, for example, using an isotropic etching process. For example, the sacrificial material layer (142, 242) can include silicon nitride, and the insulating layer (132, 232), the first and second insulating capping layers (170, 270), the stepped dielectric material portion (165, 265), and the material of the outermost layer of the memory film 50 can include a silicon oxide material.

[0113] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which the etchant is introduced in the vapor phase into the backside trench 79. For example, if the sacrificial material layer (142, 242) includes silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0114] A backside recess (143, 243) may be formed in a volume from which a sacrificial material layer (142, 242) is removed. The backside recess (143, 243) includes a first backside recess 143 that may be formed in a volume from which a first sacrificial material layer 142 is removed and a second backside recess 243 that is formed in a volume from which a second sacrificial material layer 242 is removed. Each of the backside recesses (143, 243) may be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243) may be greater than the height of the corresponding backside recess (143, 243). Multiple backside recesses (143, 243) may be formed in a volume from which material of the sacrificial material layer (142, 242) is removed. Each of the backside recesses (143, 243) can extend substantially parallel to the top surface of the carrier substrate layer 909. The backside recesses (143, 243) can be vertically bounded by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143, 243) can have a uniform height throughout.

[0115] See also Fig.15A and Fig. 15B , an oxidation process may be performed to oxidize the physically exposed portion of the base channel portion 11. A tubular insulating spacer (not explicitly shown) may be formed around each base channel portion 11. A backside blocking dielectric layer (not shown) may be optionally deposited in the backside recess (143, 243) and the backside trench 79 and above the first contact level dielectric layer 280. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the backside blocking dielectric layer may include aluminum oxide. The backside blocking dielectric layer may be formed by a conformal deposition process such as atomic layer deposition or chemical vapor deposition. The thickness of the backside blocking dielectric layer may be in the range of 1 nm to 20 nm, such as 2 nm to 10 nm, but smaller and larger thicknesses may also be used.

[0116] At least one conductive material may be deposited in the plurality of backside recesses (243, 243), on the sidewalls of the backside trenches 79, and above the first contact level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

[0117] In one embodiment, at least one conductive material may include at least one metallic material, i.e., a conductive material including at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the back recess (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive fill material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, at least one conductive material used to fill the back recess (143, 243) may be a combination of a titanium nitride layer and a tungsten fill material.

[0118] A conductive layer (146, 246) may be formed in the backside recess (143, 243) by depositing at least one conductive material. A plurality of first conductive layers 146 may be formed in a plurality of first backside recesses 143, a plurality of second conductive layers 246 may be formed in a plurality of second backside recesses 243, and a continuous metal material layer (not shown) may be formed on the sidewalls of each backside trench 79 and over the first contact-level dielectric layer 280. Each of the first conductive layer 146 and the second conductive layer 246 may include a corresponding conductive metal nitride liner and a corresponding conductive filling material. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) may be replaced with the first conductive layer and the second conductive layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 may be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with the continuous layer of metal material.

[0119] The residual conductive material may be removed from the inside of the backside trench 79. Specifically, the deposited metal material of the continuous metal material layer may be etched back from the sidewalls of each backside trench 79 and from above the first contact level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first backside recess constitutes the first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes the second conductive layer 246. The sidewalls of the first conductive material layer 146 and the second conductive layer may be physically exposed to the corresponding backside trench 79. The backside trench may have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a non-linear width variation along the vertical direction.

[0120] Each conductive layer (146, 246) can be a conductive sheet including openings therein. A first subset of the openings through each conductive layer (146, 246) can be filled with a memory opening filling structure 58. A second subset of the openings through each conductive layer (146, 246) can be filled with a support pillar structure 20. Due to the first stepped surface and the second stepped surface, each conductive layer (146, 246) can have a smaller area than any underlying conductive layer (146, 246). Due to the first stepped surface and the second stepped surface, each conductive layer (146, 246) can have a larger area than any overlying conductive layer (146, 246).

[0121] In some embodiments, a drain select level isolation structure 72 may be provided at the topmost level of the second conductive layer 246. A subset of the second conductive layer 246 positioned at the level of the drain select level isolation structure 72 constitutes a drain select gate electrode. A subset of the conductive layers (146, 246) located below the drain select gate electrode may be used as a combination of a control gate and a word line located at the same level. The control gate electrode within each conductive layer (146, 246) is a control gate electrode for a vertical memory device including the memory stack structure 55.

[0122] Each of the memory stack structures 55 includes a vertical stack of memory elements positioned at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. The memory level assembly is located above the carrier substrate layer 909. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 extending vertically through at least one alternating stack (132, 146, 232, 246).

[0123] See also FIG. 16A to FIG. 16CAs shown, a backside trench filling structure 76 may be formed in each backside trench 79. Each backside trench filling structure 76 may be composed of at least one dielectric filling material such as silicon oxide, silicon nitride and / or a dielectric metal oxide material. Alternatively, the backside trench filling structure 76 may include a laterally insulated source contact via structure, which includes a conductive via structure contacting the source semiconductor layer 10 and a dielectric spacer laterally surrounding the conductive via structure.

[0124] refer to Fig.17A and Fig. 17B A second contact level dielectric layer 282 may be formed over the first contact level dielectric layer 280. The second contact level dielectric layer 282 includes a dielectric material such as silicon oxide and may have a thickness in a range of 100 nm to 600 nm, although lesser and greater thicknesses may also be used.

[0125] A photoresist layer (not shown) may be applied over the second contact level dielectric layer 282 and may be photolithographically patterned to form various contact via openings. For example, an opening for forming a drain contact via structure 88 may be formed in the memory array region 100, and an opening for forming a staircase area contact via structure 86 may be formed in the staircase region 300. An anisotropic etching process is performed to transfer the pattern in the photoresist layer through the second contact level dielectric layer and the first contact level dielectric layer (282, 280) and the dielectric material portion below. The drain region 63 and the conductive layer (146, 246) may be used as an etching stop structure. A drain contact via cavity may be formed over each drain region 63, and a staircase area contact via cavity may be formed over each conductive layer (146, 246) at the stepped surface below the first stepped dielectric material portion 165 and the second stepped dielectric material portion 265. The photoresist layer may then be removed, for example, by ashing.

[0126] The drain contact via structure 88 is formed in the drain contact via cavity and on the top surface of a corresponding one of the drain regions 63. The staircase area contact via structure 86 is formed in the staircase area contact via cavity and on the top surface of a corresponding one of the conductive layers (146, 246). The staircase area contact via structure 86 may include drain selection level contact via structures that contact a subset of the second conductive layer 246 used as a drain selection level gate electrode. In addition, the staircase area contact via structure 86 may include word line contact via structures that contact the conductive layer (146, 246) below the drain selection level gate electrode and serve as a word line of the memory stack structure 55.

[0127] An optional first through-memory level through hole cavity may be formed by passing through the second contact level dielectric layer and the first contact level dielectric layer (282, 280), the second stepped dielectric material portion and the first stepped dielectric material portion (265, 165), and the source side dielectric material layer 910 to reach the top surface of the carrier substrate layer 909 in the through hole interconnection area 400. An optional second through-memory level through hole cavity may be formed by passing through the interconnection area dielectric filling material portion 584 and the source side dielectric material layer 910 to reach the top surface of the carrier substrate layer 909. At least one conductive material may be deposited in the first through-memory level through hole cavity and in the second through-memory level through hole cavity. Excess portions of the at least one conductive material may be removed from above the horizontal plane including the top surface of the second contact level dielectric layer 282. Each remaining portion of the at least one conductive material in the first through-memory level through hole cavity constitutes an optional first through-memory level through hole structure 488. Each remaining portion of the at least one conductive material in the second through-memory level via cavity constitutes an optional second through-memory level via structure 588. The optional first through-memory level via structure 488 and the second through-memory level via structure 588 may be used in embodiments in which more than two chips (e.g., more than two dies) are bonded together, as will be described with reference to Fig.23 and Fig.24 In another embodiment, the first through-memory level via structure 488 and the second through-memory level via structure 588 may be omitted, especially if only two chips (eg, two dies) are bonded together.

[0128] At least one additional dielectric layer may be formed above the contact level dielectric layer (280, 282), and an additional metal interconnect structure (referred to herein as a higher level metal interconnect structure) may be formed in the at least one additional dielectric layer. For example, the at least one additional dielectric layer may include a line level dielectric layer 290 formed above the contact level dielectric layer (280, 282). The higher level metal interconnect structure may include a first line level metal interconnect structure (98, 96). The first line level metal interconnect structure (98, 96) may include: a bit line 98 that contacts a corresponding one of the drain contact via structures 88; and an interconnect line structure 96 that contacts and / or is electrically connected to at least one of the staircase area contact via structure 86 and / or the first through memory level via structure 488 and / or the second through memory level via structure 588.

[0129] In one embodiment, the three-dimensional memory device comprises a single three-dimensional NAND memory device, the conductive strip (146, 246) comprises or is electrically connected to a corresponding word line of the single three-dimensional NAND memory device, the carrier substrate 908 comprises a silicon substrate, the single three-dimensional NAND memory device comprises a single three-dimensional NAND string array above the silicon substrate, and at least one memory cell in a first device level of the single three-dimensional NAND string array is located above another memory cell in a second device level of the single three-dimensional NAND string array. The conductive strip (146, 246) comprises a plurality of control gate electrodes having a strip shape extending substantially parallel to a top surface of the carrier substrate 908, the plurality of control gate electrodes comprising at least a first control gate electrode positioned in the first device level and a second control gate electrode positioned in the second device level. The single three-dimensional NAND string array comprises a plurality of semiconductor channels 60, wherein at least one end portion of each semiconductor channel of the plurality of semiconductor channels 60 extends substantially perpendicular to the top surface of the carrier substrate 908, and one semiconductor channel of the plurality of semiconductor channels comprises a vertical semiconductor channel 60. The single three-dimensional NAND string array includes a plurality of charge storage elements (which include portions of the memory film 50 ), each charge storage element being positioned adjacent to a respective one of the plurality of semiconductor channels 60 .

[0130] See also Fig.19A and Fig.19B , a memory die dielectric material layer 960 may be deposited over the line level dielectric layer 290. Various additional memory die metal interconnect structures 980 may be formed in the memory die dielectric material layer 960. In general, with appropriate shifting of the metal interconnect levels, various metal interconnect structures (88, 86, 98, 96, 980) may be formed in a combination of the first contact level dielectric layer 280, the second contact level dielectric layer 282, the line level dielectric layer 290, and the memory die dielectric material layer 960. The thickness of the memory die dielectric material layer 960 may be in the range of 300 nm to 3,000 nm, although lesser and greater thicknesses may also be used.

[0131] The pad cavities may be formed in the upper portion of the additional memory die metal interconnect structures 980 such that a corresponding one of the memory die metal interconnect structures 980 is exposed at the bottom of each pad cavity. In one embodiment, the pad cavities may be arranged in a one-dimensional array or a two-dimensional array and may have corresponding polygonal, circular, elliptical, or generally curved shapes.

[0132] Conductive material may be deposited in the pad cavity to form various memory die bonding pads 988. The memory die bonding pads 988 may include: a source network memory die bonding pad electrically connected to the source semiconductor layer 10; a word line connection memory die bonding pad electrically connected to a corresponding one of the conductive layers (146, 246) used as a word line; and a bit line connection memory die bonding pad electrically connected to the bit line 98. The exemplary structure includes a memory die 900.

[0133] A plurality of memory dies 900 may be provided. Each of the memory dies 900 may include an alternating stack of insulating layers (132, 232) and word lines, the word lines including a subset of conductive layers (146, 246). The alternating stack {(132, 146), (232, 246)} has a stepped surface, wherein the subset of conductive layers (146, 246) has a lateral extent that increases with distance from a bonding surface of the memory die 900 including a memory die bonding pad 988. The memory stack structure 55 extends vertically through the alternating stack {(132, 146), (232, 246)}. Each of the memory stack structures 55 includes a corresponding vertical semiconductor channel 60 and a corresponding group of vertically stacked memory elements located at each level of the conductive layer (146, 246). Each group of vertically stacked memory elements may include a portion of a charge storage layer 54 located at each level of the conductive layer (146, 246). The word line contact via structures (which are a subset of the stepped region contact via structures 86 that contact a subset of the conductive layer 46 used as word lines) may contact a corresponding one of the word lines. Each of the word line contact via structures vertically extends from a corresponding one of the word lines toward the bonding surface of the memory die 900.

[0134] Multiple instances of the memory die 900 may be provided with the same design or different designs. Where multiple instances of the memory die 900 are provided, the multiple instances of the memory die 900 are referred to herein as a first memory die (or first die), a second memory die (or second die), a third memory die (or third die), etc. The three-dimensional memory device in the first memory die is referred to herein as a first three-dimensional memory device, the three-dimensional memory device in the second memory die is referred to herein as a second three-dimensional memory device, etc. The alternating stacking of the insulating layer (132, 232) and the conductive layer (146, 246) in the first memory die is referred to herein as a first die alternating stacking of the first die insulating layer and the first die conductive layer, the alternating stacking of the insulating layer (132, 232) and the conductive layer (146, 246) in the second memory die is referred to herein as a second die alternating stacking of the second die insulating layer and the second die conductive layer, etc. The memory die dielectric material layer 960 in the first memory die is referred to herein as the first memory die dielectric material layer, the memory die dielectric material layer 960 in the second memory die is referred to herein as the second memory die dielectric material layer, and so on. The memory die bonding pad 988 in the first memory die is referred to herein as the first memory die bonding pad, the memory die bonding pad 988 in the second memory die is referred to herein as the second memory die bonding pad, and so on. Within each memory die 900, the memory die bonding pad 988 is formed in the memory die dielectric material layer 960 and is located on the alternating stack {(132, 146), (232, 246)} and on opposite sides of the semiconductor substrate of the corresponding memory die 900. The memory die bonding pad 988 is electrically connected to the nodes of the three-dimensional memory device in the memory die 900. In one embodiment, the area of ​​the memory die bonding pad 988 can overlap with the areas of the first direct memory level via structure 488 and the second direct memory level via structure 588 in a plan view (i.e., in a view along a direction perpendicular to the interface between the source semiconductor layer 10 and the alternating stack {(132, 146), (232, 246)}).

[0135] In general, each memory die 900 includes at least one three-dimensional memory element array, a memory die metal interconnect structure 980 formed within a memory die dielectric material layer 960, and a memory die bond pad 988, which is located on or formed within the memory die dielectric material layer 960 and electrically connected to a corresponding node of the at least one three-dimensional memory element array. In one embodiment, each of the at least one three-dimensional memory element array includes: an alternating stack of insulating layers (132, 232) and conductive layers (146, 246) configured as word lines; a memory stack structure 55, which includes a corresponding vertical stack of memory elements and a corresponding vertical semiconductor channel 60; a bit line 98 connected to a first end of a corresponding subset of the vertical semiconductor channels 60; and a source line (which may include a combination of an optional metal plate layer 6 and a source semiconductor layer 10) connected to a second end of the vertical semiconductor channel 60.

[0136] See also Fig. 20A and Fig. 20B , a support die 700 is provided, which includes various semiconductor devices formed on a support die substrate 708. The support die substrate 708 includes a support die semiconductor layer 706. The support die semiconductor layer 706 may include at least one elemental semiconductor material (e.g., a single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0137] A shallow trench isolation structure 720 may be provided in a surface region of the support die semiconductor layer 706 to provide electrical isolation for semiconductor devices of peripheral circuits. Various semiconductor devices may include a field effect transistor including a corresponding transistor active region 742 (i.e., a source region and a drain region), a channel 746, and a gate structure 750. The field effect transistor may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758. For example, a semiconductor device may include: a word line driver for electrically biasing a word line of a memory die 900, the word line driver including a conductive layer (146, 246); and a source power supply field effect transistor that generates power to be supplied to a source semiconductor layer in the memory die 900.

[0138] A dielectric material layer is formed over the semiconductor device, which is referred to herein as a support die dielectric layer 760. Optionally, a dielectric liner 762 (such as a silicon nitride liner) may be formed to apply mechanical stress to various field effect transistors and / or to prevent hydrogen or impurities from diffusing from the support die dielectric layer 760 into the semiconductor device. A support die metal interconnect structure 780 is formed within the support die dielectric layer 760. The support die metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes contacting corresponding source and drain nodes of a device or gate electrode contact), a memory die metal line structure 784, a memory die metal via structure 786, and a support die bonding pad 788. The support die bonding pad 788 may be located on or formed within the support die dielectric material layer. The support die bonding pad 788 may be electrically connected to a corresponding node of at least one peripheral circuit 740 of the support die 700. Support die bond pads 788 are configured to mate with memory die bond pads 988 of memory die 900 , or with backside bond pads to be subsequently formed on memory die 900 , to provide a conductive path between memory die 900 and support die 700 .

[0139] In one embodiment, the semiconductor device supporting the die 700 may include a complementary metal oxide semiconductor (CMOS) device. The semiconductor device includes at least one peripheral circuit 740 for the operation of each three-dimensional memory array in the at least one memory die 900, and a functional module 790 configured to provide functions unrelated to the operation of any three-dimensional array of memory elements. For example, the at least one peripheral circuit 740 may include a CMOS device and is configured to generate control signals for and receive sensing signals from at least one three-dimensional array of memory elements disposed in the at least one memory die 900. In one embodiment, the at least one peripheral circuit 740 may include a plurality of peripheral circuits 740 configured to generate control signals for and receive sensing signals from a plurality of three-dimensional arrays of memory elements disposed in a single memory die 900 or a plurality of memory dies 900.

[0140] Each peripheral circuit 740 may include a word line driver that drives word lines of a three-dimensional memory array (including conductive layers (146, 246)) within the memory die 900; a bit line driver that drives bit lines 98 in the memory die 900; a word line decoder circuit that decodes the address of the conductive layer (146, 246); a bit line decoder circuit that decodes the address of the bit line 98; a sense amplifier circuit that senses the state of memory elements within the memory stack structure 55 in the memory die 900; a source power supply circuit that provides power to the source semiconductor layer 10 in the memory die 900; a data buffer and / or latch; or any other semiconductor circuit that can be used to operate the array of memory stack structures 55 in the memory die 900.

[0141] In general, the peripheral circuit 740 for driving each three-dimensional memory element array within the memory die 900 having a corresponding area (which is referred to herein as the memory die area) can use an area significantly smaller than the memory die area. The area of ​​the peripheral circuit 740 can be in the range of 10% to 80%, such as 20% to 60%, of the memory die area of ​​the memory die 900, which includes the entire set of at least one three-dimensional memory element array controlled by the peripheral circuit 740. Therefore, if the support die 700 has a size comparable to or the same size as the memory die 900, the functional module 790 can be formed in an area not occupied by at least one peripheral circuit 740 of the support die 700.

[0142] In one embodiment, the functional module 790 of the support die 700 may include a system-level controller module configured to control the operation of an additional die that is not a memory die. In this case, the additional die is not included in the bonded assembly including the support die 700 and the at least one memory die 900, and may be attached to the same printed circuit board (PCB) to which the bonded assembly including the support die 700 and the at least one memory die 900 is attached.

[0143] Additionally or alternatively, functional module 790 may include an error correction code (ECC) module configured to detect and correct data corruption in at least one three-dimensional array of memory elements in memory die 900 to which support die 700 may subsequently be bonded.

[0144] Additionally or alternatively, the functional module 790 may include a memory module configured to interact with an external processor module located outside a bonding assembly that includes the support die 700 and at least one memory die 900 and is attached to the same PCB as the support die 700. The memory module may be selected from, but is not limited to, a dynamic random access memory module, a static random access memory module, a two-dimensional NAND memory module, and a storage class memory (SCM) module.

[0145] Additionally or alternatively, the functional module 790 may include a module selected from a microprocessor unit module including a central processing unit and a memory management unit and a wireless communication module configured to generate or receive wireless signals.

[0146] See also Fig.21 , shows a first exemplary bonding assembly according to an embodiment of the present disclosure, which can be formed by attaching a first memory die 900A (which is Fig.19A and Fig.19B The memory die bonding pad 988 of the memory die 900 shown in the example is bonded to the first support die 700A (which is Fig. 20A and Fig. 20B The support die 700 of the embodiment shown in FIG. 7 is formed by supporting die bonding pads 788 of the support die 700. Metal-to-metal bonding can be used to bond the first memory die 900A to the first support die 700A.

[0147] refer to Fig. 22 , the support die substrate 708 may be thinned from the back side of the support die substrate 708. A grinding process, a wet etching process, a polishing process, and / or a dry etching process may be used to thin the support die substrate 708. The thickness of the thinned support die substrate 708 may be in the range of 500 nm to 20 microns, although smaller and larger thicknesses may also be used.

[0148] A support die backside insulating layer 714 may be deposited on the backside surface of the thinned support die substrate 708. The support die backside insulating layer 714 comprises a dielectric material such as silicon oxide and may have a thickness in the range of 30 nm to 1,000 nm, although lesser and greater thicknesses may also be used. A photoresist layer (not shown) may be applied over the backside of the thinned support die substrate 708 and photolithographically patterned to form openings therein. The openings in the photoresist layer may be formed directly over a corresponding one of the support die metal interconnect structures 780.

[0149] An anisotropic etching process may be performed using the photoresist layer as an etching mask layer to etch through the thinned support die substrate 708 to the surface of a corresponding one of the support die metal interconnect structures 780. A through-substrate via cavity is formed through the support die backside insulating layer 714 and the thinned support die substrate 708. The photoresist layer may then be removed, for example, by ashing. An insulating liner layer may be deposited in the through-substrate via cavity and deposited over the support die backside insulating layer 714. A horizontal portion of the insulating liner layer may be removed from over the support die backside insulating layer 714 by an anisotropic etching process. Each remaining tubular portion of the insulating liner layer constitutes a tubular insulating spacer 711. The tubular insulating spacer 711 includes a dielectric material such as silicon oxide and may have a lateral thickness in the range of 10 nm to 300 nm between the inner sidewall and the outer sidewall. At least one conductive material such as a combination of a metal liner (eg, TiN) and a metal fill material (eg, W) may be deposited in the remaining volume of the through substrate via cavity to form a through substrate via structure 712 .

[0150] The support die backside bonding pad 716 may be formed directly on a corresponding one of the through substrate via structures 712. Optionally, the support die backside bonding pad 716 may have a mirror image pattern of the pattern of the front support die bonding pad 788. Each combination of the through substrate via structure 712 and the support die backside bonding pad 716 constitutes a backside bonding structure (712, 716). Each of the backside bonding structures (712, 716) may include: a through substrate via structure 712 extending through the semiconductor substrate (including the support die substrate 708) of the first support die 700A and being laterally electrically insulated from the semiconductor substrate by a tubular insulating spacer 711; and a support die backside bonding pad 716 contacting the through substrate via structure 712.

[0151] See also Fig.23 , the carrier substrate layer 909 may be removed from the first exemplary bonded component (700A, 900A). A grinding process, a wet etching process, a polishing process, and / or a dry etching process may be used to remove the carrier substrate layer 909. In the illustrative example, the grinding process may remove a major portion of the carrier substrate layer 909, and the trimming wet etching process may apply a chemistry that selectively removes the material of the carrier substrate layer 909 relative to the material of the source side dielectric material layer 910. For example, if the carrier substrate layer 909 includes silicon, a wet etching process using a KOH solution may be used to selectively remove the carrier substrate layer 909 relative to the material of the source side dielectric material layer 910.

[0152] refer to Figures 1 to 23According to all the drawings of the present disclosure, a bonding assembly including a first memory die 900A and a first support die 700A can be formed according to one embodiment of the present disclosure. The first memory die 900A includes at least one first three-dimensional memory element array, a first memory die metal interconnect structure 980 formed in a first memory die dielectric material layer 960, and a first memory die bonding pad 988, which is located on the first memory die dielectric material layer 960 or formed in the first memory die dielectric material layer 960 and is electrically connected to the corresponding nodes of the at least one first three-dimensional memory element array. The first support die 700A includes: at least one first peripheral circuit 740, the at least one first peripheral circuit includes a complementary metal oxide semiconductor (CMOS) device and is configured to generate control signals for the at least one first three-dimensional memory element array and receive sensing signals therefrom; and a first functional module 790, the first functional module is configured to provide functions unrelated to the operation of the at least one first three-dimensional memory element array. The first support die 700A includes: a first support die bonding pad 788 , which is located on or formed in the first support die dielectric material layer 760 , is electrically connected to a corresponding node of at least one first peripheral circuit 740 , and is bonded to the first memory die bonding pad 988 .

[0153] In one embodiment, at least a subset of the support die backside bonding pads 716 can be external bonding pads that can be bonded to a printed circuit board via solder balls and / or bonding wires. In one embodiment, the first support die 700A includes a first external bonding pad that includes a subset of the support die backside bonding pads 716. A first subset of the first external bonding pads can be electrically connected to corresponding nodes of at least one first peripheral circuit 740 in the first support die 700A, and a second subset of the first external bonding pads can be electrically connected to corresponding nodes of devices of the first functional module 790 in the first support die 700A.

[0154] In one embodiment, a first through-substrate via structure 712 may extend through the substrate of the first support die 700A and may provide an electrical connection between a first external bonding pad and a node of at least one first peripheral circuit 740. And a second through-substrate via structure 712 may extend through the substrate of the first support die 700A and may provide an electrical connection between a second external bonding pad and a node of a device of the first functional module 790.

[0155] See also Fig.24In an alternative embodiment, more than three chips (e.g., more than three dies) may be bonded together. The memory die backside dielectric layer 660 may be optionally deposited on the source side dielectric material layer 910. The memory die backside via structure 684 and the backside memory die bonding pad 688 may be formed through the optional memory die backside dielectric layer 660 and the source side dielectric material layer 910. A first subset of the backside memory die bonding pads 688 may be electrically connected to corresponding nodes of at least one three-dimensional memory element array of the first memory die 900A. A second subset of the backside memory die bonding pads 688 may be electrically isolated from at least one three-dimensional memory element array of the first memory die 900A and may be connected to corresponding nodes of the functional module 790 of the first support die 700A. In one embodiment, the pattern of the back side memory die bonding pads 688 can be a mirror image pattern of the pattern of the back side support die bonding pads 716 (when viewed toward the interface between the first memory die 900A and the first support die 700A).

[0156] The same method used to provide the bonded assembly of the first memory die 900A and the first support die 700A can be used to provide the bonded assembly of the second memory die 900B and the second support die 700B. The bonded assembly of the second memory die 900B and the second support die 700B can be bonded to the bonded assembly of the first memory die 900A and the first support die 700A. For example, the backside support die bond pad 716 of the second support die 700B can be bonded to the backside memory die bond pad 688 of the first memory die 900A, or the backside support die bond pad 716 of the first support die 700A can be bonded to the backside memory die bond pad 688 of the second memory die 900B.

[0157] In the case where the second memory die 900B and the second support die 700B are bonded to the assembly of the first memory die 900A and the first support die 700A. In addition to the first memory die 900A and the first support die 700A, the bonded assembly may also include the second memory die 900B and the second support die 700B. The second memory die 900B may include at least one second three-dimensional memory element array, a second memory die metal interconnect structure 980 formed in the second memory die dielectric material layer 960, and a second memory die bonding pad 988, which is located on the second memory die dielectric material layer 960 or formed in the second memory die dielectric material layer 960 and is electrically connected to the corresponding nodes of the at least one second three-dimensional memory element array. The second support die 700B includes: at least one second peripheral circuit 740, the at least one second peripheral circuit including a complementary metal oxide semiconductor (CMOS) device and configured to generate control signals for the at least one second three-dimensional memory element array and receive sensing signals therefrom; and a second functional module 790, the second functional module configured to provide functions unrelated to the operation of the at least one second three-dimensional memory element. Each of the first functional module 790 in the first support die 700A and the second functional module 790 in the second support die 700B can be independently selected from the various functional modules described above.

[0158] In one embodiment, functional module 790 may also include a complementary metal oxide semiconductor (CMOS) device.

[0159] In one embodiment, the second support die 700B may include: a second support die bonding pad 788 located on or formed in the second support die dielectric material layer 760, electrically connected to a corresponding node of the at least one second peripheral circuit 740, and bonded to the second memory die bonding pad 988 of the second memory die 900B; and a support die backside bonding pad 716 located on an opposite side of the second support die bonding pad 788 and bonded to the backside memory die bonding pad 688 of the first memory die 900A. In one embodiment, the second functional module 790 of the second support die 700B may be configured to provide a different type of function than the first functional module 790 of the first support die 700A.

[0160] refer to Fig.25, at least one additional memory die (such as the third memory die 900C) and at least one additional support die (such as the third support die 700C) may optionally be bonded to a bonded assembly including the first memory die 900A, the first support die 700A, the second memory die 900B and the second support die 700B.

[0161] See also Fig.26 , which can be further modified by attaching at least one system function die (500A, 500B) Fig.25 The at least one system function die (500A, 500B) may include a single system function die or a plurality of system function dies. For example, the at least one system function die (500A, 500B) may include a first system function die 500A and a second system function die 500B.

[0162] Each system function die (500A, 500B) may be directly bonded to the first memory die 900A and the first support die 700A or indirectly bonded to the first memory die 900A and the first support die 700A through a stack of at least one additional memory die (such as the second memory die 900B) and at least one support die (such as the second support die 700B). Each system function die (500A, 500B) may include additional CMOS devices that provide functions different from the first functional module 790 or the second functional module 790.

[0163] Each system function die (500A, 500B) may include a system function die bond pad 588 bonded to a memory die backside bond pad 688 or a support die backside bond pad 716, and may include a system function die bond pad 588 bonded to another system function die (500A, 500B) or a backside system function die bond pad 516 that may be used as an external bond pad. Each system function die (500A, 500B) may include a first side metal interconnect structure 580 connected to a corresponding one of the system function die bond pads 588, and a second side metal interconnect structure 512 that may be connected to a corresponding one of the backside system function die bond pads 516. Solder balls 798 may be bonded to the backside system function die bond pad 516 or the second side metal interconnect structure 512.

[0164] See also Fig. 27 , shows a second exemplary bonding assembly according to one embodiment of the present disclosure, which can be formed by laterally offsetting the edges of each bonding pair of the memory die 900 and the support die 700 from Fig.24 , Fig.25 or Fig.26If more than two pairs of memory die 900 and support die 700 are used, the edges of the bonded pairs of memory die 900 and support die 700 can be gradually offset laterally to physically expose at least one backside support die bond pad 716 or at least one backside memory die bond pad 688.

[0165] In one embodiment, the edge of the second support die 700B can be laterally offset relative to the edge of the first support die 700A, the first support die 700A can include a first external bonding pad (which can be a subset of the backside support die bonding pads 716 of the first support die 700A) on the opposite side of the first memory die bonding pads 988, and the second support die 700B can include a second external bonding pad (which can be a subset of the backside support die bonding pads 716 of the second support die 700B) on the opposite side of the second memory die bonding pads 988 that is not in contact with and not covered by the first memory die 900A or the first support die 700A. The solder ball 798 can be attached to at least one of the physically exposed bonding pads (such as a physically exposed bonding pad selected from the backside support die bonding pads 716). At least one inter-die connection bond wire 799 may be used to electrically connect a corresponding pair of one of the first external bond pads on the first support die 700A and one of the second external bond pads on the second support die 700B.

[0166] Various structures of the embodiments of the present disclosure can be used to utilize the area of ​​each support die 700 that is not used to form the peripheral circuit 740 of the memory die 900, and provide additional functions to the bonded assembly including at least one memory die 900 and at least one support die 700 in addition to the functions of the three-dimensional memory element array. Various embodiments can provide a memory die bonded to a support die containing a functional module with an integrated system-level function, which improves the system form factor, improves the speed (for example, due to the shorter metal connection between the peripheral device and the system-level component on the same support die) and reduces the operating power (for example, due to the peripheral device and the system-level component being located on the same support die) because the system does not require the signals between the peripheral device and the system-level component to be transmitted through a printed circuit board supporting a separate system and memory die or chip. In some embodiments, functional modules with the same system-level functional module can be integrated into each support die. In other embodiments, functional modules with different system-level functional modules can be integrated into each support die. The system-level functional module can be used as one system-level function or multiple system-level functions. In other embodiments, the functional modules with system-level functions may be integrated into each supporting die, and the functional modules with system-level functions may also be integrated with the system-level functional dies packaged together to improve system performance.

[0167] Although specific embodiments are mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A joining assembly, comprising: A first memory die, the first memory die comprising: at least one first three-dimensional array of memory elements; a first memory die metal interconnect structure formed within a first memory die dielectric material layer; and first memory die bond pads located on or formed within the first memory die dielectric material layer and electrically connected to respective nodes of the at least one first three-dimensional array of memory elements; and A first supporting tube core, wherein the first supporting tube core comprises: at least one first peripheral circuit including a complementary metal oxide semiconductor (CMOS) device and configured to generate control signals for the at least one first three-dimensional array of memory elements and to receive sensing signals from the at least one first three-dimensional array of memory elements; a first functional module configured to provide functionality unrelated to the operation of the at least one first three-dimensional array of memory elements; and a first support die bonding pad, the first support die bonding pad being located on or formed in the first support die dielectric material layer, being electrically connected to a corresponding node of the at least one first peripheral circuit, and being bonded to the first memory die bonding pad, and wherein The engagement assembly further comprises: A second memory die, the second memory die comprising: at least one second three-dimensional array of memory elements; a second memory die metal interconnect structure formed within a second memory die dielectric material layer; and second memory die bond pads located on or formed within the second memory die dielectric material layer and electrically connected to respective nodes of the at least one second three-dimensional array of memory elements; and A second supporting tube core, wherein the second supporting tube core comprises: at least one second peripheral circuit including a complementary metal oxide semiconductor (CMOS) device and configured to generate control signals for the at least one second three-dimensional memory element array and receive sensing signals from the at least one second three-dimensional memory element array; a second functional module configured to provide a function unrelated to the operation of the at least one second three-dimensional memory element; and a second support die bonding pad located on or formed within the second support die dielectric material layer, electrically connected to a corresponding node of the at least one second peripheral circuit, and bonded to the second memory die bonding pad; and A support die back side bond pad is located on an opposite side of the second support die bond pad and is bonded to a back side memory die bond pad of the first memory die.

2. The joint assembly of claim 1, wherein: The first support die includes a first external bonding pad; a first subset of the first external bond pads electrically connected to respective nodes of the at least one first peripheral circuit; and A second subset of the first external bond pads are electrically connected to corresponding nodes of devices of the first functional module. 3 . The bonded assembly of claim 2 , wherein the first support die includes a system-level controller module configured to control operation of additional dies not present within the bonded assembly.

4. The engagement assembly of claim 2, further comprising: a first through-substrate via structure extending through a substrate of the first support die and providing an electrical connection between the first external bond pad and a node of the at least one first peripheral circuit; and A second through substrate via structure extends through the substrate of the first support die and provides an electrical connection between a second external bonding pad and the node of the device of the first functional module.

5. The bonding assembly of claim 1 , further comprising a system function die, the system function die being directly bonded to the second memory die or being indirectly bonded to the second memory die through a stack of at least one additional memory die and at least one support die, wherein the system function die comprises an additional complementary metal oxide semiconductor device that provides a function different from that of the first function module or the second function module.

6. The joint assembly of claim 1, wherein: The edge of the second support tube core is laterally offset relative to the edge of the first support tube core; the first support die comprising first external bonding pads on opposite sides of the first memory die bonding pads; and The second support die includes second external bond pads on opposite sides of the second memory die bond pads, the second external bond pads not in contact with and not covered by the first memory die or the first support die. 7 . The bonding assembly of claim 6 , further comprising at least one inter-die connection bond wire electrically connecting a corresponding pair of one of the first external bond pads and one of the second external bond pads.

8. The engagement assembly of claim 1, wherein the second functional module is configured to provide a different type of functionality than the first functional module.

9. The bonded assembly of claim 1, wherein the first functional module comprises an error correction code (ECC) module configured to detect and correct data corruption in the at least one first three-dimensional array of memory elements.

10. The bonded assembly of claim 1, wherein the first functional module comprises a memory module configured to interact with an external processor module external to the first memory die, wherein the memory module is selected from: Dynamic random access memory module; Static random access memory module; A two-dimensional NAND memory module; or Storage class memory (SCM) module.

11. The joint assembly of claim 1 , wherein the first functional module comprises a module selected from the group consisting of: a microprocessor unit module, the microprocessor unit module comprising a central processing unit and a memory management unit; and A wireless communication module is configured to generate or receive a wireless signal.

12. The bonded assembly of claim 1 , wherein each of the at least one first three-dimensional array of memory elements comprises: an alternating stack of insulating layers and conductive layers, the conductive layers being configured as word lines; a memory stack structure comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel; bit lines connected to first ends of respective subsets of the vertical semiconductor channels; and A source line is connected to the second end of the vertical semiconductor channel.

13. A method of forming a joint assembly, the method comprising: A first memory die is provided, wherein the first memory die comprises: at least one first three-dimensional array of memory elements; a first memory die metal interconnect structure formed within a first memory die dielectric material layer; and first memory die bond pads located on or formed within the first memory die dielectric material layer and electrically connected to respective nodes of the at least one first three-dimensional array of memory elements; A first support tube core is provided, wherein the first support tube core comprises: at least one first peripheral circuit including a complementary metal oxide semiconductor (CMOS) device and configured to generate control signals for the at least one first three-dimensional array of memory elements and to receive sensing signals from the at least one first three-dimensional array of memory elements; a first functional module configured to provide functionality unrelated to the operation of the at least one first three-dimensional array of memory elements; a first support die bonding pad, the first support die bonding pad being located on or formed in the first support die dielectric material layer, electrically connected to a corresponding node of the at least one first peripheral circuit; and bonding the first support die bonding pad to the first memory die bonding pad, and wherein The method further comprises: attaching a second support die to the first memory die; and attaching a second memory die to the second support die, in: The second memory die comprises: at least one second three-dimensional array of memory elements; a second memory die metal interconnect structure formed within a second memory die dielectric material layer; and second memory die bond pads located on or formed within the second memory die dielectric material layer and electrically connected to respective nodes of the at least one second three-dimensional array of memory elements; The second supporting tube core comprises: at least one second peripheral circuit including a complementary metal oxide semiconductor (CMOS) device and configured to generate control signals for the at least one second three-dimensional memory element array and receive sensing signals from the at least one second three-dimensional memory element array; a second functional module configured to provide a function unrelated to the operation of the at least one second three-dimensional memory element; and a second support die bonding pad located on or formed within the second support die dielectric material layer, electrically connected to a corresponding node of the at least one second peripheral circuit, and bonded to the second memory die bonding pad; and A support die back side bond pad is located on an opposite side of the second support die bond pad and is bonded to a back side memory die bond pad of the first memory die.

14. The method according to claim 13, wherein: The first support die includes a first external bonding pad; a first subset of the first external bond pads electrically connected to respective nodes of the at least one first peripheral circuit; A second subset of the first external bonding pads are electrically connected to respective nodes of devices of the first functional module; and The method also includes attaching a bond wire to at least one of the first external bond pads.

15. The method of claim 14, wherein the first support die includes a system-level controller module configured to control operation of additional dies not present within the bonded assembly.

16. The method according to claim 14, further comprising: forming a first through-substrate via structure extending through a substrate of the first support die, wherein the first through-substrate via structure provides an electrical connection between the first external bond pad and a node of the at least one first peripheral circuit; as well as A second through-substrate via structure is formed extending through the substrate of the first support die, wherein the second through-substrate via structure provides an electrical connection between a second external bonding pad and the node of the device of the first functional module.

17. The method of claim 13, further comprising attaching a system function die directly to the second memory die or indirectly to the second memory die through a stack of at least one additional memory die and at least one support die, wherein the system function die includes an additional complementary metal oxide semiconductor device that provides a function different from the first function module or the second function module.

18. The method of claim 13, wherein each of the at least one first three-dimensional array of memory elements comprises: an alternating stack of insulating layers and conductive layers, the conductive layers being configured as word lines; a memory stack structure comprising a respective vertical stack of memory elements and a respective vertical semiconductor channel; bit lines connected to first ends of respective subsets of the vertical semiconductor channels; and A source line is connected to the second end of the vertical semiconductor channel.

Images