Superconducting switches with continuous and discontinuous states

Abstract

A superconducting switch having persistent and non-persistent states and its use as a driver in a memory system is described. The example superconducting switch includes a first superconducting layer and a second superconducting layer. The superconducting switch includes a first magnetic layer having a fixed magnetization state. The superconducting switch includes a second magnetic layer capable of being in at least a first magnetization state or a second magnetization state. The superconducting switch is capable of being in either the first state or the second state, and the superconducting switch is configured such that application of a magnetic field to the second magnetic layer changes the magnetization of the second magnetic layer from the first magnetization state to the second magnetization state, thereby placing the superconducting switch in the second state, and removal of the magnetic field automatically returns the superconducting switch from the second state to the first state.

Description

Background Art

[0001] Semiconductor-based integrated circuits used in electronic devices include digital circuits based on complementary metal-oxide-semiconductor (CMOS) technology. However, CMOS technology has reached its limits in terms of device size. Furthermore, leakage currents in CMOS-based circuits can lead to high power consumption even when these circuits are not being accessed.

[0002] For example, servers in data centers consume increasingly large amounts of power. This power consumption is partially due to energy dissipation, resulting in power losses even when the CMOS circuits are inactive. This is because, even though such circuits are inactive and not consuming any dynamic power, they still consume power due to the need to maintain the state of the CMOS transistors. Furthermore, because CMOS circuits are powered by a DC voltage, a certain amount of current leaks even when the CMOS circuits are inactive. Therefore, even when such circuits are not processing operations such as read / write operations, a certain amount of power is wasted, not only due to the need to maintain the state of the CMOS transistors, but also due to the leakage current.

[0003] An alternative to using circuits based on CMOS technology is to use circuits based on superconducting logic. Summary of the Invention

[0004] In one example, the present disclosure relates to a superconducting switch comprising a first superconducting layer and a second superconducting layer. The superconducting switch may further comprise a first magnetic layer having a fixed magnetization state. The superconducting switch may further comprise a second magnetic layer capable of being in at least a first magnetization state or a second magnetization state different from the first magnetization state. The superconducting switch may be capable of being in a first state or a second state, wherein the second state corresponds to an opposite state of the first state, and wherein the superconducting switch is configured such that application of a magnetic field to the second magnetic layer changes the magnetization of the second magnetic layer from the first magnetization state to the second magnetization state, thereby placing the superconducting switch in the second state, and removal of the magnetic field automatically returns the superconducting switch from the second state to the first state.

[0005] In another aspect, the present disclosure relates to a superconducting switch comprising a first superconducting layer and a second superconducting layer. The superconducting switch may further comprise a first magnetic layer having a fixed magnetization state. The superconducting switch may further comprise a second magnetic layer capable of being in at least a first magnetization state or a second magnetization state different from the first magnetization state. The superconducting switch may further comprise a third magnetic layer having a second fixed magnetization state. The superconducting switch may further comprise a conductor inductively coupled to the second magnetic layer such that flow of current through the conductor causes application of a magnetic field to the second magnetic layer. The superconducting switch may be capable of being in a first state or a second state, wherein the second state corresponds to an opposite state of the first state, and wherein the superconducting switch is configured such that application of a magnetic field changes the magnetization of the second magnetic layer from the first magnetization state to the second magnetization state, thereby placing the superconducting switch in the second state, and removal of the magnetic field automatically returns the switch from the second state to the first state.

[0006] In another aspect, the present disclosure relates to a memory system comprising a row of memory cells coupled to at least one write word line and a write word line driver coupled to the at least one write word line. The write word line driver may include a superconducting switch. The superconducting switch may include a magnetic layer configured to be in a first magnetization state or a second magnetization state, wherein a first superconducting switch is capable of being in the first state or the second state, and wherein the second state corresponds to an opposite state of the first state, and wherein the first superconducting switch is configured such that application of a magnetic field to the magnetic layer changes the magnetization of the magnetic layer from the first magnetization state to the second magnetization state, thereby placing the first superconducting switch in the second state, and removal of the magnetic field automatically returns the switch from the second state to the first state.

[0007] This Summary is provided to introduce some concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like reference numerals indicate like elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0009] Figure 1A is a top view of a schematic diagram of a superconducting switch according to one example, and Figure 1B is a side view of a schematic diagram of a superconducting switch according to one example;

[0010] Figure 2A and Figure 2Bshows the structure of a FS valve for use in a superconducting switch according to one example;

[0011] Figure 2C shows a change in the magnitude of a current flowing through the FS valve in response to a change in the magnitude of a magnetic field applied to the FS valve according to one example;

[0012] Figure 3A and Figure 3B Another structure of a FS valve according to one example is shown;

[0013] Figure 3C shows a change in the magnitude of a current flowing through the FS valve in response to a change in the magnitude of a magnetic field applied to the FS valve according to one example;

[0014] Figure 4 An example based on Figures 2A-2C superconducting switches and Figures 3A-3C Schematic diagram of a superconducting switch driver;

[0015] Figure 5 A memory system including a write word line driver using superconducting switches according to one example is shown; and

[0016] Figure 6 A schematic diagram of a computing system including a processor coupled to a memory is shown according to one example. DETAILED DESCRIPTION

[0017] Examples described in this disclosure relate to superconducting logic-based devices, including superconducting switches, which may be magnetic Josephson junction (MJJ) devices. A superconducting switch can exist in a resistive state or a superconducting state. Only one of the two states is persistent, while the other state may only be engaged when a magnetic field is applied to the superconducting switch. Certain examples also relate to using the superconducting switch as part of a driver (e.g., a write wordline driver) for Josephson magnetic random access memory (JMRAM). Certain examples also relate to using reciprocal quantum logic (RQL)-compatible superconducting switches and circuits. Unlike CMOS transistors, RQL circuits are superconducting circuits that use Josephson junction-based devices. An exemplary Josephson junction may include two superconductors coupled via a region that blocks supercurrent. The region that blocks supercurrent may be the superconductor itself, a metallic region, or a physical narrowing of a thin insulating barrier. For example, a superconductor-insulator-superconductor (SIS) type Josephson junction may be implemented as part of an RQL circuit. For example, a superconductor is a material that can carry direct current (DC) in the absence of an electric field. Superconductors such as niobium have a critical temperature (Tc), below which their electrical resistance is zero. Niobium, one such superconductor, has a critical temperature (Tc) of 9.3 degrees Kelvin. Below Tc, niobium exhibits superconductivity; however, above Tc, it behaves like a resistive ordinary metal. Therefore, in an SIS-type Josephson junction, the superconductor can be a niobium superconductor, and the insulator can be an Al2O3 barrier. In an SIS-type junction, superconducting electrons are described by a quantum mechanical wave function. The phase difference between the superconducting electron wave functions of the two superconductors over time corresponds to the potential difference between the two superconductors. In an RQL circuit, in one example, an SIS-type junction can be part of a superconducting loop. When the potential difference between the two superconductors is integrated with respect to time over a phase transition period, the magnetic flux through the loop will vary by an integer multiple of a single flux quantum. The voltage pulse associated with a single flux quantum is called a single flux quantum (SFQ) pulse. For example, an overdamped Josephson junction can produce individual single-flux quantum (SFQ) pulses. In an RQL circuit, each Josephson junction can be part of one or more superconducting loops. The phase difference across the junction can be adjusted by applying a magnetic flux to the loop.

[0018] Various RQL circuits, including transmission lines, can be formed as needed by coupling multiple Josephson junctions using inductors or other components. SFQ pulses can travel through these transmission lines under the control of at least one clock. SFQ pulses can be positive or negative. For example, when a sinusoidal bias current is supplied to the junction, both positive and negative pulses can travel to the right on the transmission line during opposite clock phases. Because there are no bias resistors, the RQL circuit advantageously has zero quiescent power consumption. Furthermore, the RQL circuit can be powered using an alternating current (AC) power supply, eliminating ground loop currents. The AC power supply also serves as a stable clock reference signal for the RQL circuit. In one example, digital data can be encoded using a pair of positive and negative (inverse) SFQ pulses. For example, a logical one bit can be encoded as a pair of inverse SFQ pulses generated in the positive and negative phases of a sinusoidal clock. A logical zero bit can be encoded by the absence of a positive / negative pulse pair within a clock cycle. A positive SFQ pulse can arrive during the positive portion of the clock, while a negative pulse can arrive during the negative portion of the clock.

[0019] The building blocks of an exemplary RQL circuit may include various types of logic gates. Exemplary logic gates include AND gates, OR gates, logic A and NOT B (AanB) gates, and logic AND and OR gates (AndOr). The AanB gate may have two inputs and one output (Q). Input pulse A may propagate to output Q unless pulse B arrives first. The AndOr gate may have two inputs and two outputs (Q1 and Q2). The first input pulse (input pulse A or input pulse B) arrives at output Q1, and the second input pulse arrives at output Q2. The logical behavior of these gates may be based on the reciprocal data encoding mentioned above. For example, a positive pulse changes the internal flux state of the inductive loop, but a trailing negative pulse erases the internal state at each clock cycle, resulting in combinational logic behavior.

[0020] An example superconducting switch can allow supercurrent to flow in one state but restrict supercurrent in a second state. Only one of these two states is stable, and the other state can only be activated by applying a magnetic field to the superconducting switch. The stable state can be determined by the arrangement of ferromagnetic materials in the superconducting switch. Unlike other switches that may require a person to actively open it and actively close it, the example superconducting switch may automatically return to one of the states (open or closed) when no magnetic field is applied to the switch. This can advantageously reduce the amount of power consumed by a driver or other circuit that may use such a superconducting switch.

[0021] Figure 1A is a top view 110 of a schematic diagram of a superconducting switch 100 according to one example, and Figure 1B1 is a side view 120 of a schematic diagram of a superconducting switch 100 according to one example. The superconducting switch may include a ferromagnetic superconducting valve (FS valve) 114 that may be configured to allow (or not allow) a supercurrent to flow through a wire 112 coupled to the FS valve 114. Another wire 116 may be inductively coupled to the FS valve 114 such that current flowing through the wire 116 may be used to change the magnetization state of at least one layer of the FS valve 114.

[0022] Figure 2A and Figure 2B The structure of an FS valve 200 for use in a superconducting switch and the magnetization states of the magnetic layers in the FS valve are shown according to one example. In this example, the FS valve 200 may include a superconducting layer 212, a free magnetic layer 214, a fixed magnetic layer 216, and another superconducting layer 218. In this example, the free magnetic layer 214 has perpendicular magnetic anisotropy (PMA), such that the magnetization of the free magnetic layer 214 points in a direction perpendicular to the plane of the FS valve 200. In contrast, the magnetization of the fixed magnetic layer 216 points in the same direction as the plane of the FS valve 200. In this example and elsewhere in this disclosure, the term "free magnetic layer" means that the magnetization of the magnetic layer is free to change, and the term "fixed magnetic layer" means that the magnetization of the magnetic layer is fixed.

[0023] Figure 2A shows that in the absence of an external magnetic field (H ext ) is applied to the FS valve 200 in state 210 of the free magnetic layer 214. In this state, the superconducting switch comprising the FS valve 200 is in an off state. This is because, in this state, no supercurrent flows through the FS valve 200. In terms of the basic operation of the FS valve 200, no supercurrent flows because, when the superconducting layers 212 and 218 are in the singlet superconducting state, the free magnetic layer 214 and the fixed magnetic layer 216 are in the triplet superconducting state. In the singlet superconducting state, one of a pair of trapped electrons can have an upward spin, while the other of the pair can have a downward spin, or vice versa. In the triplet superconducting state, the trapped electron pair can have perfectly aligned spins, allowing both electrons to have either an upward or downward spin. The layer in the singlet superconducting state does not support electron pairs in the triplet superconducting state. This maintains the FS valve 200 in a resistive state, and no supercurrent flows through the FS valve 200.

[0024] Figure 2B shows that when an external magnetic field (H ext =H1). For example, an external magnetic field can be applied using the wire 116, as described with respect to Figures 1A-1BIn this example, the application of an external magnetic field bends the magnetization of the free magnetic layer 214 so that it aligns with the magnetization of the fixed magnetic layer 216. The alignment of the magnetizations of these layers creates a transient state that allows electron pairs in a singlet superconducting state to pass through the magnetic layers, including the free magnetic layer 214 and the fixed magnetic layer 216. Figure 2C The response of the free magnetic layer 214 of the FS valve 200 to an external magnetic field (H ext ) changes in the magnitude of the supercurrent (Ic) 252 flowing through the FS valve 200.

[0025] Continue to refer Figure 2A and Figure 2B , superconducting layers 212 and 218 may be formed using niobium. Free magnetic layer 214 may be formed using a multilayer stack comprising nickel and cobalt or cobalt and palladium. Alternatively, free magnetic layer 214 may be formed by growing iron and platinum on a chromium seed layer. Alloys may also be used to form free magnetic layer 214. For example, free magnetic layer 214 may be an alloy comprising cobalt and palladium (e.g., Co 50 Pd 50 ). The fixed magnetic layer 216 may be formed using a metal such as nickel. Alternatively, the fixed magnetic layer 216 may be formed using an alloy including an alloy containing nickel and iron, an alloy containing nickel, iron, and cobalt, or an alloy containing nickel, iron, and chromium. Although Figure 2A and Figure 2B While a certain number of layers are shown arranged in a certain manner, FS valve 200 may include additional layers. For example, the additional layers may include at least one insulating barrier layer (e.g., an aluminum oxide, aluminum nitride, or tantalum oxide barrier layer). The presence of the insulating barrier layer may increase the resistance of FS valve 200. Without such an insulating barrier layer, the FS valve may only have a resistance in the milliohms, while the addition of the insulating barrier layer may increase the resistance by up to three orders of magnitude. This allows for greater flexibility in impedance matching the FS valve to circuits that may have varying impedance requirements.

[0026] Figure 3A and Figure 3B Another structure of an FS valve 300 according to one example is shown. In this example, the FS valve 300 may include a superconducting layer 312, a fixed magnetic layer 314, a free magnetic layer 316, another fixed magnetic layer 318, and another superconducting layer 320. In this example, the free magnetic layer 316 has perpendicular magnetic anisotropy (PMA), such that the magnetization of the free magnetic layer 314 points in a direction perpendicular to the plane of the FS valve 300. In contrast, the magnetization of the fixed magnetic layer 314 and the magnetization of the fixed magnetic layer 318 point in the same direction as the plane of the FS valve 300. Figure 3A shows that in the absence of an external magnetic field (H ext) is applied to the free magnetic layer 316 in the state 310 of the FS valve 300. In this state, the superconducting switch including the FS valve 300 is in the on state. This is because, even without an external magnetic field (e.g., H ext ) is applied to FS valve 300, and a supercurrent also flows through FS valve 300. In terms of the basic operation of FS valve 300, a supercurrent flows because, when superconducting layers 312 and 318 are in a singlet superconducting state and free magnetic layer 316 is in a triplet superconducting state, fixed magnetic layer 314 converts the current from the singlet superconducting type to the triplet superconducting type, and fixed magnetic layer 318 converts the current from the triplet superconducting type back to the singlet superconducting type. This keeps FS valve 300 in the "on" state, and a supercurrent flows through FS valve 300.

[0027] Figure 3B shows that when an external magnetic field (H ext =H1). For example, an external magnetic field can be applied using the wire 116, as described with respect to Figures 1A-1B In this example, the application of an external magnetic field bends the magnetization of the free magnetic layer 316 so that it aligns with the magnetizations of the fixed magnetic layer 314 and the fixed magnetic layer 318. The alignment of the magnetizations of these layers achieves a transient state that prevents electron pairs in a singlet superconducting state from traversing the magnetic layers, including the fixed magnetic layer 314, the free magnetic layer 316, and the fixed magnetic layer 318. Figure 3C The response of the free magnetic layer 316 of the FS valve 300 to an external magnetic field (H ext ) changes in the magnitude of the supercurrent (Ic) 352 flowing through the FS valve 300.

[0028] Continue to refer Figure 3A and Figure 3B , superconducting layers 312 and 320 may be formed using niobium. Free magnetic layer 316 may be formed using a multilayer stack including nickel and cobalt or cobalt and palladium. Alternatively, free magnetic layer 316 may be formed by growing iron and platinum on a chromium seed layer. Alloys may also be used to form free magnetic layer 316. For example, free magnetic layer 316 may be an alloy including cobalt and palladium (e.g., Co 50 Pd 50 ). Each of the fixed magnetic layers 314 and 318 may be formed using a metal such as nickel. Alternatively, each of the fixed magnetic layers 314 and 318 may be formed using an alloy including an alloy containing nickel and iron, an alloy containing nickel, iron, and cobalt, or an alloy containing nickel, iron, and chromium. Although Figure 3A and Figure 3BWhile a certain number of layers are shown arranged in a certain manner, FS valve 300 may include additional layers. For example, the additional layers may include at least one insulating barrier layer (e.g., an aluminum oxide, aluminum nitride, or tantalum oxide barrier layer). The insulating barrier layer may enhance the resistance of FS valve 300. Without such an insulating barrier layer, the FS valve may only have a resistance in the milliohms, while adding an insulating barrier layer may increase the resistance by up to three orders of magnitude. This allows for greater flexibility in impedance matching the FS valve to circuits that may have varying impedance requirements.

[0029] Figure 4 An example based on Figures 2A-2C The superconducting switch 200 and Figures 3A-3C Schematic diagram of a driver 400 for a superconducting switch 300. In this example, the driver 400 can be used to drive a superconducting circuit, including a superconducting circuit based on RQL logic. The driver 400 can include two branches 408 and 410; one of the branches (e.g., branch 408) can include a superconducting switch 404, which can be implemented as Figures 3A-3C Another branch of the driver 400 (eg, branch 410) may include a superconducting switch 406, which may be implemented as Figures 2A-2C The superconducting switch 200. Figure 4 As shown, the top portion of the branches can be coupled via inductor 402, and the bottom portion can be directly connected. In this example, superconducting switches 404 and 406 can replace a pair of superconducting quantum interference devices (SQUIDs), which can be arranged in parallel branches. In such a conventional driver, the two SQUIDs need to be triggered alternately to drive current through the two branches of the driver circuit. Due to the current trapping in each SQUID, the current cost is 10%; therefore, a conventional driver may only have an efficiency of 90%. In this example, by utilizing these complementary superconducting switches, a more efficient driver can be constructed. Superconducting switch 404 (implemented as superconducting switch 300) will serve as part of the direct channel branch of the driver, while superconducting switch 406 (implemented as superconducting switch 200) will act on the other branch. Then, using a single activation line, both devices can be triggered, allowing one device to direct current into each branch as needed. In addition, conventional drivers with SQUIDs require flux storage and flux dissipation. Advantageously, driver 400 can solve this problem because at least one of the superconducting switches of driver 400 has a persistent resistance state (or open state). In this example, the resistance of the superconducting switch having a persistent resistance state can be used to dissipate any circulating current.

[0030] Figure 5A portion of a memory system 500 including a write word line driver using superconducting switches is shown according to one example. The memory system 500 may include memory cells organized into an array 510 of memory cells. The array 510 of memory cells may include X columns and Y rows (e.g., each of X and Y is an integer greater than at least 16). For example, the rightmost column may include memory cells M 11 522, M 12 524 and M 1Y 526. The column to the left of the rightmost column may include memory cells M 21 528, M 22 530 and M 2Y 532. The leftmost column may include memory cells M X1 534、M X2 536 and M XY 538. The top row may include memory cells M X1 534、M 21 528 and M 11 522. The second row from the top may include memory cells M X2 536、M 22 530 and M 12 524. The bottom row may include memory cells M XY 538、M 2Y 532 and M 1Y 526. An example memory cell may include a first magnetic Josephson junction (MJJ) device in parallel with a second MJJ device. The combination of the two can be configured such that, given the application of an appropriate amount of current bias and magnetic flux, the memory cell can be in a logic "1" state or a logic "0" state. In one example, if the memory cell is in a logic "1" state, the MJJ can transition to a "voltage state" when current is applied via a word line. A sense amplifier 520 coupled to the memory cell can sense the voltage as representing a logic "1" state. The logic "0" state can correspond to a "substantially zero voltage state" such that in the logic "0" state, despite the application of current via the word line, the MJJ can remain in a "substantially zero voltage state." The sense amplifier can sense this as representing a logic "0" state. Typically, a microwave signal (e.g., an SFQ pulse) can be used to control the state of the memory cell. During read / write operations, the word line and bit line can be selectively activated by an SFQ pulse arriving via an address bus. These pulses, in turn, may control wordline and bitline drivers, which may provide wordline and bitline currents to associated memory cells.

[0031] Continue to refer Figure 5, in this example, each memory cell can be coupled to a read word line (e.g., RWL1 for the memory cells in the top row) to perform a read operation. Each memory cell can also be coupled to a read bit line (e.g., RBL1, RBL2, and RBLX) and a write bit line (e.g., WBL1, WBL2, and WBLX). Each memory cell can also be coupled to a write word line (e.g., WWL1 and WWL2 can be coupled to the memory cells in the top row, WWL3 and WWL4 can be coupled to the memory cells in the next row, and WWL2X-1 and WWL2X can be coupled to the memory cells in the bottom row). The memory system 500 can also include drivers 550, 560, and 570 coupled to the common line 540. Each of these drivers can be coupled to a common line 540 in accordance with Figure 4 Driver 550 may be implemented in a similar manner to driver 400. Driver 550 may include an inductor 552 coupled to write word line WWL1. Driver 550 may also include a superconducting switch 554 in one of the branches and a superconducting switch 556 in the other branch. As previously described, superconducting switch 554 (implemented as superconducting switch 300) will act as part of the direct channel branch of driver 550, while superconducting switch 556 (implemented as superconducting switch 200) will act on the other branch. Then, with a single activation line, both switches can be triggered to allow one switch to direct current into each branch as part of driving write word lines WWL1 and WWL2. Driver 560 may include an inductor 562 coupled to write word line WWL3. Driver 560 may also include a superconducting switch 564 in one of the branches and a superconducting switch 566 in the other branch. As previously described, superconducting switch 564 (implemented as superconducting switch 300) will act as part of the direct channel branch of driver 560, while superconducting switch 566 (implemented as superconducting switch 200) will act on the other branch. Then, with a single activation line, both switches can be triggered to allow one switch to direct current into each branch as part of driving write word lines WWL3 and WWL4. Driver 570 can include inductor 572 coupled to write word line WWL2X-1. Driver 570 can also include superconducting switch 574 in one of the branches and superconducting switch 576 in the other branch. As previously described, superconducting switch 574 (implemented as superconducting switch 300) will act as part of the direct channel branch of driver 570, while superconducting switch 576 (implemented as superconducting switch 200) will act on the other branch. Then, through a single activation line, both switches can be triggered to allow one switch to direct current into each branch as part of driving the write word lines WWL2X-1 and WWL2X.

[0032] although Figure 5A certain number of components of the memory system 500 are shown arranged in a certain manner, but there may be a greater or lesser number of components arranged differently. Figure 5 One driver is shown for each write word line, but the drivers may be shared by a larger group of write word lines.

[0033] Figure 6 620 (e.g., Figure 5 The computing system 600 includes a processor 610 (e.g., a memory system 500) and a processor 610. The processor 610 can perform read or write operations on the memory 620 in the manner previously explained. In addition, the processor 610 and the memory 620 can be used in conjunction with other superconducting logic-based devices. Generally, any superconducting device that operates in a cryogenic environment and needs to store instructions or data can include the memory 620. In addition, the processor 610 does not need to be in a cryogenic environment; instead, it can operate at a non-cryogenic temperature. In this example, the memory 620 can be in a separate cryogenic environment and can be coupled to the processor 610 via a connector in a manner that can maintain the cryogenic environment. The memory 620 can be used as part of the storage in a data center to deliver cloud-based services such as software as a service, platform as a service, or other services.

[0034] In summary, the present disclosure relates to a superconducting switch comprising a first superconducting layer and a second superconducting layer. The superconducting switch may further comprise a first magnetic layer having a fixed magnetization state. The superconducting switch may further comprise a second magnetic layer capable of being in at least a first magnetization state or a second magnetization state different from the first magnetization state. The superconducting switch may be capable of being in a first state or a second state, wherein the second state corresponds to an opposite state of the first state, and wherein the superconducting switch is configured such that application of a magnetic field to the second magnetic layer changes the magnetization of the second magnetic layer from the first magnetization state to the second magnetization state, thereby placing the superconducting switch in the second state, and removal of the magnetic field automatically returns the superconducting switch from the second state to the first state.

[0035] The first state may correspond to a persistent state of the superconducting switch, and the second state may correspond to a discontinuous state of the superconducting switch. The superconducting switch may be configured to be in the second state only when a magnetic field is applied to the second magnetic layer. The first state of the second superconducting switch may correspond to an off state, such that no supercurrent can flow between the first superconducting layer and the second superconducting layer in the off state, and the second state of the superconducting switch may correspond to an on state, such that current can flow between the first superconducting layer and the second superconducting layer in the on state. The superconducting switch may further include an insulating layer.

[0036] Each of the first fixed magnetization state and the second fixed magnetization state may correspond to magnetization in a first direction parallel to the plane, and wherein in the first state of the superconducting switch, the first magnetization state of the second magnetic layer may correspond to magnetization in a direction perpendicular to the first direction, and wherein in the second state of the superconducting switch, the first magnetization state of the second magnetic layer may correspond to magnetization in a second direction substantially parallel to the first direction. Each of the first superconducting layer and the second superconducting layer may include at least niobium, and each of the first magnetic layer and the second magnetic layer may include at least one of the following: nickel, iron, or cobalt.

[0037] In another aspect, the present disclosure relates to a superconducting switch comprising a first superconducting layer and a second superconducting layer. The superconducting switch may further comprise a first magnetic layer having a fixed magnetization state. The superconducting switch may further comprise a second magnetic layer capable of being in at least a first magnetization state or a second magnetization state different from the first magnetization state. The superconducting switch may further comprise a third magnetic layer having a second fixed magnetization state. The superconducting switch may further comprise a conductor inductively coupled to the second magnetic layer such that flow of current through the conductor causes application of a magnetic field to the second magnetic layer. The superconducting switch may be capable of being in a first state or a second state, wherein the second state corresponds to an opposite state of the first state, and wherein the superconducting switch is configured such that application of a magnetic field changes the magnetization of the second magnetic layer from the first magnetization state to the second magnetization state, thereby placing the superconducting switch in the second state, and removal of the magnetic field automatically returns the switch from the second state to the first state.

[0038] The first state may correspond to a persistent state of the superconducting switch, and the second state may correspond to a discontinuous state of the superconducting switch. The superconducting switch may be configured to be in the second state only when a magnetic field is applied to the second magnetic layer. The first state of the second superconducting switch may correspond to an on-state, thereby enabling supercurrent to flow between the first superconducting layer and the second superconducting layer in the on-state, and the second state of the second superconducting switch may correspond to an off-state, thereby enabling no supercurrent to flow between the first superconducting layer and the second superconducting layer in the off-state. The superconducting switch may further include an insulating layer.

[0039] Each of the first fixed magnetization state and the second fixed magnetization state may correspond to magnetization in a first direction parallel to the plane, and wherein in the first state of the superconducting switch, the first magnetization state of the second magnetic layer may correspond to magnetization in a direction perpendicular to the first direction, and wherein in the second state of the superconducting switch, the first magnetization state of the second magnetic layer may correspond to magnetization in a second direction substantially parallel to the first direction. Each of the first superconducting layer and the second superconducting layer may include niobium, and wherein each of the first magnetic layer, the second magnetic layer, and the third magnetic layer may include at least one of the following: nickel, iron, or cobalt.

[0040] In another aspect, the present disclosure relates to a memory system comprising a row of memory cells coupled to at least one write word line and a write word line driver coupled to the at least one write word line. The write word line driver may include a superconducting switch. The superconducting switch may include a magnetic layer configured to be in a first magnetization state or a second magnetization state, wherein a first superconducting switch is capable of being in the first state or the second state, and wherein the second state corresponds to an opposite state of the first state, and wherein the first superconducting switch is configured such that application of a magnetic field to the magnetic layer changes the magnetization of the magnetic layer from the first magnetization state to the second magnetization state, thereby placing the first superconducting switch in the second state, and removal of the magnetic field automatically returns the switch from the second state to the first state.

[0041] The write word line driver may further include a first limb and a second limb coupled together, wherein the second limb may be arranged parallel to the first limb, and wherein the first superconducting switch may be arranged along the first limb. The write word line driver may include a second superconducting switch, and wherein the second superconducting switch may be arranged along the second limb.

[0042] The second superconducting switch may include a second magnetic layer configured to be in a third magnetization state or a fourth magnetization state, wherein the second superconducting switch may be capable of being in the third state or the fourth state, and wherein the fourth state may correspond to an opposite state of the third state, and wherein the second superconducting switch is configured such that application of a magnetic field to the second magnetic layer may change the magnetization of the second magnetic layer from the third magnetization state to the fourth magnetization state, thereby placing the second superconducting switch in the fourth state, and removal of the magnetic field may automatically return the switch from the fourth state to the third state.

[0043] The first state of the first superconducting switch may correspond to an off-state, such that no supercurrent can flow through the first superconducting switch in the off-state, and wherein the second state of the first superconducting switch may correspond to an on-state, such that supercurrent can flow through the first superconducting switch in the on-state. The third state of the second superconducting switch may correspond to an on-state, such that supercurrent can flow through the second superconducting switch in the on-state, and wherein the fourth state of the second superconducting switch may correspond to an off-state, such that no supercurrent can flow through the second superconducting switch in the off-state.

[0044] It should be understood that the methods, modules and components described herein are exemplary only. Alternatively or additionally, the functions described herein may be performed at least in part by one or more hardware logic components. For example, and not limitation, illustrative types of hardware logic components that can be used include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), etc. In an abstract but still clear sense, any arrangement of components that implement the same function is effectively "associated" to achieve the desired function. Therefore, any two components combined herein to achieve a specific function can be considered to be "associated" with each other to achieve the desired function, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be considered to be "operably connected" or "coupled" to each other to achieve the desired function.

[0045] Functionality associated with the examples described in this disclosure may also include instructions stored in non-transient media. As used herein, the term "non-transient media" refers to any medium that stores data and / or instructions that cause a machine (such as processor 610) to operate in a particular manner. Exemplary non-transient media include non-volatile media and / or volatile media. Non-volatile media include, for example, hard disks, solid-state drives, magnetic disks or tapes, optical disks or tapes, flash memory, EPROM, NVRAM, PRAM or other such media, or networked versions of such media. Volatile media include, for example, dynamic memories such as DRAM, SRAM, cache or other such media. Non-transient media are distinct from, but may be used in conjunction with, transmission media. Transmission media are used to transmit data and / or instructions to or from a machine. Exemplary transmission media include coaxial cables, fiber optic cables, copper wires, and wireless media, such as radio waves.

[0046] Furthermore, those skilled in the art will recognize that the boundaries between the functions of the above-described operations are merely illustrative. The functions of multiple operations may be combined into a single operation, and / or the functions of a single operation may be distributed among other operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of the operations may vary in various other embodiments.

[0047] Although the present disclosure provides specific examples, various modifications and changes may be made without departing from the scope of the present disclosure as set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems described herein with respect to specific examples should not be construed as a key, required, or essential feature or element of any or all the claims.

[0048] Furthermore, the terms "a" or "an" as used herein are defined as one or more. Likewise, the use of introductory phrases such as "at least one" and "one or more" in a claim should not be construed as implying that the introduction of another claim element by the indefinite article "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "an." The same applies to the use of definite articles.

[0049] Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims

1. A first superconducting switch, comprising: a first superconducting layer; a first magnetic layer having a fixed magnetization state; a second magnetic layer capable of being in at least a first magnetization state or a second magnetization state different from the first magnetization state; as well as a second superconducting layer, wherein the first superconducting switch is capable of being in a first state or a second state, and wherein the second state corresponds to an opposite state of the first state, and wherein the first superconducting switch is configured such that application of a magnetic field to the second magnetic layer changes the magnetization of the second magnetic layer from the first magnetization state to the second magnetization state, thereby placing the first superconducting switch in the second state, and removal of the magnetic field automatically returns the first superconducting switch from the second state to the first state, and The first state is an off state, and the second state is an on state, the first superconducting switch is arranged along a first branch of a write word line driver, in response to the first superconducting switch being placed in the off state, the second superconducting switch arranged along a second branch of the write word line driver is placed in the on state, and in response to the first superconducting switch being placed in the on state, the second superconducting switch is placed in the off state. 2 . The first superconducting switch of claim 1 , wherein the first state corresponds to a sustained state of the first superconducting switch, and wherein the second state corresponds to a non-sustainable state of the first superconducting switch. 3 . The first superconducting switch of claim 2 , wherein the first superconducting switch is configured to be in the second state only when the magnetic field is applied to the second magnetic layer.

4. The first superconducting switch according to claim 1 , wherein in the off-state of the first superconducting switch, no supercurrent can flow between the first superconducting layer and the second superconducting layer, and in the on-state of the first superconducting switch, a supercurrent can flow between the first superconducting layer and the second superconducting layer. The first superconducting switch according to claim 1 , further comprising an insulating layer.

6. The first superconducting switch of claim 1 , wherein the fixed magnetization state corresponds to magnetization in a first direction parallel to a plane, and wherein in the first state of the first superconducting switch, the first magnetization state of the second magnetic layer corresponds to magnetization in a direction perpendicular to the first direction, and wherein in the second state of the first superconducting switch, the second magnetization state of the second magnetic layer corresponds to magnetization in a second direction substantially parallel to the first direction.

7. The first superconducting switch of claim 1, wherein each of the first superconducting layer and the second superconducting layer comprises at least niobium, and wherein each of the first magnetic layer and the second magnetic layer comprises at least one of the following: nickel, iron, or cobalt.

8. A second superconducting switch, comprising: a first superconducting layer; a first magnetic layer having a first fixed magnetization state; a second magnetic layer capable of being in at least a first magnetization state or a second magnetization state different from the first magnetization state; a third magnetic layer having a second fixed magnetization state; a conductor inductively coupled to the second magnetic layer such that flow of current through the conductor results in application of a magnetic field to the second magnetic layer; as well as a second superconducting layer, wherein the second superconducting switch is capable of being in a first state or a second state, and wherein the second state corresponds to an opposite state of the first state, and wherein the second superconducting switch is configured such that application of the magnetic field changes the magnetization of the second magnetic layer from the first magnetization state to the second magnetization state, thereby placing the second superconducting switch in the second state, and removal of the magnetic field automatically returns the switch from the second state to the first state, and The first state is an on state, and the second state is an off state, the second superconducting switch is arranged along the second branch of a write word line driver, in response to the second superconducting switch being placed in the on state, the first superconducting switch arranged along the first branch of the write word line driver is placed in the off state, and in response to the second superconducting switch being placed in the off state, the first superconducting switch is placed in the on state. 9 . The second superconducting switch of claim 8 , wherein the first state corresponds to a sustained state of the second superconducting switch, and wherein the second state corresponds to a non-sustained state of the second superconducting switch. 10 . The second superconducting switch of claim 9 , wherein the second superconducting switch is configured to be in the second state only when the magnetic field is applied to the second magnetic layer.

11. The second superconducting switch according to claim 8 , wherein in the on-state of the second superconducting switch, a supercurrent can flow between the first superconducting layer and the second superconducting layer, and in the off-state of the second superconducting switch, no supercurrent can flow between the first superconducting layer and the second superconducting layer. 12 . The second superconducting switch according to claim 8 , further comprising an insulating layer.

13. The second superconducting switch of claim 8 , wherein each of the first fixed magnetization state and the second fixed magnetization state corresponds to magnetization in a first direction parallel to a plane, and wherein in the first state of the second superconducting switch, the first magnetization state of the second magnetic layer corresponds to magnetization in a direction perpendicular to the first direction, and wherein in the second state of the second superconducting switch, the first magnetization state of the second magnetic layer corresponds to magnetization in a second direction substantially parallel to the first direction.

14. The second superconducting switch of claim 8, wherein each of the first superconducting layer and the second superconducting layer comprises niobium, and wherein each of the first magnetic layer, the second magnetic layer, and the third magnetic layer comprises at least one of the following: nickel, iron, or cobalt.

15. A memory system comprising: a row of memory cells coupled to at least one write word line; as well as a write word line driver coupled to the at least one write word line, wherein the write word line driver comprises: a first superconducting switch disposed along a first branch of the write wordline driver, and comprising a magnetic layer configured to be in a first magnetization state or a second magnetization state, wherein the first superconducting switch is capable of being in the first state or the second state, and wherein the second state corresponds to an opposite state of the first state, and wherein the first superconducting switch is configured such that application of a magnetic field to the magnetic layer changes the magnetization of the magnetic layer from the first magnetization state to the second magnetization state, thereby placing the first superconducting switch in the second state, and removal of the magnetic field automatically returns the switch from the second state to the first state, and The first state is an off state, and the second state is an on state. In response to the first superconducting switch being placed in the off state, a second superconducting switch arranged along the second branch of the write word line driver is placed in the on state. In response to the first superconducting switch being placed in the on state, the second superconducting switch is placed in the off state.

16. The memory system of claim 15, wherein the write word line driver further comprises the first branch and the second branch being coupled, wherein the second branch is arranged parallel to the first branch, and wherein the first superconducting switch is arranged along the first branch. 17 . The memory system of claim 16 , wherein the write word line driver comprises the second superconducting switch, and wherein the second superconducting switch is arranged along the second branch.

18. The memory system of claim 17 , wherein the second superconducting switch comprises a second magnetic layer, the second magnetic layer being configured to be in a third magnetization state or a fourth magnetization state, wherein the second superconducting switch is capable of being in the third state or the fourth state, and wherein the fourth state corresponds to an opposite state of the third state, and wherein the second superconducting switch is configured such that application of a magnetic field to the second magnetic layer changes the magnetization of the second magnetic layer from the third magnetization state to the fourth magnetization state, thereby placing the second superconducting switch in the fourth state, and removal of the magnetic field automatically returns the switch from the fourth state to the third state.

19. The memory system of claim 18, wherein in the off-state of the first superconducting switch, no supercurrent can flow through the first superconducting switch, and wherein in the on-state of the first superconducting switch, a supercurrent can flow through the first superconducting switch.

20. The memory system of claim 19, wherein the third state of the second superconducting switch corresponds to the on-state, such that a supercurrent can flow through the second superconducting switch in the on-state, and wherein the fourth state of the second superconducting switch corresponds to the off-state, such that no supercurrent can flow through the second superconducting switch in the off-state.

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