Semiconductor device and method of forming the same

Abstract

The semiconductor device includes a substrate. A gate structure is disposed above the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction. Embodiments of the present application also relate to a method of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling process typically provides benefits by increasing production efficiency and reducing associated costs. This scaling also increases the complexity of processing and manufacturing ICs.

[0003] For example, methods have been developed to form gate spacers with a low dielectric constant, such as air spacers. However, as device sizes continue to decrease, conventional methods of forming air spacers may cause problems, such as gate structure collapse, undesirable etch by-products, excessive damage to other components, etc. Thus, while conventional methods of forming low-k dielectric gate spacers have generally been adequate, they have not been satisfactory in all respects. Summary of the Invention

[0004] Some embodiments of the present application provide a semiconductor device, comprising: a substrate; a gate structure disposed above the substrate in a vertical direction, wherein the gate structure extends in a first horizontal direction; and an air spacer disposed adjacent to a first portion of the gate structure in a second horizontal direction different from the first horizontal direction, wherein the air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

[0005] Other embodiments of the present application provide a semiconductor device, comprising: a substrate; a gate structure located above the substrate in a vertical direction, wherein the gate structure extends in a first horizontal direction; an air spacer extending in the first horizontal direction, wherein the air spacer is separated from the gate structure in a second horizontal direction different from the first horizontal direction, wherein the air spacer is located adjacent to a first segment of the gate structure; and a first dielectric spacer extending in the second horizontal direction, wherein the first dielectric spacer is located adjacent to a second segment of the gate structure, and wherein the first dielectric spacer and the air spacer form a boundary.

[0006] Some other embodiments of the present application provide a method of forming a semiconductor device, including: forming a gate structure over a substrate, wherein the gate structure includes at least a first dielectric spacer and a second dielectric spacer, and wherein, in a top view, each of the gate structure, the first dielectric spacer, and the second dielectric spacer extends in a first horizontal direction; forming a patterned hard mask structure over the gate structure, wherein the patterned hard mask structure defines an opening exposing a portion of the gate structure; and performing an etching process through the opening to form an air spacer by at least partially removing the first dielectric spacer, wherein the patterned hard mask structure serves as an etching mask during the etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for the sake of clear discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 is a perspective view of a FinFET device in accordance with various aspects of the present invention.

[0009] Figure 2A is a cross-sectional view of an embodiment of a FinFET device at various stages of manufacture in accordance with various aspects of the present invention.

[0010] Figure 2B is a top view of an embodiment of a FinFET device at various stages of manufacture in accordance with various aspects of the present invention.

[0011] Figure 3 and Figures 3A to 7 is a cross-sectional view of an embodiment of a FinFET device at various stages of manufacture in accordance with various aspects of the present invention.

[0012] Figures 8 to 9 is a top view of a portion of an IC layout in accordance with various aspects of the present invention.

[0013] Figures 10 to 11 is a top view of a portion of an IC at various stages of manufacture in accordance with various aspects of the present invention.

[0014] Figure 12 shows a circuit diagram of a ring oscillator.

[0015] Figure 13 is a circuit diagram of a SRAM in accordance with various aspects of the present invention.

[0016] Figure 14 shows an integrated circuit manufacturing system in accordance with an embodiment of the present invention.

[0017] Figure 15 is a flowchart of a method of manufacturing a semiconductor device in accordance with various aspects of the present invention. Detailed Description

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components are not in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Further, in the present invention hereinafter, the formation of a component on, connected to, and / or coupled to another component may include embodiments where the components are formed in direct contact, and may include embodiments where additional components may intervene between the components such that the components are not in direct contact. In addition, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "on", "above", "below", "beneath", "up", "down", "top", "bottom", and derivatives thereof (e.g., "horizontally", "downwardly", "upwardly", etc.) are used to facilitate an understanding of the relationship of one component of the present invention to another component. The spatial relative terms are intended to encompass different orientations of the components of the device. Still further, when a numerical value or numerical range is described using "about", "substantially", etc., the term is intended to cover a numerical value within a reasonable range including the recited value, such as within + / - 10% of the numerical value or other values understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0020] The present invention generally relates to semiconductor devices, and more particularly to field effect transistors (FETs), such as planar FETs or three-dimensional fin FETs (FinFETs). One aspect of the present invention relates to forming a high-k metal gate spacer as part of the manufacture of a semiconductor device.

[0021] During the fabrication of a FinFET structure, an air gap (referred to as an air spacer) can be formed instead of a gate spacer disposed on the sidewalls of a gate structure (e.g., a high-k metal gate (HKMG) structure). In some embodiments, the air spacer formed between the gate structure and an additional dielectric layer in the active device region reduces the capacitance of the gate structure, thereby improving the overall performance (e.g., speed) of the FinFET structure. However, conventional methods of forming air spacers may still need improvement. For example, it may be difficult to form an air spacer with a high aspect ratio (e.g., the ratio of the height to the width of a trench) without causing the gate structure to wobble or collapse. As another example, conventional air spacer formation processes may cause damage to certain other components such as shallow trench isolation (STI) structures. As yet another example, conventional air spacer formation processes may generate undesirable etch by-products, which may affect device performance.

[0022] Many of these problems discussed above stem from the fact that conventional air spacer formation processes form air spacers that are used indiscriminately for all types of IC devices. However, in practical applications, certain types of IC devices (e.g., ring oscillators) may benefit more from having air spacers, while other types of IC devices (SRAM) may not require air spacers. The present invention takes this into account before forming air spacers and thus forms air spacers for IC devices that need them, but does not form air spacers for IC devices that may not need them. In other words, the present invention selectively forms air spacers for a specific type of IC device on a wafer, without forming air spacers for the remaining IC devices on the wafer. In some embodiments, lithography can be used to pattern a hard mask to achieve the formation of selective air spacers, and the patterned hard mask can be used to define the regions in the wafer where air spacers are to be formed. The formation of selective air spacers alleviates the problem of gate structure wobbling or collapse, reduces undesirable etch by-products, and alleviates damage to the STI structure. Various aspects of the present invention are discussed in more detail below.

[0023] Reference Figure 1, a perspective view of an exemplary FinFET device 10 is shown. The FinFET device structure 10 includes an N-type FinFET device structure (NMOS) 15 and a P-type FinFET device structure (PMOS) 25. The FinFET device structure 10 includes a substrate 102. The substrate 102 may be made of silicon or other semiconductor materials. Optionally or additionally, the substrate 102 may include other elemental semiconductor materials, such as germanium. In some embodiments, the substrate 102 is made of a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate 102 is made of an alloy semiconductor, such as silicon germanium, silicon carbide germanium, gallium phosphoarsenide, or gallium indium phosphide. In some embodiments, the substrate 102 includes an epitaxial layer. For example, the substrate 102 may include an epitaxial layer over a bulk semiconductor.

[0024] The FinFET device structure 10 further includes one or more fin structures 104 (e.g., Si fins) extending from the substrate 102 in the Z direction and surrounded by spacers 105 in the Y direction. The fin structures 104 are elongated in the X direction and may optionally include germanium (Ge). The fin structures 104 may be formed by using appropriate processes, such as lithography and etching processes. In some embodiments, the fin structures 104 are etched from the substrate 102 using a dry etching or plasma process. In some other embodiments, the fin structures 104 may be formed by a multiple patterning lithography process, such as a double patterning lithography (DPL) process. DPL is a method of constructing a pattern on a substrate by dividing the pattern into two interleaved patterns. DPL allows for an increased density of components (e.g., fins). The fin structures 104 further include an epitaxial growth material 120, which may (along with portions of the fin structures 104) be used as the source / drain of the FinFET device structure 10.

[0025] An isolation structure 108 (such as a shallow trench isolation (STI) structure) is formed to surround the fin structures 104. In some embodiments, the lower portions of the fin structures 104 are surrounded by the isolation structure 108, and the upper portions of the fin structures 104 protrude from the isolation structure 108, as Figure 1 shown. In other words, portions of the fin structures 104 are embedded in the isolation structure 108. The isolation structure 108 prevents electrical interference or crosstalk.

[0026] The FinFET device structure 10 further includes a gate stack structure, including a gate electrode 110 and a gate dielectric layer (not shown) under the gate electrode 110. The gate electrode 110 may include polysilicon or metal. The metal includes tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other suitable materials. The gate electrode 110 may be formed in a back-gate process (or gate replacement process). Hard mask layers 112 and 114 may be used to define the gate electrode 110. One or more dielectric layers 115 may also be formed on the sidewalls of the gate electrode 110 and above the hard mask layers 112 and 114. In at least one embodiment, the dielectric layer 115 may be in direct contact with the gate electrode 110. One or more dielectric layers 115 may be patterned to form gate spacers, and some of the gate spacers may be removed to form air spacers according to the present invention, as discussed in more detail below.

[0027] The gate dielectric layer (not shown) may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a dielectric material with a high dielectric constant (high-k), or a combination thereof. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, hafnium-aluminum oxide alloy, hafnium-silicon oxide, hafnium-silicon oxynitride, hafnium-tantalum oxide, hafnium-titanium oxide, hafnium-zirconium oxide, etc., or a combination thereof.

[0028] In some embodiments, the gate stack structure includes additional layers, such as an interface layer, a capping layer, a diffusion / barrier layer, or other suitable layers. In some embodiments, the gate stack structure is formed above the central portion of the fin structure 104. In some other embodiments, multiple gate stack structures are formed above the fin structure 104. In some other embodiments, the gate stack structure includes a dummy gate stack and is later replaced by a metal gate (MG) after implementing a high thermal budget process.

[0029] The gate stack structure is formed by a deposition process, a lithography process, and an etching process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metalorganic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), plating, other suitable methods, and / or combinations thereof. The lithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking). The etching process includes a dry etching process or a wet etching process. Optionally, the lithography process may be implemented or replaced by other appropriate methods, such as maskless lithography, electron beam writing, and ion beam writing.

[0030] Figure 2A is a schematic partial cross-sectional side view of a portion of a semiconductor device 200 along the X-Z plane. In some embodiments, a cross-sectional cut is taken corresponding to Figure 1 the position of the tangent line A-A' shown. Since the tangent line A-A' extends in the X direction, Figure 2A it may also be referred to as an X cut. For reasons of consistency and clarity, components similar to those that appear in Figure 1 are labeled the same in Figure 2A here.

[0031] Figure 2A A portion of the fin structure 104 and an epitaxial layer 120 grown on the fin structure 104 are shown. An interlayer dielectric (ILD) structure 210 is disposed above the epitaxial layer 120. A cap structure 220 is disposed above the ILD structure 210.

[0032] Meanwhile, a gate dielectric layer 106 is disposed above the fin structure 104. In some embodiments, the gate dielectric layer 106 includes a high-k gate dielectric (e.g., a material having a dielectric constant greater than about 4). As a non-limiting example, the high-k gate dielectric may include: hafnium oxide, zirconium oxide, aluminum oxide, hafnium-aluminum oxide alloy, hafnium silicate, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, etc. or a combination thereof. It should be understood that the gate dielectric layer 106 may also include an interfacial layer (IL) (or formed above the interfacial layer), which may include, as a non-limiting example, silicon oxide. For simplicity, the IL is not shown separately here. The gate dielectric layers 106 may each have a U shape because they may be formed by filling an opening left due to the removal of a dummy gate structure. Then a gate electrode 110 is formed above the gate dielectric layer 106. The gate electrode 110 and the gate dielectric layer 106 may be collectively referred to as a gate structure, e.g., a high-k metal gate (HKMG) structure.

[0033] A gate spacer structure 250 is disposed on the sidewalls of the gate dielectric layer 106. The gate spacer structure 250 may be formed by patterning one or more of the dielectric layers 115 discussed above with reference to Figure 1 here. In some embodiments, the gate spacer structure 250 may include a dielectric spacer 260 disposed directly on the sidewalls of the gate electrode 110, an air spacer 270 disposed adjacent to the dielectric spacer 260, and a dielectric spacer 280 disposed adjacent to the air spacer 270. The dielectric spacer 260 is substantially thinner in the X direction than the air spacer 270 and the dielectric spacer 280, e.g., many times thinner. In some embodiments, the air spacer 270 is formed after the HKMG structure is formed. However, it should be understood that this is not intended to be limiting, as the air spacer 270 may also be formed before the HKMG structure is formed.

[0034] Since the air spacer 270 is disposed between the dielectric spacer 260 and the dielectric spacer 280, the dielectric spacer 260 may also be referred to as an internal dielectric spacer, the dielectric spacer 280 may also be referred to as an external dielectric spacer, and the air spacer 270 may also be referred to as an intermediate spacer. Although the air spacer 270 includes air (which is technically a dielectric material), the dielectric spacer 260 and the dielectric spacer 280 may each include one or more dielectric materials different from air, such as silicon carbonitride (SiCN), silicon oxynitride (SiCON), or a suitable low-k dielectric material other than air (e.g., a dielectric material having a dielectric constant less than about 4).

[0035] In some embodiments, the air spacer 270 may be formed by removing a non-air dielectric material that may have been initially formed in place of the air spacer 270. Such a dielectric material may have a different material composition from the spacers 260 and 280. For example, the dielectric material may include silicon oxide, while the dielectric spacer 260 and the dielectric spacer 280 may include SiCN, SiCON, or a low-k material. Subsequently, the air spacer 270 may be formed by selectively removing the dielectric material with substantially no effect on the dielectric spacer 260 and the dielectric spacer 280. Due to their different material compositions, an etching process may be implemented using the etching selectivity between the dielectric material to be removed and other materials (such as the dielectric spacers 260 and 280). As will be discussed in more detail below, Figure 3 an embodiment of such a dielectric material before it is removed to form the air spacer 270 is shown.

[0036] Still referring to Figure 2A , the air spacer 270 has a high aspect ratio (e.g., greater than 10:1), which is the ratio of its depth (measured in the Z direction) divided by its width (measured in the X direction). Such a high aspect ratio means that it is difficult to form the air spacer 270 and, if appropriate measures are not taken to avoid it, may cause damage to the rest of the semiconductor device 200 as not expected.

[0037] Figure 2B A top view of the semiconductor device 200 is shown to further illustrate the concept of the present invention. It should be understood that Figure 2A the cross-sectional view of Figure 2B is taken along the tangent C-C' of Figure 2BAs shown, a gate structure including a gate dielectric layer 106 and a gate electrode 110 is formed over active regions 550 - 551 that may include fin structures. The gate dielectric layer 106 and the gate electrode 110 each extend in the Y direction, while the active regions 550 - 551 each extend in the X direction. Gate spacers 260, 275, and 280 are also formed on sidewalls of the gate dielectric layer 106. However, a portion of the gate spacer 275 is removed to form an air spacer 270 in a selected region. The gate spacer 275 and the air spacer 270 form a boundary or interface 500A, which is one of the unique physical characteristics of the present invention. As will be discussed in more detail below, selectively forming the air spacer 270 will improve device fabrication and performance.

[0038] According to various aspects of the present invention, forming the air spacer 270 involves using a lithography process to pattern a hard mask structure, which is then used to define a region of the wafer where the air spacer (such as the air spacer 270) is to be formed. Such a selective air spacer formation scheme helps avoid many problems associated with conventional air spacer formation processes, as will be discussed in more detail below.

[0039] Figures 3 to 7 is a schematic partial cross-sectional side view of a portion of a semiconductor device 200 along the Y-Z plane. In some embodiments, the cross-section corresponds to Figure 1 the position of the tangent line B-B’ shown. Since the tangent line B-B’ extends in the Y direction, Figures 3 to 7 it can also be referred to as a Y cut. For reasons of consistency and clarity, components similar to those that appear in Figure 1 are labeled the same in Figures 3 to 7 .

[0040] Referring to Figure 3 , a plurality of fin structures 104A - 104F project vertically from a substrate 102. Some of these fin structures 104A - 104F may be fin structures for NFETs, while some of these fin structures 104A - 104F may be fin structures for PFETs. It should be understood that an epitaxial layer, such as the epitaxial layer 120 (see Figure 1 or Figure 2A ), may be grown epitaxially on the fin structures 104A - 104F. However, since Figure 3 the cross-section in Figure 1 is taken at the tangent line B-B’ (see Figure 3 ), which is a region outside where the epitaxial layer 120 is grown, the epitaxial layer is not visible in

[0041] The dielectric spacer layer 300 is vertically disposed above the isolation structure 108 and above the fin structures 104A - 104F in the Z direction. The dielectric spacer layer 300 can be formed by patterning one of the dielectric layers 115 discussed above. In some embodiments, the dielectric spacer layer 300 includes a material composition similar to (or the same as) the isolation structure 108. Due to their substantially similar (or even identical) material compositions, if appropriate measures are not taken to avoid it, etching the dielectric spacer layer 300 may also damage the isolation structure 108 unexpectedly. In some embodiments, the dielectric spacer layer 300 can include silicon oxide. In other embodiments, the dielectric spacer layer 300 can each include a low-k dielectric material.

[0042] The dielectric spacer layer 300 is also a dielectric layer disposed between Figure 2A the dielectric spacers 260 and 280. Figures 3 to 7 And the following discussion explains how to at least partially remove the dielectric spacer layer 300 according to various aspects of the present invention to form Figure 2A the air spacer 270. Similarly, due to the Y-cut corresponding to the cross-sectional view of Figure 3 (e.g., along the tangent B - B' in Figure 1 ), the metal gate electrode itself or the epitaxial layer may not be directly visible in Figure 3 .

[0043] Still referring to Figure 3 , a hard mask layer 310 is formed above the dielectric spacer layer 300, a hard mask layer 320 is formed above the hard mask layer 310, and a hard mask layer 330 is formed above the hard mask layer 320. The hard mask layer 310 has a different material composition from the gate electrode 110 (see Figures 1 to 2A ), so that the etching selectivity can be configured to exist between the hard mask layer 310 and the gate electrode 110. In some embodiments, the etching selectivity between the hard mask layer 310 and the gate electrode 110 is greater than or equal to 2:1, which means that in the etching process, the etching rate for the hard mask layer 310 is at least twice the etching rate for the gate electrode 110 (and vice versa).

[0044] The hard mask layer 330 has a different material composition from the hard mask layer 320, so that the etching selectivity can be configured to exist between the hard mask layer 330 and the hard mask layer 320. In some embodiments, the etching selectivity between the hard mask layer 330 and the hard mask layer 320 is greater than or equal to 2:1, which means that in the etching process, the etching rate for the hard mask layer 330 is at least twice the etching rate of the hard mask layer 320 (and vice versa). In some embodiments, the etching selectivity between the hard mask layer 330 and the hard mask layer 310 is also greater than or equal to 2:1.

[0045] In some embodiments, the hard mask layer 310 may include silicon nitride, silicon oxide, or silicon oxynitride, the hard mask layer 320 may include silicon nitride, silicon oxide, or silicon oxynitride, and the hard mask layer 330 may include silicon nitride, silicon oxide, or silicon oxynitride.

[0046] A three-layer photoresist 350 is formed over the hard mask layer 330. The three-layer photoresist 350 may include a bottom layer 360, an intermediate layer 370, and a top layer 380. In some embodiments, the bottom layer 360 includes an anti-reflective coating material and may thus be referred to as a bottom anti-reflective coating (BARC). Using a lithography process, which may include one or more steps such as photoresist coating, exposure, post-exposure bake, development, hard bake, etc., the top layer 380 may be patterned into a plurality of segments such as segments 381, 382, and 383. The segments 381 - 383 define openings 390 and 391.

[0047] Figure 3A A stacked cross-sectional view showing different cross-sections of the semiconductor device 200 is presented. In addition to Figure 3 the cross-sectional view of, Figure 3A the epitaxial layer 120 stacked over the fin structures 104A - 104F is shown. Since the epitaxial layer 120 is formed outside the gate structure, the epitaxial layer 120 is not directly visible in the Figure 3 cross-sectional view of. Thus, Figure 3A the epitaxial layer 120 is shown to assist the reader in understanding the relative positions and arrangements of the respective layers.

[0048] Now referring to Figure 4 , a hard mask etching process 400 is performed on the semiconductor device 200. The etching process 400 may include a wet etching process in some embodiments or a dry etching process in other embodiments. The pattern defined by the segments 381 - 383 of the top layer 380 of the three-layer photoresist 350 is transferred to the bottom layer 360, which is used to pattern the underlying hard mask layers 330 and 320. It should be understood that two or more types of etchants may be used in the etching process. For example, a first type of etchant may be used in etching the hard mask layer 330, and a second type of etchant may be used for etching the hard mask 320. In any case, the openings 390 and 391 are etched vertically through the hard mask layers 330 and 320, and a portion of the hard mask layer 310 is exposed. Due to the etching selectivity between the hard mask layer 310 and the hard mask layers 320 and 330, the hard mask etching process 400 can "open" the hard mask layers 330 and 320 with substantially no effect on the hard mask layer 310. In this way, the hard mask layer 310 can be used as an etch stop layer for the hard mask etching process 400 herein.

[0049] Now referring to Figure 5, a BARC removal process 420 is performed on the semiconductor device 200 to remove the remaining segments of the underlying layer 360. In some embodiments, the BARC removal process 420 includes a photoresist stripping or ashing process. Note that the BARC removal process 420 is performed while the hard mask layer 310 is still in place. Thus, the hard mask layer 310 serves as a protective layer for the underlying layers during the BARC removal process 420, which prevents the underlying layers from being damaged during the BARC removal process 420.

[0050] Now referring to Figure 6 , a hard mask etching process 450 is performed on the semiconductor device 200 to vertically etch openings 390 and 391 through the hard mask layer 310. In other words, the hard mask etching process 450 "opens" the hard mask layer 310, thereby exposing regions of the dielectric spacer layer 300. Due to the etching selectivity between the hard mask layer 310 and 330, the hard mask etching process 450 can substantially remove the hard mask layer 310 while the hard mask layer 330 remains substantially unaffected. In some embodiments, the hard mask etching process 450 includes a wet etching process. In other embodiments, the hard mask etching process 450 includes a dry etching process.

[0051] Now referring to Figure 7 , an air spacer formation process 480 is performed on the semiconductor device 200. With the remaining portions of the hard mask layers 310-330 serving as a protective mask, the air spacer formation process 480 can include a wet etching process or a dry etching process to etch away portions of the dielectric spacer layer 300 that are not protected (e.g., exposed by the openings 390-391). In some embodiments, the etching process can use HF, H2O, He, and / or N2 as etchants.

[0052] Removing the dielectric spacer layer 300 creates the air spacer 270. The air spacer 270 can at least partially expose a subset of the fin structures, such as portions of the top and side surfaces of the fin structures 104B, 104C, 104D, and 104E. One of the unique physical characteristics of the air spacer 270 formed by the present invention is that it can have a boundary 500 that has a vertical component 500A. In other words, the remaining portion of the dielectric spacer layer 300 and the air spacer 270 can share a boundary 500 that extends partially vertically in the Z direction. Note that the vertical boundary 500A may not be linear, but can have a semi-circular profile (or curved) or a trapezoidal profile. Additionally, in a real device, the vertical boundary 500A may not be perfectly linear, semi-circular, or trapezoidal. Instead, the vertical boundary 500A can have depressions, bumps, protrusions, or otherwise exhibit surface topography variations or roughness. However, the overall profile of the vertical boundary 500A can still resemble a straight line, a semi-circle (or arc), or a trapezoid.

[0053] Since the hard mask layers 310 - 330 are used to define the air spacer 270, such vertical boundaries 500A can be formed. In other words, the hard mask layers 310 - 330 are used as a protection mask for an etching process that removes the dielectric spacer layer 300 to generate the vertical boundaries 500A. In contrast, conventional air spacers may lack such vertical boundaries 500A because conventional air spacer formation processes do not use a hard mask to define the air spacer.

[0054] The vertical boundaries 500A exist because the air spacer 270 is selectively formed for devices that require them, but not for devices that do not. For example, the transistors associated with the fin structures 104B - 104F can be transistors in an IC application where the benefits of having an air spacer far outweigh the drawbacks. These transistors can be transistors in an IC application where speed is critical, such as a ring oscillator. Other exemplary devices that can utilize an air spacer can include SRAM devices, logic devices (such as row / column decoders), shift registers, etc. Transistor speed is inversely proportional to the time constant, which is the product of resistance and capacitance. Reducing the dielectric constant (e.g., by implementing an air spacer) will reduce the capacitance, which in turn will decrease the time constant and increase the speed. Thus, it can be seen that air spacers are most suitable for applications where transistor speed needs to be fast.

[0055] On the other hand, the transistors associated with the fin structure 104A do not form an air spacer because the transistors associated with the fin structure 104 are in an IC application where speed is not a critical issue. For example, for a memory device, such as an SRAM device, transistor speed may not be a major concern, and thus the SRAM device may not require an air spacer. More specifically, implementing an air spacer may pose a certain amount of risk. For example, they may cause the gate structure to wobble or even collapse. Additionally, implementing a manufacturing process to form an air spacer may result in unexpected etching damage to certain device components (e.g., the STI structure under the air spacer) and / or generate undesired etching by-products or waste, which may also degrade device performance. Thus, the inventors of the present disclosure recognized that it is optimal to selectively implement an air spacer for transistor devices in applications where speed is critical (e.g., associated with the fin structures 104B - 104F), rather than treating all transistors the same (e.g., as if they all require an air spacer), because for these devices, the benefits of having an air spacer far outweigh the risks. However, for transistor devices where speed is not an important issue (e.g., associated with the fin structure 104A), the present invention recognizes that any potential benefits obtained from an air spacer may not exceed the risks of its implementation. Thus, the present disclosure does not form an air spacer for these transistor devices.

[0056] It should be understood that although the embodiments discussed above with reference to Figures 3 to 7 utilize three hard mask layers (e.g., hard mask layers 310, 320, and 330) to define the regions where air spacers are to be formed, in other embodiments of the present invention, two hard mask layers can also be used to define the regions for air spacers. For example, in some embodiments, hard mask layer 330 can be omitted.

[0057] Figure 8 FIG. shows a schematic partial top view of a portion of the IC layout of semiconductor device 200. Figure 8 Helps to show how to define a photolithography mask for generating hard mask layers 310 - 330 (or for defining the regions for air spacers 270). More specifically, Figure 8 The top view of shows exemplary active regions 550 - 551, each of which has an elongated rectangular shape extending in the X direction. Figure 8 The top view of also shows exemplary gate structures 580 - 584, each of which has an elongated rectangular shape extending in the Y direction. When forming gate structures 580 - 584, they can be formed as HKMG structures and can each include an HKMG gate structure having a metal gate electrode similar to gate electrode 110 and a high - k gate dielectric layer similar to the high - k gate dielectric layer 106 discussed above. For simplicity, the gate electrodes and gate dielectric layers of gate structures 580 - 584 are not shown separately or individually herein, but it should be understood that their deposition can be similar to Figure 2B as shown.

[0058] The layout information of active regions 550 - 551 and gate structures 580 - 584 can be extracted from the IC design layout, which can be received from an IC design house and can be in the form of a Graphics Data System (GDS) file. The GDS file and / or other data files received from the IC design house can also indicate the types of application programs associated with transistor devices in different regions. Based on this information, a photolithography mask is generated to implement hard mask layers (such as hard mask layers 310 - 330) that define the regions for air spacer formation. For example, Figure 8 FIG. shows a region 600 corresponding to the opening defined by the hard mask layer, such that etching can be implemented through the opening to form an air spacer. For example, region 600 can correspond to one of the openings 390 or 391 discussed above with reference to Figures 3 to 7 FIG..

[0059] Region 600 can be defined as follows. First, determine which IC devices should have implemented air spacers (e.g., ring oscillators or other high-speed applications), and determine the locations of the corresponding active regions for these IC devices. For the purpose of providing an example, assume that active region 551 is one such active region. Next, "push out" or extend in the Y direction the X-direction boundaries 620 and 621 of active region 551 by a distance 640. In some embodiments, distance 640 is greater than about 0 and less than about 50 nanometers (nm). This range of distance 640 helps to improve the resulting device while minimizing the likelihood of the gate structures 581 - 583 wobbling or collapsing. After this operation, region 600 has X-direction boundaries 650 and 651.

[0060] The Y-direction boundaries 670 and 671 of active region 551 are also "pushed in" or contracted in the X direction by a distance 680. In some embodiments, distance 680 is greater than about 20 nm and less than about 50 nanometers (nm). This range of distance 680 helps to improve the resulting device while minimizing the likelihood of the gate structures 581 - 583 wobbling or collapsing. After this operation, region 600 has Y-direction boundaries 690 and 691.

[0061] With region 600 already defined, a photolithography mask can be generated to define a hard mask layer. For example, the hard mask layer will correspond to the regions of the IC layout other than region 600. Or rather, the hard mask layer will define an opening corresponding to region 600. Since the air spacer etch process is implemented through region 600 (or the opening corresponding to region 600), air spacers can be selectively formed in region 600, but not outside region 600. Since the transistors inside region 600 are more speed-critical than the transistors outside region 600, the selective implementation of air spacers in region 600 will help to optimize the performance of different types of transistor devices (e.g., for the transistors inside and outside region 600).

[0062] As discussed above, the selective implementation of the air spacers of the present invention also gives rise to unique physical characteristics, such as the vertical boundary 500A discussed above. In Figure 8 the top view, for each of the gate structures 581 - 583, the vertical boundary 500A will appear at or near boundary 650 or 651. More specifically, gate structures 580 - 584 will each have a dielectric gate spacer formed on its sidewalls, where each dielectric gate spacer extends in the Y direction.

[0063] For the purpose of providing a simple illustration, now refer to Figure 9, where exemplary dielectric gate spacers 260, 275, and 280 are shown in a top view as gate spacers for gate structures 580 - 584. Specifically, dielectric gate spacer 260 is directly disposed on the sidewalls of each of gate structures 580 - 584, dielectric spacer 275 is disposed on the sidewalls of dielectric spacer 260, and dielectric spacer 280 is disposed on the sidewalls of dielectric spacer 275.

[0064] However, within region 600, air spacer 270 (disposed between gate dielectric spacers 260 and 280) is formed as an air spacer for gate structures 581 - 583. This is because the etching process for forming air spacer 270 is implemented through a hard mask opening corresponding to region 600. Thus, a portion of dielectric spacer 275 within region 600 is etched away to form air spacer 270. At the same time, after forming air spacer 270, portions of dielectric spacer 275 outside region 600 remain because they are protected by the hard mask layer and are not etched. Thus, vertical boundary 500A of air spacer 270 is formed at or near boundary 650 / 651 of region 600. As Figure 9 shown, each vertical boundary 500A is the demarcation line between air spacer 270 and the remaining dielectric spacer 275.

[0065] Gate structures 580 and 584 do not have air spacers because they can belong to device types that do not require air spacers (e.g., SRAM). Similarly, portions of gate structures 581 - 583 outside region 600 can also belong to device types that do not require air spacers, or at least the benefits of air spacers do not outweigh the potential risks. Portions of gate structures 581 - 583 within region 600 belong to devices where the benefits of having air spacers far outweigh the risks, such as they can belong to high - speed devices, such as ring oscillators.

[0066] Figure 10 is a simplified schematic partial top view of semiconductor device 200 at a manufacturing stage according to an embodiment of the present invention. At this stage of manufacturing, gate structures, such as gate structures 580 - 583, have been formed, each of which extends in the Y direction and is separated from each other in the X direction by ILD 210. Air spacers 270 have also been formed on either side of each of the gate structures. The position of air spacers 270 is at least partially defined by hard mask structure 340, which can include hard mask layers 310, 320, and 330. In other words, each hard mask structure 340 extends in the X direction and is separated from each other in the Y direction, thereby defining openings 345. Air spacers 270 are formed below openings 345. For simplicity, other dielectric gate spacers other than air spacers 270 are not specifically shown herein.

[0067] Figure 11 is a simplified schematic partial top view of a semiconductor device 200 at a manufacturing stage according to an embodiment of the present invention. Figure 11 also includes Figure 2A the tangent line A-A' shown. In other words, it can be obtained by Figure 11 a cross-section taken along the tangent line A-A' in Figure 2A However, in the top view shown, the ILD 210 and the cap structure 220 provided above the epitaxial layer 120 are removed, thus exposing the epitaxial layer 120. Figure 11 At this manufacturing stage, the hard mask structure 340 is removed. Air spacers 270 are formed on opposite sides of gate structures such as gate structures 580-582 and gate structures 590-592. Dielectric gate spacers 280 are also provided adjacent to the air spacers 270. In other words, the air spacers 270 are provided between the gate structures 580 / 581 / 582 and the dielectric gate spacers 280. The ILD 210 is located between the dielectric gate spacers 280. The epitaxial layer 120 is provided between adjacent gate structures in the Y direction, for example, between the gate structures 580 and 590, between the gate structures 581 and 591, and between the gate structures 582 and 592.

[0068]

[0069] Figure 12 Figure 12 shows a circuit diagram of a simple ring oscillator according to an aspect of the present invention to provide an example of a device for which air spacers are to be formed. For example, the ring oscillator may include an odd number of inverters, which may be three inverters M1, M2, and M3 in the illustrated embodiment. The output terminal of the inverter M1 is electrically connected to the input terminal of the inverter M2, the output terminal of the inverter M2 is electrically connected to the input terminal of the inverter M3, and the output terminal of the inverter M3 is electrically connected to the input terminal of the inverter M1, thus forming a loop or ring composed of the inverters M1, M2, and M3 connected in series. In some embodiments, the inverters M1, M2, and M3 may be implemented using CMOS transistors. For example, each of the inverters M1, M2, and M3 may include a PMOS and an NMOS. The gates of the PMOS and the NMOS are connected to each other and serve as the input terminal of the inverter. One of the source / drain of the PMOS is connected to Vdd (for example, a voltage rail). The other of the source / drain of the PMOS is connected to one of the source / drain of the NMOS and serves as the output terminal of the inverter. The other of the source / drain of the NMOS is grounded. Using a capacitor C L models the capacitance (for example, the output capacitance of the inverter). Of course, it should be understood that Figure 12Only a simple embodiment of the ring oscillator is shown and is not intended to be limiting. Additionally, the air spacer of the present invention can be formed into other suitable devices that are not ring oscillators.

[0070] Figure 13 A circuit diagram of a SRAM device is shown as an example of a device that does not require the formation of the air spacer of the present invention. A SRAM device is a type of semiconductor memory that uses bistable latch circuits (e.g., flip-flops) to store binary information bits. Figure 13 An exemplary circuit schematic of a single-port SRAM cell (e.g., a 1-bit SRAM cell) 5 is shown. The single-port SRAM cell 5 includes pull-up transistors PU1, PU2; pull-down transistors PD1, PD2; and transmission gate transistors PG1, PG2. As shown in the circuit diagram, transistors PU1 and PU2 are p-type transistors, such as the p-type FinFETs discussed above, while transistors PG1, PG2, PD1, and PD2 are the n-type FinFETs discussed above.

[0071] The drains of the pull-up transistor PU1 and the pull-down transistor PD1 are coupled together, and the drains of the pull-up transistor PU2 and the pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled together and coupled to the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and coupled to the drains of transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of the pull-up transistors PU1 and PU2 are coupled to the power supply voltage Vcc (also referred to as Vdd), and the sources of the pull-down transistors PD1 and PD2 are coupled to the voltage Vss, which can be electrically grounded in some embodiments.

[0072] The first storage node SN1 of the first data latch is coupled to the bit line BL through the transmission gate transistor PG1, and the complementary first storage node SNB1 is coupled to the complementary bit line BLB through the transmission gate transistor PG2. The first storage node N1 and the complementary first storage node SNB1 are complementary nodes that are typically at opposite logic levels (logic high or logic low). The gates of the transmission gate transistors PG1 and PG2 are coupled to the word line WL.

[0073] Of course, it should be understood that Figure 13 Only a simple embodiment of the SRAM device is shown and is not intended to be limiting. Additionally, the air spacer of the present invention can be formed for other suitable devices that are not SRAM devices.

[0074] Figure 14An integrated circuit manufacturing system 700 according to an embodiment of the present invention is shown. The manufacturing system 700 includes a plurality of entities 702, 704, 706, 708, 710, 712, 714, 716......, N connected by a communication network 718. The network 718 can be a single network or can be various different networks, such as an intranet and the Internet, and can include wired and wireless communication channels.

[0075] In an embodiment, the entity 702 represents a service system for manufacturing collaboration; the entity 704 represents a user, such as a product engineer monitoring a product of interest; the entity 706 represents an engineer, such as a process engineer controlling a process and related scenarios, or an equipment engineer to monitor or adjust the conditions and settings of a processing tool; the entity 708 represents a metrology tool for IC testing and measurement; the entity 710 represents a semiconductor processing tool; the entity 712 represents a virtual metrology module associated with the processing tool 710; the entity 714 represents an advanced process control module associated with the processing tool 710 and other additional processing tools; and the entity 716 represents a sampling module associated with the processing tool 710.

[0076] Each entity can interact with other entities and can provide and / or receive integrated circuit manufacturing, process control, and / or computing capabilities from other entities. Each entity can also include one or more computer systems for implementing computing and implementing automation. For example, the advanced process control module of the entity 714 can include a plurality of computer hardwares encoded with software instructions. The computer hardwares can include a hard disk drive, a flash drive, a CD-ROM, a RAM memory, a display device (e.g., a monitor), and input / output devices (e.g., a mouse and a keyboard). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0077] The integrated circuit manufacturing system 700 enables interaction between entities for integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In an embodiment, the advanced process control includes adjusting the processing conditions, settings, and / or scenarios of a processing tool applicable to a relevant wafer according to metrology results.

[0078] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to an optimal sampling field / point determined based on various characteristics of process quality and / or product quality.

[0079] One capability provided by the IC manufacturing system 700 enables collaboration and information access in areas such as design, engineering and processing, metrology, and advanced process control. Another capability provided by the IC manufacturing system 700 can integrate systems between facilities such as metrology tools and processing tools. This integration enables the facilities to coordinate their activities. For example, integrating metrology tools and processing tools can enable manufacturing information to be more effectively incorporated into the manufacturing process and can utilize the metrology tools integrated in the relevant processing tools to enable wafer data from in-line or in-situ measurements.

[0080] In some embodiments, the IC manufacturing system 700 can be used to obtain an IC layout design (e.g., obtained from an IC design house in the form of a GDS file), modify the IC layout design according to the above discussion (e.g., determine devices or regions to selectively form air spacers), and facilitate the manufacture of a photolithography mask (e.g., a photolithography mask for defining a hard mask layer), which may involve manufacturing the photolithography mask or sending the design for the photolithography mask to a third-party manufacturer.

[0081] Figure 15 is a flowchart showing a method 900 of manufacturing a semiconductor device according to another embodiment of the present invention. The method 900 includes a step 910 of forming a gate structure over a substrate. The gate structure includes at least a first dielectric spacer and a second dielectric spacer. In a top view, each of the gate structure, the first dielectric spacer, and the second dielectric spacer extends in a first horizontal direction.

[0082] The method 900 includes a step 920 of forming a patterned hard mask structure over the gate structure. The patterned hard mask structure defines an opening exposing a portion of the gate structure. In some embodiments, forming the patterned hard mask structure includes at least forming a first hard mask layer and a second hard mask layer formed over the first hard mask layer. There is an etch selectivity between the first hard mask layer and the second hard mask layer.

[0083] The method 900 includes a step 930 of performing an etching process through the opening to form an air spacer by at least partially removing the first dielectric spacer. The hard mask structure serves as an etch mask during the etching process. In some embodiments, the etching process forms a vertical boundary between the air spacer and the non-removed portion of the first dielectric spacer. In some embodiments, the vertical boundary includes segments having a linear shape, a semi-circular shape, or a trapezoidal shape. In some embodiments, the second dielectric spacer is substantially unaffected by the etching process.

[0084] It should be understood that additional steps may still be implemented before, during, or after steps 910 - 930 discussed above. For example, method 900 may include the following steps: receiving an integrated circuit (IC) layout design; analyzing the IC layout design; based on the analysis, determining a first region of the IC layout design in which an air spacer should be formed and a second region of the IC layout design in which an air spacer need not be formed; and facilitating the generation of one or more lithography masks for patterning a hard mask structure such that the openings defined by the hard mask structure correspond to the first region rather than the second region of the IC layout design. In some embodiments, the analysis includes analyzing the types of transistor devices located in multiple regions of the IC layout design, including the first region and the second region. In some embodiments, the determination includes determining that the transistor devices located in the first region have a faster speed than the transistor devices located in the second region.

[0085] In summary, the present invention employs multiple techniques to facilitate the formation of air spacers. For example, an IC layout design containing multiple types of transistors is analyzed. These different types of transistors may be located in different regions of the IC layout design. Based on the analysis, it is determined which types of transistors should have implemented air spacers and which types of transistors should not have implemented air spacers. For example, the types of transistors that should have implemented air spacers may include transistors with a faster speed. Thereafter, a hard mask structure may be provided to define openings corresponding to the regions of the IC layout design where air spacers are to be formed. An etching process is implemented through the openings to selectively form air spacers in these regions, while the remaining IC layout design is covered by the hard mask structure and thus no air spacers are formed.

[0086] Based on the above discussion, it can be seen that the present invention provides advantages over conventional air spacers. However, it should be understood that not all advantages have been discussed herein, different embodiments may provide different advantages, and no particular advantage is required for all embodiments. One advantage is that the risk of gate structure swing or collapse can be significantly reduced. This is because the air spacer extends through a portion of the gate structure (or along the sidewalls of a portion of the gate structure), rather than extending along the entire gate structure. Another advantage is that unintended etch damage to other device components such as STI can be prevented or mitigated. Yet another advantage is that unwanted etch by-products can be eliminated. Other advantages may include compatibility with existing manufacturing processes and ease and low cost of implementation.

[0087] The advanced lithography processes, methods, and materials described above can be used in many applications, including fin field-effect transistors (FinFETs). For example, fins can be patterned to create relatively tight spacings between components, and the foregoing disclosure is well-suited for these. Additionally, spacers, also known as mandrels, used in forming the fins of a FinFET can be processed in accordance with the foregoing disclosure.

[0088] One aspect of the present invention relates to a semiconductor device. The semiconductor device includes: a substrate and a gate structure disposed above the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

[0089] In some embodiments, the vertical boundary includes a linear component. In some embodiments, the vertical boundary includes a semi-circular component. In some embodiments, the vertical boundary includes a trapezoidal component. In some embodiments, the semiconductor device further includes: a first dielectric spacer disposed directly on a sidewall of the gate structure; and a second dielectric spacer disposed adjacent to the air spacer, wherein the air spacer is disposed between the first dielectric spacer and the second dielectric spacer. In some embodiments, the semiconductor device further includes: a third dielectric spacer disposed between the first dielectric spacer and the second dielectric spacer, wherein the third dielectric spacer forms a vertical boundary with the air spacer. In some embodiments, the gate structure includes a second portion that does not have an air spacer disposed adjacent thereto. In some embodiments, the first portion of the gate structure is part of a first transistor; the second portion of the gate structure is part of a second transistor; and the first transistor has a greater speed than the second transistor. In some embodiments, the semiconductor device further includes: a fin structure protruding vertically from the substrate, wherein the fin structure extends in the second horizontal direction, and wherein the gate structure partially wraps the fin structure.

[0090] Another aspect of the present invention relates to a semiconductor device. The semiconductor device includes: a substrate and a gate structure located above the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer extends in the first horizontal direction. The air spacer is separated from the gate structure in a second horizontal direction different from the first horizontal direction. The air spacer is located adjacent to a first segment of the gate structure. A first dielectric spacer extends in the second horizontal direction. The first dielectric spacer is located adjacent to a second segment of the gate structure. The first dielectric spacer and the air spacer form a boundary.

[0091] In some embodiments, the first segment of the gate structure belongs to a first type of transistor; the second segment of the gate structure belongs to a second type of transistor; and the first type of transistor has a greater speed than the second type of transistor. In some embodiments, the semiconductor device further includes: a second dielectric spacer directly on sidewalls of the first and second segments of the gate structure; and a third dielectric spacer spaced apart from the second dielectric spacer in the second direction, wherein the air spacer and the first dielectric spacer are disposed between the second dielectric spacer and the third dielectric spacer. In some embodiments, the first dielectric spacer has a different material composition from the second dielectric spacer and the third dielectric spacer.

[0092] Another aspect of the present invention relates to a method of manufacturing a semiconductor device. A gate structure is formed over a substrate. The gate structure includes at least a first dielectric spacer and a second dielectric spacer. In a top view, the gate structure, the first dielectric spacer, and the second dielectric spacer each extend in a first horizontal direction. A patterned hard mask structure is formed over the gate structure. The patterned hard mask structure defines an opening exposing a portion of the gate structure. An etching process is performed through the opening to form an air spacer by at least partially removing the first dielectric spacer. The patterned hard mask structure serves as an etch mask during the etching process.

[0093] In some embodiments, the method further includes: receiving an integrated circuit (IC) layout design; analyzing the integrated circuit layout design; based on the analysis, determining a first region of the integrated circuit layout design in which an air spacer should be formed and a second region of the integrated circuit layout design in which an air spacer need not be formed; and facilitating generation of one or more lithography masks for patterning a hard mask structure such that the openings defined by the patterned hard mask structure correspond to the first region rather than the second region of the integrated circuit layout design. In some embodiments, the analysis includes analyzing the types of transistor devices in a plurality of regions of the integrated circuit layout design, the plurality of regions including the first region and the second region; and the determination includes determining that the transistor devices located in the first region have a faster speed than the transistor devices located in the second region. In some embodiments, the etching forms a vertical boundary between the air spacer and the unremoved portion of the first dielectric spacer. In some embodiments, the vertical boundary includes segments having a linear shape, a semi-circular shape, or a trapezoidal shape. In some embodiments, the second dielectric spacer is substantially unaffected by the etching process. In some embodiments, forming the patterned hard mask structure includes at least forming a first hard mask layer and a second hard mask layer formed over the first hard mask layer, wherein there is an etching selectivity between the first hard mask layer and the second hard mask layer.

[0094] The features of several embodiments are outlined above so that those of ordinary skill in the art may better understand aspects of the present invention. Those of ordinary skill in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: A substrate; A gate structure disposed above the substrate in a vertical direction, wherein the gate structure extends in a first horizontal direction; and An air spacer disposed adjacent to a first portion of the gate structure in a second horizontal direction different from the first horizontal direction, wherein the air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction, Wherein the gate structure includes a second portion not disposed adjacent to the air spacer, the first portion of the gate structure is a part of a first transistor, the second portion of the gate structure is a part of a second transistor, and the first transistor has a greater speed than the second transistor.

2. The semiconductor device according to claim 1, wherein, The vertical boundary includes a linear component.

3. The semiconductor device according to claim 1, wherein, The vertical boundary includes a semi-circular component.

4. The semiconductor device according to claim 1, wherein The vertical boundary includes a trapezoidal component.

5. The semiconductor device according to claim 1, further comprising: A first dielectric spacer disposed directly on a sidewall of the gate structure; And A second dielectric spacer disposed adjacent to the air spacer, wherein the air spacer is disposed between the first dielectric spacer and the second dielectric spacer.

6. The semiconductor device according to claim 5 further comprises: A third dielectric spacer disposed between the first dielectric spacer and the second dielectric spacer, wherein the third dielectric spacer forms a vertical boundary with the air spacer.

7. The semiconductor device according to claim 6, wherein, The first dielectric spacer has a different material composition from the second dielectric spacer and the third dielectric spacer.

8. The semiconductor device according to claim 5, wherein: The first dielectric spacer is a low-k dielectric material.

9. The semiconductor device according to claim 1 further comprises: A fin structure protruding vertically from the substrate, wherein the fin structure extends in the second horizontal direction, and wherein the gate structure partially wraps the fin structure.

10. A semiconductor device, comprising: A substrate; A gate structure located above the substrate in a vertical direction, wherein the gate structure extends in a first horizontal direction; An air spacer extending in the first horizontal direction, wherein the air spacer is separated from the gate structure in a second horizontal direction different from the first horizontal direction, and wherein the air spacer is located adjacent to a first segment of the gate structure; and A first dielectric spacer extending in the second horizontal direction, wherein the first dielectric spacer is located adjacent to a second segment of the gate structure, and wherein the first dielectric spacer and the air spacer form a boundary, Wherein the first segment of the gate structure belongs to a first type of transistor, the second segment of the gate structure belongs to a second type of transistor, and the first type of transistor has a greater speed than the second type of transistor.

11. The semiconductor device according to claim 10, wherein: The first dielectric spacer is a low-k dielectric material.

12. The semiconductor device according to claim 10, further comprising: A second dielectric spacer directly located on sidewalls of the first segment and the second segment of the gate structure; And A third dielectric spacer, spaced apart from the second dielectric spacer in the second horizontal direction, wherein the air spacer and the first dielectric spacer are disposed between the second dielectric spacer and the third dielectric spacer.

13. The semiconductor device according to claim 12, wherein, The first dielectric spacer has a material composition different from that of the second dielectric spacer and the third dielectric spacer.

14. A method of forming a semiconductor device, comprising: Forming a gate structure over a substrate, wherein the gate structure includes at least a first dielectric spacer and a second dielectric spacer, and wherein, in a top view, each of the gate structure, the first dielectric spacer, and the second dielectric spacer extends in a first horizontal direction; Receiving an integrated circuit layout design; Analyzing the integrated circuit layout design; Based on the analysis, determining a first region of the integrated circuit layout design in which an air spacer should be formed and a second region of the integrated circuit layout design in which an air spacer need not be formed, wherein transistor devices located in the first region have a faster speed than transistor devices located in the second region; Forming a patterned hard mask structure over the gate structure, wherein the patterned hard mask structure defines an opening exposing a portion of the gate structure, and the opening defined by the patterned hard mask structure corresponds to the first region rather than the second region of the integrated circuit layout design, wherein forming the patterned hard mask structure includes at least forming a first hard mask layer and a second hard mask layer formed over the first hard mask layer, and wherein there is an etch selectivity between the first hard mask layer and the second hard mask layer; and Performing an etching process through the opening to form the air spacer by at least partially removing the first dielectric spacer, wherein the patterned hard mask structure serves as an etch mask during the etching process.

15. The method according to claim 14, wherein, The first dielectric spacer has a material composition different from that of the second dielectric spacer.

16. The method according to claim 14, wherein: The analysis includes analyzing the types of transistor devices located in a plurality of regions of the integrated circuit layout design, the plurality of regions including the first region and the second region.

17. The method according to claim 14, wherein, The etching forms a vertical boundary between the air spacer and the unremoved portion of the first dielectric spacer.

18. The method according to claim 17, wherein, The vertical boundary includes segments having a linear shape, a semi-circular shape, or a trapezoidal shape.

19. The method according to claim 14, wherein, The second dielectric spacer is not affected by the etching process.

20. The method according to claim 14, wherein The integrated circuit layout design is for forming an integrated circuit including a ring oscillator.

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