Ferroelectric memory device including word line and channel gate and method of forming the same

Abstract

The present disclosure provides a memory device, which includes a semiconductor channel extending between a source region and a drain region, a plurality of channel gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of channel gate electrodes, and a ferroelectric material portion located between the semiconductor channel and the plurality of word lines.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Non-Provisional Application No. 16 / 457,687, filed on June 28, 2019, and U.S. Non-Provisional Application No. 16 / 457,721, filed on June 28, 2019, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor memory devices, and in particular, to a ferroelectric memory device including a word line and a pass gate and a method of manufacturing the same. Background Art

[0004] Ferroelectric materials are materials that show spontaneous polarization of charges in the absence of an applied electric field. The net polarization P of the charges within the ferroelectric material is non-zero in the minimum energy state. Therefore, spontaneous ferroelectric polarization of the material occurs, and the ferroelectric material accumulates surface charges of opposite polarity types on two opposing surfaces. The polarization P of the ferroelectric material shows hysteresis as a function of the applied voltage V. The product of the remnant polarization and the coercive field of a ferroelectric material is a measure used to characterize the effectiveness of a ferroelectric material.

[0005] A ferroelectric memory device is a memory device that includes a ferroelectric material for storing information. The ferroelectric material acts as a memory material for the memory device. Depending on the polarity of the electric field applied to the ferroelectric material, the dipole moment of the ferroelectric material is programmed in two different orientations (e.g., "up" or "down" polarization positions based on atomic positions in the lattice (such as oxygen and / or metal atom positions)) to store information in the ferroelectric material. The different orientations of the dipole moment of the ferroelectric material can be detected by the electric field generated by the dipole moment of the ferroelectric material. For example, the orientation of the dipole moment can be detected by measuring the current flowing through a semiconductor channel disposed adjacent to the ferroelectric material in an adjacent field effect transistor ferroelectric memory device. Summary of the invention

[0006] According to an embodiment of the present disclosure, a memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of channel gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of channel gate electrodes, and a ferroelectric material portion located between the semiconductor channel and the plurality of word lines.

[0007] According to another embodiment of the present disclosure, a method for forming a three-dimensional memory device is provided, the method comprising: forming a vertical alternating sequence of insulating layers and conductive layers above a substrate; forming linear grooves extending laterally along a first horizontal direction through the vertical alternating sequence, wherein the remaining portion of the vertical alternating sequence comprises an alternating stack of insulating strips and conductive strips; forming a row of in-process memory pillar structures in each of the linear grooves, wherein each of the in-process memory pillar structures comprises a ferroelectric material layer, an interlayer dielectric layer, a sacrificial pillar portion, and a gate dielectric layer from one side to the other; forming a channel cavity by removing the sacrificial pillar portion; and forming a semiconductor channel in each channel cavity on a corresponding pair of the interlayer dielectric layer and the gate dielectric layer.

[0008] According to another aspect of the present disclosure, a method for forming a memory device is provided, the method comprising: forming channel gate electrodes embedded in a dielectric material layer above a substrate; forming a gate dielectric layer above these channel gate electrodes; forming a semiconductor channel, a source region, and a drain region above the gate dielectric layer; and forming an interlayer dielectric portion, a ferroelectric material portion, and a word line above the semiconductor channel.

[0009] According to another aspect of the present disclosure, a three-dimensional memory device includes a word line type stack of alternating first insulating strips and word lines located above a substrate, a channel gate type stack of alternating second insulating strips and channel gate electrodes located above the substrate, a vertical semiconductor channel located between the channel gate type stack and the word line type stack, a gate dielectric located between the vertical semiconductor channel and the channel gate type stack, and a ferroelectric material portion located between the vertical semiconductor channel and the word line type stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a vertical cross-sectional view of a first exemplary structure for forming a first ferroelectric memory device after forming a channel gate electrode and a gate dielectric layer according to the first embodiment of the present disclosure.

[0011] Figure 1B yes Figure 1A A top view of a first exemplary structure.

[0012] Figure 2A is a vertical cross-sectional view of the first exemplary structure after forming a semiconductor channel, a source region, and a drain region according to the first embodiment of the present disclosure.

[0013] Figure 2B yes Figure 2A A top view of a first exemplary structure.

[0014] Figure 3Ais a vertical cross-sectional view of the first exemplary structure after forming an interlayer dielectric layer, a ferroelectric material layer, and a word line according to the first embodiment of the present disclosure.

[0015] Figure 3B yes Figure 3A A top view of a first exemplary structure.

[0016] Figure 4A is a vertical sectional view of an alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure.

[0017] Figure 4B yes Figure 4A A top view of a first exemplary structure.

[0018] Figure 5A is a vertical cross-sectional view of a second exemplary structure after forming a vertical alternating sequence of insulating layers and conductive layers according to the second embodiment of the present disclosure.

[0019] Figure 5B is along Figure 5A A horizontal cross-sectional view of the second exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Figure 5A A plane of a vertical section.

[0020] Fig. 6A is a vertical cross-sectional view of a second exemplary structure after forming line trenches and vertical alternating stacks of insulating strips and conductive strips according to the second embodiment of the present disclosure.

[0021] Figure 6B is along Fig. 6A A horizontal cross-sectional view of the second exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig. 6A A plane of a vertical section.

[0022] Fig. 7A is a vertical cross-sectional view of a second exemplary structure after forming a ferroelectric material layer according to the second embodiment of the present disclosure.

[0023] Figure 7B is along Fig. 7A A horizontal cross-sectional view of the second exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig. 7A A plane of a vertical section.

[0024] Fig. 8A is a vertical cross-sectional view of a second exemplary structure after patterning a ferroelectric material layer into a plurality of portions according to the second embodiment of the present disclosure.

[0025] Figure 8B is along Fig. 8AA horizontal cross-sectional view of the second exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig. 8A A plane of a vertical section.

[0026] Fig.9A is a vertical cross-sectional view of a second exemplary structure after deposition of a continuous layer of dielectric material according to the second embodiment of the present disclosure.

[0027] Fig. 9B is along Fig.9A A horizontal cross-sectional view of the second exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig.9A A plane of a vertical section.

[0028] Fig. 10A is a vertical cross-sectional view of a second exemplary structure after forming a combination of a ferroelectric material layer, an interlayer dielectric layer, a sacrificial post guide, and a gate dielectric layer in each line trench according to the second embodiment of the present disclosure.

[0029] Fig. 10B is along Fig. 10A A horizontal cross-sectional view of the second exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig. 10A A plane of a vertical section.

[0030] Fig.11A is a vertical cross-sectional view of a second exemplary structure after a laterally alternating sequence of memory pillar structures and dielectric pillar structures during formation in each line trench according to the second embodiment of the present disclosure.

[0031] Fig. 11B is along Fig.11A A horizontal cross-sectional view of the second exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig.11A A plane of a vertical section.

[0032] Fig. 12A is a vertical cross-sectional view of a second exemplary structure after forming a channel cavity in each linear trench according to the second embodiment of the present disclosure.

[0033] Fig. 12B is along Fig. 12A A horizontal cross-sectional view of the second exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig. 12A A plane of a vertical section.

[0034] Fig.13A is a vertical cross-sectional view of a second exemplary structure after forming a semiconductor channel, a dielectric core, and a drain region in a pillar cavity according to the second embodiment of the present disclosure.

[0035] Fig. 13B is along Fig.13A A horizontal cross-sectional view of the second exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig.13A A plane of a vertical section.

[0036] Fig. 13C is a vertical cross-sectional view of a second exemplary structure after forming a word line, a pass gate, and a bit line according to the second embodiment of the present disclosure.

[0037] Fig.13D is along Fig. 13C A horizontal cross-sectional view of the second exemplary structure taken along the horizontal plane D-D'. A vertical plane CC' is Fig. 13C A plane of a vertical section.

[0038] Fig.14A is a vertical cross-sectional view of a first configuration of a third exemplary structure including a three-dimensional array of ferroelectric memory elements according to a third embodiment of the present disclosure.

[0039] Fig. 14B is along Fig.14A A horizontal cross-sectional view of the first configuration of the third exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig.14A A plane of a vertical section.

[0040] Fig. 14C is along Fig. 14B A vertical cross-sectional view of the first configuration of the third exemplary structure taken along the vertical plane CC'. A horizontal plane BB' is Fig. 14B Horizontal section of a plane.

[0041] Fig.14D is along Fig.14A and Fig. 14C A horizontal cross-sectional view of the first configuration of the third exemplary structure taken along the horizontal plane D-D'. A vertical plane AA' is Fig.14A The vertical plane C-C' is Fig. 14C A plane of a vertical section.

[0042] Fig.15A is a vertical cross-sectional view of a second configuration of a third exemplary structure including a three-dimensional array of ferroelectric memory elements according to the third embodiment of the present disclosure.

[0043] Fig. 15B is along Fig.15A A horizontal cross-sectional view of the second configuration of the third exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig.15A A plane of a vertical section.

[0044] Fig.16A is a vertical cross-sectional view of a third configuration of a third exemplary structure including a three-dimensional array of ferroelectric memory elements according to a third embodiment of the present disclosure.

[0045] Fig. 16B is along Fig.16A A horizontal cross-sectional view of the third configuration of the third exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig.16A A plane of a vertical section.

[0046] Fig. 16C is along Fig. 16B A vertical cross-sectional view of the third configuration of the third exemplary structure taken along the vertical plane CC'. A horizontal plane BB' is Fig. 16B Horizontal section of a plane.

[0047] Fig.17A is a vertical cross-sectional view of a first configuration of a fourth exemplary structure including a three-dimensional array of ferroelectric memory elements according to a fourth embodiment of the present disclosure.

[0048] Fig. 17B is along Fig.17A A horizontal cross-sectional view of the first configuration of the fourth exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig.17A A plane of a vertical section.

[0049] Fig. 17C is along Fig.17A A horizontal cross-sectional view of the first configuration of the fourth exemplary structure taken along the horizontal plane CC'. A vertical plane AA' is Fig.17A A plane of a vertical section.

[0050] Fig.18A is a vertical cross-sectional view of a second configuration of a fourth exemplary structure including a three-dimensional array of ferroelectric memory elements according to the fourth embodiment of the present disclosure.

[0051] Fig.18B is along Fig.18A A horizontal cross-sectional view of the second configuration of the fourth exemplary structure taken along the horizontal plane BB'. A vertical plane AA' is Fig.18A A plane of a vertical section.

[0052] Fig.18C is a vertical cross-sectional view of a third configuration of a fourth exemplary structure including a three-dimensional array of ferroelectric memory elements according to a fourth embodiment of the present disclosure.

[0053] Fig.19A is a vertical cross-sectional view of a fourth configuration of a fourth exemplary structure including a three-dimensional array of ferroelectric memory elements according to a fourth embodiment of the present disclosure.

[0054] Fig.19B is along Fig.19A A horizontal cross-sectional view of a fourth configuration of a fourth exemplary structure taken along a horizontal plane BB'. A vertical plane AA' is Fig.19A A plane of a vertical section.

[0055] Fig. 20 is a vertical cross-sectional view of a fifth configuration of the fourth exemplary structure including a three-dimensional array of ferroelectric memory elements according to the fourth embodiment of the present disclosure.

[0056] Fig.21A is a circuit diagram of a second exemplary structure, a third exemplary structure, and a fourth exemplary structure according to the present disclosure. Fig. 21B and Fig. 21C is shown for operation Fig.21A Table of exemplary voltages for the circuit. DETAILED DESCRIPTION

[0057] As described above, embodiments of the present disclosure relate to ferroelectric memory devices and methods of manufacturing the same that include both word lines and pass gate electrodes, various aspects of which are described in detail herein. The pass gate electrodes reduce or eliminate interference between adjacent ferroelectric memory cells in the same memory string.

[0058] The drawings are not drawn to scale. Multiple instances of elements can be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of elements. Serial numbers such as "first", "second" and "third" are only used to identify similar elements, and different serial numbers can be used throughout the specification and claims of the present disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. As used herein, a first element "on" a second element can be located on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0059] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0060] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0061] A monomeric three-dimensional memory array is a memory array in which multiple memory levels are formed on a single substrate such as a semiconductor wafer without a substrate in between. The term "monomeric" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monomeric memory device. For example, as described in U.S. Pat. No. 5,915,167, entitled "Three-dimensional Structure Memory", a non-monomeric stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory level before bonding, but since the memory level is initially formed above a separate substrate, such memory is not a true monomeric three-dimensional memory array. Various three-dimensional memory devices disclosed herein include monomeric three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein.

[0062] See also Figure 1A and Figure 1B, shows a first exemplary structure for forming a first ferroelectric memory device according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 109, which may be a semiconductor substrate, an insulating substrate, or a conductive substrate. For example, the substrate 109 may include a commercially available silicon wafer. In the case where the substrate 109 includes a semiconductor material or a conductive material, an insulating spacer 10 may be formed over the substrate 109 to provide electrical isolation from the substrate 109 for the device to be formed thereon. The insulating spacer 10 includes a dielectric material such as silicon oxide, silicon nitride, or a dielectric metal oxide. For example, the insulating spacer 10 may include undoped silicate glass or doped silicate glass, and may have a thickness in the range of 10 nm to 500 nm, but smaller and larger thicknesses may also be used.

[0063] The channel gate isolation dielectric layer 132 is deposited on the insulating spacer layer 10 and is patterned to form a line groove extending laterally in a horizontal direction, which is referred to as the gate direction gd in this article. The gate isolation dielectric layer 132 is an insulating material layer having a horizontal top surface. At least one conductive material can be deposited in the line groove. The at least one conductive material may include at least one metal material and / or at least one heavily doped semiconductor material. For example, a combination of a conductive metal nitride (such as TiN, TaN or WN) and a conductive filling material (such as W, Co, Mo, Ru, Cu, etc.) can be deposited in the line groove. The excess portion of the at least one conductive material can be removed from above the horizontal plane of the top surface of the remaining portion of the channel gate isolation dielectric layer 132. The remaining portion of the at least one conductive material in the line groove includes a channel gate electrode 36. As used herein, "channel gate electrode" refers to an electrode, such as a back gate electrode, for controlling the flow of current flowing through a semiconductor channel, regardless of the voltage applied to the word line positioned adjacent to the semiconductor channel. In addition to the channel gate electrode 36, a select gate electrode (26, 66) may be formed. As used herein, a "select gate electrode" refers to an electrode that can enable or disable current flow through a semiconductor channel. The select gate electrode (26, 66) may include a source-side select gate electrode 26 formed on one side of the channel gate electrode 36 and a drain-side select gate electrode 66 formed on the other side of the channel gate electrode 66.

[0064] Alternatively, the select gate electrodes (26, 66) and the channel gate electrode 36 may be formed before forming the channel gate isolation dielectric layer 132. A conductive layer may be formed and patterned to form the rail-shaped select gate electrodes (26, 66) and the channel gate electrode 36. A dielectric material is then formed over and between these electrodes and planarized to remove the dielectric material from over these electrodes, thereby forming the gate isolation dielectric layer 132 between the electrodes (26, 66, 36).

[0065] A gate dielectric layer 52 may be deposited on top surfaces of the channel gate electrode 36, the select gate electrode (26, 66), and the channel gate isolation dielectric layer 132. The gate dielectric layer 52 includes a gate dielectric layer material such as silicon oxide and / or a dielectric metal oxide.

[0066] See also Figure 2A and Figure 2B , a semiconductor material may be deposited over the gate dielectric layer 52 and may be patterned into strips extending laterally along a channel direction cd, which may be perpendicular to the gate direction gd. The semiconductor material may include, for example, silicon (e.g., amorphous silicon or polycrystalline silicon), a silicon-germanium alloy, or a compound semiconductor material. The semiconductor material may have a first conductivity type of doping, which may be p-type or n-type. The atomic concentration of the first conductivity type of electrical dopant in the semiconductor material may be between 1.0×10 15 / cm 3 to 1.0×10 18 / cm 3 The thickness of the patterned semiconductor material strips may be in the range of 3 nm to 60 nm, such as 6 nm to 30 nm, but smaller and larger atomic concentrations may also be used. The patterned semiconductor material strips may be laterally spaced apart by linear trenches extending laterally in the channel direction cd.

[0067] Source regions 28 and drain regions 68 may be formed on or in opposite ends of the strip of semiconductor material. The source regions and drain regions may include corresponding source and drain lines or discrete doped semiconductor regions electrically connected to the corresponding source and drain lines. For example, a masked ion implantation process may be used to implant dopants of the second conductivity into the end portions of the strip of semiconductor material. The implanted portions of the patterned strip of semiconductor material may be located outside the region including the channel gate electrode 36 and the select gate electrode (26, 66). Source regions 28 may be formed in each implanted portion of the strip of semiconductor material adjacent to the source side select gate electrode 26, and drain regions 68 may be formed in each implanted portion of the strip of semiconductor material adjacent to the drain side select gate electrode 66. Each continuous portion of the strip of semiconductor material extending between the source region 28 and the drain region 68 constitutes a semiconductor channel 160. The atomic concentration of the dopant of the second conductivity type in the source region 28 and the drain region 68 may be between 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3 However, smaller and larger atomic concentrations may also be used.

[0068] Dielectric material such as silicon oxide is deposited in the line trench. The excess portion of the dielectric material covering the horizontal plane above the top surface of the semiconductor channel 160 is removed by a planarization process. The planarization process may use recess etching and / or chemical mechanical planarization. The remaining portion of the deposited dielectric material constitutes a channel isolation dielectric layer 162, which may include a plurality of strips extending laterally along the channel direction cd and a matrix portion laterally surrounding the entire area including the semiconductor channel 160, the source region 28 and the drain region 68.

[0069] Alternatively, the trench isolation dielectric layer 162 may be first formed by depositing a dielectric material and patterning the dielectric material into the track-shaped portions of the trench isolation dielectric layer 162. The semiconductor channel 160 is then formed by depositing a semiconductor material between and over the track-shaped portions of the trench isolation dielectric layer 162 and planarizing the semiconductor material to leave the track-shaped semiconductor channel 160 between the track-shaped portions of the trench isolation dielectric layer 162.

[0070] See also Figure 3A and Figure 3B , an interlayer (e.g., blocking) dielectric layer 156, a ferroelectric material layer 154L, and at least one conductive material layer may be sequentially deposited over the semiconductor channel 160 and the channel isolation dielectric layer 162. The interlayer dielectric layer 156 includes a dielectric material such as silicon oxide, silicon nitride, or a dielectric metal oxide. The thickness of the interlayer dielectric layer 156 may be in the range of 0.5 nm to 6 nm, such as 1 nm to 3 nm, but smaller and larger thicknesses may also be employed.

[0071] The ferroelectric material layer 154L includes a ferroelectric material. As used herein, "ferroelectric material" refers to a crystalline material that exhibits spontaneous electric polarization in the absence of an external electric field. The ferroelectric material in the ferroelectric material layer 154L can be an insulating ferroelectric material. In one embodiment, the ferroelectric material layer 154L includes an orthorhombic hafnium oxide layer, which contains at least one dopant selected from Al, Zr and / or Si. Other suitable ferroelectric materials may also be used, such as titanate ferroelectric materials (e.g., barium titanate, lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate ("PLZT"), etc.). The ferroelectric material layer 154L may have a thickness in the range of 3nm to 60nm, such as 6nm to 30nm, but smaller and larger thicknesses may also be used. In one embodiment, the ferroelectric material layer 154L may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0072] The at least one conductive material may include at least one metal material and / or at least one heavily doped semiconductor material. In one embodiment, the at least one conductive material may include a layer stack of a conductive metal nitride barrier layer and a metal layer, the conductive metal nitride barrier layer comprising a conductive metal nitride material (such as TiN, TaN and / or WN), and the metal layer comprising a metal (such as W, Mo, Cu, Co, Ru, etc.). The at least one conductive material may be patterned into a strip shape extending in the direction gd and covering the semiconductor channel 160. Each patterned strip of the at least one conductive material constitutes a word line 46, which is the control gate electrode of each semiconductor channel in the semiconductor channel 160 below. In one embodiment, each word line 46 covers a corresponding one of the channel gate electrodes 36. In another embodiment, the word line and the channel gate electrode may be laterally offset from each other.

[0073] A dielectric material may be deposited around word lines 46 and may be planarized to provide word line isolation dielectric layer 142. Alternatively, word line isolation dielectric layer 142 may be formed and patterned before word lines 46 are formed, and word lines 46 are formed in openings in word line isolation dielectric layer 142 by a damascene process. A stack of interlayer dielectric portions and ferroelectric material portions may be formed between each word line 46 and each semiconductor channel in semiconductor channel 160. Each interlayer dielectric portion includes a portion of interlayer dielectric layer 156. Each ferroelectric material portion is a portion of ferroelectric material layer 154L. Thus, the interlayer dielectric portion is formed as a portion of interlayer dielectric layer 156 and is located below a corresponding one of word lines 46. The ferroelectric material portion is formed as a portion of ferroelectric material layer 154L and is located below a corresponding one of word lines 46.

[0074] See also Figure 4A and Figure 4B , showing an alternative configuration of the first exemplary structure according to the first embodiment of the present disclosure. In this configuration, Figure 3A and Figure 3B In the processing step for patterning the at least one conductive material,

[0075] The anisotropic etching process is used to etch through the at least one conductive material and the ferroelectric material layer 154L. In other words, the ferroelectric material layer 154L is patterned using the same etching mask used to pattern the at least one conductive material into the word line 46. The ferroelectric material layer 154L is patterned into a ferroelectric material portion 154 having the same horizontal cross-sectional shape as the overlying word line in the word line 46.

[0076] Generally, a layer stack of ferroelectric material layer 154L and at least one conductive material layer may be formed above interlayer dielectric layer 156. An anisotropic etching process may be used to pattern the layer stack into discrete material stacks. Each of the discrete material stacks may include a patterned portion of ferroelectric material layer 154L constituting one of ferroelectric material portions 154, and a patterned portion of the at least one conductive material layer constituting one of word lines 46.

[0077] See also Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B , each combination of the semiconductor channel 160 and the adjacent portions of the word line 46, the channel gate electrode 36, the select gate electrode (26, 66), the gate dielectric layer 52, and the interlayer dielectric layer 156 constitutes a ferroelectric memory string, wherein data can be stored in the form of ferroelectric polarization directions in the ferroelectric material portion located between the semiconductor channel 160 and the word line 46. The ferroelectric polarization of each ferroelectric material portion can point toward or away from the semiconductor channel 160.

[0078] The present invention provides a memory device including at least one ferroelectric memory string. Each of the at least one ferroelectric memory string includes: a semiconductor channel 160 extending between a source region 28 and a drain region 68; a gate dielectric layer 52 located on a first longitudinal surface (such as a bottom surface) of the semiconductor channel 160, the first longitudinal surface extending between the source region 28 and the drain region 68, for example, along a channel direction cd; a channel gate electrode 36 located on the gate dielectric layer 52 and extending between the source region 28 and the drain region 68; and a word line 46 located above a second longitudinal surface (such as a top surface) of the semiconductor channel 160 between the source region 28 and the drain region 68, wherein the second longitudinal surface is located on an opposite side of the first longitudinal surface, and each of the word lines 46 is separated from the second longitudinal surface by a corresponding ferroelectric material portion (154L or 154) and a corresponding interlayer dielectric portion (i.e., a portion of the interlayer dielectric layer 156).

[0079] In one embodiment, the interlayer dielectric portion within each of the at least one ferroelectric memory string includes a portion of the interlayer dielectric layer 156 that extends across each of the word lines 46 .

[0080] In one embodiment, the ferroelectric material portion within each of the at least one ferroelectric memory string includes a portion of the ferroelectric material layer 154L that extends from an area overlying the source region 28 to an area overlying the drain region 68 .

[0081] In one embodiment, the ferroelectric material portions within each of the at least one ferroelectric memory string include discrete ferroelectric material portions 154 separated from one another by intervening dielectric material portions, such as portions of the word line isolation dielectric layer 142 .

[0082] In one embodiment, each of the at least one ferroelectric memory string is located above an insulating material layer 10 having a horizontal top surface. The first longitudinal surface and the second longitudinal surface are parallel to the horizontal top surface of the insulating material layer 10.

[0083] See also Figure 5A and Figure 5B , showing a second exemplary structure for forming a second ferroelectric memory device according to a second embodiment of the present disclosure. A vertical alternating sequence (32L, 42L) of insulating layers 32L and sacrificial layers 42L may be formed above a substrate including a substrate semiconductor layer 9. The substrate semiconductor layer 9 may include doped single crystal silicon having a first conductivity type (e.g., p-type). The dopant may include a well in a single crystal silicon wafer (i.e., a well in the substrate semiconductor layer 9) or a background of a doped wafer. The atomic concentration of the dopant of the first conductivity type in the substrate semiconductor layer 9 may be between 1.0×10 15 / cm 3 Up to 3.0×10 18 / cm 3 The source region 28 (e.g., a portion of a doped source line or a doped region positioned to make electrical contact with the source line) may be formed in an upper portion of the substrate semiconductor layer 9. The source region 28 has a second conductivity type (e.g., n-type) that is opposite to the first conductivity type. The atomic concentration of the second conductivity type dopant in the source region within the substrate semiconductor layer 9 may be in the range of 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 However, smaller and larger atomic concentrations may also be used.

[0084] Insulating materials that can be used for insulating layer 32L include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, insulating layer 32L may include silicon oxide. Sacrificial layer 42L may be formed of any suitable sacrificial material that selectively removes the first material of insulating layer 32L. If insulating layer 32L includes silicon oxide, sacrificial layer 42L may include an insulating material such as silicon nitride, or a semiconductor material such as amorphous silicon or polycrystalline silicon.

[0085] Each of the insulating layer 32L and the sacrificial layer 42L may be deposited, for example, by chemical vapor deposition (CVD). Each of the insulating layer 32L and the sacrificial layer 42L may have a thickness in the range of 20nm to 50nm, but smaller and larger thicknesses may also be used. In one embodiment, each of the insulating layers 32L may have a first thickness, and each of the sacrificial layers 42L may have a second thickness. In one embodiment, the topmost insulating layer in the insulating layer 32L may have a greater thickness than the insulating layer 32L below. The combination of the insulating layer 32L and the sacrificial layer 42L constitutes a repeating unit that is repeated multiple times in the vertical direction. The total number of repetitions of the repeating unit may be in the range of 8 to 1,024, such as 32 to 256, but fewer and larger numbers of repetitions may also be used.

[0086] See also Fig. 6A and 6B , a photoresist layer may be applied over the topmost insulating layer 32L and may be photolithographically patterned to form a line and space pattern extending laterally along a first horizontal direction hd1. The line and space pattern may be transferred by the vertical alternating sequence (32L, 42L) to divide the vertical alternating sequence (32L, 42L) into a plurality of separated portions, which are laterally spaced from each other by line grooves 49 extending laterally along the first horizontal direction hd1 and laterally spaced along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The anisotropic etching process may stop on the top surface of the substrate semiconductor layer 9. The photoresist layer may then be removed, for example, by ashing.

[0087] The patterned portion of the insulating layer 32L includes the insulating strips 32. The patterned portion of the sacrificial layer 42L includes the sacrificial strips 42. The remaining portion of the vertical alternating sequence (32L, 42L) includes the word line stacks 31 and the channel gate stacks 33 of the insulating strips 32 and the sacrificial strips 42. The word line stacks 31 and the channel gate stacks 33 can be laterally alternated along the second horizontal direction hd2. Each adjacent pair of the word line stacks 31 and the channel gate stacks 33 can be laterally spaced apart by corresponding line trenches 49.

[0088] The width of each word line type stack 31 along the second horizontal direction hd2 may be in the range of 20nm to 200nm, but may also be smaller and larger widths. The width of each channel gate type stack 33 of the insulating strip 32 and the channel gate electrode 36 along the second horizontal direction hd2 may be in the range of 20nm to 200nm, but may also be smaller and larger widths. The width of each line trench 49 may be in the range of 20nm to 200nm, but may also be smaller and larger widths.

[0089] See also Fig. 7A and Figure 7B , a continuous ferroelectric material layer 54L can be formed on the physically exposed surface of the alternating stack (31, 33) and the substrate semiconductor layer 9 by conformal deposition such as chemical vapor deposition or atomic layer deposition. The continuous ferroelectric material layer 54L may include an insulating ferroelectric material. In one embodiment, the continuous ferroelectric material layer 54L includes an orthorhombic hafnium oxide layer, which contains at least one dopant selected from Al, Zr and / or Si. Other suitable ferroelectric materials may also be used, such as titanate ferroelectric materials (for example, barium titanate, lead titanate, lead zirconate titanate, lead lanthanum zirconate titanate ("PLZT"), etc.). The continuous ferroelectric material layer 54L may have a thickness in the range of 3nm to 60nm, such as 6nm to 30nm, but smaller and larger thicknesses may also be used.

[0090] See also Fig. 8A and Figure 8B , the volume of the line trench 49 is partially filled with a mask material layer 53 covering the continuous ferroelectric material layer 54L. The mask material layer 53 may include a material capable of being used as an etching mask. For example, the mask material layer 53 may include a hard mask material such as borosilicate glass, carbon or amorphous silicon.

[0091] The mask material layer 53 may be patterned so that the patterned portion of the mask material layer 53 covers each word line type stack 31 but does not cover the channel gate type stack 33. Therefore, the mask material layer 53 covers the first longitudinal sidewall of each line trench 49 (i.e., the sidewall of each word line type stack 31) but does not cover the second longitudinal sidewall of each line trench 49 (i.e., the sidewall of each channel gate type stack 33). In other words, the patterned mask material layer 53 covers one of a pair of longitudinal sidewalls of each line trench 49 and does not cover the other of a pair of longitudinal sidewalls of each line trench 49. As used herein, "longitudinal sidewall" refers to a sidewall extending laterally along the longitudinal direction of the line trench 49.

[0092] For example, a photoresist layer (not shown) may be applied over the mask material layer and may be patterned photolithographically. The pattern of the photoresist layer may then be transferred through the mask material layer 53 by anisotropic etching. The photoresist layer may then be removed, for example, by ashing. Unmasked portions of the continuous ferroelectric material layer 54L may be removed by an etching process. The continuous ferroelectric material layer 54L is divided into a plurality of ferroelectric material layers 54 that are laterally spaced apart along the second horizontal direction hd2. Each ferroelectric material layer 54 covers each word line type stack 31, but does not cover each channel gate type stack 33. The first longitudinal sidewall of each line groove 49 contacts a corresponding one of the ferroelectric material layers 54L, and the second longitudinal sidewall of each line groove 49 does not contact any one of the ferroelectric material layers 54. A line cavity 49' extending laterally along the first horizontal direction hd1 is present in each line groove 49. Each second longitudinal sidewall of the wire groove 49 is physically exposed to a corresponding one of the wire cavities 49 ′.

[0093] See also Fig.9A and 9B , portions of the masking material layer 53 and the ferroelectric material layer 54 overlying a horizontal plane including the top surface of the topmost insulating strip 32 may be removed, for example, by a planarization process such as chemical mechanical planarization. The ferroelectric material layer 54 may be divided into a pair of ferroelectric material layers 54 located on the sidewalls of each word line stack 31. Subsequently, the remaining portion of the masking material layer 53 may be removed selectively to the ferroelectric material layer 54, the alternating stacks (31, 33), and the substrate semiconductor layer 9. As used herein, removal of a first material is "selective" to a second material if the removal process removes the first material at a rate at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0094] The continuous dielectric material layer 56L may be deposited on the physically exposed surfaces of the ferroelectric material layer 54, the substrate semiconductor layer 9, and the alternating stack (31, 33). The continuous dielectric material layer 56L comprises a dielectric material such as silicon oxide, silicon nitride, or a dielectric metal oxide. The thickness of the continuous dielectric material layer 56L may be in the range of 0.5 nm to 6 nm, such as 1 nm to 3 nm, but smaller and larger thicknesses may also be employed. A line cavity 49' exists within each line trench 49.

[0095] See also Fig. 10A and Fig. 10B , an anisotropic etching process may be performed to remove horizontal portions of the continuous dielectric material layer 56L. Each remaining vertical portion of the continuous dielectric material layer 56L contacting the ferroelectric material layer 54 constitutes an interlayer dielectric layer 56. Each remaining vertical portion of the continuous dielectric material layer 56L contacting the sidewalls of the alternating stack (31, 33) constitutes a gate dielectric layer 52.

[0096] Subsequently, a sacrificial fill material may be deposited in each of the line cavities 49'. The sacrificial fill material includes a material that is selectively removable with respect to the material of the gate dielectric layer 52, the interlayer dielectric layer 56, the insulating strips 32, and the substrate semiconductor layer 9. For example, the sacrificial fill material may include amorphous carbon, diamond-like carbon (DLC), a silicon-germanium alloy, amorphous silicon, or a polymer material. The portion of the sacrificial fill material covering the horizontal plane including the topmost surface of the alternating stack (31, 33) may be removed by a planarization process such as chemical mechanical planarization and / or recess etching. Each remaining portion of the sacrificial fill material constitutes a sacrificial post guide 67R.

[0097] A group of contiguous material portions filling the line trench 49 constitute a line trench filling assembly (67R, 52, 56, 54). Each line trench filling assembly (67R, 52, 56, 54) includes a sacrificial post rail 67R, a gate dielectric layer 52, an interlayer dielectric layer 56 and a ferroelectric material layer 54.

[0098] See also Fig.11A and Fig. 11B A first photoresist layer may be optionally applied over the alternating stacks (31, 33) and the line trench fill components (67R, 52, 56, 54) and may be photolithographically patterned to form linear openings extending along a first horizontal direction and overlying a respective one of the alternating stacks (31, 33). Each linear opening in the photoresist layer may overlying a middle portion of a respective one of the word line stacks 31. An anisotropic etching process may be performed to transfer the pattern of the linear openings in the first photoresist layer through the topmost insulating strips 32 and the sacrificial strips 42. The first photoresist layer may then be removed, for example, by ashing.

[0099] A second photoresist layer may be applied over the topmost insulating strip 32 and the line trench fill component (67R, 52, 56, 54) and may be patterned photolithographically to form a two-dimensional array of discrete openings. The two-dimensional array of discrete openings may include multiple rows of discrete openings. Each row of discrete openings extends laterally along a first horizontal direction hd1 and overlies a corresponding one of the line trench fill components (67R, 52, 56, 54). In one embodiment, each discrete opening in the second photoresist layer may include a pair of straight edges parallel to the second horizontal direction hd2 and extend along the second horizontal direction hd2 across the entire width of the corresponding underlying line trench fill component (67R, 52, 56, 54). In one embodiment, each discrete opening in the second photoresist layer may have a rectangular shape.

[0100] An anisotropic etching process is performed to transfer the pattern of discrete openings in the second photoresist layer through the line trench filling component (67R, 52, 56, 54). A two-dimensional array of rectangular column cavities can be formed in the volume of the etched portion from which the line trench filling component (67R, 52, 56, 54) is removed. Each rectangular column cavity can extend vertically through the entire height of the line trench filling component (67R, 52, 56, 54), and the top surface of the substrate semiconductor layer 9 can be physically exposed at the bottom of each rectangular column cavity. Each line trench filling component (67R, 52, 56, 54) can be divided into a plurality of separated portions spaced laterally apart along a first horizontal direction hd1. Each of the plurality of separated portions constitutes a memory column structure (67, 52, 56, 54) in the process. The second photoresist layer can be removed, for example, by ashing.

[0101] Each of the memory pillar structures (67, 52, 56, 54) in the process includes, from one side to the other, a ferroelectric material layer 54, an interlayer dielectric layer 56, a sacrificial pillar portion 67, and a gate dielectric layer 52. Each ferroelectric material layer 54 in the memory pillar structures (67, 52, 56, 54) in the process is a patterned portion of the ferroelectric material layer 54 in the corresponding line trench filling component (67R, 52, 56, 54). Each interlayer dielectric layer 56 in the memory pillar structures (67, 52, 56, 54) in the process is a patterned portion of the interlayer dielectric layer 56 in the corresponding line trench filling component (67R, 52, 56, 54).

[0102] Each sacrificial pillar portion 67 in the process memory pillar structure (67, 52, 56, 54) is a patterned portion of the sacrificial pillar guide 67R in the corresponding line trench filling component (67R, 52, 56, 54). Each gate dielectric layer 52 in the process memory pillar structure (67, 52, 56, 54) is a patterned portion of the gate dielectric layer 52 in the corresponding line trench filling component (67R, 52, 56, 54). Each process memory pillar structure (67, 52, 56, 54) may have a pair of straight sidewalls extending along the second horizontal direction. Each component of the process memory pillar structure (67, 52, 56, 54) may have a uniform width along the first horizontal direction hd1, which is the width of the corresponding process memory pillar structure (67, 52, 56, 54).

[0103] Dielectric material such as silicon oxide may be conformally deposited within rectangular pillar cavities located between each pair of laterally adjacent in-process memory pillar structures (67, 52, 56, 54) and within the line trenches separating the alternating stacks (31, 33). Excess portions of the dielectric fill material may be removed from above a horizontal plane including the topmost surface of the topmost insulating strip 32. Each remaining portion of the dielectric material filling a corresponding rectangular pillar cavity constitutes a dielectric pillar structure 64. Each remaining portion of the dielectric material filling a corresponding line trench constitutes a drain select level dielectric isolation structure 72.

[0104] In one embodiment, a corresponding dielectric pillar structure 64 is formed between each pair of laterally adjacent in-process memory pillar structures (67, 52, 56, 54) within each of the line trenches 49. A row of dielectric pillar structures 64 is formed within each line trench 49. The row of dielectric pillar structures 64 is interleaved with a row of in-process memory pillar structures (67, 52, 56, 54) within each line trench 49. Thus, a laterally alternating sequence of in-process memory pillar structures (67, 52, 56, 54) and dielectric pillar structures 64 is formed in each line trench 49.

[0105] See also Fig. 12A and Fig. 12B , the sacrificial pillar portion 67 can be selectively removed with respect to the materials of the gate dielectric layer 52, the interlayer dielectric layer 56, the substrate semiconductor layer 9, and the dielectric pillar structure 64. A channel cavity 69 is formed in each volume from which the sacrificial pillar portion 67 is removed. The top surface of the substrate semiconductor layer 9 can be physically exposed at the bottom of each channel cavity 69. The gate dielectric layer 52 is physically exposed on one side of each channel cavity 69, and the interlayer dielectric layer 56 is physically exposed on the opposite side of each channel cavity 69. The sidewalls of a pair of dielectric pillar structures 64 can be physically exposed to the channel cavity 69.

[0106] See also Fig.13A and Fig. 13B, a doped semiconductor material having a first conductivity type may be deposited in the channel cavity 69 by a conformal deposition process. The semiconductor material may be selected from at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the conformally deposited semiconductor material comprises amorphous silicon or polycrystalline silicon. The atomic concentration of the first conductivity type electrical dopant in the semiconductor material may be between 1.0×10 15 / cm 3 to 1.0×10 18 / cm 3 The semiconductor material may be deposited in the range of 2 nm to 20 nm, although smaller and greater atomic concentrations may also be used. The semiconductor material may be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the deposited semiconductor material may be in the range of 2 nm to 20 nm, although smaller and greater thicknesses may also be used. After deposition of the semiconductor material, an optional unfilled volume may exist within each channel cavity 69.

[0107] A dielectric fill material such as silicon oxide may be deposited in the unfilled volume of the channel cavity 69. The deposited semiconductor material and the excess portion of the dielectric fill material overlying the horizontal plane including the top surface of the topmost insulating strip 32 may be removed by a planarization process. For example, the first recess etching process may vertically recess the dielectric fill material to a height below the horizontal plane including the top surface of the topmost insulating strip 32. The first recess etching process may etch the dielectric fill material selective to the underlying semiconductor material. Each remaining portion of the dielectric fill material in the channel cavity 69 constitutes a dielectric core 62. The horizontal portion of the semiconductor material overlying the horizontal plane including the top surface of the topmost insulating strip 32 may be removed by a second recess etching process. The second recess etching process may etch the semiconductor material selective to the materials of the insulating strip 32 and the dielectric core 62. Each remaining portion of the semiconductor material in the channel cavity 69 constitutes a vertical semiconductor channel 60. Each vertical semiconductor channel 60 is formed in a corresponding channel cavity 69 on a corresponding pair of interlayer dielectric layers 56 and gate dielectric layers 52.

[0108] Drain regions 68 may be formed by depositing a doped semiconductor material within each recessed region above dielectric core 62. Drain regions 68 may have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in drain regions 68 may be between 5.0×10 18 / cm 3 Up to 2.0×10 21 / cm 3, but smaller and larger dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material may be removed from above the top surface of the topmost insulating strip 32 to form a drain region 68, for example, by chemical mechanical planarization (CMP) or recess etching. In one embodiment, a surface portion of the substrate semiconductor layer 9 extending between the vertical semiconductor channel 60 and the bottom end of the source region 28 constitutes a horizontal semiconductor channel 59. In this case, each semiconductor channel (59, 60) may include a vertical semiconductor channel 60 and a horizontal semiconductor channel 59. Alternatively, the source region 28 may be constructed so that the bottom end of each vertical semiconductor channel 60 contacts a corresponding one of the source regions 28. In this case, each semiconductor channel 60 may be composed of a vertical semiconductor channel 60.

[0109] The memory pillar structure (54, 56, 60, 62, 68, 52) may be formed between each pair of laterally adjacent dielectric pillar structures 64 within each line trench 49. Each memory pillar structure (54, 56, 60, 62, 68, 52) may include a ferroelectric material layer 54, an interlayer dielectric layer 56, a vertical semiconductor channel 60, a dielectric core 62, and a gate dielectric layer 52.

[0110] Subsequently, openings such as trenches or vias are formed through the structure to expose the sacrificial strips 42. The sacrificial strips 42 are removed through the openings by selective etching to form horizontal recesses between the insulating strips 32. Conductive material is deposited into the recesses through the openings. The conductive material may include a conductive metal nitride barrier material (such as TiN, WN or TN) and / or a metal fill material (such as W, Al, Cu, Ru, Ti, Mo and / or their alloys). The conductive material is then removed from the openings by anisotropic etching to leave various electrodes and lines in the recesses.

[0111] like Fig. 13C and Fig.13D As shown, these electrodes and lines include word lines 46, channel gate electrodes 36, and two types of drain side select gate electrodes (44, 66). The word lines 46 and the first type of drain side select gate electrodes 44 are located in the word line type stack 31. The channel gate electrodes 36 and the second type of drain side select gate electrodes 66 are located in the channel gate type stack 33. The respective drain side select gate electrodes (44, 66) overlie the respective word lines 46 and channel gate electrodes 36 in their respective alternating stacks (31, 33). Each of the drain side select gate electrodes (44, 66) serves as a select gate electrode that selects or deselects the vertical semiconductor channel 60 for programming, erasing, or reading operations.

[0112] A bit line level insulating layer 82 is formed over drain region 68 and alternating stack (31, 33). An opening is formed in bit line level insulating layer 82 to expose drain region 68. Bit line 98 and optional drain contact via structure 88 are formed in the opening in electrical contact with drain region 68.

[0113] See also FIG. 5A to FIG. 13D All the figures of the present invention provide a memory device including at least one ferroelectric memory string. Each of the at least one ferroelectric memory string includes: a semiconductor channel (59, 60) extending between a source region 28 and a drain region 68; a gate dielectric layer 52 located on a first longitudinal surface (which is a first vertical surface) of the semiconductor channel 60; a channel gate electrode 36 located on the gate dielectric layer 52 and extending between the source region and the drain region 68; and a word line 46 located above a second longitudinal surface of the semiconductor channel (59, 60) between the source region 28 and the drain region 68, wherein the second longitudinal surface is located on an opposite side of the first longitudinal surface, and each of the word lines 46 is separated from the second longitudinal surface by a corresponding ferroelectric material portion (which is a portion of a ferroelectric material layer 54) and a corresponding interlayer dielectric portion (which is a portion of a corresponding interlayer dielectric layer 56).

[0114] In one embodiment, the interlayer dielectric portion within each of the at least one ferroelectric memory string includes a portion of the interlayer dielectric layer 56 that extends across each of the word lines 46 .

[0115] In one embodiment, the source region 28 is located in an upper portion of the substrate semiconductor layer 9 below the word line 46 , and the first and second longitudinal surfaces are perpendicular to a top surface of the substrate semiconductor layer 9 .

[0116] In one embodiment, each of the word lines 46 is located at the same vertical distance from the top surface of the substrate semiconductor layer 9 as a corresponding one of the channel gate electrodes 36 within each ferroelectric memory string. In one embodiment, each of the word lines 46 has the same material composition and the same thickness as a corresponding one of the channel gate electrodes 36.

[0117] In one embodiment, the gate dielectric layer 52, the semiconductor channel 60, the ferroelectric material portion 54, and the interlayer dielectric portion 56 within each ferroelectric memory string have the same width along a longitudinal direction perpendicular to the semiconductor channel 60 (i.e., a vertical direction) and parallel to the first longitudinal surface and the second longitudinal surface (such as the first horizontal direction hd1).

[0118] In one embodiment, the semiconductor channel 60 within each ferroelectric memory string has a hollow rectangular horizontal cross-sectional shape having an outer rectangular perimeter and an inner rectangular perimeter (e.g., as shown in FIG. Fig. 13B shown).

[0119] In one embodiment, the at least one ferroelectric memory string includes at least one row of ferroelectric memory strings spaced laterally along a first horizontal direction hd1; each of the word lines 46 extends laterally along the first horizontal direction hd1 and is shared between each row of ferroelectric memory strings; and each of the channel gate electrodes 36 extends laterally along the first horizontal direction hd1 and is shared between each row of ferroelectric memory strings.

[0120] In one embodiment, a memory device includes a two-dimensional array of ferroelectric memory strings including a plurality of rows of ferroelectric memory strings laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0121] The third exemplary structure in various configurations of the third embodiment may be derived from the second exemplary structure of the second embodiment. FIG. 14A to FIG. 14D , Fig.15A and Fig. 15B as well as FIG. 16A to FIG. 16C Various configurations of the third exemplary structure of the third embodiment that can be derived from the second exemplary structure of the second embodiment are shown.

[0122] See also FIG. 14A to FIG. 14D , shows a first configuration of a third exemplary structure according to a third embodiment of the present disclosure, which includes a three-dimensional array of discrete ferroelectric memory portions 154 instead of the ferroelectric material layer 54 shown in the second embodiment. The discrete ferroelectric memory portions 154 include the same ferroelectric material as the ferroelectric material layer 54. The discrete ferroelectric memory portions 154 are located in lateral recesses between adjacent insulating strips 32 adjacent to the word lines 46. The discrete ferroelectric memory portions 154 positioned adjacent to the same vertical semiconductor channel 60 are vertically separated from each other by a corresponding one of the insulating strips 32.

[0123] Optionally, a blocking dielectric portion 157 is located between each word line 46 and an adjacent discrete ferroelectric memory portion 154. The blocking dielectric portion 157 may be located in the same lateral recess as the adjacent discrete ferroelectric memory portion 154. The blocking dielectric portion 157 may include any suitable electrically insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a dielectric metal oxide, such as aluminum oxide.

[0124] The first configuration of the third exemplary structure also includes a dielectric pillar structure 364, which may be wider than the dielectric pillar structure 64 of the second exemplary structure in the first horizontal direction hd1. In one embodiment, each of the dielectric pillar structures 364 may have a corresponding rectangular horizontal cross-sectional shape. The vertical semiconductor channel 60 in the first configuration of the third exemplary structure has a strip shape extending in the first horizontal direction hd1, such as Fig. 14B and Fig.14D shown, instead of Fig.13D The second exemplary structure shown has a hollow rectangular shape.

[0125] A laterally alternating sequence of memory pillar structures (52, 60, 62, 68, 56, 154, 157) and dielectric pillar structures 364 may be located in each line trench extending in the first horizontal direction hd1. A two-dimensional array of memory pillar structures (52, 60, 62, 68, 56, 154, 157) may be provided, which includes a three-dimensional array of discrete ferroelectric memory portions 154.

[0126] See also Fig.15A and Fig. 15B , shows a second configuration of the third exemplary structure that can be derived from the first configuration of the third exemplary structure. In the second configuration, the insulating strip 32 of the first configuration is replaced with an insulating strip 332 containing a cavity. The insulating strip 332 containing a cavity may include a cavity (i.e., an air gap) 333 surrounded by a dielectric material such as silicon oxide of the insulating strip 332 containing a cavity.

[0127] The cavity-containing insulating strip 332 can be formed by selectively removing the insulating strip 32 to form a lateral recess before or after forming the word line 46. A dielectric material layer can be deposited in the lateral recess by a non-conformal deposition process (such as plasma enhanced chemical vapor deposition) to form the cavity-containing insulating strip 332. The dielectric material may include, for example, porous or non-porous organic silicate glass or silicate glass. Each of the cavity-containing insulating strips 332 may include a corresponding encapsulated cavity 333 (e.g., an air gap) and an encapsulated insulating material portion that does not contain any solid phase material. Each encapsulated cavity may be filled with an inert gas or air. Each encapsulated insulating material portion includes a closed inner surface that defines the scope of the cavity encapsulated therein.

[0128] Generally, the layout of dielectric pillar structures 364 may be selected to facilitate the electrical routing of various metal interconnect structures that are subsequently formed. For example, each of drain regions 68 may be connected to a corresponding drain contact via structure 88 (at Fig. 13C The bit line 98 extending laterally along the second horizontal direction hd2 (in Fig. 13C) may be formed on a corresponding subset of the drain contact via structures 88. The dielectric pillar structures 364 in adjacent line trenches 49 may be aligned in a row in the second horizontal direction hd2, as shown in FIG. Fig. 13B and Fig.13D , Fig. 14B and Fig.14D as well as Fig. 15B shown.

[0129] See also Fig.16A and Fig. 16B , a third configuration of the third exemplary structure can be derived from the second configuration by staggering the dielectric pillar structures 364 along the second horizontal direction hd2. In this case, adjacent rows of dielectric pillar structures 364 can be laterally offset by p / N along the first horizontal direction, where p is the pitch of the dielectric pillar structures 364 within each row of dielectric pillar structures 364 located in the corresponding line trench 49 (i.e., the center-to-center distance between adjacent pairs), and N is an integer greater than 1. N can be, for example, 2, 3, 4, 5, etc. The lateral offset of the drain region 68 facilitates routing the drain contact via structure to the bit line.

[0130] See also FIG. 14A to FIG. 16B And according to various embodiments of the present disclosure, there is provided a three-dimensional memory device, the three-dimensional memory device comprising: a vertical alternating stack (31, 33) of insulating strips (32 or 332) and conductive strips (46, 36, 44, 66) located above a substrate 9, wherein the vertical alternating stacks extend laterally along a first horizontal direction hd1 and are laterally spaced apart from each other along a second horizontal direction hd2 by line grooves 49; and a laterally alternating sequence of memory pillar structures (157, 154, 56, 60, 62, 68, 52) and dielectric pillar structures 364 located in the line grooves 49, wherein the memory pillar structures (157, 154, 56, 60, 62, 68, 52) are arranged in a plurality of layers. 2) each includes: a vertical semiconductor channel 60 contacting the substrate (9, 28) and extending to a horizontal plane including the topmost surface of the vertical alternating stacks (31, 33); a gate dielectric layer 52 contacting a first sidewall of the vertical semiconductor channel 60 and a conductive strip (36, 66) within a first vertical alternating stack 33 of a pair of alternating stacks (31, 33); an interlayer dielectric layer 56 contacting a second sidewall of the vertical semiconductor channel 60 and a conductive strip (46, 44) within a second vertical alternating stack 31; and a vertical stack of discrete ferroelectric material portions 154 located between the interlayer dielectric layer 56 and the conductive strips (46, 44) of the second vertical alternating stack 31. The conductive strips (46, 36, 44, 66) may or may not include a drain side control gate electrode 44 and / or a drain side select gate electrode 66.

[0131] In one embodiment, vertical semiconductor channel 60 includes: a first vertical extending portion having a first sidewall; a second vertical extending portion having a second sidewall; and a horizontal portion adjoining a bottom end of the first vertical extending portion and a bottom end of the second vertical extending portion.

[0132] In one embodiment, the rectangular dielectric core 62 is located between the first vertical extension and the second vertical extension, overlying the horizontal portion of the vertical semiconductor channel 60 , and contacting a corresponding pair of dielectric pillar structures 364 .

[0133] In one embodiment, the vertical semiconductor channel 60 includes a doped semiconductor material having a first conductivity type; and a drain region 68 including a doped semiconductor material having a second conductivity type contacts an upper end of the vertical semiconductor channel 60. In one embodiment, the substrate 9 includes a source region 28 electrically connected to the vertical semiconductor channel 60.

[0134] In one embodiment, the three-dimensional memory device includes a blocking dielectric portion 157 located between the vertical stack of discrete ferroelectric material portions 154 and the conductive strips ( 46 , 44 ) of the second vertical alternating stack 31 .

[0135] In one embodiment, each of the blocking dielectric portions 157 contacts a corresponding one of the conductive strips (46, 44) of the second vertical alternating stack 31 and has the same height as the conductive strip. In one embodiment, each of the blocking dielectric portions 157 contacts a corresponding one of the discrete ferroelectric material portions 154 in the vertical stack of discrete ferroelectric material portions 154 and has the same height and width as the discrete ferroelectric material portion.

[0136] In one embodiment, the vertical semiconductor channel 60 , gate dielectric layer 52 , interlayer dielectric layer 56 , and vertical stack of discrete ferroelectric material portions 154 within each memory pillar structure ( 157 , 154 , 56 , 60 , 62 , 68 , 52 ) have a uniform width along the first horizontal direction hd1 .

[0137] In one embodiment, a subset of insulating strips 332 include corresponding cavities 333 therein, wherein each cavity is free of any solid phase material.

[0138] The fourth exemplary structure among various configurations of the fourth embodiment may be derived from the second exemplary structure of the second embodiment and the third exemplary structure of the third embodiment. FIG. 17A to FIG. 17C , 18A to 18C , Fig.19A and 19B as well as Fig. 20Various configurations of the fourth exemplary structure of the fourth embodiment that can be derived from the second exemplary structure of the second embodiment and the third exemplary structure of the third embodiment are shown.

[0139] See also FIG. 17A to FIG. 17C , shows a first configuration of a fourth exemplary structure according to a fourth embodiment of the present disclosure, which includes a ferroelectric material layer 54 and a virtual discrete ferroelectric memory portion 254 of the second embodiment, instead of the discrete ferroelectric memory portion 154 of the third embodiment. The virtual discrete ferroelectric memory portion 254 of the fourth embodiment is located in a vertical level adjacent to the insulating strip 32 between the vertical levels of the channel gate electrode 36. In other words, the virtual discrete ferroelectric memory portion 254 is located between a first horizontal plane corresponding to the top surface of the nearest underlying channel gate electrode 36 and a second horizontal plane corresponding to the bottom surface of the nearest overlying channel gate electrode 36. Therefore, the channel gate electrode 36 is located at a different distance from the substrate 9 than the virtual discrete ferroelectric memory portion 254. In other words, the virtual discrete ferroelectric memory portion 254 is positioned adjacent to the channel gate type stack 33 and is not intended to store data (e.g., 1 or 0). In contrast, the ferroelectric material layer 54 is positioned adjacent to the word line type stack 31 , and the portion of the ferroelectric material layer 54 positioned adjacent to the word line 46 serves as a memory cell for storing data (eg, 1 or 0).

[0140] The virtual discrete ferroelectric memory portion 254 of the fourth embodiment is located in the same vertical level as the corresponding insulating strips 32 and the virtual spacer dielectric layer 51 and is laterally located between these corresponding insulating strips and the virtual spacer dielectric layer. The virtual spacer dielectric layer 51 is located in the same vertical level as the corresponding virtual discrete ferroelectric memory portion 254 and the vertical semiconductor channel 60, and is laterally located between these corresponding virtual discrete ferroelectric memory portions and the vertical semiconductor channel. In other words, the virtual discrete ferroelectric memory portion 254, its laterally adjacent insulating strips 32, and its laterally adjacent virtual dielectric 51 are located between a first horizontal plane corresponding to the top surface of the nearest underlying channel gate electrode 36 and a second horizontal plane corresponding to the bottom surface of the nearest overlying channel gate electrode 36.

[0141] In addition, in the fourth embodiment, the dielectric pillar structures (64, 364) of the second and third embodiments may be omitted if necessary. Instead, dielectric trench filling structures 76 may be formed in the trenches extending through the channel gate type stack 33. The dielectric trench filling structures 76 extend continuously in the first horizontal direction hd1 and laterally separate the channel gate electrodes 36.

[0142] See also Fig.18A and Fig.18B, the second configuration of the fourth exemplary structure can be derived from the first configuration of the fourth exemplary structure by reducing the vertical height of the virtual discrete ferroelectric memory portion 254, so that each virtual discrete ferroelectric memory portion 254 is vertically spaced farther from the overlying and underlying channel gate electrodes 36 compared to the first configuration. For example, each virtual discrete ferroelectric memory portion 254 is vertically spaced farther from the overlying channel gate electrode and the underlying channel gate electrode 36 by the corresponding overlying protrusion and underlying protrusion 32P of the insulating strip 32. The protrusion 32P protrudes horizontally (i.e., laterally) from each insulating strip 31. The corresponding overlying protrusion and underlying protrusion 32P of the insulating strip 32 cover the upper and lower sides of the corresponding virtual discrete ferroelectric memory portion 254 in the vertical direction perpendicular to the substrate 9.

[0143] See also Fig.18C , the third configuration of the fourth exemplary structure can be derived from the second configuration of the fourth exemplary structure by increasing the vertical height of the channel gate electrode 36 in the area covering the virtual discrete ferroelectric memory portion 254 with reduced height. For example, each channel gate electrode 36 includes an upper protrusion and a lower protrusion 36P. In the vertical direction perpendicular to the substrate 9, the corresponding upper protrusion and lower protrusion 36P of the channel gate electrode cover the upper and lower sides of the corresponding adjacent virtual discrete ferroelectric memory portion 254. The protrusion 36P protrudes vertically from the channel gate electrode 36. Therefore, each virtual discrete ferroelectric memory portion 254 is located between the corresponding overlying protrusion 36P of the lower channel gate electrode 36 and the corresponding lower protrusion 36P of the overlying channel gate electrode 36 in the vertical direction perpendicular to the substrate 9.

[0144] See also Fig.19A and Fig.19B The fourth configuration of the fourth exemplary structure can be derived from the first configuration, the second configuration or the third configuration of the fourth exemplary structure by replacing the first insulating strip 32 in the word line type stack 31 of the first configuration, the second configuration or the third configuration with an insulating strip 332 containing a cavity (i.e., an air gap) 333 between the word lines 46 in the word line type stack 31.

[0145] See also Fig. 20 The fifth configuration of the fourth exemplary structure can be derived from the fourth configuration by replacing the second insulating strip 32 in the channel gate type stack 33 of the fourth configuration with an insulating strip 332 containing a cavity (i.e., an air gap) 333 between the channel gate electrodes 36 in the channel gate type stack 33, in addition to forming a cavity 333 in the word line type stack 31.

[0146] See also FIG. 17A to FIG. 20And according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which includes: a first vertical alternating stack 31 of a first insulating strip (32 or 332) and a first conductive strip including a word line 46 located above a substrate 9, wherein the first vertical alternating stack 31 extends laterally along a first horizontal direction hd1; a second vertical alternating stack 33 of a second insulating strip (32 or 332) and a second conductive strip including a channel gate electrode 36 located above the substrate 9, wherein the second vertical alternating stack 33 extends laterally along the first horizontal direction hd1 and is laterally spaced apart from the first alternating stack 31 along a second horizontal direction hd2; and a memory structure component including a combination of the following items: a line trench filling structure (254, 51, 60, 62, 68, 56, 54) located between the first vertical alternating stack 31 and the second vertical alternating stack 33, and a portion of a gate dielectric layer 52 located between adjacent channel gate electrodes 36 and the line trench filling structure (254, 51, 60, 62, 68, 56, 54). The memory structure component (254, 51, 60, 62, 68, 56, 54, 52) includes: a first ferroelectric material layer 54 contacting the sidewalls of each of the first insulating strip (32 or 332) and the first conductive strip (i.e., word line 46); and a virtual second ferroelectric material portion 254 located above the sidewall of the second vertical alternating stack 33; and a vertical semiconductor channel 60 located between the first ferroelectric material layer (i.e., ferroelectric material layer 54) and the virtual ferroelectric material portion 254. The semiconductor channel 60 extends vertically from the substrate 9 to a horizontal plane including the topmost surface of the first vertical alternating stack 31 and the second vertical alternating stack 33.

[0147] In one embodiment, the three-dimensional memory device includes an interlayer dielectric layer 56 contacting the first ferroelectric material layer (ie, ferroelectric material layer 54 ) and a first outer sidewall of the vertical semiconductor channel 60 .

[0148] In one embodiment, the spacer dielectric layer 51 contacts the second outer sidewall of the vertical semiconductor channel 60. In one embodiment, the spacer dielectric layer 51 can have the same composition and the same thickness as the interlayer dielectric layer 56. In one embodiment, the vertical semiconductor channel 60 includes a first vertical extension having a first outer sidewall, a second vertical extension having a second outer sidewall, and a horizontal portion connecting the bottom end of the first vertical extension portion and the bottom end of the second vertical extension portion and contacting the top surface of the substrate 9.

[0149] In one embodiment, a subset of the first insulating strips (32 or 332) and the second insulating strips (32 or 332) include corresponding cavities 333 therein. Each cavity does not contain any solid phase material.

[0150] Fig.21A1 is a circuit diagram of the first exemplary structure, the second exemplary structure, the third exemplary structure and the fourth exemplary structure of the present invention. Fig.21A Each channel gate electrode PL (which corresponds to the channel gate electrode 36 of the above-mentioned device) (represented by NFET in FIG. 1 ) provides a parallel gate conduction path to each vertical ferroelectric memory element control transistor (FeFET) controlled by a word line WL (which corresponds to the word line 46 of the above-mentioned device). The corresponding NFET and FeFET share a common semiconductor channel (60, 160) and are electrically connected in parallel between a common source line SL (e.g., 28) and a common bit line BL (e.g., 98). In one embodiment, a plurality of FeFETs electrically connected in series between a source line SL (e.g., 28) and a bit line BL (e.g., 98) share a common semiconductor channel (60, 160) and common drain side and source side select gate transistors SGD, SGS (including corresponding drain side and source select gate electrodes (26, 66)), which have a plurality of channel gate transistors (NFFETs) that are also connected in series between the same source line SL and the same bit line BL as the plurality of FeFETs. Although the pass-gate transistors are shown as NFETs, these transistors may alternatively comprise PFETs if desired.

[0151] The plurality of FeFETs connected in series form a NAND string comprising a series connection of field effect transistors having a variable threshold voltage controlled by the polarization of a corresponding ferroelectric material portion adjacent to a corresponding word line WL. A first end of each NAND string (e.g., the bottom end of each vertical NAND string) is connected to a source line SL, which may include a source region 28 in the device shown above. A second end of each NAND string (e.g., the top end of each vertical NAND string) is connected to a bit line BL (e.g., 98). Optionally, a source side select gate electrode 26 and a drain side select gate electrode 66 may be provided.

[0152] Fig. 21B and Fig. 21C is shown for operation Fig.21A Table of exemplary voltages for the circuit. Fig. 21B Exemplary voltages that may be used to operate a single level cell in a channel boosting scheme (columns 2, 3, and 4) and a direct channel potential control scheme (columns 5, 6, and 7) are shown. Fig. 21C Exemplary voltages for operating the multi-level cell in a channel boosting scheme (columns 2, 3, and 4) and a direct channel potential control scheme (columns 5, 6, and 7) are shown. The voltages shown are exemplary, and other suitable voltages may be used for different device sizes and materials.

[0153] As shown in these tables, the selected word line 46 (i.e., the word line of the selected memory cell) is set to a high negative voltage for writing / inhibiting, a high positive voltage for erasing / inhibiting, and 0V or a low positive / negative voltage for reading / inhibiting. The unselected word lines are floated for writing and erasing, and are set to 0V for reading / inhibiting. The selected channel gate electrode 36 (i.e., the channel gate electrode adjacent to the selected memory cell) is set to the channel voltage for writing and erasing, and is set to 0V for reading / inhibiting. The unselected channel gate electrodes are set to the channel voltage for writing and erasing, and are set to the read voltage for reading / inhibiting. The bit line is set to 0V / positive voltage for writing / inhibiting and erasing / inhibiting, and is set to Vdd for reading / inhibiting of the channel boosting scheme, and is set to 0V / negative voltage for writing / inhibiting, is set to 0V / positive voltage for erasing / inhibiting, and is set to Vdd for reading / inhibiting of the direct channel potential control scheme. The source line is set to a positive voltage for write / inhibit and erase / inhibit, and to 0V for read / inhibit. The SGD and SGS select transistors are set as shown in the table. The unit of operation is each page of the device.

[0154] Various configurations of the exemplary structure provide a memory device including at least one ferroelectric memory string, the at least one ferroelectric memory string including a word line and a channel gate electrode. In other words, the word line 46 and the ferroelectric memory element (i.e., the ferroelectric material portion 54, 154) are located on at least one side of the semiconductor channel 60, and the channel gate electrode 36 and the gate dielectric 52 are located on at least the other side of the semiconductor channel 60.

[0155] A pass gate transistor including a pass gate electrode 36 but lacking a ferroelectric memory element (ie, ferroelectric material portion 54, 154) reduces or eliminates interference between adjacent memory cells (ie, between adjacent FeFETs) in the same memory string.

[0156] Referring to all figures and embodiments of the present disclosure, the memory device includes a semiconductor channel (60, 160) extending between a source region 28 and a drain region 68, a plurality of channel gate electrodes 36, a plurality of word lines 46, a gate dielectric 52 located between the semiconductor channel (60, 160) and the plurality of channel gate electrodes 36, and a ferroelectric material portion (54, 154) located between the semiconductor channel and the plurality of word lines 46.

[0157] In one embodiment, the gate dielectric 52 includes a gate dielectric layer located on a first longitudinal surface of the semiconductor channel (60, 160), the channel gate electrode 36 is located on the gate dielectric layer in a first row between the source region and the drain region, the word line 46 is located above the second longitudinal surface of the semiconductor channel in a second row between the source region 28 and the drain region 68, the second longitudinal surface is located on the opposite side of the first longitudinal surface of the semiconductor channel (60, 160), and each of the word lines 46 is separated from the second longitudinal surface by a corresponding ferroelectric material portion (54, 154) and one of the corresponding interlayer dielectric portions 56.

[0158] In one embodiment, the interlayer dielectric portion 56 includes a portion of the interlayer dielectric layer located between the second longitudinal surface of the semiconductor channel and the ferroelectric material portion (54, 154). In one embodiment, the ferroelectric material portion (54, 154) includes a portion of the ferroelectric material layer 54 located above the second longitudinal surface of the semiconductor channel (60, 160), the ferroelectric material layer extending from an area overlying the source region 28 to an area overlying the drain region 68. In another embodiment, the ferroelectric material portion (54, 154) includes discrete ferroelectric material portions 154 separated by intervening dielectric material portions (32, 142). In one embodiment, the ferroelectric material portion (54, 154) includes orthorhombic hafnium oxide, the orthorhombic hafnium oxide including at least one dopant selected from at least one of Al, Zr or Si.

[0159] In Figures 1 to Figure 4B In the first embodiment shown, the semiconductor channel 160 extends horizontally above the insulating material layer 10 having a horizontal top surface, and the first and second longitudinal surfaces of the semiconductor channel are parallel to the horizontal top surface of the insulating material layer 10 .

[0160] exist FIG. 5A to FIG. 13D In the second embodiment shown, the semiconductor channel 60 extends vertically above the substrate 9 having a horizontal top surface, and the first and second longitudinal surfaces of the semiconductor channel 60 are perpendicular to the horizontal top surface of the substrate 9 .

[0161] In one embodiment, the source region 28 is located in an upper portion of the substrate 9 below the word lines 46, each of the word lines 46 is located at the same vertical distance from the top surface of the substrate 9 as a corresponding one of the channel gate electrodes 36, and each of the word lines 46 has the same material composition and the same thickness as a corresponding one of the channel gate electrodes 36.

[0162] In one embodiment, the word lines 46 are separated from each other by respective first insulating strips ( 32 , 332 ) in the word line type stack 31 , and the channel gate electrodes 36 are separated from each other by respective second insulating strips ( 32 , 332 ) in the channel gate type stack 33 .

[0163] In one embodiment, the semiconductor channel 60 has a hollow rectangular horizontal cross-sectional shape having an outer rectangular perimeter and an inner rectangular perimeter. The ferroelectric material portion (54, 154) is located in multiple rows of ferroelectric memory strings, the multiple rows of ferroelectric memory strings are laterally spaced apart along a first horizontal direction hd1 and extend along a second horizontal direction hd2 perpendicular to the first horizontal direction, each of the word lines 46 extends laterally along the first horizontal direction and is shared between the multiple rows of ferroelectric memory strings, and each of the channel gate electrodes 36 extends laterally along the first horizontal direction and is shared between the multiple rows of ferroelectric memory strings.

[0164] In the second embodiment, the third embodiment and the fourth embodiment, the three-dimensional memory device includes a word line type stack 31 of alternating first insulating strips (32, 332) and word lines 46 located above a substrate 9, a channel gate type stack 33 of alternating second insulating strips (32, 332) and channel gate electrodes 36 located above the substrate 9, a vertical semiconductor channel 60 located between the channel gate type stack 33 and the word line type stack 31, a gate dielectric 52 located between the vertical semiconductor channel 60 and the channel gate type stack 33, and a ferroelectric material portion (54, 154) located between the vertical semiconductor channel 60 and the word line type stack 31.

[0165] exist FIG. 14A to FIG. 16B In the third embodiment shown, the ferroelectric material portion (54, 154) includes discrete ferroelectric material portions 154 located in a lateral recess adjacent to the word line 46 and between adjacent first insulating strips 32, and the discrete ferroelectric memory portions 154 are vertically separated from each other by a corresponding one of the first insulating strips 32.

[0166] In one embodiment, the device further includes an interlayer dielectric layer 56 contacting a second sidewall of the vertical semiconductor channel 60 and contacting the discrete ferroelectric memory portion 154 , and a gate dielectric layer 52 contacting a first sidewall of the vertical semiconductor channel 60 and contacting the channel gate stack 33 .

[0167] In one embodiment, vertical semiconductor channel 60 includes a first vertical extending portion having a first sidewall, a second vertical extending portion having a second sidewall, and a horizontal portion adjoining a bottom end of the first vertical extending portion and a bottom end of the second vertical extending portion.

[0168] In one embodiment, the device also includes a pair of dielectric pillar structures 364 and a rectangular dielectric core 62, which is located between the first vertical extension portion and the second vertical extension portion of the vertical semiconductor channel 60, covers the horizontal portion of the vertical semiconductor channel 60, and contacts the pair of dielectric pillar structures 364.

[0169] In one embodiment, vertical semiconductor channel 60 includes a doped semiconductor material having a first conductivity type, and drain region 68 including a doped semiconductor material having a second conductivity type contacts an upper end of the vertical semiconductor channel. Substrate 9 includes source region 28 electrically connected to vertical semiconductor channel 60.

[0170] In one embodiment, blocking dielectric portions 157 are located in lateral recesses between discrete ferroelectric material portions 154 and word lines 46. Each of blocking dielectric portions 157 contacts a corresponding one of word lines 46 and has the same height as the word line. Each of blocking dielectric portions 157 contacts a corresponding one of discrete ferroelectric material portions 154 and has the same height and width as the discrete ferroelectric material portion. Fig.15A In one embodiment shown, the first and second insulating strips 332 include corresponding cavities 333 therein, wherein each cavity is free of any solid phase material.

[0171] exist FIG. 17A to FIG. 20 In the fourth embodiment shown, the ferroelectric material portion (54, 154) includes a portion of the ferroelectric material layer 54 located between the vertical semiconductor channel 60 and the word line stack 31. The virtual discrete ferroelectric memory portion 254 is located between the vertical semiconductor channel 60 and the channel gate electrode 36, in a vertical level adjacent to the second insulating strip (32, 332) between the vertical levels of the channel gate electrode 36. The channel gate electrode 36 is located at a different distance from the substrate 9 than the virtual discrete ferroelectric memory portion 254.

[0172] In such FIG. 18A to FIG. 18B In one embodiment shown, each virtual discrete ferroelectric memory portion 254 is vertically spaced apart from overlying and underlying channel gate electrodes 36 by respective overlying and underlying protruding portions 32P of the second insulating strip 32 .

[0173] exist Fig.18CIn another embodiment shown, each channel gate electrode 36 includes an upper protrusion and a lower protrusion 36P. In the vertical direction perpendicular to the substrate 9, the upper protrusion and the lower protrusion 36P of the channel gate electrode 36 cover the upper and lower sides of the corresponding adjacent virtual discrete ferroelectric memory portions 254. Each virtual discrete ferroelectric memory portion 254 is located between the corresponding overlying protrusion of the lower channel gate electrode and the lower protrusion of the overlying channel gate electrode in the vertical direction perpendicular to the substrate 9.

[0174] exist Fig. 20 In one embodiment shown, the first and second insulating strips 332 include corresponding cavities 333 therein, wherein each cavity is free of any solid phase material.

[0175] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A memory device, comprising: a semiconductor channel extending between the source region and the drain region; a plurality of channel gate electrodes; multiple word lines; a gate dielectric between the semiconductor channel and the plurality of channel gate electrodes; and a stack of an interlayer dielectric layer and a ferroelectric material portion between the semiconductor channel and the plurality of word lines, wherein the interlayer dielectric layer and the gate dielectric have the same material composition and the same thickness; and The gate dielectric and the interlayer dielectric layer include remaining vertical portions of a continuous dielectric material layer that is anisotropically etched to remove horizontal portions thereof.

2. The memory device according to claim 1, wherein: The gate dielectric includes a gate dielectric layer located on a first longitudinal surface of the semiconductor channel; The channel gate electrode is located on the gate dielectric layer in a first row between the source region and the drain region; The word line is located above a second longitudinal surface of the semiconductor channel in a second row between the source region and the drain region; the second longitudinal surface is located on an opposite side of the first longitudinal surface; and Each of the word lines is spaced apart from the second longitudinal surface by one of the ferroelectric material portion and an interlayer dielectric layer. 3 . The memory device of claim 2 , wherein the interlayer dielectric layer is located between the second longitudinal surface of the semiconductor channel and the ferroelectric material portion.

4. A memory device according to claim 2, wherein the ferroelectric material portion includes a portion of a ferroelectric material layer located above the second longitudinal surface of the semiconductor channel, and the ferroelectric material layer extends from an area overlying the source region to an area overlying the drain region.

5. The memory device of claim 2, wherein the ferroelectric material portions comprise discrete ferroelectric material portions separated by intervening dielectric material portions.

6. The memory device according to claim 1, wherein: The semiconductor channel extends vertically above a substrate having a horizontal top surface; and The first and second longitudinal surfaces of the semiconductor channel are perpendicular to the horizontal top surface of the substrate.

7. The memory device according to claim 6, wherein: The source region is located in an upper portion of the substrate below the word line; each of the word lines is located at the same vertical distance from the top surface of the substrate as a corresponding one of the pass gate electrodes; and Each of the word lines has the same material composition and the same thickness as a corresponding one of the pass gate electrodes.

8. The memory device according to claim 6, wherein: The word lines are separated from each other by respective first insulating strips in a word line type stack; and The channel gate electrodes are separated from each other by corresponding second insulating strips in the channel gate type stack. 9 . The memory device of claim 6 , wherein the semiconductor channel has a hollow rectangular horizontal cross-sectional shape having an outer rectangular perimeter and an inner rectangular perimeter.

10. The memory device of claim 1, wherein: The ferroelectric material portions are located in a plurality of rows of ferroelectric memory strings that are laterally spaced apart along a first horizontal direction and extend in a second horizontal direction that is perpendicular to the first horizontal direction; Each of the word lines extends laterally along the first horizontal direction and is shared between the plurality of rows of ferroelectric memory strings; and Each of the pass gate electrodes extends laterally along the first horizontal direction and is shared between the plurality of rows of ferroelectric memory strings.

11. The memory device of claim 1, wherein the ferroelectric material portion comprises orthorhombic hafnium oxide containing at least one dopant selected from at least one of Al, Zr, or Si.

12. The memory device of claim 1 , wherein: The semiconductor channel contacts a surface of the gate dielectric at a first interface; and The semiconductor channel contacts a surface of the interlayer dielectric layer at a second interface.

13. The memory device of claim 12, wherein: The first interface and the second interface are vertical; The first interface is located in a first vertical plane parallel to a first horizontal direction; and The second interface is located in a second vertical plane that is parallel to the first horizontal direction and is laterally spaced from the first vertical plane along a second horizontal direction that is perpendicular to the first horizontal direction.

14. The memory device of claim 1, further comprising a substrate including a substrate semiconductor layer having a horizontal top surface, wherein the gate dielectric and the interlayer dielectric layer extend in a vertical direction. 15 . The memory device of claim 14 , wherein the ferroelectric material portion is a portion of a ferroelectric material layer extending along the vertical direction.

16. The memory device of claim 15, wherein: The bottom end of the gate dielectric is in direct contact with the top surface of the substrate semiconductor layer; and A bottom end of the interlayer dielectric layer is vertically spaced apart from a top surface of the substrate semiconductor layer by a bottom portion of the ferroelectric material layer.

17. The memory device of claim 16, wherein a bottom portion of the ferroelectric material layer is in direct contact with a top surface of the substrate semiconductor layer.

18. The memory device of claim 16, wherein a sidewall of a bottom portion of the ferroelectric material layer directly contacts a sidewall of a bottom end of the semiconductor channel.

19. The memory device according to claim 14 further includes an alternating stack of insulating layers and conductive layers covering the substrate semiconductor layer, wherein each of the ferroelectric material portions is located between corresponding vertically adjacent pairs of insulating layers within the alternating stack and contacts horizontal surfaces of corresponding vertically adjacent pairs of insulating layers within the alternating stack and has the same height as a corresponding one of the conductive layers.

20. A three-dimensional memory device, comprising: a wordline stack of alternating first insulating strips and wordlines over the substrate; a channel-gate type stack of alternating second insulating strips and channel gate electrodes over the substrate; a vertical semiconductor channel between the channel gate type stack and the word line type stack; a gate dielectric between the vertical semiconductor channel and the channel-gate stack; and a portion of a ferroelectric material between the vertical semiconductor channel and the wordline stack; and The gate dielectric includes a remaining vertical portion of a continuous dielectric material layer that is anisotropically etched to remove horizontal portions thereof.

21. The three-dimensional memory device according to claim 20, wherein: The ferroelectric material portions include discrete ferroelectric material portions located in lateral recesses adjacent to the word line and between adjacent first insulating strips; and The discrete ferroelectric memory portions are vertically separated from each other by a respective one of the first insulating strips.

22. The three-dimensional memory device of claim 21 , further comprising an interlayer dielectric layer contacting a second sidewall of the vertical semiconductor channel and contacting the discrete ferroelectric memory portion, wherein a gate dielectric layer contacts a first sidewall of the vertical semiconductor channel and contacts the channel gate stack.

23. The three-dimensional memory device of claim 22, wherein the vertical semiconductor channel comprises: a first vertically extending portion having said first side wall; a second vertically extending portion having said second side wall; as well as A horizontal portion adjoins a bottom end of the first vertically extending portion and a bottom end of the second vertically extending portion.

24. The three-dimensional memory device according to claim 23, further comprising: a pair of dielectric pillar structures; as well as A rectangular dielectric core is located between the first vertical extension portion and the second vertical extension portion of the vertical semiconductor channel, the rectangular dielectric core covers the horizontal portion of the vertical semiconductor channel and contacts the pair of dielectric pillar structures.

25. The three-dimensional memory device of claim 23, wherein: The vertical semiconductor channel comprises a doped semiconductor material having a first conductivity type; and A drain region including a doped semiconductor material having a second conductivity type contacts an upper end of the vertical semiconductor channel.

26. The three-dimensional memory device of claim 25, wherein the substrate includes a source region electrically connected to the vertical semiconductor channel.

27. The three-dimensional memory device of claim 21, further comprising a blocking dielectric portion in the lateral recess between the discrete ferroelectric material portion and the word line. 28 . The three-dimensional memory device of claim 27 , wherein each of the blocking dielectric portions contacts a corresponding one of the word lines and has the same height as the word line.

29. The three-dimensional memory device of claim 27, wherein each of the blocking dielectric portions contacts a corresponding one of the discrete ferroelectric material portions and has the same height and the same width as the discrete ferroelectric material portions.

30. The three-dimensional memory device of claim 21, wherein the first insulating strip and the second insulating strip include corresponding cavities therein, wherein each cavity does not contain any solid phase material.

31. The three-dimensional memory device of claim 20, wherein the ferroelectric material portion comprises a portion of a ferroelectric material layer between the vertical semiconductor channel and the word line stack.

32. The three-dimensional memory device of claim 31 , further comprising a virtual discrete ferroelectric memory portion located between the vertical semiconductor channel and the channel gate electrode, in the vertical level adjacent to the second insulating strip between the vertical levels of the channel gate electrode.

33. The three-dimensional memory device of claim 32, wherein the channel gate electrode is located at a different distance from the substrate than the virtual discrete ferroelectric memory portion.

34. The three-dimensional memory device of claim 32, wherein each virtual discrete ferroelectric memory portion is vertically spaced apart from overlying and underlying channel gate electrodes by respective overlying and underlying protruding portions of the second insulating strip.

35. The three-dimensional memory device of claim 32, wherein each channel gate electrode comprises an upper protruding portion and a lower protruding portion.

36. The three-dimensional memory device according to claim 35, wherein the upper protruding portion and the lower protruding portion of the channel gate electrode cover above and below corresponding adjacent virtual discrete ferroelectric memory portions in a vertical direction perpendicular to the substrate.

37. The three-dimensional memory device of claim 36, wherein each virtual discrete ferroelectric memory portion is located between a corresponding overlying protruding portion of a lower channel gate electrode and a lower protruding portion of the overlying channel gate electrode in a vertical direction perpendicular to the substrate.

38. The three-dimensional memory device of claim 31, wherein the first insulating strip and the second insulating strip include corresponding cavities therein, wherein each cavity is free of any solid phase material.

39. The three-dimensional memory device of claim 20, wherein the ferroelectric material portion comprises orthorhombic hafnium oxide containing at least one dopant selected from at least one of Al, Zr, or Si.

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