A computing device and a computing method

Abstract

The present disclosure relates to a computing device, wherein the computing device may be included in a combined processing device, and the combined processing device may also include a universal interconnection interface and other processing devices. The computing device interacts with other processing devices to jointly complete a computing operation specified by a user. The combined processing device may also include a storage device, which is connected to the computing device and other processing devices respectively, and is used for data of the computing device and other processing devices. The present disclosure can improve the computing accuracy without sacrificing computing speed under the constraint of fixed bandwidth.

Description

Technical Field

[0001] The present disclosure relates to the field of data processing, and more particularly, to conversion of data types. Background Art

[0002] When traditional CPUs and GPUs perform neural network training or inference, under the condition that the input data type is Float16, in order to improve the accuracy of the neural network, it is necessary to convert the Float16 type data to the Float32 data type for further calculations. After the calculation is completed, the Float32 type result is converted to Float16 type data for storage.

[0003] There are two main ways of implementing the method in the traditional way. The first way is to first read the data of the Float16 data type from the memory in rows, convert the data type of the read data from Float16 to Float32, and then store the Float32 data generated after the conversion back into the memory. Next, the Float32 data is read out for calculation. However, the disadvantage of this method is that the amount of data after the above calculation process is completed is doubled, occupying twice the storage space relative to the Float16 data type. The second way is to first read half a row of Float16 type data, and then generate one row of Float32 type data for calculation.

[0004] Regardless of the above methods, for a row of data that is sent to a 32-bit floating-point operator group to perform calculation operations, the number of elements of the Float32 data type in each row is halved relative to the Float16 data type due to the fixed bandwidth, that is, the calculation efficiency is halved. This increases the number of times data is read from the storage device, and more instructions are required to complete this operation, resulting in long execution time, high power consumption and complex programming. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the defects of the prior art such as large storage space occupation or low conversion efficiency.

[0006] According to a first aspect of the present disclosure, a computing device is provided, comprising: a first conversion unit (T1), configured to convert first data with a first precision m into second data with a second precision n, wherein the second data occupies a space that is n / m times that of the first data and includes n / m parts, wherein n and m are integers, and n is greater than m; an operation unit (C), configured to be connected to the first conversion unit (T1), to operate on the n / m parts of the second data respectively to obtain third data with a second precision n, wherein the third data includes n / m parts; and a second conversion unit (T2), configured to convert the third data with the second precision n into result data with the first precision m.

[0007] According to a second aspect of the present disclosure, a chip is provided, comprising the above-mentioned computing device.

[0008] According to a third aspect of the present disclosure, a board is provided, comprising the computing device as described above or the chip as described above.

[0009] According to a fourth aspect of the present disclosure, there is provided an electronic device, comprising the computing device as described above, or the chip as described above, or the board as described above.

[0010] According to a fifth aspect of the present disclosure, a calculation method is provided, comprising: converting first data with a first precision m into second data with a second precision n, wherein the second data occupies a space that is n / m times that of the first data and includes n / m parts, wherein n and m are integers, and n is greater than m; performing operations on the n / m parts of the second data respectively to obtain third data with a second precision n, the third data including n / m parts; and converting the third data with the second precision n into result data with the first precision m.

[0011] At least one beneficial effect of the technical solution disclosed herein includes that, under the constraint of fixed bandwidth, the calculation accuracy can be improved without sacrificing the calculation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] By reading the detailed description below with reference to the accompanying drawings, the above and other purposes, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0013] Figure 1 A block diagram of a computing device according to one embodiment of the present disclosure is shown;

[0014] Figure 2A schematic diagram showing converting first data into multiple rows of second data according to an embodiment of the present disclosure is shown;

[0015] Figure 3 A schematic block diagram of processing second data according to an embodiment of the present disclosure is shown;

[0016] Figure 4 A schematic block diagram of a computing device according to one embodiment of the present disclosure is shown;

[0017] Figure 5 A schematic block diagram showing a second conversion unit converting third data into result data according to an embodiment of the present disclosure;

[0018] Figure 6 A flow chart showing a calculation method according to one embodiment of the present disclosure is shown;

[0019] Figure 7 is a schematic diagram of a combined processing device; and

[0020] Figure 8 An exemplary board is shown. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0022] It should be understood that the terms "first", "second", "third", "fourth", etc. in the claims, specifications and drawings of the present disclosure are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specifications and claims of the present disclosure indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections.

[0023] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0024] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0025] The specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0026] Figure 1 A block diagram of a computing device according to one embodiment of the present disclosure is shown.

[0027] like Figure 1 As shown, the computing device of the present disclosure may include a first conversion unit T1, configured to convert first data with a first precision m into second data with a second precision n, wherein the second data occupies a space that is n / m times that of the first data and includes n / m parts, such as the zeroth part, ..., the i-th part, ..., the n / m-1th part of the second data, wherein n and m are integers and n is greater than m; an operation unit C, which is configured to be connected to the first conversion unit T1, and to perform operations on the n / m parts of the second data respectively to obtain third data with a second precision n, the third data including n / m parts, such as the zeroth part, ..., the i-th part, ..., the n / m-1th part of the third data; and a second conversion unit T2, configured to convert the third data with the second precision n into result data with the first precision m.

[0028] exist Figure 1 In the example, the data type of the first data may be a Float type, and the precision may be 4, 8, 14, 32, etc. These data may sometimes need to be increased to a higher precision data type for higher precision calculations, such as Float type data of 8, 16, 32, and 64. Low precision data may be converted to high precision data, thereby improving the precision of calculations.

[0029] For example, if first data of Float16 is converted into second data of Float32, the space occupied by the second data is twice that of the first data; and if first data of Float8 is converted into second data of Float64, the space occupied by the second data is eight times that of the first data.

[0030] In the above description, data may include multiple "parts", where the "parts" may be of a preset size or may be divided according to the rules for storing data in the memory. Preferably, each part may represent a row of data in the memory. However, it should be understood that the "parts" described above may also be of any other limited size.

[0031] According to an embodiment of the present disclosure, the first data may be stored in a memory as multiple lines, and the first conversion unit T1 is further configured to read one line of the first data each time, so that each time the read first data is converted into n / m lines of second data.

[0032] Since the space occupied by the second data is multiple times that of the first data, the second data can be stored as multiple parts. For example, if the first data is stored as a row in the memory, then the second data can be stored as multiple rows accordingly. Thus, when a row of first data of Float16 is converted to second data of Float32, it can be stored as 2 rows, and when a row of first data of Float8 is converted to second data of Float64, it can be stored as 8 rows. In other words, the prior art first converts a part of each first data (such as the first half of the row) into the second data, and then converts another part of the first data (such as the second half of the row) into the second data, while the present disclosure converts the first data into second data containing multiple parts at one time or simultaneously, which significantly improves the conversion efficiency.

[0033] The above-mentioned “operating on the n / m parts of the second data respectively” may mean that the operations are performed simultaneously.

[0034] In one embodiment, for example, operations on the second data comprising multiple parts can be performed simultaneously, that is, the technical solution disclosed in the present invention includes multiple parallel operation units, and the multiple operation units convert multiple corresponding parts of the second data in parallel or simultaneously, thereby overcoming the limitation of the prior art of operating on the second data one by one and improving the operation efficiency.

[0035] Figure 2 A schematic diagram of converting first data into multiple rows of second data according to an embodiment of the present disclosure is shown.

[0036] like Figure 2 As shown, each row of the first data may be divided into n / m segments, and the first conversion unit T1 is configured to convert each segment into a row of second data, thereby converting a row of first data into n / m rows of second data.

[0037] exist Figure 2In the example, a row of first data has 16 data 0-15; n=32, m=8, that is, Float8 data is converted into Float32 data, thus, n / m=4. Therefore, each row of first data is divided into 4 segments, and there may be four sub-conversion units, namely T10, T11, T12 and T13, each of which converts the corresponding segment of the first data into the second data of Float32. Specifically, sub-conversion unit T10 is responsible for converting data 0-3, sub-conversion unit T11 is responsible for converting data 4-7, sub-conversion unit T12 is responsible for converting data 8-11, and sub-conversion unit T13 is responsible for converting data 12-15.

[0038] Sub-conversion unit T10 converts data 0-3 into the 0th row of second data, sub-conversion unit T11 converts data 4-7 into the 1st row of second data, sub-conversion unit T12 converts data 8-11 into the 2nd row of second data, and sub-conversion unit T13 converts data 12-15 into the 3rd row of second data.

[0039] It should be understood that the first conversion unit T1 and the sub-conversion units T10-T13 can be implemented by software or by hardware. When implemented by software, the sub-conversion units T10-T13 can be conversion modules that are logically or functionally separated; when implemented by hardware, the sub-conversion units T10-T13 can be physically distinguished converters. Furthermore, the sub-conversion units T10-T13 can be conversion modules or conversion circuits that are implemented as a whole and can convert multiple (for example, 4) data, or each of the sub-conversion units T10-T13 can be split into multiple (for example, four) converters, and each converter converts one data. More specifically, for example, the sub-conversion unit T10 can be split into four converters, and these four converters convert the data types of data 0-3 respectively.

[0040] In combination with the above description, the conversion unit can take various forms, and the present disclosure is not limited to any specific form.

[0041] According to one embodiment of the present disclosure, the operation unit C may include n / m accumulators, configured to perform accumulation operations on n / m rows of second data each time. It should be understood that the operation unit C may be an adder, a subtractor, a multiplier, or any other independent unit or combination unit that operates on data, and the present disclosure does not impose any restrictions on the type of the operator.

[0042] Figure 3 A schematic block diagram of processing second data according to an embodiment of the present disclosure is shown.

[0043] exist Figure 3In the example of the operation unit, an accumulator is used for explanation. Where n=32, m=4, the first data can be converted into 4 parts, and the operation unit C can include 4 accumulators C0, C1, C2 and C3. Figure 3 The number of accumulators shown in FIG. 1 is only an example, and the number can be adjusted according to actual conditions.

[0044] exist Figure 3 middle, Figure 2 The 0th row of the second data shown in is input into the accumulator C0, the 1st row of the second data is input into the accumulator C1, the 2nd row of the second data is input into the accumulator C2, and the 3rd row of the second data is input into the accumulator C3.

[0045] When the first set of second data enters the accumulator, since no other data is originally stored in the accumulator, the first set of second data only enters and is temporarily stored in the accumulator without any operation. When the second set of second data enters the accumulator, it is operated with the first set of second data. After passing through the accumulator, the second data is output as the third data.

[0046] The following is a more detailed explanation using the operator as the accumulator.

[0047] In order to perform continuous accumulation operations, the accumulator further includes a feedback path, wherein the feedback path feeds the output of the accumulator back to the accumulator, so that the accumulator accumulates the third data with current data in the accumulator.

[0048] Figure 4 A schematic block diagram of a computing device according to one embodiment of the present disclosure is shown.

[0049] like Figure 4 As shown, four accumulators C0-C3 are exemplarily shown. The first data is multiple lines of data, and the first conversion unit T1 reads one line of the first data each time and converts the one line of the first data into second data, and the second data includes part 0, part 1, part 2 and part 3. Accumulator C0 receives part 0 of the second data, accumulator C1 receives part 1 of the second data, accumulator C2 receives part 2 of the second data, and accumulator C3 receives part 3 of the second data.

[0050] More specifically, the first conversion unit T1 can, for example, read the first data of the 0th row in the first cycle and convert it into four rows of second data; the accumulators C0-C3 respectively receive the second data of the 0th row, the second data of the 1st row, the second data of the 2nd row, and the second data of the 3rd row. Since there is no data in the accumulators C0-C3 currently, no operation occurs in the accumulators C0-C3, and the output of the accumulators C0-C3 is the same as the input.

[0051] Next, in the second cycle, the first conversion unit T1 can read the first data of the first row and convert it into four rows of second data; the accumulators C0-C3 respectively receive the four newly received second data, and respectively add the outputs of the accumulators C0-C3 as feedback to the four newly received second numbers. Similarly, the accumulator can perform accumulation operations on the first data of all rows and finally output them as the third data, which also includes four parts, namely, part 0, part 1, part 2, and part 3.

[0052] It should be understood that the cycle described above can be one clock cycle, multiple clock cycles, or any self-defined cycle. The above operations can be completed in different time slots of one cycle.

[0053] It should also be understood that the accumulators C0-C3 can be implemented by software or by hardware. Each accumulator can be divided into a corresponding number of sub-accumulators according to the number of data in each row of the second data. For example, when there are 16 data in each row of the second data, each accumulator C0-C3 may include 16 sub-accumulators, each of which corresponds to one data. When implemented in software, the sub-accumulator may be an accumulation module that is logically or functionally separated; when implemented in hardware, the sub-accumulator may be an accumulation circuit that is physically distinguished. Accumulators C0-C3 may also be integral modules that can read a row of second data at one time. The present disclosure does not impose any restrictions on the structure of the accumulator.

[0054] In some cases, all the first data may not necessarily be stored in a whole row, and the amount of first data in some rows may be less than that of first data in other rows, so that a whole row cannot be filled.

[0055] In addition, in some other cases, although the elements in some rows are filled with specific data, this data may not participate in the subsequent specific operation, so the data is invalid data for the operation. The validity or invalidity of the data can be recorded in the data indicator, for example, 0 can represent invalidity and 1 can represent validity.

[0056] It can be seen that some storage spaces of the memory may be empty, that is, the storage space does not store any data content; in addition, although some storage spaces of the memory store specific data content, these data contents do not participate in subsequent operations. Empty elements or elements that do not participate in subsequent operations can be called "invalid data".

[0057] According to an embodiment of the present disclosure, the first conversion unit T1 is configured to, in response to detecting that an element in the first data is invalid data, skip conversion of the invalid data.

[0058] In this embodiment, the first conversion unit T1 can determine whether there is invalid data in each row of the first data, that is, whether there is empty storage space or whether there is data that does not participate in subsequent calculation operations. When these situations exist, the conversion of these data can be directly skipped, thereby saving conversion time and improving conversion efficiency. It should be understood that the first conversion unit T1 can determine whether there is invalid data in each row of the first data by itself, and can also receive information about whether there is invalid data in each row of data from other units.

[0059] According to another embodiment of the present disclosure, the operation unit C may be configured to, in response to detecting that an element in the first data and / or the second data is invalid data, skip the operation on the invalid data.

[0060] In this embodiment, the operation unit C can determine whether there is invalid data in each row of the first data, that is, whether there is an empty storage space or whether there is data that does not participate in subsequent operation operations; or, the operation unit C can determine whether there is invalid data in the second data converted by the first conversion unit T1. When there is invalid data in the first data or the second data, the operation unit C can also directly skip the operation on these data, thereby saving operation time and improving operation efficiency. It should be understood that the operation unit C can determine whether there is invalid data in the first data or the second data by itself, or receive information about whether there is invalid data in the first data or the second data from other units. For example, after the first conversion unit T1 determines whether there is invalid data in the first data, the information can be forwarded to the operation unit C.

[0061] According to yet another embodiment of the present disclosure, the operation unit C may be configured to, in response to detecting that an element in the first data and / or the second data is invalid data, regard the element as zero.

[0062] In this implementation, when the operation unit C determines that certain data or elements in the corresponding first data or second data are invalid data, these data may be directly regarded as zero, or the data may be modified to zero for further operation.

[0063] In addition, if the first conversion unit T1 detects that some data or elements in the first data are invalid data, these invalid data may be directly modified to zero to facilitate further operations of the subsequent operation unit C.

[0064] Further, according to one embodiment of the present disclosure, the second conversion unit T2 is configured to convert n / m rows of third data into one row of result data, that is, after the operation is completed, the output of the operation unit C is n / m rows of data, whose form is the same as the storage form of the second data, but the content of the data is different from the second data, and the second conversion unit T2 restores the n / m rows of third data to result data.

[0065] Figure 5 A schematic block diagram showing a second conversion unit converting third data into result data according to an embodiment of the present disclosure is shown.

[0066] like Figure 5 As shown, the third data is, for example, 4 parts of data, namely, part 0, part 1, part 2 and part 3. The "part" mentioned here can be a row of data in the memory, so it can also be called row 0 to row 3.

[0067] In order to convert these four parts of data, various operations can be performed.

[0068] For example, the second conversion unit T2 can be divided into four sub-conversion units T20-T23, each of which is responsible for converting a row of third data, that is, the 0th row of third data is converted by the sub-conversion unit T20 of the second converter T2, the 1st row of third data is converted by the sub-conversion unit T21 of the second converter T2, the 2nd row of third data is converted by the sub-conversion unit T22 of the second converter T2, and the 3rd row of third data is converted by the sub-conversion unit T23 of the second converter T2. Each sub-conversion unit converts a row of third data into 1 / 4 result data, and then splices these result data together to form the final data.

[0069] Alternatively, the second conversion unit T2 or the sub-conversion units T20-T21 can be divided into a plurality of sub-converters according to the number of data in the third data. For example, if the second data in row 0 has 16 data, the sub-conversion unit T20 can include 16 converters, each of which converts one data, so that the second conversion unit T2 can have 64 converters.

[0070] Similarly, the second conversion unit T2 and the sub-conversion units T20-T23 can be implemented by software or by hardware. When implemented by software, the sub-conversion units T20-T23 can be conversion modules separated logically or functionally; when implemented by hardware, the sub-conversion units T20-T23 can be physically distinguished converters.

[0071] Figure 6 A flow chart of a calculation method according to one embodiment of the present disclosure is shown.

[0072] like Figure 6 As shown, the method of the present disclosure includes: in operation S610, converting first data with first precision m into second data with second precision n, wherein the space occupied by the second data is n / m times that of the first data and includes n / m parts, wherein n and m are integers, and n is greater than m; in operation S620, respectively operating on the n / m parts of the second data to obtain third data with second precision n, wherein the third data includes n / m parts; and in operation S630, converting the third data with second precision n into result data with first precision m.

[0073] By combining Figure 1-Figure 5 The content of the method disclosed in the present invention can be clearly understood through the description, so it will not be repeated here.

[0074] The beneficial effects of the technical solution disclosed in the present invention include that the calculation accuracy can be improved without sacrificing the calculation speed under the constraint of fixed bandwidth. In addition, the technical solution disclosed in the present invention does not lose performance, does not increase the number of operations, and does not increase the amount of memory access to the storage device, thereby having the advantages of high performance, simple programming and low power consumption.

[0075] The present disclosure also provides a combined processing device 700, which includes the above-mentioned computing device 702, a universal interconnection interface 704, and other processing devices 706. The computing device according to the present disclosure interacts with other processing devices to jointly complete the operation specified by the user. Figure 7 A schematic diagram of a combined processing device.

[0076] Other processing devices include one or more types of processors such as central processing unit (CPU), graphics processing unit (GPU), neural network processor, and other general / special processors. There is no limit on the number of processors included in other processing devices. Other processing devices serve as interfaces between the machine learning computing device and external data and control, including data handling, to complete basic control of the machine learning computing device such as starting and stopping; other processing devices can also collaborate with the machine learning computing device to complete computing tasks.

[0077] A universal interconnect interface is used to transmit data and control instructions between a computing device (including, for example, a machine learning computing device) and other processing devices. The computing device obtains the required input data from other processing devices and writes it into the storage device on the computing device chip; it can obtain control instructions from other processing devices and write them into the control cache on the computing device chip; it can also read data in the storage module of the computing device and transmit it to other processing devices.

[0078] Optionally, the structure may further include a storage device 708, which is connected to the computing device and the other processing device respectively. The storage device is used to store data in the computing device and the other processing device, and is particularly suitable for data that cannot be fully stored in the internal storage of the computing device or other processing device.

[0079] The combined processing device can be used as a SOC chip system for mobile phones, robots, drones, video surveillance equipment and other devices, effectively reducing the core area of ​​the control part, improving the processing speed, and reducing the overall power consumption. In this case, the universal interconnection interface of the combined processing device is connected to certain components of the device. Certain components include cameras, displays, mice, keyboards, network cards, and wifi interfaces.

[0080] In some embodiments, the present disclosure further provides a chip, which includes the above-mentioned computing device or combined processing device.

[0081] In some embodiments, the present disclosure also provides a board card, which includes the above-mentioned chip or the above-mentioned computing device.

[0082] In some embodiments, the present disclosure further provides an electronic device, which includes the above-mentioned computing device, or the above-mentioned chip, or the above-mentioned board.

[0083] See also Figure 8 , which provides an exemplary board card, which, in addition to the chip 802, may also include other supporting components, including but not limited to: a storage device 804, an interface device 806 and a control device 808;

[0084] The memory device is connected to the chip in the chip package structure via a bus for storing data. The memory device may include multiple groups of memory cells 810. Each group of memory cells is connected to the chip via a bus. It is understood that each group of memory cells may be DDR SDRAM (English: Double Data Rate SDRAM, double rate synchronous dynamic random access memory).

[0085] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read out on the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In one embodiment, the storage device may include 4 groups of storage units. Each group of storage units may include multiple DDR4 particles (chips). In one embodiment, the chip may include 4 72-bit DDR4 controllers, 64 bits of the above 72-bit DDR4 controllers are used for data transmission, and 8 bits are used for ECC verification. In one embodiment, each group of storage units includes multiple double-rate synchronous dynamic random access memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling DDR is set in the chip to control the data transmission and data storage of each storage unit.

[0086] The interface device is electrically connected to the chip in the chip packaging structure. The interface device is used to realize data transmission between the chip and an external device 812 (such as a server or a computer). For example, in one embodiment, the interface device can be a standard PCIE interface. For example, the data to be processed is transmitted to the chip by the server through the standard PCIE interface to realize data transfer. In another embodiment, the interface device can also be other interfaces. The present disclosure does not limit the specific forms of expression of the above-mentioned other interfaces. The interface unit can realize the switching function. In addition, the calculation results of the chip are still transmitted back to the external device (such as a server) by the interface device.

[0087] The control device is electrically connected to the chip. The control device is used to monitor the state of the chip. Specifically, the chip and the control device can be electrically connected via an SPI interface. The control device may include a single-chip microcomputer (Micro Controller Unit, MCU). For example, the chip may include multiple processing chips, multiple processing cores or multiple processing circuits, which can drive multiple loads. Therefore, the chip can be in different working states such as multi-load and light load. The control device can realize the regulation of the working states of multiple processing chips, multiple processing and / or multiple processing circuits in the chip.

[0088] Electronic devices or apparatuses include data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, vehicles, household appliances, and / or medical equipment.

[0089] The transportation means include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound machines and / or electrocardiographs.

[0090] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present disclosure is not limited by the order of the actions described, because according to the present disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present disclosure.

[0091] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0092] In the several embodiments provided in the present disclosure, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, optical, acoustic, magnetic or other forms.

[0093] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0094] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software program module.

[0095] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product, the computer software product is stored in a memory, including a number of instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0096] The embodiments of the present disclosure are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present disclosure, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

[0097] The following terms can help you better understand the content of this disclosure:

[0098] Clause 1. A computing device comprising:

[0099] a first conversion unit (T1) configured to convert first data having a first precision m into second data having a second precision n, wherein the second data occupies a space n / m times that of the first data and includes n / m parts, wherein n and m are integers and n is greater than m;

[0100] an operation unit (C), the operation unit being configured to be connected to the first conversion unit (T1), and to respectively operate on the n / m parts of the second data to obtain third data with a second precision n, the third data comprising the n / m parts;

[0101] The second conversion unit (T2) is configured to convert the third data having the second precision n into result data having the first precision m.

[0102] Clause 2. A computing device according to Clause 1, wherein the first data is any one of Float data with a precision of 4, 8, 16 and 32, and the second data is any one of Float data with a precision of 8, 16, 32 and 64.

[0103] Item 3. A computing device according to Item 1, wherein the first data is stored as multiple rows in a memory, and the first conversion unit (T1) is further configured to read one row of the first data each time, so that each time a row of the first data is read is converted into n / m rows of second data.

[0104] Item 4. A computing device according to Item 3, wherein each row of the first data is divided into n / m segments, and the first conversion unit (T1) is configured to convert each segment into a row of second data, thereby converting a row of first data into n / m rows of second data.

[0105] Clause 5. The computing device according to Clause 4, wherein the operation unit includes n / m accumulators configured to perform accumulation operations on n / m rows of second data each time.

[0106] Clause 6. The calculator according to clause 5, wherein the accumulator further comprises a feedback path, wherein the feedback path feeds back the output of the accumulator into the accumulator so that the accumulator accumulates the third data with current data in the accumulator.

[0107] Clause 7. A computing device according to any one of clauses 1 to 6, wherein the first conversion unit (T1) is configured to, in response to detecting that an element in the first data is invalid data, skip conversion of the invalid data.

[0108] Clause 8. A computing device according to any one of clauses 1 to 6, wherein the operation unit (C) is configured to, in response to detecting that an element in the first data and / or the second data is invalid data, skip the operation on the invalid data.

[0109] Clause 9. A computing device according to any one of clauses 1 to 6, wherein the operation unit (C) is configured to, in response to detecting that an element in the first data and / or the second data is invalid data, regard the element as zero.

[0110] Clause 10. The computing device according to any one of Clauses 1 to 9, wherein the second conversion unit (T2) is configured to convert n / m rows of third data into one row of result data.

[0111] Clause 11. A chip comprising a computing device as described in any one of clauses 1-10.

[0112] Clause 12. A board comprising a computing device as described in any one of Clauses 1 to 10 or a chip as described in Clause 11.

[0113] Clause 13. An electronic device comprising a computing device as described in any one of Clauses 1 to 10, or a chip as described in Clause 11, or a board as described in Clause 12.

[0114] Clause 14. A method of calculation comprising:

[0115] Converting first data with a first precision m into second data with a second precision n, wherein the second data occupies n / m times the space of the first data and includes n / m parts, wherein n and m are integers, and n is greater than m;

[0116] respectively performing operations on the n / m parts of the second data to obtain third data with a second precision n, the third data including the n / m parts; and

[0117] The third data having the second precision n is converted into result data having the first precision m.

Claims

1. A computing device, comprising: A first conversion unit (T1) configured to convert first data with a first precision m into second data with a second precision n, wherein the second data occupies a space n / m times that of the first data and includes n / m parts, wherein n and m are integers, and n is greater than m, wherein the first data is stored as a plurality of rows in a memory, the first conversion unit (T1) is further configured to read a row of the first data each time, so that each row of the first data read is converted into n / m rows of second data, each row of the first data is divided into n / m segments, the first conversion unit (T1) is configured to convert each segment into a row of second data, so that a row of the first data is converted into n / m rows of second data; an operation unit (C), the operation unit being configured to be connected to the first conversion unit (T1), and to respectively operate on the n / m parts of the second data to obtain third data with a second precision n, the third data comprising the n / m parts; The second conversion unit (T2) is configured to convert the third data with the second precision n into result data with the first precision m, wherein the second conversion unit (T2) is configured to convert n / m rows of the third data into one row of result data.

2. The computing device according to claim 1, wherein: The first data is any one of Float data with a precision of 4, 8, 16, and 32, and the second data is any one of Float data with a precision of 8, 16, 32, and 64.

3. The computing device according to claim 1, wherein: The operation unit includes n / m accumulators, which are configured to perform accumulation operations on n / m rows of second data each time.

4. The computing device according to claim 3, wherein: The accumulator further includes a feedback path, wherein the feedback path feeds back the output of the accumulator into the accumulator, so that the accumulator accumulates the third data with current data in the accumulator.

5. The computing device according to any one of claims 1 to 4, wherein: The first conversion unit (T1) is configured to, in response to detecting that an element in the first data is invalid data, skip conversion of the invalid data.

6. The computing device according to any one of claims 1 to 4, wherein: The operation unit (C) is configured to, in response to detecting that an element in the first data and / or the second data is invalid data, skip the operation on the invalid data.

7. The computing device according to any one of claims 1 to 4, wherein: The operation unit (C) is configured to, in response to detecting that an element in the first data and / or the second data is invalid data, regard the element as zero.

8. A chip comprising the computing device as claimed in any one of claims 1 to 7.

9. A board comprising the computing device according to any one of claims 1 to 7 or the chip according to claim 8.

10. An electronic device comprising the computing device according to any one of claims 1 to 7, or the chip according to claim 8, or the board according to claim 9.

11. A calculation method comprising: Converting first data with a first precision m into second data with a second precision n, wherein the second data occupies a space n / m times that of the first data and includes n / m parts, wherein n and m are integers, and n is greater than m, wherein the first data is stored as a plurality of lines in a memory, and a line of the first data is read each time, so that each line of the first data read is converted into n / m lines of second data, each line of the first data is divided into n / m segments, and each segment is converted into a line of second data, so that a line of the first data is converted into n / m lines of second data; respectively performing operations on the n / m parts of the second data to obtain third data with a second precision n, the third data including the n / m parts; and The third data having the second precision n is converted into result data having the first precision m, wherein n / m rows of the third data are converted into one row of result data.

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