Substrate processing method and substrate processing system

Abstract

The present invention relates to a substrate processing method and a substrate processing system capable of appropriately performing static removal treatment on a substrate after plasma treatment. The substrate processing method is used to process a substrate and includes the following steps: step (a) placing the substrate on an electrostatic chuck and applying a DC voltage to the electrostatic chuck to adsorb the substrate to the electrostatic chuck; step (b) supplying high-frequency power to an electrode and generating plasma using an inert gas; step (c) stopping the application of the DC voltage to the electrostatic chuck; and step (d) gradually reducing the high-frequency power supplied to the electrode to 0W.

Description

Technical Field

[0001] The present disclosure relates to a substrate processing method and a substrate processing system. Background Art

[0002] Patent Document 1 discloses a method for removing a wafer adsorbed on an electrostatic chuck. In the above method, a charge removal voltage V is applied to the chuck electrode while removing residual charge from the wafer adsorbed on the electrostatic chuck using plasma of an inert gas. plasma . V plasma The self-bias potential V of the wafer when plasma is applied dc quite.

[0003] Patent Document 2 discloses a method for detaching a wafer adsorbed to a sample stage. In this method, after the process of detaching the sample from the sample stage begins, the DC voltage applied to the electrode used to electrostatically adsorb the wafer to the sample stage is changed from a predetermined value to approximately 0V after a predetermined time has passed since the supply of high-frequency power for plasma generation was stopped. This predetermined value is a pre-determined value such that the potential of the wafer is approximately 0V when the DC voltage is approximately 0V. This predetermined time is based on the time it takes for charged particles generated by the plasma to disappear or the time it takes for afterglow discharge to disappear.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-47511

[0007] Patent Document 2: Japanese Patent Application Laid-Open No. 2018-22756 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] The technology according to the present disclosure appropriately performs static elimination treatment on a substrate after plasma treatment.

[0010] Solutions for solving problems

[0011] One embodiment of the present disclosure is a method for processing a substrate, comprising the following steps: step (a), placing the substrate on an electrostatic chuck and applying a DC voltage to the electrostatic chuck, thereby adsorbing the substrate to the electrostatic chuck; step (b), supplying high-frequency power to an electrode and generating plasma using an inert gas; step (c), stopping the application of the DC voltage to the electrostatic chuck; and step (d), gradually reducing the high-frequency power supplied to the electrode to 0 W.

[0012] Effects of the Invention

[0013] According to the present disclosure, it is possible to appropriately perform static elimination treatment on a substrate after plasma treatment. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is an explanatory diagram schematically showing the configuration of a plasma processing system according to this embodiment.

[0015] Figure 2 It is an explanatory diagram showing the processing steps of the wafer release process in this embodiment.

[0016] Figure 3 The graph shows temporal changes in the potential of the wafer, the speed of the lift pins, and the high-frequency power supplied to the lower electrode during the wafer detachment process.

[0017] Figure 4 The following shows temporal changes in the potential of the wafer, the speed of the lift pins, and the high-frequency power supplied to the lower electrode during the wafer detachment process, and compares the example with the comparative example.

[0018] Figure 5 The graph shows temporal changes in the potential of the wafer, the speed of the lift pins, and the high-frequency power supplied to the lower electrode during the wafer detachment process, and the comparison is made by varying the high-frequency power reduction time.

[0019] Figure 6 This is a graph showing the change in potential of the wafer when the high-frequency power is reduced from 200 W to 0 W while changing the reduction time.

[0020] Figure 7 It is an explanatory diagram showing the processing steps of the wafer release process in another embodiment.

[0021] Figure 8 It is an explanatory diagram showing the processing steps of the wafer release process in another embodiment.

[0022] Figure 9 It is an explanatory diagram showing the processing steps of the wafer release process in another embodiment.

[0023] Description of Reference Numerals

[0024] 1: plasma processing system; 1a: plasma processing apparatus; 1b: control unit; 20: gas supply unit; 111: lower electrode; 112: electrostatic chuck; W: wafer. DETAILED DESCRIPTION

[0025] In the semiconductor device manufacturing process, a plasma processing apparatus generates plasma by exciting a process gas, and uses this plasma to process a semiconductor wafer (hereinafter referred to as a "wafer"). The plasma processing apparatus is equipped with an electrostatic chuck (ESC) for placing and holding the wafer. Plasma processing is performed while the wafer is held by the electrostatic chuck.

[0026] There are various ways to hold an electrostatic chuck together. For example, applying a DC voltage to the chuck generates a Coulomb force between the chuck and the wafer, which then holds the wafer. In this case, when the wafer is detached from the chuck, residual charge remains on the wafer. As a result, the chuck's holding force on the wafer is maintained, and sometimes, improper detachment can cause the wafer to shift or break. Therefore, various methods have been developed to address residual charge during wafer detachment. For example, there is a method that uses plasma to remove residual charge from the wafer.

[0027] However, even if residual charge on the wafer can be removed to a level that allows for proper wafer detachment, particles may still adhere to the wafer due to the residual charge. Specifically, when a wafer is raised using lift pins while still having residual charge, the position of the residual charge changes, causing a change in the electric field and electrically attracting charged particles around the wafer to the wafer.

[0028] In principle, the charge on the wafer is proportional to the high-frequency power (power) used to generate the plasma. Therefore, reducing the plasma power is a method for removing residual charge from the wafer. However, due to device structure, there are limits to controlling the plasma power, and it is impossible to reduce the residual charge on the wafer to zero.

[0029] Another approach is to increase the processing pressure during static elimination to reduce the self-bias potential of the wafer during plasma application. However, this approach makes it difficult to adequately replace the processing gas when switching from plasma treatment to static elimination. Furthermore, even with increased static elimination pressure, the residual charge on the wafer cannot be reduced to zero.

[0030] Another method is to transfer the charge on the wafer to the process gas while maintaining the supply of the process gas after the charge removal process to reduce the residual charge on the wafer. However, this method significantly reduces the throughput of wafer processing.

[0031] Furthermore, the detachment method disclosed in Patent Document 1 also uses plasma to remove residual charge from the wafer. Specifically, a voltage equivalent to the self-bias potential of the wafer when the plasma is applied is applied to the chuck electrode, reducing the potential difference between the wafer and the chuck electrode to nearly zero, thereby achieving near-zero self-bias-based suction force. However, the self-bias potential of each wafer is not necessarily uniform, so accurate measurement of the self-bias potential is necessary to implement this detachment method. However, this self-bias potential measurement is difficult, and it is not practical to achieve zero residual charge on the wafer.

[0032] Furthermore, the detachment method disclosed in Patent Document 2 takes into account the time it takes for charged particles on the wafer to disappear after the high-frequency power for plasma generation is stopped, and a predetermined time is set to zero the DC voltage applied to the sample stage (electrostatic chuck). However, when the DC voltage applied to the electrostatic chuck is reduced to zero after the high-frequency power is stopped, the potential of the wafer changes significantly, resulting in the generation of a large number of particles.

[0033] Here, when dry etching, a plasma treatment, is performed, residual charge remains in the wiring structure formed on the wafer by this dry etching process. This residual charge can sometimes cause defects such as melting out or corrosion of the wiring metal during subsequent wet processing. Furthermore, wet processing involves, for example, treating a wafer with a chemical solution to remove specific layers or foreign matter. Furthermore, to prevent these defects, it is necessary to employ a method that minimizes the residual charge on the wafer after the dry etching process. However, in the conventional wafer static elimination processes described above, it is impossible to reduce the residual charge on the wafer to zero.

[0034] As described above, regardless of the method used, it is impossible to reduce the residual charge on the wafer to zero when removing it from the electrostatic chuck, leaving particles attached to the wafer. Furthermore, even after the dry etching process is complete, the residual charge on the wafer cannot be reduced to zero, potentially causing defects in the wafer during subsequent wet etching steps. Therefore, conventional methods for removing static electricity from wafers have room for improvement.

[0035] The technology disclosed herein effectively removes a substrate held by an electrostatic chuck by suppressing the adhesion of particles to the substrate during the removal process. This embodiment is described below with reference to the accompanying drawings. Throughout this specification and the accompanying drawings, elements with substantially identical functional structures are denoted by the same reference numerals to omit repeated descriptions.

[0036] Plasma treatment system

[0037] First, a plasma processing system as a substrate processing system according to one embodiment will be described. Figure 1 It is a longitudinal sectional view schematically showing the outline of the structure of the plasma processing system 1 .

[0038] In one embodiment, a plasma processing system 1 includes a plasma processing apparatus 1a and a control unit 1b. The plasma processing apparatus 1a includes a plasma processing chamber 10, a gas supply unit 20, an RF (Radio Frequency) power supply unit 30, and an exhaust system 40. Furthermore, the plasma processing apparatus 1a includes a support unit 11 and an upper electrode showerhead 12. The support unit 11 is disposed in the lower region of a plasma processing space 10s within the plasma processing chamber 10. The upper electrode showerhead 12 is disposed above the support unit 11 and functions as part of the ceiling of the plasma processing chamber 10.

[0039] The support portion 11 is configured to support the wafer W in the plasma processing space 10s. In one embodiment, the support portion 11 includes a lower electrode 111, an electrostatic chuck 112, and an edge ring 113. The electrostatic chuck 112 is disposed on the lower electrode 111 and is configured to support the wafer W via the upper surface of the electrostatic chuck 112. The edge ring 113 is disposed on the upper surface of the peripheral portion of the lower electrode 111 so as to surround the wafer W. Although not shown in the figure, in one embodiment, the support portion 11 may also include lift pins that are configured to pass through the support portion 11 and be freely raised and lowered in contact with the lower surface of the wafer W. Furthermore, although not shown in the figure, in one embodiment, the support portion 11 may also include a temperature adjustment module that is configured to adjust at least one of the electrostatic chuck 112 and the wafer W to a target temperature. The temperature adjustment module may include a heater, a flow path, or a combination thereof. A temperature adjustment fluid such as a refrigerant or a heat transfer gas flows through the flow path.

[0040] The upper electrode shower head 12 is configured to supply one or more processing gases from the gas supply unit 20 to the plasma processing space 10s. In one embodiment, the upper electrode shower head 12 has a gas inlet 12a, a gas diffusion chamber 12b, and a plurality of gas outlets 12c. The gas inlet 12a is fluidically connected to the gas supply unit 20 and the gas diffusion chamber 12b. The plurality of gas outlets 12c are fluidically connected to the gas diffusion chamber 12b and the plasma processing space 10s. In one embodiment, the upper electrode shower head 12 is configured to supply one or more processing gases from the gas inlet 12a to the plasma processing space 10s via the gas diffusion chamber 12b and the plurality of gas outlets 12c.

[0041] The gas supply unit 20 may include one or more gas sources 21 and one or more flow controllers 22. In one embodiment, the gas supply unit 20 is configured to supply one or more process gases from the gas sources 21 corresponding to each process gas to the gas inlet 12a via the flow controllers 22 corresponding to each process gas. Each flow controller 22 may, for example, comprise a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may also include one or more flow modulation devices for modulating or pulsing the flow of one or more process gases.

[0042] The RF power supply unit 30 is configured to supply RF power, such as one or more RF signals, to the lower electrode 111, to the upper electrode showerhead 12, or to one or more electrodes of both the lower electrode 111 and the upper electrode showerhead 12. This generates plasma from one or more process gases supplied to the plasma processing space 10s. Thus, the RF power supply unit 30 can function as at least a portion of a plasma generation unit configured to generate plasma from one or more process gases in the plasma processing chamber. In one embodiment, the RF power supply unit 30 includes two RF generators 31a and 31b and two matching circuits 32a and 32b. In one embodiment, the RF power supply unit 30 is configured to supply a first RF signal, a first high-frequency power HF, from the first RF generator 31a via the first matching circuit 32a to the lower electrode 111. For example, the first RF signal can have a frequency in the range of 27 MHz to 100 MHz.

[0043] In one embodiment, the RF power supply unit 30 is configured to supply a second RF signal, representing a second high-frequency power LF, from a second RF generator 31b via a second matching circuit 32b to the lower electrode 111. For example, the second RF signal has a lower frequency than the first RF signal and may have a frequency within the range of 400 kHz to 13.56 MHz. However, a DC (direct current) pulse generator may be used in place of the second RF generator 31b.

[0044] Although not shown in the figure, other embodiments are contemplated within the present disclosure. For example, in an alternative embodiment, the RF power supply unit 30 may be configured such that a first RF signal is supplied from an RF generator to the lower electrode 111, a second RF signal is supplied from another RF generator to the lower electrode 111, and a third RF signal is supplied from another RF generator to the lower electrode 111. Furthermore, in other alternative embodiments, a DC voltage may be applied to the upper electrode showerhead 12.

[0045] In addition, in various embodiments, the amplitude of one or more RF signals (i.e., the first RF signal, the second RF signal, etc.) may be pulsed or modulated. Amplitude modulation may include pulsing the amplitude of the RF signal between an on state and an off state, or between two or more different on states.

[0046] The exhaust system 40 can be connected to the exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 can include a pressure valve and a vacuum pump. The vacuum pump can include a turbomolecular pump, a pre-pump, or a combination thereof.

[0047] In one embodiment, the control unit 1b processes computer-executable commands for causing the plasma processing apparatus 1a to perform the various processes described herein. The control unit 1b can be configured to control various components of the plasma processing apparatus 1a to perform the various processes described herein. In one embodiment, a portion or all of the control unit 1b can be located within the plasma processing apparatus 1a. The control unit 1b can include, for example, a computer 51. The computer 51 can include, for example, a processing unit (CPU) 511, a storage unit 512, and a communication interface 513. The processing unit 511 can be configured to perform various control operations based on programs stored in the storage unit 512. The storage unit 512 can include RAM (Random Access Memory), ROM (Read Only Memory), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 513 communicates with the plasma processing apparatus 1a via a communication link such as a LAN (Local Area Network).

[0048] Various exemplary embodiments have been described above, but the present invention is not limited to the exemplary embodiments described above, and various additions, omissions, substitutions, and changes can be made. In addition, elements in different embodiments can be combined to form other embodiments.

[0049] Plasma treatment method

[0050] Next, a description will be given of plasma processing performed using the plasma processing system 1 configured as described above. The plasma processing is not particularly limited, and examples thereof include dry etching processing and film formation processing.

[0051] First, wafer W is loaded into plasma processing chamber 10 and placed on electrostatic chuck 112 by raising and lowering lift pins. A DC voltage is then applied to the electrodes of electrostatic chuck 112, causing Coulomb force to electrostatically attract and hold wafer W on electrostatic chuck 112. After wafer W is loaded, the interior of plasma processing chamber 10 is depressurized to a predetermined vacuum level by exhaust system 40.

[0052] Next, the processing gas is supplied from the gas supply unit 20 via the upper electrode showerhead 12 into the plasma processing space 10s. Furthermore, the RF power supply unit 30 supplies a first high-frequency power HF for generating plasma to the lower electrode 111, thereby exciting the processing gas and generating plasma. At this time, the RF power supply unit 30 may also supply a second high-frequency power LF for attracting ions. The generated plasma then causes plasma processing on the wafer W.

[0053] Furthermore, during plasma processing, the temperature of wafer W held on electrostatic chuck 112 is adjusted by a temperature adjustment module. To efficiently transfer heat to wafer W, a heat transfer gas such as He gas or Ar gas is supplied toward the back surface of wafer W held on the upper surface of electrostatic chuck 112.

[0054] When plasma processing is terminated, first, the supply of first high-frequency power HF from RF power supply unit 30 and the supply of processing gas from gas supply unit 20 are stopped. Furthermore, if second high-frequency power LF was supplied during plasma processing, the supply of this second high-frequency power LF is also stopped. Next, the supply of heat transfer gas to the back surface of wafer W is stopped, and the electrostatic chuck 112 ceases to hold wafer W.

[0055] Afterwards, the wafer W is lifted by lift pins and detached from the electrostatic chuck 112. The details of the method for detaching the wafer W will be described later. The wafer W is then unloaded from the plasma processing chamber 10, and the series of plasma processing on the wafer W is completed.

[0056] Wafer detachment method

[0057] Next, use Figure 2 and Figure 3 A method of detaching the wafer W from the electrostatic chuck 112 after the wafer W has been subjected to the plasma processing as described above will be described.

[0058] Figure 2 1 is an explanatory diagram showing the process steps in the separation process of the wafer W. Figure 2 The following parameters are shown as they change with time. "RF" indicates the high frequency power (HF) supplied to the lower electrode 111. "B.He" indicates the pressure of the heat transfer gas (He gas in this embodiment). "ESC HV" indicates the DC voltage applied to the electrostatic chuck 112. "ChamberPress" indicates the internal pressure of the plasma processing chamber 10. "Pin" indicates the timing for raising and lowering the lift pin. In addition, Figure 2In the figure, “Dechuck-Step” indicates the detachment process of the wafer W, and “Pre-Step” indicates the process before detaching the wafer W (including plasma treatment, etc.). Figure 2 The values ​​of electric power, voltage, and pressure are examples and vary depending on the plasma processing process.

[0059] Figure 3 The potential of the wafer W during the release process of the wafer W is shown ( Figure 3 "Wafer V" in the figure), the speed of the lifting pin ( Figure 3 "Pin SPD") in the lower electrode 111) Figure 3 The time variation of "HF" in Figure 3 When the separation process of the wafer W is started ( Figure 2 The "Dechuck-Step" in the figure is set to 0 seconds, and the time-dependent changes of the above parameters after 2 seconds are shown. Figure 3 The potential of the wafer W in Figure 3 "Voltage" in), high-frequency power ( Figure 3 The value of "RF Power" in FIG. 1 is also an example and changes according to the plasma treatment process.

[0060] In the following description, the separation process of the wafer W is divided into steps S1 to S4 .

[0061] (Step S1)

[0062] Step S1 is a step immediately after the plasma treatment is completed. In step S1, the supply of high-frequency power to the lower electrode 111 is stopped, and the high-frequency power becomes 0W. In addition, the supply of heat transfer gas to the back side of the wafer W is stopped, and the pressure of the heat transfer gas becomes 0Torr. In addition, Ar gas is supplied from the gas supply unit 20 at a flow rate of 600sccm, for example, and the pressure in the plasma processing chamber 10 rises from 50mTorr to 100mTorr~250mTorr, and in this embodiment, rises to 100mTorr. Increasing the pressure in the plasma processing chamber 10 in this way is to reduce the self-bias potential of the wafer W to make it easier for the wafer W to detach. In addition, in step S1, a DC voltage is continuously applied to the electrostatic chuck 112 to adsorb and hold the wafer W on the electrostatic chuck 112.

[0063] (Step S2)

[0064] In step S2, high-frequency power (HF) is supplied to the lower electrode 111, and plasma is generated using an inert gas. Specifically, an inert gas containing only Ar gas is supplied from the gas supply unit 20 to the plasma processing space 10s via the upper electrode shower head 12. In addition, high-frequency power is supplied by the RF power supply unit 30 to excite the inert gas to generate plasma. When the high-frequency power changes rapidly, the plasma may become unstable due to the untimely follow-up of the matching circuit 32a. In order to prevent this, the high-frequency power is gradually increased from 0W to, for example, 100W to 400W, or 200W in this embodiment. In addition, the reason why the high-frequency power is 100W to 400W will be described later.

[0065] Furthermore, in step S2, the application of the DC voltage to the electrostatic chuck 112 is stopped. This DC voltage is stopped after a predetermined time has passed since the high-frequency power reaches 200 W and plasma is generated. This predetermined time is the time required for the high-frequency power to fully stabilize, and is, for example, 2 seconds. The plasma generated after the DC voltage is stopped is then used to remove any residual charge from the wafer.

[0066] (Step S3)

[0067] In step S3, the high-frequency power supplied to the lower electrode 111 is gradually reduced and the high-frequency power is reduced to 0 W. The timing for starting to reduce the high-frequency power is the timing after a predetermined time (hereinafter referred to as "delay time") has passed since the application of the DC voltage to the electrostatic chuck 112 was stopped. The delay time is set to suppress the influence of changes in the electric field around the wafer W by stopping the application of the DC voltage to the electrostatic chuck 112 while the plasma is stably generated. The delay time is, for example, 1 second. Moreover, the high-frequency power is reduced at a fixed speed, that is, linearly reduced. In addition, the time for reducing the high-frequency power is, for example, 0.5 seconds to 4 seconds. In addition, the basis for the reduction time being 0.5 seconds to 4 seconds will be described later.

[0068] Here, the inventors of the present invention have conducted intensive research and found that when the high-frequency power supplied to the lower electrode 111 is instantly reduced from 200W to 0W, charges generated by the self-bias potential will remain on the wafer W, and the potential of the wafer W cannot be completely reduced to zero. The self-bias potential of the wafer W is proportional to the high-frequency power when the plasma is generated. Therefore, the inventors of the present invention have come up with the idea that by gradually reducing the high-frequency power supplied to the lower electrode 111, the residual charge on the wafer W can be reduced. Moreover, as Figure 3 As shown, it can be seen that by gradually reducing the high-frequency power in step S3 , the residual charge on the wafer W can be reduced to approximately zero, and the potential of the wafer W can be reduced to approximately zero.

[0069] (Step S4)

[0070] In step S4, the wafer W is lifted by the lift pins, and the wafer W is separated and released from the electrostatic chuck 112. Figure 3 The lift pin speed has three peaks, P1 to P3. The first peak, P1, is the lift pin speed before the lift pins come into contact with the lower surface of the wafer W. The lift pin speed is increased to improve productivity. The second peak, P2, is the lift pin speed when the wafer W is detached from the electrostatic chuck 112 and raised immediately after the lift pins come into contact with the lower surface of the wafer W. The third peak, P3, is the lift pin speed when the wafer W is raised to the unloading position after being detached from the electrostatic chuck 112. At this time, there is no suction force between the electrostatic chuck 112 and the wafer W, and the lift pin speed is increased to improve productivity.

[0071] Here, if charge remains on wafer W during the second peak P2, the electrostatic capacitance between the upper surface of electrostatic chuck 112 and wafer W decreases when wafer W is detached from electrostatic chuck 112, causing fluctuations in the potential of wafer W. In this regard, in the present embodiment, the residual charge on wafer W is reduced to approximately zero by gradually decreasing the high-frequency power in step S3, thereby reducing the potential fluctuation of wafer W to approximately zero.

[0072] According to the above embodiment, since the high-frequency power supplied to lower electrode 111 is gradually reduced in step S3, the residual charge on wafer W can be reduced to approximately zero when wafer W is detached from electrostatic chuck 112, thereby reducing the potential of wafer W to approximately zero. In other words, wafer W can be appropriately de-electrified after plasma treatment. Consequently, the adhesion of particles to wafer W can be suppressed. Furthermore, the particles are composed of, for example, Si, O, C, Al, etc., and have a diameter of, for example, 20 nm to 100 nm.

[0073] Furthermore, since the potential of wafer W can be reduced to approximately zero in this manner, the Coulomb force acting between electrostatic chuck 112 and wafer W can be reduced, allowing smooth lifting of wafer W using the lift pins. Furthermore, this prevents damage to wafer W when it is removed from electrostatic chuck 112. Furthermore, it prevents the center position of wafer W from shifting.

[0074] <Effects of this embodiment>

[0075] According to the above embodiment, the potential of the wafer W can be made substantially zero as described above. The effect will be described below.

[0076] exist Figure 41 shows temporal changes in the potential of the wafer W, the speed of the lift pins, and the high-frequency power supplied to the lower electrode 111 during the detachment process of the wafer W, and compares an example of this embodiment (hereinafter referred to as “Example”) with a comparative example. Figure 4 (a) is Comparative Example 1, which shows an example in which the pressure in the plasma processing chamber 10 is 100 mTorr and the high-frequency power supplied to the lower electrode 111 is instantly reduced from 200 W to 0 W. Figure 4 (b) is Comparative Example 2, which shows an example in which the pressure in plasma processing chamber 10 is 250 mTorr and the high-frequency power supplied to lower electrode 111 is instantly reduced from 100 W to 0 W. Figure 4 (c) is Example 1, showing an example in which the pressure in the plasma processing chamber 10 is 100 mTorr and the high-frequency power supplied to the lower electrode 111 is gradually reduced from 200 W to 0 W over 2 seconds.

[0077] As described above, if there is charge remaining on the wafer W at the second peak P2 of the lift pin velocity, the potential of the wafer W will fluctuate when the wafer W is detached from the electrostatic chuck 112. Therefore, the potential fluctuation of the wafer W in Example 1 is compared with the potential fluctuation of the wafer W in Comparative Examples 1 and 2. Figure 4 In (a), the potential change of the wafer W is represented as “ΔV”.

[0078] exist Figure 4 In the comparative example 1 shown in (a), the potential change ΔV of the wafer W is -470V. Figure 4 In Comparative Example 2 shown in (b), the potential variation ΔV of the wafer W is −95 V. This result indicates that in Comparative Examples 1 and 2, electric charge remains on the wafer W when the wafer W is detached.

[0079] On the other hand, Figure 4 In Example 1 shown in (c), the potential variation ΔV of the wafer W is -10 V. This -10 V is within the error range and is substantially zero. Therefore, in Example 1, the residual charge when the wafer W is detached is substantially zero, and the adhesion of particles to the wafer W can be suppressed.

[0080] In addition, for multiple wafers W, Figure 4 Comparative Example 1 shown in (a) and Figure 4 (c) shows Example 1. Furthermore, the number of particles adhering to multiple wafers W was measured and the average number of particles per wafer W was calculated. The average number of particles in Comparative Example 1 was 8.5, while the average number of particles in Example 1 was 3.5. Therefore, it can be seen that the present embodiment can effectively suppress the adhesion of particles to wafers W.

[0081] <Conditions of Step S3>

[0082] Next, as described above, when the high-frequency power supplied to the lower electrode 111 is gradually reduced in step S3 , the reduction time and the preferred range of the high-frequency power (electric power) when the reduction is started will be described.

[0083] exist Figure 5 3 shows temporal changes in the potential of the wafer W, the speed of the lift pins, and the high-frequency power supplied to the lower electrode 111 during the detachment process of the wafer W, and the comparison is made by varying the lowering time. Figure 5 (a) is the same as Figure 4 (a) is similar to Comparative Example 1, but shows an example in which the reduction time is 0 seconds, that is, the high-frequency power is reduced instantaneously. Figure 5 (b) is the same as Figure 4 (c) Same as Example 1, but with a reduction time of 2 seconds. Figure 5 (c) is Example 2, and the reduction time is 4 seconds. Figure 5 In (a) to (c), the high-frequency power is reduced from 200W to 0W.

[0084] exist Figure 5 In Comparative Example 1 shown in (a), the potential variation ΔV of the wafer W is −470 V. Therefore, in Comparative Example 1, when the wafer W is detached, electric charge remains on the wafer W.

[0085] On the other hand, Figure 5 In the embodiment shown in (b), the potential change ΔV of the wafer W is -10V. Figure 5 In Example 2 shown in (c), the potential change ΔV of wafer W is 23 V. These -10 V and 23 V are within the error range and are essentially zero. Therefore, in Examples 1 and 2, the residual charge when wafer W is released is substantially zero, which can suppress the adhesion of particles to wafer W.

[0086] Figure 6 : is a graph showing the potential variation ΔV of the wafer W when the reduction time is changed when the high frequency power is reduced from 200W to 0W. Figure 6 In FIG. 1 , the horizontal axis represents the decrease time, and the vertical axis represents the potential change ΔV of the wafer W.

[0087] Reference Figure 6It can be seen that when the high-frequency power reduction time is 0.5 to 4 seconds, the absolute value of the potential change ΔV on the wafer W is less than 65V, essentially zero. In other words, the preferred range of the reduction time is 0.5 to 4 seconds. Furthermore, if the reduction time is too short, it means that the wafer W cannot be completely de-charged, and this is the basis for determining the lower limit of the reduction time. On the other hand, if the reduction time is too long, it means that the plasma for de-charge cannot be maintained, and the wafer W cannot be completely de-charged, and this is the basis for determining the upper limit of the reduction time.

[0088] Here, the high-frequency power is proportional to the self-bias potential of the wafer W. When the high-frequency power is large, the self-bias potential of the wafer W also increases. Therefore, it is preferable to keep the high-frequency power as low as possible. After careful research, the inventors of the present invention found that the upper limit of the high-frequency power is 400W. In addition, in reality, there is a limit to the reduction of the high-frequency power from the perspective of plasma stability. After careful research, the inventors of the present invention found that the lower limit of the high-frequency power is 100W. Therefore, the preferred range of the high-frequency power (power) when starting to reduce is 100W to 400W.

[0089] <Other embodiments>

[0090] In the above embodiments, Figure 2 As shown, after the delay time has elapsed since the application of the DC voltage to the electrostatic chuck 112 was stopped in step S2, the high frequency power supplied to the lower electrode 111 is reduced in step S3. Figure 7 As shown, the delay time may be zero. However, it is preferable to provide a delay time so that the high frequency power can be reduced after the change in the electric field around the wafer W caused by the application of the DC voltage to the electrostatic chuck 112 is reliably reduced.

[0091] In addition, in the above embodiments, Figure 2 As shown in FIG. 1 , the DC voltage applied to the electrostatic chuck 112 is stopped instantaneously in step S2. However, the DC voltage applied to the electrostatic chuck 112 may be stopped instantaneously as shown in FIG. Figure 8 As shown, the applied DC voltage is gradually reduced and stopped. In this case, the change in the electric field around the wafer W can be suppressed to a minimum, and the particles electrically attracted to the wafer W can be reduced.

[0092] The plasma processing apparatus 1a of the above embodiment supplies the first high frequency power HF to the lower electrode 111, but may also supply the first high frequency power HF to the upper electrode shower head 12. In the above case, the second high frequency power LF may also be supplied to the lower electrode 111.

[0093] Even when the first high-frequency power HF is supplied to the upper electrode shower head 12, the self-bias potential of the wafer during plasma application is not zero. Therefore, as in the above-described embodiment, in step S3, by gradually reducing the high-frequency power supplied to the lower electrode 111, the potential of the wafer W can be reduced to approximately zero.

[0094] However, when the first high-frequency power HF is supplied to the lower electrode 111 , the self-bias potential of the wafer is higher when plasma is applied. Therefore, the above-mentioned effect of making the potential of the wafer W substantially zero is further enhanced.

[0095] In the above embodiment, high-frequency power HF is supplied to lower electrode 111 when wafer W is detached from electrostatic chuck 112. However, low-frequency power LF may be supplied. In this case, the same effect as in the above embodiment can be achieved, namely, the potential of wafer W can be reduced to substantially zero. However, the high-frequency power supplied when wafer W is detached from electrostatic chuck 112 is either high-frequency power HF or high-frequency power LF.

[0096] <Other embodiments>

[0097] In the above embodiment, the charge of the wafer W is removed by utilizing the plasma generated in step S2, and the high-frequency power supplied to the lower electrode 111 is gradually reduced in step S3, thereby reducing the residual charge caused by the self-bias potential of the wafer W. As a result, the potential of the wafer W can be made substantially zero. However, depending on the surface state of the electrostatic chuck 112, sometimes, even if the application of the DC voltage to the electrostatic chuck 112 is stopped, charge remains on the surface of the electrostatic chuck 112. For example, there can be cited a case where deposits are attached to the surface of the electrostatic chuck 112, or a case where the surface of the electrostatic chuck 112 is deteriorated due to repeated plasma treatment. In the above case, charge sometimes remains on the wafer W due to the influence of the charge remaining on the surface of the electrostatic chuck 112.

[0098] Therefore, in this embodiment, wafer W is separated and detached from electrostatic chuck 112 before the plasma generated in step S2 is extinguished. Thereafter, the high-frequency power supplied to lower electrode 111 is gradually reduced to extinguish the plasma. The inventors of the present invention have discovered that, in this manner, the charge on wafer W can be removed without being affected by the surface condition of electrostatic chuck 112. Furthermore, the residual charge caused by the self-bias potential of wafer W, which is generated when the plasma is generated in step S2, can be reduced. As a result, the potential of wafer W can be more reliably brought to approximately zero.

[0099] Next, use Figure 9A method of detaching the wafer W from the electrostatic chuck 112 in this embodiment will be described. Figure 9 1 and 2 are explanatory diagrams showing the process steps in the wafer W release process. Figure 9 Compared with the above embodiment Figure 2 Correspondingly, the terms in the figure also correspond.

[0100] In the following description, similarly to the above-described embodiment, the separation process of the wafer W is divided into steps T1 to T4 .

[0101] (Step T1)

[0102] Step T1 is a step immediately after the plasma treatment is completed. In step T1, the same process as step S1 of the above embodiment is performed.

[0103] (Step T2)

[0104] In step T2, high-frequency power (LF) is supplied to the lower electrode 111, and plasma is generated using the inert gas. In step T1, the same process as step S2 of the above embodiment is performed, except that the second high-frequency power LF is used as the high-frequency power instead of the first high-frequency power HF in step S2 of the above embodiment.

[0105] (Step T3)

[0106] In step T3 , while the high frequency power supplied to lower electrode 111 in step T2 is maintained, that is, while plasma generation is maintained, wafer W is lifted by lift pins to separate and detach from electrostatic chuck 112 .

[0107] (Step T4)

[0108] In step T4, the high-frequency power supplied to the lower electrode 111 is gradually reduced to 0 W, thereby extinguishing the plasma. As in the aforementioned embodiment, when the high-frequency power supplied to the lower electrode 111 is instantaneously reduced from 200 W to 0 W, charge generated by the self-bias potential remains on the wafer W, making it impossible to completely reduce the potential of the wafer W to zero. Therefore, by gradually reducing the high-frequency power supplied to the lower electrode 111, the residual charge on the wafer W is reduced. Furthermore, by gradually reducing the high-frequency power in step T4, the residual charge on the wafer W can be reduced to approximately zero, thereby reducing the potential of the wafer W to approximately zero. Furthermore, at this time, the residual charge on the wafer W can be reduced to approximately zero without being affected by the surface condition of the electrostatic chuck 112.

[0109] According to the above embodiment, after wafer W is separated from electrostatic chuck 112 and detached in step T3, the high-frequency power supplied to lower electrode 111 is gradually reduced in step T4. This allows the residual charge on wafer W to be reduced to approximately zero, thereby reducing the potential of wafer W to approximately zero. In other words, wafer W can be appropriately de-electrified after plasma treatment.

[0110] As described above, when dry etching, which is a plasma process, is performed, if charge remains in the wiring structure on the wafer W, defects such as melting out of the wiring metal or corrosion may occur during subsequent wet processing due to the residual charge. According to this embodiment, the potential of the wafer W after plasma processing can be reduced to approximately zero, thereby suppressing such defects.

[0111] The embodiments disclosed herein are to be considered in all respects as illustrative and non-restrictive, and may be omitted, replaced, or modified in various ways without departing from the scope of the appended claims and the spirit thereof.

Claims

1. A substrate processing method for processing a substrate, comprising the following steps: Step (a) of placing the substrate on an electrostatic chuck and applying a DC voltage to the electrostatic chuck to adsorb the substrate onto the electrostatic chuck; Step (b) of supplying high-frequency power to the electrodes and generating plasma using an inert gas; Step (c), stopping applying the DC voltage to the electrostatic chuck; Step (d) of gradually reducing the high-frequency power supplied to the electrode to 0 W, The method further includes a step (e) between the step (c) and the step (d), wherein the substrate is lifted to separate from the electrostatic chuck.

2. The substrate processing method according to claim 1, wherein: The following steps are further included between the steps (a) and (b): (f) supplying a first high-frequency power to the electrode to perform plasma processing on the substrate; and Step (g): stopping the supply of the first high-frequency power.

3. The substrate processing method according to claim 2, wherein: In the step (f), the first high-frequency power and a second high-frequency power having a frequency different from that of the first high-frequency power are supplied to the electrode.

4. The substrate processing method according to claim 3, wherein: The frequency of the first high-frequency power is higher than the frequency of the second high-frequency power.

5. The substrate processing method according to any one of claims 1 to 3, wherein: The following steps are further included between the steps (a) and (b): Step (h), supplying a heat transfer gas to the back side of the substrate; and In step (i), the supply of the heat transfer gas is stopped.

6. The substrate processing method according to any one of claims 1 to 3, wherein: In the step (d), the high-frequency power is gradually reduced over 0.5 to 4 seconds.

7. The substrate processing method according to any one of claims 1 to 3, wherein: In the step (d), the high-frequency power is reduced at a constant speed.

8. The substrate processing method according to any one of claims 1 to 3, wherein: In the step (c), the DC voltage is gradually reduced.

9. The substrate processing method according to any one of claims 1 to 3, wherein: In the step (b), the high-frequency power is gradually increased.

10. The substrate processing method according to any one of claims 1 to 3, wherein: In the step (b), the inert gas contains only argon gas.

11. The substrate processing method according to any one of claims 1 to 3, wherein: In the step (b), the high-frequency power is 100W to 400W.

12. The substrate processing method according to any one of claims 1 to 3, wherein: The electrode is a lower electrode disposed below the electrostatic chuck.

13. The substrate processing method according to any one of claims 1 to 3, wherein: The electrode is an upper electrode disposed on an upper portion of the electrostatic chuck.

14. A substrate processing system for processing a substrate, the substrate processing system comprising: An electrostatic chuck that absorbs and holds the substrate; electrode; a high-frequency power supply unit for supplying high-frequency power to the electrodes; a gas supply unit that supplies an inert gas; and a control unit that controls the electrostatic chuck, the high-frequency power supply unit, and the gas supply unit, The control unit controls the electrostatic chuck, the high-frequency power supply unit, and the gas supply unit so that the following steps are performed: Step (a) of placing the substrate on the electrostatic chuck and applying a DC voltage to the electrostatic chuck to adsorb the substrate onto the electrostatic chuck; (b) supplying the high-frequency power to the electrode and generating plasma using an inert gas; Step (c), stopping applying the DC voltage to the electrostatic chuck; and Step (d) of gradually reducing the high-frequency power supplied to the electrode to 0 W, The method further includes a step (e) between the step (c) and the step (d), wherein the substrate is lifted to separate from the electrostatic chuck.

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