Semiconductor Structure, Self-Annealing Chip and Method for Fabricating Semiconductor Structure

Abstract

The present invention discloses a semiconductor structure, a self-annealing chip and a manufacturing method of the semiconductor structure. The semiconductor structure includes an N-type MOSFET and a heating element connected in series between an excitation signal input terminal and a reference ground. The gate of the N-type MOSFET receives a bias voltage. When the N-type MOSFET is irradiated externally, its threshold voltage decreases and conducts when the decrease is less than or equal to the bias voltage, thereby controlling the heating element to generate heat. During the heating process, self-annealing recovers and turns off when the recovery is greater than the bias voltage, thereby controlling the heating element to stop generating heat. The heating element is located in a dielectric layer on the upper layer of the N-type MOSFET and is connected to the source electrode of the N-type MOSFET via a wiring layer. In this semiconductor structure, the settable area of the heating element is not restricted and the layout is flexible. At the same time, the semiconductor structure can automatically start / stop the thermal annealing processing function according to the drift of the threshold voltage of the N-type MOSFET, effectively ensuring the real-time performance and accuracy of the thermal annealing processing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor structure, a self-annealing chip and a manufacturing method of the semiconductor structure. Background Art

[0002] For devices that work in an external radiation environment for a long time, the semiconductor devices therein will have problems such as threshold voltage drift, transconductance reduction, subthreshold current increase, low-frequency noise increase, etc. under the action of continuous ionizing radiation, and may even cause device failure. This is the total dose irradiation effect. The total dose irradiation effect is mainly caused by the charges and defects generated by ionizing radiation in the oxide layer and at the oxide layer or silicon interface.

[0003] Existing research shows that when heat treatment, i.e., annealing treatment, is performed on a radiation-damaged semiconductor device, the trapped holes in the device oxide layer will be excited to the valence band of the oxide layer and recombine with the electrons at the Si / SiO2 interface or the silicon substrate, so that the trapped charges in the device oxide layer are continuously reduced, and finally the threshold voltage of the device can be restored to the normal value. Therefore, currently, the general method is to heat-anneal the semiconductor device or chip to be protected to reduce the impact of the total dose radiation effect on the device.

[0004] One existing method for heating and annealing a semiconductor device or chip is to use multiple discrete devices to build a heating system, and integrate the circuit such as the structure to be protected corresponding to the semiconductor device or chip to be protected and the heating system through a PCB board to perform heating and annealing work at the board level. However, the integration degree of this solution is low, and since the heating system needs to be evenly distributed on the PCB board, a large area is occupied; at the same time, when applying this method, the heating system needs to be adaptively arranged according to different structures to be protected, resulting in low versatility.

[0005] Another existing method for heating and annealing a semiconductor device or chip is to integrate a heater or heating wire into the active region of the structure to be protected when manufacturing the structure to be protected, and when the structure to be protected works subsequently, heat-anneal the structure to be protected by applying an external current or voltage to the heater or heating wire through a reserved contact hole. The integration degree of this solution is relatively high, but it mainly performs annealing treatment by applying an external control source, and its annealing effect depends relatively on the external control program. When the external radiation environment changes irregularly, the real-time performance, accuracy and reliability of the annealing treatment cannot be guaranteed. When a total dose irradiation effect is missed in one treatment, it is easy to cause the collapse of the entire system. At the same time, the available layout area of the heater or heating element integrated in the semiconductor substrate is limited, and the versatility is poor.

[0006] Therefore, it is necessary to provide an improved technical solution to overcome the above technical problems existing in the prior art. SUMMARY OF THE INVENTION

[0007] To solve the above technical problems, the present invention provides a semiconductor structure, a self-annealing chip and a manufacturing method of the semiconductor structure. In this semiconductor structure, the settable area of the heating element is not restricted, and the layout is flexible. At the same time, the semiconductor structure can automatically start / stop the thermal annealing treatment function according to the drift of the threshold voltage of the N-type MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), effectively ensuring the real-time performance and accuracy of the thermal annealing treatment, with high integration, small size and simple structure.

[0008] According to the first aspect of the present disclosure, a self-annealing chip is provided, including an N-type MOSFET and a heating element connected in series between the excitation signal input terminal and the reference ground.

[0009] Wherein, the gate of the N-type MOSFET is used to receive a bias voltage. When the N-type MOSFET is irradiated externally, its threshold voltage decreases and conducts when it decreases to be less than or equal to the bias voltage, thereby controlling the heating element to generate heat. During the heating process, self-annealing is restored and it turns off when the threshold voltage returns to be greater than the bias voltage, thereby controlling the heating element to stop generating heat.

[0010] The above-mentioned heating element is located in the dielectric layer on the upper layer of the N-type MOSFET and is connected to the source electrode of the N-type MOSFET via a wiring layer.

[0011] Optionally, the semiconductor structure includes a substrate, a dielectric layer and a wiring layer. The substrate includes a field region and an active region, and the heating element is located on the field region and surrounds the active region.

[0012] Optionally, the electrical connection between the heating element and the wiring layer is realized via a plurality of first contact holes, and the electrical connection between the source electrode of the N-type MOSFET and the wiring layer is realized via a plurality of second contact holes.

[0013] Optionally, the heating element is arranged in a continuous bent shape.

[0014] Optionally, the heating element is made of polysilicon material, the N-type MOSFET has a polysilicon gate, and the heating element is fabricated synchronously with the polysilicon gate of the N-type MOSFET.

[0015] According to the second aspect of the present disclosure, a self-annealing chip is provided, including: a structure to be protected and the semiconductor structure described in the first aspect above, and the semiconductor structure can perform thermal annealing treatment on the structure to be protected.

[0016] Optionally, the threshold voltage of the N-type MOSFET in the semiconductor structure is less than the threshold voltage of the structure to be protected.

[0017] Optionally, the semiconductor structure and the structure to be protected are located within the same packaging structure, or the semiconductor structure and the structure to be protected are located within the same semiconductor device.

[0018] According to a third aspect of the present disclosure, there is provided a method for fabricating a semiconductor structure, including:

[0019] Simultaneously forming a gate of an N-type MOSFET on the active region of the substrate and a heating element on the field region of the substrate;

[0020] Forming a source and a drain of the N-type MOSFET within the active region;

[0021] Forming an electrical connection channel between one end of the source and the heating element, and forming external electrodes corresponding to the gate, the drain, and the other end of the heating element respectively.

[0022] Optionally, simultaneously forming a gate of an N-type MOSFET on the active region of the substrate and a heating element on the field region of the substrate includes:

[0023] Forming a field oxide layer on the substrate to define the active region and the field region;

[0024] Successively forming an oxide layer and a polysilicon layer covering the substrate;

[0025] Etching the polysilicon layer to form a gate of the N-type MOSFET on the active region and a heating element on the field region.

[0026] Optionally, after defining the active region and the field region, it further includes:

[0027] Performing P-type ion implantation in the region of the active region corresponding to the gate of the N-type MOSFET to adjust the threshold voltage of the N-type MOSFET.

[0028] Optionally, the semiconductor structure is used for performing thermal annealing treatment on the structure to be protected, and the threshold voltage of the N-type MOSFET in the semiconductor structure is less than the threshold voltage of the structure to be protected.

[0029] Optionally, the heating element is disposed surrounding the active region, preferably, the heating element surrounds the active region for at least one week.

[0030] Optionally, the heating element is arranged in a continuous curved pattern.

[0031] The beneficial effects of the present invention are:

[0032] 1. The semiconductor structure disclosed by the present invention includes an N-type MOSFET and a heating element connected in series between the excitation signal input terminal and the reference ground in sequence. Based on the different changes in the threshold voltage of the N-type MOSFET under the action of external radiation and thermal annealing treatment, the semiconductor structure can realize the automatic switching control of the N-type MOSFET for the heating or stopping of the heating element, and further realize the automatic start or shutdown of the self-annealing function without setting an additional control source and a manually set control program. Therefore, it can effectively ensure the real-time performance and accuracy of the thermal annealing treatment for the structure to be protected. At the same time, the heating element in the semiconductor structure is located in the dielectric layer on the upper layer of the N-type MOSFET and is connected to the source electrode of the N-type MOSFET via the wiring layer, so that the settable area of the heating element is not limited by the size of the active region of the N-type MOSFET, and the flexible layout of the heating element in the semiconductor structure can be realized, enhancing the versatility of the semiconductor structure.

[0033] 2. The self-annealing chip based on the semiconductor structure disclosed by the present invention can easily realize the co-packaging of the structure to be protected and the semiconductor structure therein, and even co-fabrication. In this way, not only does it not require a large area on the PCB board like the board-level heating annealing system, but also the structure to be protected with the self-annealing function will not be restricted by the layout and wiring of the circuit on the PCB board when applied to different circuits. Therefore, the self-annealing chip has higher versatility.

[0034] 3. When manufacturing the semiconductor structure disclosed by the present invention, it can be improved based on the existing manufacturing process of the N-type MOSFET without adding complex process steps. In addition, the manufacturing process of the semiconductor structure can be well compatible with the existing CMOS process. Therefore, it can greatly reduce the design and manufacturing difficulty and lower the production cost. At the same time, it can also reduce the probability of failure of the self-annealing system composed of the self-annealing chip and the structure to be protected, improving the reliability of the thermal annealing treatment for the structure to be protected. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer.

[0036] Figure 1 FIG. shows a schematic structural diagram of a self-annealing chip provided according to an embodiment of the present disclosure;

[0037] Figure 2 FIG. shows a schematic layout diagram of a semiconductor structure provided according to an embodiment of the present disclosure;

[0038] Figure 3 FIG. shows a layout diagram of a semiconductor structure provided according to another embodiment of the present disclosure;

[0039] Figures 4a - 4l Show Figure 2 A cross-sectional view during the manufacturing process of the semiconductor structure in Detailed implementation mode

[0040] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0041] Below, the technical solution of the present invention will be described in detail with reference to the drawings.

[0042] As Figure 1 shown, in the present disclosure, the self-annealing chip includes a semiconductor structure 100 and a structure 200 to be protected, and the semiconductor structure 100 can perform thermal annealing treatment on the structure 200 to be protected. Among them, the semiconductor structure 100 and the structure 200 to be protected can be located in the same packaging structure, or can be fabricated based on the same semiconductor substrate, that is, the semiconductor structure 100 and the structure 200 to be protected can be separately fabricated and then packaged together, or even the semiconductor structure 100 and the structure 200 to be protected can be fabricated together based on the same semiconductor substrate (wherein, for the sake of understanding, Figure 1 in, the relationship between the semiconductor structure 100 and the structure 200 to be protected is indicated by a dotted line connection). In this way, the integration method between the structure 200 to be protected and the semiconductor structure 100 does not have to be limited to PCB board integration. Therefore, compared with the existing board-level heating annealing system, on the one hand, the size of the chip can be reduced to achieve miniaturization of the chip, and on the other hand, it is not restricted by the layout and wiring of the circuit on the PCB board, improving the versatility.

[0043] Refer to Figure 2 and Figure 3 and in combination with Figure 1 , the semiconductor structure 100 specifically includes an N-type MOSFET Q1 and a heating element 110 connected in series between the excitation signal input terminal and the reference ground in sequence. Among them, the drain 140 of the N-type MOSFET Q1 is used to receive excitation signals such as voltage and current, the gate 130 of the N-type MOSFET Q1 is used to receive the bias voltage V TH(REF) , the source 120 of the N-type MOSFET Q1 is electrically connected to one end of the heating element 110, and the other end of the heating element 110 is electrically connected to the reference ground. Optionally, when the drain 140 of the N-type MOSFET Q1 receives a voltage as the excitation signal, the voltage can be the power supply voltage VDD or the voltage of a circuit node with a high potential in the system, and can be reasonably selected according to the actual situation.

[0044] In the present disclosure, the heating element 110 is located in the dielectric layer on the upper surface of the N-type MOSFET Q1, and is connected to the source of the N-type MOSFET Q1 via the wiring layer. The dielectric layer may also be referred to as a pre-metal dielectric (PMD). Since the heating element 110 is located in the dielectric layer, the area in which the heating element 110 can be set is not limited by the size of the active area 1001 of the N-type MOSFET Q1. At the same time, no matter where the heating element 110 is located in the semiconductor structure 100, it can be connected to the source of the N-type MOSFET Q1 through the wiring layer, and then receive current when the N-type MOSFET Q1 is turned on to generate heat, thereby realizing a flexible arrangement of the heating element 110 in the semiconductor structure 100 and enhancing the versatility of the semiconductor structure 100. Specifically, it can be combined with Figure 2 , Figure 4k and Figure 4l To understand.

[0045] refer to Figure 4k and Figure 4l In the present disclosure, a pre-metal dielectric layer is provided on the substrate 101 in the semiconductor structure 100, a metal wiring layer 109′ is provided on the pre-metal dielectric layer, a conductive plug corresponding to the source 120 and one end of the heating element 110 is penetrated in the pre-metal dielectric layer, and the metal wiring layer 109′ is electrically connected to the conductive plug, thereby realizing the electrical connection between the source 120 and one end of the heating element 110. Among them, the metal wiring layer 109′ corresponds to the etched metal layer 109, specifically, corresponds to the metal lead etched through the metal layer 109 for realizing the electrical connection between the source 120 of the N-type MOSFET Q1 and one end of the heating element 110. Based on the electrical signal transmission function of the wiring layer, the area where the heating element 110 in the semiconductor structure 100 can be set is expanded, so that the arrangement of the heating element 110 in the field area is more flexible in actual application, which helps to improve the efficiency of thermal annealing.

[0046] It can be understood that the semiconductor structure 100 of the present disclosure and the structure to be protected 200 may share the same substrate 101 , including the active region 1001 and the field region corresponding to the substrate 101 .

[0047] Further references Figure 2, in this embodiment, the source 120 and the drain 140 of the N-type MOSFET Q1 are both formed in the active region 1001 of the substrate, and the gate 130 is located in the dielectric layer on the active region 1001 and between the source 120 and the drain 140; while the heating element 110 is formed in the dielectric layer on the field region of the substrate. Among them, when the heating element 110 is disposed on the field region, it will not cause any shielding to the radiation induction region of the N-type MOSFET Q1 in the active region 1001, which can improve the radiation induction ability of the N-type MOSFET, and further improve the accuracy and reliability of the thermal annealing treatment of the structure 200 to be protected.

[0048] In this embodiment, the working principle of the semiconductor structure 100 is specifically as follows:

[0049] Under the action of external radiation, the threshold voltage (denoted as V TH ) of the N-type MOSFET Q1 in the semiconductor structure 100 drifts in the negative direction (i.e., the threshold voltage V TH gradually decreases), and at the same time, this drift has an accumulative effect. When the drift amount of the threshold voltage V TH meets a certain preset condition, for example, when the threshold voltage V TH of the N-type MOSFET Q1 decreases to be less than the bias voltage V TH(REF) received by its gate, the N-type MOSFET Q1 will conduct and generate a conduction current (denoted as I R ). For example, in the normal state, the designed threshold voltage V TH of the N-type MOSFET Q1 is 1.0V, while the externally applied bias voltage V TH(REF) on its gate is 0.8V, and at this time, the N-type MOSFET Q1 will not conduct. Under the action of external radiation, the actual threshold voltage V TH of the N-type MOSFET Q1 will decrease. When the threshold voltage V TH decreases to be lower than 0.8V, the N-type MOSFET Q1 will automatically conduct and generate a conduction current I R .

[0050] Furthermore, the conduction current I R generated after the N-type MOSFET Q1 conducts will act on the heating element 110, so that the heating element 110 generates heat. When the heat accumulates continuously and finally reaches the annealing temperature, the semiconductor structure 100 will be in a high-temperature state, and then the N-type MOSFET Q1 and the structure 200 to be protected in the semiconductor structure 100 will be thermally annealed simultaneously to suppress the influence of the total dose radiation effect on the semiconductor structure 100 and the structure 200 to be protected. Among them, the calculation formula for the value of the annealing temperature is as follows:

[0051] Q = CM(T1 - T0)..................................(1)

[0052] After transformation, the formula (1) can be obtained as follows:

[0053]

[0054] Among them, Q is the calorific value, C is the specific heat capacity, M is the mass, T1 is the final temperature, and T0 is the initial temperature. Therefore, the calorific value Q can be calculated from the resistance R and the conduction current I of the heating element 110 R to obtain the annealing temperature (i.e., T1).

[0055] Among them, the calculation formula for the calorific value Q of the heating element 110 is as follows:

[0056]

[0057]

[0058] Among them, R is the total resistance of the heating element 110, ρ is the resistivity of the material forming the heating element 110, L is the length of the heating element 110, S is the cross-sectional area of the heating element 110, Q is the calorific value of the heating element 110, and I R is the current value of the conduction current flowing through the heating element 110.

[0059] Based on formula (4), it can be seen that in the present disclosure, the calorific value Q of the heating element 110 can be changed by changing the current value I of the conduction current flowing through the heating element 110 R , and / or by changing the total resistance R of the heating element 110. Among them, the current value I of the conduction current R can be adjusted by changing the amplitude of the excitation signal received by the drain 140 of the N-type MOSFET Q1, which is a controllable variable and can still be externally adjusted according to requirements after the semiconductor structure 100 is formed. This will not be elaborated too much herein. And based on formula (3), it can be seen that the total resistance R of the heating element 110 can be adjusted by changing at least one of the material of the heating element 110, the length L of the heating element 110, and the cross-sectional area S of the heating element 110. Among them, considering the simplification of the manufacturing process and facilitating the synchronous fabrication of the heating element 110 and the gate 130 of the N-type MOSFET Q1, therefore, in the present disclosure, the heating element 110 is selected to be the same material as the gate 130 of the N-type MOSFET Q1, for example, both are polysilicon materials.

[0060] Furthermore, in a specific embodiment of the present disclosure, with reference to Figure 2, it is designed such that the heating element 110 is disposed around the active region 1001 of the N-type MOSFET Q1, so as to increase the length L of the heating element 110 to increase the total resistance R of the heating element 110, so that the heat generated when the heating element 110 generates heat is sufficient to basically cover the active region of the N-type MOSFET Q1 in the entire semiconductor structure 100 and the structure 200 to be protected, achieving the effect of thermal annealing, and can also provide the heat generated as evenly as possible to the active region of the N-type MOSFET Q1 in the semiconductor structure 100 and the structure 200 to be protected, improving the efficiency and accuracy of the thermal annealing process, and further better suppressing the influence of the total dose radiation effect on the structure 200 to be protected. Optionally, the heating element 110 may surround the active region 1001 at least one week, and specific settings should be reasonably made according to actual requirements.

[0061] It should be noted that considering the actual layout design and process limitations, the so-called "surrounding the active region at least one week" in this article does not mean that the heating element 110 must be a complete closed structure. For example, the heating element 110 can only surround 4 / 5, 7 / 8, 7 / 4, etc. of the active region.

[0062] In another specific embodiment of the present disclosure, refer to Figure 3 , it is designed such that the heating element 110 around the active region 1001 is arranged in a continuous bending type. In this way, the total resistance R of the heating element 110 can be further increased by further increasing the length L of the heating element 110 and reducing the cross-sectional area of the heating element 110, and then the ability of the heating element 110 to generate heat is enhanced, so that when the heating element 110 receives the same magnitude of conduction current I R more heat can be provided. At the same time, the heating element 110 with such a structure can also have better uniformity during heat transfer, so that even if the conduction current I R is small, the heating element 110 can also provide sufficient heat to complete the thermal annealing process of the structure 200 to be protected and the N-type MOSFET Q1, having better reliability. However, it can be understood that Figure 3 the continuous bending type arrangement structure (continuous equal-amplitude right-angle bending) shown in

[0063] is only exemplary. The heating element 110 in the present disclosure can also be a continuous bending type arrangement of curved lines with the same or different radian, and even can be a non-continuous bending type arrangement with only partial bending. The specific length and arrangement method of the heating element 110 can be selected according to the actual situation, and the present disclosure does not limit this. TH Under the action of the thermal annealing process, the threshold voltage V of the N-type MOSFET Q1 in the semiconductor structure 100 will have a positive drift, that is, the threshold voltage V THwill gradually recover. When the threshold voltage V of the N-type MOSFET Q1 TH drifts back to be greater than the bias voltage V received by its gate 130 TH(REF) in this case, the N-type MOSFET Q1 will turn off and interrupt the conduction current I transmitted to the heating element 110 R , thereby causing the heating element 110 to stop heating and stopping the thermal annealing treatment of the N-type MOSFET Q1 and the structure 200 to be protected in the semiconductor structure 100.

[0064] In this embodiment, the threshold voltage of the N-type MOSFET Q1 and the threshold voltage of the structure 200 to be protected may be the same or different. However, in addition, the N-type MOSFET Q1 has basically the same characteristics as the structure 200 to be protected (such as in the same radiation environment, the drift amount of the threshold voltage is basically the same). Therefore, during the self-annealing operation of the semiconductor structure 100, the generated heat will also perform thermal annealing treatment on the structure 200 to be protected. Because the annealing temperatures of the two (i.e., the temperatures required to eliminate the threshold voltage drift) are basically the same, the threshold voltage drift of the structure 200 to be protected can be suppressed.

[0065] Furthermore, the threshold voltage of the N-type MOSFET Q1 is preferably equal to or less than the threshold voltage of the structure 200 to be protected. In this way, it can be ensured that in the same total dose radiation environment, if the threshold voltage of the N-type MOSFET Q1 in the semiconductor structure 100 is restored after thermal annealing treatment, the threshold voltage of the structure 200 to be protected can also be restored. In the specific implementation process, generally, the threshold voltage of the N-type MOSFET Q1 is controlled to be less than the threshold voltage of the structure 200 to be protected to ensure the restoration of the threshold voltage of the structure 200 to be protected.

[0066] It can be understood that the main factors affecting the threshold voltage of the N-type MOSFET Q1 are the thickness of the gate oxide layer in the N-type MOSFET Q1 and the impurity concentration of the substrate under the gate. Therefore, when manufacturing the N-type MOSFET Q1, the threshold voltage of the N-type MOSFET Q1 can be reduced by fabricating a thin and dense gate oxide layer. Or, the ion implantation method can also be used to inject a certain amount of impurity ions into the region where the channel is located to reduce the threshold voltage of the N-type MOSFET Q1. At this time, the impurity distribution in the channel region can be adjusted by controlling the implantation dose and implantation depth, so as to achieve the purpose of adjusting the threshold voltage. Of course, a combination of the two can also be used to achieve the purpose of adjusting the threshold voltage of the N-type MOSFET Q1. The present disclosure does not limit this.

[0067] Reference Figure 2 、 Figure 4k and Figure 4l, in the present disclosure, the drain 140 of the N-type MOSFET Q1 is used to receive an excitation signal. Specifically, an external electrode corresponding to the drain 140 can be formed through the fourth contact hole 154 and the metal wiring layer 109' to realize the electrode lead-out of the drain 140. The gate 130 of the N-type MOSFET Q1 is used to receive a bias voltage V TH(REF) , specifically, an external electrode corresponding to the gate 130 can be formed through the third contact hole 153 and the metal wiring layer 109' to realize the electrode lead-out of the gate 130.

[0068] One end of the heating element 110 is electrically connected to the metal wiring layer 109' via the first contact hole 151, and the source 120 of the N-type MOSFET Q1 is electrically connected to the metal wiring layer 109' via the second contact hole 152. Wherein, a conductive material can be filled in both the first contact hole 151 and the second contact hole 152 to form a conductive plug. In this embodiment, both the first contact hole 151 and the second contact hole 152 are multiple, and the number of the multiple first contact holes 151 and the multiple second contact holes 152 is the same and their arranged positions correspond one by one. Thus, when the conduction current I R flows between the source 120 of the N-type MOSFET Q1 and the heating element 110, it is more evenly distributed, which can avoid the situation that the conductive plug is burned out due to local current concentration, and improves the reliability of the electrical connection relationship between the source 120 and the heating element 110.

[0069] The other end of the heating element 110 is led out through a plurality of fifth contact holes 155 and another metal lead etched from the metal layer 109, so as to realize the electrical connection with the reference ground. Specifically, it can be combined with Figures 4a - 4l and Figure 2 for understanding.

[0070] Next, the manufacturing method of the semiconductor structure provided by the present disclosure will be described in conjunction with Figures 4a - 4l . In the embodiment of the present disclosure, the manufacturing method of the semiconductor structure 100 is as follows:

[0071] 1) Synchronously form the gate of the N-type MOSFET Q1 on the active region of the substrate 101 and the heating element 110 on the field region of the substrate 101.

[0072] In this embodiment, synchronously forming the gate of the N-type MOSFET Q1 on the active region of the substrate 101 and the heating element 110 on the field region of the substrate 101 includes: forming a field oxide layer 104 on the substrate 101 to define the active region and the field region; sequentially forming a silicon oxide layer and a polysilicon layer covering the substrate 101 (i.e., covering the field region and the active region); etching the polysilicon layer to form the gate of the N-type MOSFET Q1 corresponding to the active region and the heating element 110 corresponding to the field region.

[0073] Specifically, as Figure 4a shown, a protective layer 102 and a silicon nitride layer 103 are sequentially formed on the P-type substrate 101. Among them, the P-type substrate 101 can be an epitaxial wafer or a single crystal wafer; the protective layer 102 can specifically be a silicon oxide layer.

[0074] As Figure 4b shown, a field oxide layer 104 is formed. The silicon nitride layer 103 covering the field region is etched away, and silicon oxide is regrown in this part to form the field oxide layer 104. In other words, the region of the substrate 101 covered by the field oxide layer 104 is the field region, and the region of the substrate 101 not covered by the field oxide layer 104 is the active region.

[0075] Based on the foregoing description, to ensure the accuracy and reliability of the thermal annealing treatment of the structure 200 to be protected, it is preferably to control the threshold voltage of the N-type MOSFET Q1 to be less than the threshold voltage of the structure 200 to be protected. Therefore, after defining the active region and the field region, it further includes: performing P-type ion implantation in the region corresponding to the gate of the N-type MOSFET Q1 in the active region to adjust the threshold voltage of the N-type MOSFET Q1. The adjustment of this threshold voltage requires that the threshold voltage V TH (i.e., the normal threshold voltage) of the N-type MOSFET Q1 when not affected by the total dose radiation effect is less than the normal threshold voltage of the structure 200 to be protected; at the same time, the threshold voltage V TH of the N-type MOSFET Q1 is greater than the bias voltage V TH(REF) received by its gate. The difference range between the two is preferably in the range of 0.15V to 0.35V, so that after the N-type MOSFET Q1 is affected by the total dose radiation effect, the drift degree of the threshold voltage can reasonably start / stop annealing, rather than being too sensitive or too slow.

[0076] As Figure 4c shown, the silicon nitride layer 103 and the protective layer 102 in the region 105 corresponding to the gate (i.e., the channel region) of the N-type MOSFET Q1 can be removed by wet etching, dry etching, or a combination of wet etching and dry etching to form an implantation window. Through this implantation window, P-type ions (such as boron ions) are implanted. By controlling the ion concentration and / or implantation depth injected into this region 105, the impurity concentration of the substrate 101 is adjusted, and thus the threshold voltage of the N-type MOSFET Q1 is adjusted.

[0077] As Figure 4d shown, the silicon nitride layer 103 and a part of the protective layer 102 on the surface of the active region can be removed by wet etching, and then a thin SiO2 layer is regrown on the surface of the field oxide layer 104 and the active region to form an oxide layer 106 covering the field region and the active region.

[0078] As shown Figure 4e in the figure, a layer of polysilicon is grown on the surface of the oxide layer 106 to form a polysilicon layer 107.

[0079] As shown Figure 4f in the figure, the polysilicon layer 107 is etched. Through steps such as applying photoresist, exposure, development, and etching, the polysilicon gate 130 of the N-type MOSFET Q1 located on the active region and the heating element 110 made of polysilicon material located on the field region are fabricated synchronously. Among them, during etching, chlorine atoms in chlorine gas can react with silicon to generate volatile compounds, and then a dry-wet etching process is used to remove the above-mentioned photoresist.

[0080] Furthermore, in the present disclosure, the heating element 110 surrounds the active region at least once. Of course, considering the actual layout design and process limitations, the so-called "surrounding the active region at least once" does not necessarily mean that the heating element 110 is necessarily a complete closed structure. For example, the heating element 110 can only surround 4 / 5, 7 / 8, 11 / 8, etc. of the active region.

[0081] Furthermore, in the present disclosure, the heating element 110 is arranged in a continuous and curved pattern.

[0082] 2) Form the source and drain electrodes of the N-type MOSFET Q1 located in the active region.

[0083] As shown Figure 4g in the figure, through photolithography and etching, the oxide layer 106 corresponding to the source region and the drain region on the surface of the active region is removed to form an ion implantation window; N-type impurities are implanted into the active region through the implantation window to respectively form the source electrode 120, the drain electrode 140 of the corresponding N-type MOSFET Q1, and the ohmic contact with the substrate 101.

[0084] 3) Form an electrical connection channel between the source electrode 120 of the N-type MOSFET Q1 and one end of the heating element 110, and form external electrodes corresponding to the gate electrode 130, the drain electrode 140 of the N-type MOSFET Q1, and the other end of the heating element 110 respectively.

[0085] As shown Figure 4h in the figure, a layer of SiO2 is grown on the upper surfaces of the field region and the active region to form an insulating layer 108 covering the N-type MOSFET Q1 and the heating element 110. Further, the insulating layer 108 can be planarized to have a relatively flat surface, which is beneficial for subsequent fabrication of the metal wiring layer.

[0086] As shown Figure 4iAs shown, a plurality of contact holes are formed through steps such as glue coating, exposure, development, and etching. Among them, a plurality of first contact holes 151 expose one end of the heating element 110, a plurality of second contact holes 152 expose the source electrode 120 located in the active region, a plurality of third contact holes 153 expose the gate electrode 130 above the active region, a plurality of fourth contact holes 154 expose the drain electrode 140 located in the active region, and a plurality of fifth contact holes 155 expose the other end of the heating element 110 (in combination with Figure 2 ), and then the above-mentioned photoresist is removed.

[0087] As Figure 4j shown, metal is sputtered on the insulating layer 108 and in the plurality of contact holes to form a metal layer 109.

[0088] As Figure 4k shown, a metal lead layer 109' is formed through steps such as glue coating, exposure, development, and etching, and then the above-mentioned photoresist is removed by using a dry and wet etching process. Among them, an external electrode corresponding to the drain electrode 140 of the N-type MOSFET Q1 can be formed through the plurality of fourth contact holes 154 and the metal wiring layer 109', thereby realizing the reception of the excitation signal. An external electrode corresponding to the gate electrode 130 of the N-type MOSFET Q1 can be formed through the plurality of third contact holes 153 and the metal wiring layer 109', thereby realizing the reception of the bias voltage V TH(REF) . An electrical connection path can be realized between one end of the heating element 110 and the source electrode 120 of the N-type MOSFET Q1 through the plurality of second contact holes 152, the metal wiring layer 109', and the plurality of first contact holes 151. An external electrode corresponding to the other end of the heating element 110 can be formed through the plurality of fifth contact holes 155 and the metal wiring layer 109' (refer to Figure 2 ), thereby realizing the electrical connection between the other end of the heating element 110 and the reference ground.

[0089] As Figure 4l shown, a passivation layer 111 is deposited on the upper surface of the insulating layer 108. Among them, the deposition of the passivation layer 111 can be carried out according to the standard process well-known in the art, and will not be elaborated here.

[0090] It can be understood that the manufacturing process of the above semiconductor structure 100 can be simply improved on the basis of the manufacturing process of traditional NMOS devices. Specifically, on the basis of the manufacturing process of traditional NMOS devices, the heating element 110 is formed while forming a polysilicon gate, and an electrical connection is realized between one end of the heating element 110 and the source electrode 120 during the process of realizing electrode extraction, and an electrical connection is realized between the other end of the heating element 110 and the reference ground.

[0091] Moreover, the manufacturing process of the above semiconductor structure 100 can be well compatible with the CMOS process, and thus can be fabricated on the same wafer simultaneously with other protected structures 200 manufactured using the CMOS process, without the need to develop a separate process line.

[0092] In summary, for the semiconductor structure and self-annealing chip disclosed in the present invention, based on the different changes in the threshold voltage of the N-type MOSFET under external radiation and thermal annealing treatment, the automatic switching control of the N-type MOSFET for the heating or stopping of the heating element can be achieved, and thus the automatic start or shutdown of the self-annealing function can be realized without setting an additional control source and manually set control programs. Therefore, the real-time performance and accuracy of the thermal annealing treatment for the protected structure can be effectively ensured. At the same time, the settable area of the heating element in the semiconductor structure is not limited by the size of the active region of the N-type MOSFET, and the flexible layout of the heating element in the semiconductor structure can be realized, enhancing the versatility of the semiconductor structure.

[0093] On the other hand, the manufacturing method of the semiconductor structure disclosed in the present invention is simple and has low cost.

[0094] Finally, it should be noted that: Obviously, the above embodiments are merely examples for clearly illustrating the present invention and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. The obvious changes or modifications derived therefrom still fall within the protection scope of the present invention.

Claims

1. A semiconductor structure, comprising: An N-type MOSFET and a heating element connected in series between an excitation signal input terminal and a reference ground. Wherein, the gate of the N-type MOSFET is used to receive a bias voltage. When the N-type MOSFET is irradiated externally, its threshold voltage decreases and conducts when the decreased threshold voltage is less than or equal to the bias voltage, thereby controlling the heating element to generate heat. During the heating process, it self-anneals and recovers, and turns off when the recovered threshold voltage is greater than the bias voltage, thereby controlling the heating element to stop generating heat. The heating element is located in a dielectric layer on the upper layer of the N-type MOSFET and is connected to the source electrode of the N-type MOSFET via a wiring layer.

2. The semiconductor structure according to claim 1, wherein, The semiconductor structure includes a substrate; the substrate includes a field region and an active region, and the heating element is located on the field region and surrounds the active region.

3. The semiconductor structure according to claim 1, wherein, The heating element is electrically connected to the wiring layer via a plurality of first contact holes, and the source electrode of the N-type MOSFET is electrically connected to the wiring layer via a plurality of second contact holes.

4. The semiconductor structure according to claim 2, wherein, The heating element is arranged in a continuous curved shape.

5. The semiconductor structure according to any one of claims 1-4, wherein, The heating element is made of polysilicon material, the N-type MOSFET has a polysilicon gate, and the heating element is formed synchronously with the polysilicon gate of the N-type MOSFET.

6. A self-annealing chip, wherein, Comprising: A structure to be protected and the semiconductor structure according to any one of claims 1-5, wherein the semiconductor structure can perform thermal annealing treatment on the structure to be protected.

7. The self-annealing chip according to claim 6, wherein, The threshold voltage of the N-type MOSFET in the semiconductor structure is less than the threshold voltage of the structure to be protected.

8. The self-annealing chip according to claim 6, wherein, The semiconductor structure and the structure to be protected are located in the same package structure, or the semiconductor structure and the structure to be protected are located in the same semiconductor device.

9. A method for fabricating a semiconductor structure, wherein, Comprising: Synchronously forming the gate of the N-type MOSFET on the active region of the substrate and the heating element on the field region of the substrate. Forming the source electrode and the drain electrode of the N-type MOSFET in the active region. Forming an electrical connection channel between the source electrode and one end of the heating element, and forming external electrodes corresponding to the gate, the drain electrode, and the other end of the heating element respectively. Wherein, the gate of the N-type MOSFET is used to receive a bias voltage. When the N-type MOSFET is irradiated externally, its threshold voltage decreases and conducts when the decreased threshold voltage is less than or equal to the bias voltage, thereby controlling the heating element to generate heat. During the heating process, it self-anneals and recovers, and turns off when the recovered threshold voltage is greater than the bias voltage, thereby controlling the heating element to stop generating heat.

10. The manufacturing method according to claim 9, wherein, Further comprising: Performing P-type ion implantation in the region corresponding to the gate of the N-type MOSFET in the active region to adjust the threshold voltage of the N-type MOSFET.

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