Integrated circuit and method for manufacturing the same

Abstract

An integrated circuit and a manufacturing method thereof are disclosed, wherein the integrated circuit comprises a first latch circuit, a second latch circuit and a clock circuit. The first latch circuit transmits a plurality of data signals to the second latch circuit via a plurality of first conductive lines, and the first conductive lines are arranged on the front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit via a plurality of second conductive lines, and the second conductive lines are arranged on the back side of the integrated circuit opposite to the front side.

Description

Technical Field

[0001] The present invention relates to an integrated circuit and a manufacturing method thereof, and more particularly to an integrated circuit having a backside conductive line for transmitting a clock signal and a manufacturing method thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced several generations of ICs. Summary of the invention

[0003] According to one embodiment of the present invention, an integrated circuit is disclosed, comprising a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits a plurality of data signals to the second latch circuit via a plurality of first conductive lines, and the first conductive lines are disposed on the front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit via a plurality of second conductive lines, and the second conductive lines are disposed on the back side of the integrated circuit opposite to the front side.

[0004] One embodiment of the present invention discloses an integrated circuit, including a flip-flop circuit. The flip-flop circuit includes a first unit having a first unit height and a second unit having a second unit height. The flip-flop circuit includes a first transistor in the first unit and a second transistor in the second unit. The first transistor includes a first gate and a first active region. The first gate receives a first signal from a first conductive line disposed on the front side of the integrated circuit. The first active region transmits a first clock signal to a second conductive line according to the first signal, and the second conductive line is in a first layer on the back side of the integrated circuit opposite to the front side. The flip-flop circuit further includes a third conductive line disposed in a second layer below the first layer on the back side of the integrated circuit and coupled to the second conductive line. The second transistor includes a second gate and a second active region. The second gate receives a first clock signal via a fourth conductive line, and the fourth conductive line is disposed in a first layer on the back side of the integrated circuit and coupled to the third conductive line. The second active region transmits a second clock signal to a fifth conductive line according to the first clock signal, and the fifth conductive line is in a first layer on the back side of the integrated circuit, wherein the second clock signal is generated by inverting the first clock signal.

[0005] One embodiment of the present invention discloses a method for manufacturing an integrated circuit, comprising the following steps: forming an active device operating as a scan flip-flop circuit on the front side of the integrated circuit; forming a plurality of first conductive lines extending in a first direction in a first layer on the back side of the integrated circuit to transmit a first clock signal and a second clock signal to the active device; forming a plurality of second conductive lines in the first layer on the back side of the integrated circuit to transmit a first power supply voltage and a second power supply voltage to the active device, wherein the first conductive lines are interposed between the second conductive lines; forming a plurality of third conductive lines extending in a second direction different from the first direction in a second layer on the back side of the integrated circuit to transmit the first clock signal and the second clock signal between the first conductive lines, wherein the first layer is disposed between the second layer and the front side of the integrated circuit; and forming a plurality of fourth conductive lines extending parallel to the third conductive lines in the second layer on the back side of the integrated circuit to transmit the first power supply voltage and the second power supply voltage to the second conductive lines, wherein the third conductive lines are interposed between the fourth conductive lines. In some embodiments, at least one of the second conductive lines includes a first portion extending in the first direction and a second portion extending in the second direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features are arbitrarily expanded or reduced for clarity of discussion.

[0007] Figure 1A is a top view of a portion of an integrated circuit according to some embodiments of the present invention;

[0008] Figure 1B is an example of some embodiments according to the present case along Figure 1A A cross-sectional view of the structure of some rows of cells at the mid-section line;

[0009] Figure 2A is a schematic diagram of an integrated circuit according to some embodiments of the present invention;

[0010] Figure 2B According to some embodiments of the present invention Figure 2A Detailed circuit of scanning flip-flop circuit;

[0011] FIG. 3A to FIG. 3B Examples of some embodiments of the present invention Figure 2B A plan view of the layout of the front portion of the scanning flip-flop circuit;

[0012] Figure 3C Examples of some embodiments of the present invention Figure 2B A layout diagram and a cross-sectional view of a portion of the back side of a scan flip-flop circuit;

[0013] Figure 4 is a plan view layout diagram of a portion of an integrated circuit according to various embodiments;

[0014] Figure 5 illustrates layout diagrams and cross-sectional views of portions of an integrated circuit according to various embodiments;

[0015] Figure 6 is a flow chart of a method for manufacturing an integrated circuit according to some embodiments of the present invention;

[0016] Figure 7 is a block diagram of a system for designing an integrated circuit layout design according to some embodiments of the present invention;

[0017] Figure 8 is a block diagram of an integrated circuit manufacturing system and an integrated circuit manufacturing process associated therewith according to some embodiments.

[0018]

Explanation of symbols

[0019] 10,40,50: Integrated Circuits

[0020] 110-180: Active zone

[0021] 131,132,141,142: Fin-shaped structure

[0022] 110a-110c, 120a-120e, 130a-130d, 140a, 140b: Active area

[0023] 200: Scanning Flip-flop Circuit

[0024] 210: Scanning multiplexer

[0025] 211: Scanning multiplexer input circuit

[0026] 212: Scan Enable Inverter

[0027] 220: Flip-flop circuit

[0028] 221: Main latch circuit

[0029] 222: From latch circuit

[0030] 223: Data output circuit

[0031] 224: Clock Circuit

[0032] 224a,224b: Clock Inverter

[0033] 301-328: Gate

[0034] 401-413: Conductive segment

[0035] 501-517: Conductive thread

[0036] 601-603: Conductive traces

[0037] 701-710,707',708',708",709',801-809: Back conductive wire

[0038] 901-905,1001-1007: Back conductive traces

[0039] 1100: Method

[0040] 1110-1150: Operation

[0041] 1200: EDA system

[0042] 1202:(Hardware) Processor

[0043] 1204: (Non-transitory computer readable) storage medium

[0044] 1206: Computer program code (instructions)

[0045] 1208: Bus

[0046] 1210:I / O interface

[0047] 1212: Network interface

[0048] 1214: Network

[0049] 1216: Manufacturing Tools

[0050] 1220: IC layout

[0051] 1222: Design Specifications

[0052] 1300:IC Manufacturing System

[0053] 1320:Design Agency

[0054] 1322: IC Design Layout

[0055] 1330:Mask mechanism

[0056] 1332: Data Preparation

[0057] 1344:Mask Manufacturing

[0058] 1345: Mask (marking line)

[0059] 1350: IC manufacturer / fab

[0060] 1352: Wafer Manufacturing

[0061] 1353:(Semiconductor) Wafer

[0062] 1360:IC device

[0063] CELL1-CELL2: Cell

[0064] FFCELL1-FFCELL2: Flip-flop unit

[0065] N1-N20: N-type transistor

[0066] P1-P20: P-type transistor

[0067] ROW1-ROW4: cell rows

[0068] VB1-VB21,VC,VD1-VD11,VF1-VF8,VF,VG1-VG14,VM1-VM8,VT:Through hole

[0069] VDD, VSS: supply voltage

[0070] H1,H2: unit height

[0071] AA',BB',CC',DD': cross section line

[0072] SE: Scan enable signal

[0073] SEB: Scan enable disable signal

[0074] SI: Scan Data Input

[0075] D: Normal data input

[0076] SD: Selected Data

[0077] CP: Clock signal

[0078] clkb,clk: clock signal

[0079] mq_x:signal

[0080] qf:Signal

[0081] Q: Data output signal DETAILED DESCRIPTION

[0082] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify an embodiment of the present invention. Of course, these are only examples and are not intended to be limiting. For example, forming a first feature on or on a second feature in the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, an embodiment of the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0083] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples (including examples of any term discussed herein) in this specification is illustrative only and in no way limits the scope and meaning of an embodiment of the case or any exemplified term. Likewise, an embodiment of the case is not limited to the various embodiments given in this specification.

[0084] In addition, for ease of description, spatially relative terms such as "below," "under," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or some) element or feature, as illustrated in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0085] Reference now Figure 1A . Figure 1A is a top view of a portion of integrated circuit 10 according to some embodiments. Figure 1A illustratively shown in FIG. 1 , the integrated circuit 10 includes several rows of cells ROW1-ROW4. In some embodiments, there are cells, for example, FIG. 3A to FIG. 3C and Figures 4 to 5 The cells illustrated in FIG. 1 are implemented by integrated circuits configured into the cell rows ROW1 - ROW4 . Figure 1A The number of cell rows ROW1-ROW4 in the integrated circuit 10 is given for illustrative purposes. Various numbers of cell rows ROW1-ROW4 are within the scope of an embodiment of the present invention. For example, in some embodiments, the number of cell rows in the integrated circuit 10 is greater than 4.

[0086] For illustration, the cell rows ROW1-ROW4 extend along the x-direction and are parallel to each other. In some embodiments, the cell rows ROW1-ROW4 are arranged along the y-direction that is substantially perpendicular to the x-direction.

[0087] In some embodiments, there are two groups of cell rows in rows ROW1-ROW4 in terms of their row height. Figure 1A illustratively shown in FIG. 1 , each of the cell rows ROW1 and ROW3 is configured to have a row height H1, and each of the cell rows ROW2 and ROW4 is configured to have another row height H2 that is shorter than the row height H1. The cell rows ROW1 and ROW3 having the row height H1 are considered as a first group "A" of the cell rows ROW1-ROW4, and the cell rows ROW2 and ROW4 are considered as a second group "B" of the cell rows ROW1-ROW4. In some embodiments, as Figure 1A As depicted in , a first group A of cell rows and a second group B of cell rows are staggered.

[0088] For illustration, a cell row ROW1 having a row height H1 in a first group "A" includes two active regions 110-120, and a cell row ROW2 having a row height H2 in a second group "B" includes two active regions 130-140. Similarly, a cell row ROW3 includes two active regions 150-160, and a cell row ROW4 includes two active regions 170-180. For illustration, the active regions 110-180 extend along the x-direction and are separated from each other in the y-direction. The configuration of the active regions 110-180 will be used in the following paragraphs. Figure 1B Discuss.

[0089] In some embodiments, active regions 120 and 140 have P-type conductivity, while active regions 110 and 130 have N-type conductivity. The configuration of active regions 150 and 180 is similar to active regions 110 and 140, and the configuration of active regions 160 and 170 is similar to active regions 120 and 130. In other words, the cell rows ROW1-ROW4 are staggered in a periodic sequence along the y direction. The configuration of active regions 110-180 is given for illustrative purposes. Various implementations of active regions 110-180 are included within the scope of an embodiment of the present case. For example, in some embodiments, active regions 110, 140, 150 and 180 are N-type, and active regions 120, 130, 160 and 170 are P-type.

[0090] Figure 1AThe configuration of the integrated circuit 10 is provided for illustrative purposes. Various implementations of the integrated circuit 10 are included within the scope of an embodiment of the present invention. For example, in some embodiments discussed in the following paragraphs, the cell rows are arranged in a sequence different from the cell rows ROW1-ROW4 (such as in a sequence of ROW1, ROW2, ROW4, and ROW3). In other words, cell rows having the same height are arranged adjacent to each other.

[0091] Reference now Figure 1B . Figure 1B Some examples of the following are given below: Figure 1A A cross-sectional view of the structure of the cell row ROW3-ROW4 at the cross-sectional line AA'. Figure 1A For ease of understanding, the same reference numerals are used to represent Figure 1B Similar components in .

[0092] like Figure 1B illustratively shown in FIG. 1 , a cell row ROW1 with a row height H1 in the second group “A” includes two active regions 110-120 on the substrate Sub. The active region 110 of the cell row ROW1 includes a first fin-shaped structure, and the active region 120 of the cell row ROW1 includes a second fin-shaped structure. In other words, each of the active regions 110-120 includes a fin-shaped structure.

[0093] like Figure 1B illustratively shown in FIG. 1 , a cell row ROW2 having a row height H1 in the first group “B” includes two active regions 130-140 on the substrate Sub. The active region 130 of the cell row ROW2 includes two fin-shaped structures 131 and 132, and the active region 140 of the cell row ROW2 includes another two fin-shaped structures 141 and 142. In other words, each of the active regions 130-140 includes two fin-shaped structures, such as 131 and 132 or 141 and 142.

[0094] In some embodiments, fin-shaped structures 131 and 132 are n-type fin-shaped structures, and fin-shaped structures 141 and 142 are p-type fin-shaped structures. In some other embodiments, fin-shaped structures 131 and 132 are p-type fin-shaped structures, and fin-shaped structures 141 and 142 are n-type fin-shaped structures.

[0095] The fins mentioned above may be patterned by any suitable method. For example, the fins may be patterned using one or more lithography processes, including double patterning or multi-patterning processes. Typically, the double patterning or multi-patterning process combines a lithography process with a self-aligned process, thereby allowing the created pattern to have a spacing that is, for example, smaller than the spacing that would otherwise be obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0096] In some embodiments, such an active region may include one or more fin-shaped structures of one or more three-dimensional field effect transistors (e.g., fin field effect transistors (FinFETs), gate-all-around (GAA) transistors), or oxide-definition (OD) regions of one or more planar metal-oxide-semiconductor field-effect transistors (MOSFETs). The active region may serve as a source feature or a drain feature of the corresponding transistor.

[0097] In some embodiments, the active region 130 of the cell row ROW2 includes two fin-shaped structures 131 and 132, which together serve as an active region to form an integrated circuit component (such as a transistor), so that the equivalent width of the active region of the integrated circuit component disposed on the active region 130 will be wider than the active region of another integrated circuit component disposed on the active region 110, and the active region 110 includes the first fin-shaped structure. In other words, in some embodiments, the integrated circuit component disposed on the cell row ROW2 has better performance than the integrated circuit component disposed on the cell row ROW1, for example, a faster computing speed.

[0098] Reference now Figure 2A . Figure 2A is a schematic diagram of an integrated circuit according to some embodiments of the present invention. In some embodiments, the integrated circuit includes a Figure 1A The scan flip-flop circuit 200 in the integrated circuit 10 is shown. For illustration, the scan flip-flop circuit 200 includes a scan multiplexer 210 and a flip-flop circuit 220. In some embodiments, the scan multiplexer 210 includes a scan multiplexer input circuit 211 and a scan enable inverter 212. The flip-flop circuit 220 includes a master latch circuit 221, a slave latch circuit 222, a data output circuit 223, and a clock circuit 224, and the clock circuit 224 includes clock inverters 224a and 224b.

[0099] In some embodiments, the scan multiplexer input circuit 211 receives a scan data input SI (i.e., a test vector signal such as used in a built-in self-test (BIST) scan or a boundary test scan), a normal data input D (i.e., actual application data rather than test data), a scan enable signal SE, and a scan enable disable signal SEB transmitted from a scan enable inverter 212. In operation, the scan enable signal SE controls whether the scan data input SI or the normal data input D is selected. For example, if the scan enable signal SE is enabled (e.g., set to logic "1"), the scan multiplexer 210 outputs the scan data input SI as the selected data SD. On the other hand, if the scan enable signal SE is disabled (e.g., set to logic "0"), the scan multiplexer 210 outputs the normal data input D as the selected data SD.

[0100] In some embodiments, the master latch circuit 221 and the slave latch circuit 222 are cross-coupled to store data states in a mutually reinforcing manner, and each receives clock signals clkb and clk. In various embodiments, the signal mq_x is transmitted between the master latch circuit 221 and the slave latch circuit 222. The data output circuit 223 has an input coupled to the output of the slave latch circuit 222 to receive the signal qf and output the data output signal Q. The clock signals clkb and clk are based on the clock signal CP and provided by the clock circuit 224. The clock inverter 224a inverts the clock signal CP and outputs the clock signal clkb, and the clock inverter 224b inverts the clock signal clkb and outputs the clock signal clk. Therefore, the clock signals clkb and clk are out of phase.

[0101] In operation, the flip-flop circuit 220 receives the selected data SD and generates an output data signal Q. The output data signal Q is based on the current state stored in the flip-flop circuit 220, the selected data SD, and the clock signal CP. The output data signal Q "flips" between the "1" state and the "0" state in a manner that depends on the selected data SD and the clock signal CP. In some embodiments, the flip-flop circuit 220 continues to output its currently stored state as the output data signal Q until the clock signal CP exhibits a rising and / or falling edge (regardless of whether there is a change in the selected data SD). When the clock signal CP exhibits a rising and / or falling edge, the flip-flop circuit 220 "stores" the current state of the selected data SD and delivers this state as the output data signal Q.

[0102] Reference now Figure 2B . Figure 2B According to some embodiments of the present invention Figure 2A The detailed circuit diagram of the scanning flip-flop circuit 200 is shown in FIG. Figure 2BAs shown, the scan flip-flop circuit 200 includes P-type transistors P1-P5, P7-P13, P15-P18, P20 and N-type transistors N1-N5, N7-N13, N15-N18, N20. Specifically, transistors P1-P4, P11, N1-N4 and N11 are operably coupled to form a scan multiplexer 210, and transistors P11-N11 are used to form a scan enable inverter 212. The master latch circuit 221 includes transistors P7 and N7, which establish an inverter coupled to the scan multiplexer 210, and further includes transistors P8-P9 and N8-N9, which establish another inverter selectively enabled based on clock signals clk and clkb. The inverters of transistors P10 and N10 and the transmission gates of P18 and N18 couple the master latch circuit 104 to the slave latch circuit 222. Transistors P10, P16-P18, N10 and N16-N18 are operably coupled to form a slave latch circuit 222, and the inverters of transistors P10 and N10 and the transmission gates of transistors P18 and N18 couple the master latch circuit 221 to the slave latch circuit 222. Transistors P16-P17 and N16-N17 establish inverters that are selectively enabled based on clock signals clk and clkb. Data output circuit 223 includes an inverter of transistors P15 and N15 and another inverter of transistors P12-P13 and N12-N13. Therefore, the data output signal Q has the same polarity (i.e., not inverted) with respect to the original data inputs D and SI. Transistors N5 and P5 constitute a clock inverter 224a and transistors N20 and P20 constitute a clock inverter 224b.

[0103] FIG. 2A to FIG. 2B The configuration is given for illustrative purposes. Various implementations are within the scope of an embodiment of the present invention. For example, in some embodiments, redrawing Figure 2B As an example, transistors P7 and N7 are included in the scan multiplexer 210 , transistors P10 , P18 and N10 , N18 are included in the master latch circuit 222 , and transistors P15 and N15 are included in the slave latch circuit 222 .

[0104] FIG. 3A to FIG. 3C Several layout views of portions of the scan flip-flop circuit 200 are depicted to illustrate its configuration. According to some embodiments of the present invention, FIG. 3A to FIG. 3B Example Figure 2B A plan view of a layout diagram of a front portion of the scanning flip-flop circuit 200, and Figure 3C Example Figure 2BLayout diagram and cross-sectional view of a portion of the back side of the scanning flip-flop circuit in the integrated circuit 10. In some embodiments, the scanning flip-flop circuit 200 in the integrated circuit 10 includes an active semiconductor device on its front side (i.e., having a drain / source structure implementation with an active region, a gate structure, a metal-on-device (MD) on the active region, a front metal wiring, etc.) and some metal wiring on its back side. In some embodiments, the active semiconductor device on the front side of the scanning flip-flop circuit 200 is formed on a substrate (not shown) in a front process. After the front process is completed, the inverted integrated circuit is flipped over so that the back surface of the substrate faces upward. The substrate is further thinned and removed. In some embodiments, the thinning is accomplished by a chemical mechanical planarization (CMP) process, a grinding process, etc. Therefore, a back process is performed to form a structure on the back side of the integrated circuit 100. The details of the manufacturing process will be discussed later.

[0105] Reference now Figure 3A For illustration, the scanning flip-flop circuit 200 is configured to be formed in a flip-flop cell FFCELL1 and includes active regions 110-120 in the cell CELL2 in the cell row ROW1, active regions 130-140 in the cell CELL1 in the cell row ROW2, and a gate shown as "poly", which is typically made of doped polysilicon or metal, extending over at least one of the active regions 110-140 and covering its channel region. For illustration, the gate extends in the y direction and the active regions 110-140 extend in the x direction.

[0106] In some embodiments, the gate is formed by a plurality of cut layers, the cut layers separating the continuous gates, such as Figure 3A In some embodiments, Figure 3A The corresponding Figure 2B The transistors P1-P5, P7-P13, P15-P18, P20, N1-N5, N7-N13, N15-N18 and N20 of the transistors in the embodiment are marked on the gate. Specifically, each of the transistors P1-P5, P7-P10 and N1-N5, N7-N10 includes a first number of fin structures formed in the active region 130 or 140, for example, two fin structures, and each of the transistors P11-P13, P15-P20 and N11-N13, N15-N20 includes a second number of fin structures formed in the active region 120 or 110, for example, one fin structure.

[0107] Reference now Figure 3B , which describes in more detail Figure 3A The layout of Figure 3BAs shown, the scan flip-flop circuit 200 includes gates 301-328, conductive segments (or metal on oxide definition regions (“MOOD” or “MD”)) 401-411, conductive lines (or metal layer 1 (M1)) 501-517, conductive traces (or metal layer 2 (M2)) 601-603, and vias VD1-VD11, VG1-VG14, and VM1-VM8. In some embodiments, the active regions 110-140 are disposed in a first layer on the front side of the scan flip-flop circuit 200, and the gates 301-328 and the conductive segments 401-411 cross at least one of the active regions 110-140. The conductive lines 501-517 are disposed on a second layer on the front side of the scan flip-flop circuit 200, above the first layer in a positive z-direction, wherein the z-direction is perpendicular to both the x-direction and the y-direction and above a plane including the x-axis and the y-axis. Vias VD1-VD11 and VG1-VG14 are disposed between the first and second layers. Conductive traces 601-603 are disposed on the third layer, above the second layer in the positive z-direction, on the front side of the scan flip-flop circuit 200. Vias VM1-VM8 are disposed between the second and third layers.

[0108] In some embodiments of the configuration in the front side of the scan flip-flop circuit 200, such as Figure 3B As shown in the cell CELL1 in FIG. 1 , gates 302-303 correspond to the gates of transistors P1 and N1. Gate 304 is shared as the gate of transistors P2 and N2. Gates 305-306 correspond to the gates of transistors P3 and N3. Conductive segment 401 corresponds to the drain of transistors P2-P3. Conductive segment 402 corresponds to the drain of transistors N2-N3. Gates 307-308 are shared as the gates of transistors P4, N4 and transistors P5, N5, respectively. Conductive segment 405 corresponds to the drain of transistors P5 and N5. Gate 310 corresponds to the gate of transistor P7, and gate 311 is shared as the gate of transistors N7 and P17. Conductive segment 403 corresponds to the source of transistor P7 and conductive segment 411 corresponds to the source of transistor N7. Gate 312 corresponds to the gate of transistor P8, and gate 313 is shared as the gate of transistors N8 and P18. Conductive segment 404 corresponds to the drain of transistors P7 and N7 and the source of transistors P8 and N8. Gate 314 is shared as the gate of transistors P9 and N9. Gate 315 is shared as the gate of transistors P10 and N10. Conductive segment 405 corresponds to the drain of transistors P10 and N10.

[0109] In addition, in the cell CELL2, the gate 318 is shared as the gate of the transistors P11 and N11. The conductive segment 406 corresponds to the drain of the transistors P11 and N11. The gate 319 is shared as the gate of the transistors P12 and N12. The conductive segment 407 corresponds to the drain of the transistors P12, P13 and N12, N13. The gate 322 is shared as the gate of the transistors P15 and N15. The conductive segment 408 corresponds to the drain of the transistors P15 and N15. The gate 323 is shared as the gate of the transistors P16 and N16. The gate 324 corresponds to the gate of the transistor N17, and the gate 325 corresponds to the gate of the transistor N18. The gate 327 is shared as the gate of the transistors P20 and N20. The conductive segment 413 corresponds to the drain of the transistors P20 and N20. Gates 301, 309, 316-317, 321, 326 and 328 are referred to as dummy gates, where in some embodiments, a "dummy" gate is referred to as a gate that is not electrically connected as a metal oxide semiconductor (MOS) device, where the term "dummy" corresponds to having no actual function in the circuit.

[0110] For illustration, gates 301-328 and conductive segments 401-409 extend in the y-direction and are separated from each other in the x-direction. Conductive line 501 extends in the x-direction and is separated from each other in the x or / and y-direction. Conductive traces 601-603 extend in the y-direction and are separated from each other in the x-direction.

[0111] Now common reference Figure 2B and Figure 3B The conductive trace 601 transmits the scan enable signal SE to the gate 302 via the via VM1 coupled between the conductive trace 601 and the conductive line 501 and the via VG1 coupled between the conductive line 501 and the gate 302, and also transmits the scan enable signal SE to the gate 306 via the via VM2 coupled between the conductive trace 601 and the conductive line 507 and the via VG5 coupled between the conductive line 507 and the gate 306, and transmits the scan enable signal SE to the gate 318 via the via VM3 coupled between the conductive trace 601 and the conductive line 514 and the via VG10 coupled between the conductive line 514 and the gate 318.

[0112] The scan enable disable signal SEB is output from the conductive segment 406 to the conductive trace 602 via the via VD7 coupled between the conductive segment 406 and the conductive line 512 and the via VM6 coupled between the conductive line 512 and the conductive trace 602. The scan enable disable signal SEB is further transmitted to the gate 303 via the via VM5 coupled between the conductive trace 602 and the conductive line 509 and the via VG2 coupled between the conductive line 509 and the gate 303, and is also transmitted to the gate 305 via the via VM4 coupled between the conductive trace 602 and the conductive line 503 and the via VG4 coupled between the conductive line 503 and the gate 305.

[0113] The conductive line 504 transmits the data signal D to the gate 304 via the via VG3 coupled between the conductive line 504 and the gate 304. The conductive line 505 transmits the clock signal CP to the gate 308 via the via VG7 coupled between the conductive line 505 and the gate 308.

[0114] The conductive line 508 transmits the scan data input SI to the gate 307 via the via VG6 coupled between the conductive line 508 and the gate 307 .

[0115] Conductive segment 401 is coupled to conductive segment 403 via via VD1 coupled between conductive line 502 and conductive segment 401 and via VD3 coupled between conductive line 502 and conductive segment 403. Therefore, the drains of transistors P2-P3 are coupled to the source of transistor P7.

[0116] Conductive segment 402 is coupled to conductive segment 411 via via VD2 coupled between conductive line 510 and conductive segment 402 and via VD4 coupled between conductive line 510 and conductive segment 411. Therefore, the drains of transistors N2-N3 are coupled to the source of transistor N7.

[0117] Conductive segment 404 is coupled to conductive line 506 via via VD5 and further coupled to gate 315. Therefore, the drains of transistors P7 and N7 are coupled to the gates of transistors P10 and N10. Conductive segment 405 is coupled to conductive line 513 via via VD6 and further coupled to gate 314 via via VG8. Therefore, the drains of transistors P10 and N10 are coupled to the gates of transistors P9 and N9. Conductive line 513 is coupled to conductive trace 603 via via VM7, and via VM8 couples conductive trace 603 to conductive line 516. Conductive line 516 is coupled to conductive segment 410 via via VD11. Therefore, the drains of transistors P10 and N10 are also coupled to the source / drain of transistors P18 and N18.

[0118] Conductive segment 409 is coupled to conductive line 515 via via VD10, and conductive line 515 is coupled to gate 322 via via VG13. Therefore, the drain / source of transistors P18 and N18 are coupled to the gates of transistors P15 and N15. Conductive segment 408 is coupled to conductive line 513 via via VD9. Conductive line 513 is coupled to gates 319-320 and 323 via vias VG11-VG12 and VG14, respectively. Therefore, the drains of transistors P15 and N15 are coupled to the gates of transistors P12-P13, P16, N12-N13, and N16.

[0119] The conductive segment 407 corresponding to the drains of the transistors P12-P13 and N12-N13 is coupled to the conductive line 517 via the via VD8. In some embodiments, the output signal Q is transmitted from the scan flip-flop circuit 200 via the wiring coupled to the conductive segment 407.

[0120] use FIG. 2A to FIG. 3B The scan multiplexer 210, the master latch circuit 221, the slave latch circuit 222 and the data output circuit 223 are used to transmit data signals, such as the scan enable signal SE, the scan enable disable signal SEB, the signals mq_x, mq, qf and qf_x, etc., through the wiring on the front side of the scan flip-flop circuit 200 (for example, the conductive segments 401-411, the conductive lines 501-517 and the conductive traces 601-603).

[0121] Reference now Figure 3C In some embodiments of the configuration in the back side of the scan flip-flop circuit 200, the clock circuit 224 is used to transmit the clock signals clk and clkb to the master latch circuit 221 and the slave latch circuit 222 via the wiring on the back side of the scan flip-flop circuit 200. Figure 3C , a cross-sectional view of a portion of the scan flip-flop circuit 200 taken along line BB′ and line CC′ is given.

[0122] For illustration, the scanning flip-flop circuit 200 further includes back conductive lines (i.e., back metal layer "M-1") 701-710, back conductive lines (i.e., back metal layer "M-2") 801-805, and vias VB1-VB21, VF1-VF8. In some embodiments, back conductive lines 701-710 are disposed in the fourth layer below the first layer including the action device. Back conductive lines 801-805 are disposed in the fifth layer below the fourth layer. In other words, the fourth layer is closer to the front side of the scanning flip-flop circuit 200 than the fifth layer, and the fourth layer is between the first layer and the fifth layer. Vias VB1-VB21 are disposed between the first layer and the fourth layer. Vias VF1-VF8 are disposed between the fourth layer and the fifth layer.

[0123] Reference now Figure 2B , Figure 3A and Figure 3C In some embodiments, regarding the transmission clock signals clkb and clk, Figure 3C Presented in Figure 2B and Figure 3A A detailed layout diagram of the components circled as "inter-cell back wiring". For example, as mentioned above, the clock signal CP is transmitted to the gate 308 of transistors P5 and N5. In response to the clock signal CP, the clock signal clkb is output at the drain of transistors N5 and P5. Figure 3CAs shown, the active region 130b (included in the active region 130, corresponding to the drain of the transistor N5) is coupled to the back conductive line 701 via the via VB1. The back conductive line 701 is further coupled to the gate 311 (corresponding to the gate of the transistor N7) via the via VB2. In addition, the back conductive line 701 is coupled to the back conductive line 801 via the via VF1. The back conductive line 801 is coupled to the back conductive lines 702 and 703 via the vias VF2-VF3, respectively. The back conductive line 702 is coupled to the gate 312 (corresponding to the gate of the transistor P8) via the via VB3. The back conductive line 703 is coupled to the gate 325 (corresponding to the gate of the transistor P18) via the via VB4. The back conductive line 703 is further coupled to the gate 327 (corresponding to the gates of the transistors P20 and N20) via the via VB5. Therefore, the clock signal clkb generated by the transistors N5 and P5 is transmitted to the gates of the transistors N7, P8, P18, P20 and N20.

[0124] Similarly, in the embodiment of transmitting the clock signal clk, Figure 3C As shown, the active region 120b (included in the active region 120, corresponding to the drain of the transistors P20 and N20) is coupled to the back conductive line 705 via the via VB6. The back conductive line 705 is further coupled to the gate 313 (corresponding to the gate of the transistors N8 and P18) via the via VB7. In addition, the back conductive line 705 is coupled to the back conductive line 802 via the via VF4. The back conductive line 802 is coupled to the back conductive lines 710 and 704 via the vias VF5-VF6, respectively. The back conductive line 710 is coupled to the gate 324 (corresponding to the gate of the transistor P17) via the via VB5. The back conductive line 704 is coupled to the gate 310 (corresponding to the gate of the transistor P7) via the via VB9. Therefore, the clock signal clk generated by the transistors N20 and P20 is transmitted to the gates of the transistors P7, N8, P17 and N18.

[0125] In some embodiments, the scan flip-flop circuit 200 also receives a supply voltage from the back wiring. For illustration, the back conductive lines 803 and 805 are used to input a supply voltage VSS (i.e., usually referred to as a ground voltage) to the scan flip-flop circuit 200, and the back conductive line 804 is used to input a supply voltage VDD greater than the supply voltage VSS. In addition, a via VF7 is coupled between the back conductive line 803 and the back conductive line 707 to transmit the supply voltage VSS to the back conductive line 707. A via VF8 is coupled between the back conductive line 804 and the back conductive line 706 to transmit the supply voltage VDD to the back conductive line 707.

[0126] As mentioned above, reference Figure 2B and Figure 3CIn both cases, the active region 140a (corresponding to the source of transistor P1) receives the supply voltage VDD via the via VB10 coupled between the active region 140a and the back conductive line 706. The active region 130a (corresponding to the source of transistor N1) receives the supply voltage VSS via the via VB11 coupled between the active region 130a and the back conductive line 707. The active region 140b (corresponding to the source of transistors P4-P5) receives the supply voltage VDD via the via VB12 coupled between the active region 140b and the back conductive line 706. The active region 130b (corresponding to the source of transistors N4-N5) receives the supply voltage VSS via the via VB13 coupled between the active region 130b and the back conductive line 707. Similarly, active regions 120a-120c (corresponding to sources of transistors N11-N13 and N15-N16, respectively) receive supply voltage VSS through vias VB14, VB16 and VB18, which respectively couple back conductive line 707 to active regions 120a-120c.

[0127] In some embodiments, the flip-flop cell FFCELL1 shares some of the back conductive lines 701-710 with other adjacent flip-flop cells (not shown, discussed in the following paragraphs). The back conductive line 708 provides the supply voltage VDD received from other flip-flop cells, and therefore, the active regions 110a-110c (corresponding to the sources of transistors P11-P13 and P15-P16, respectively) receive the supply voltage VDD via vias VB15, VB17, and VB19, wherein the vias VB15, VB17, and VB19 couple the back conductive line 708 to the active regions 110a-110c, respectively. Similarly, the back conductive line 709 provides the supply voltage VSS received from other flip-flop units, and therefore, the active regions 130d and 120e (corresponding to the sources of transistors N10 and N20, respectively) receive the supply voltage VSS via through holes VB20 and VB21, wherein the through holes VB20 and VB21 couple the back conductive line 709 to the active regions 130d and 120e, respectively.

[0128] Based on the above description, the back conductive lines (such as back conductive lines 706-709 and 803-805) for transmitting the supply voltages VDD and VSS are referred to as power rails. In some embodiments, the back conductive lines for transmitting the clock signals clk and clkb are surrounded by power rails or arranged beside the power rails in the same layer on the back side of the scan flip-flop circuit 200 in the layout view. For example, Figure 3CAs shown, at least one of the back conductive lines 701-709 (such as the back conductive lines 706-709) includes a first portion extending in the x-direction and a second portion extending in the y-direction. In other words, at least one of the back conductive lines 706-709 is L-shaped. The back conductive lines 801-805 extend in the y-direction. Therefore, the back conductive line 706 surrounds the back conductive lines 702 and 704. The back conductive lines 701 and 705 are between the back conductive lines 707 and 709. In addition, the back conductive lines 801-802 are between the conductive lines 804-805 in the fifth layer on the back side of the scan flip-flop circuit 200.

[0129] In some approaches, clock signals are transmitted via metal wiring on the front side of an integrated circuit, while other data signals pass through adjacent conductive lines. In such a configuration, the clock signal is easily interfered by those data signals due to the lack of shielding. In an embodiment of the present case, by configuring the conductive lines for transmitting clock signals on the back side and between the power rails on the back side, the power rails act as shielding to enhance the noise immunity of the back side conductive lines when transmitting clock signals.

[0130] FIG. 3A to FIG. 3C The configuration is given for illustrative purposes. Various implementations are within the scope of an embodiment of the present case. For example, in some embodiments, there is further a through hole coupled between the back conductive line 706 and the active region (corresponding to the source of the transistor P10) to transmit the supply voltage VDD to the transistor P10. In various embodiments, a portion of the conductive line configured with reference to the back conductive line 708 overlaps with the back conductive line 805, and the through hole couples the portion of the conductive line to the active region (corresponding to the source of the transistor P20) to transmit the supply voltage VDD to the transistor P20.

[0131] Reference now Figure 4 . Figure 4 is a plan view of a portion of an integrated circuit 40 according to various embodiments. Figures 1A to 3C For ease of understanding, the same reference numerals are used to represent Figure 4 For the sake of brevity, the specific operations of similar elements that have been discussed in detail in the above paragraphs are omitted herein.

[0132] like Figure 4 As shown, the integrated circuit 40 includes a plurality of flip-flop cells FFCELL1-FFCELL2 having the same configuration. The flip-flop cell FFCELL2 is adjacent to the flip-flop cell FFCELL1 in the y direction. The flip-flop cells FFCELL1-FFCELL2 are configured into a cell row with mixed cell heights, and the cell row has a similar Figure 1A Therefore, repeated description is omitted here.

[0133] In some embodiments, flip-flop cells FFCELL1-FFCELL2 are arranged along other cells in integrated circuit 40 and share back conductive lines 706-709, 707', 708', 708", and 709'. For illustration, back conductive lines 706-709, 707', 708', 708", and 709' extend in the x-direction and pass through cells arranged in a cell row. In addition, back conductive lines 706, 708, 708' and 708" receive the supply voltage VDD via the through holes corresponding to the back conductive lines 804, 807 and 808. Back conductive lines 707, 707', 709 and 709' receive the supply voltage VSS via the through holes corresponding to the back conductive lines 803, 806 and 809. In other words, the flip-flop units FFCELL1-FFCELL2 also share the back conductive lines 803-805 because the back conductive lines 803-805 extend in the y-direction and pass through the flip-flop units FFCELL1-FFCELL2.

[0134] Figure 4 The configuration is given for illustrative purposes. Various implementations are within the scope of an embodiment of the present invention. For example, in some embodiments, there are vias that couple the back conductive lines 709 and 709 ′ to the back conductive line 805 .

[0135] Reference now Figure 5 . Figure 5 Layout diagrams and cross-sectional views of a portion of an integrated circuit 50 are illustrated according to various embodiments. Figures 1A to 4 For ease of understanding, the same reference numerals are used to represent Figure 5 In some embodiments, the integrated circuit 50 is a reference to, for example, Figure 4 The integrated circuit 40 in the figure is configured. For the sake of simplicity, the flip-flop unit is not shown in the figure. In order to better understand Figure 5 , showing cross-sectional views of a portion of the integrated circuit 50 taken along line DD′ and line EE′.

[0136] and Figure 4In comparison, integrated circuit 50 further includes back side conductive traces (i.e., back side metal three layer "M-3") 901-905, back side conductive traces (i.e., back side metal four layer "M-4") 1001-1007, and vias VC and VT. In some embodiments, back side conductive traces 901-905 are disposed in the sixth layer below the fifth layer on the back side of integrated circuit 50. Back side conductive traces 1001-1007 are disposed in the seventh layer below the sixth layer on the back side of integrated circuit 50. Via VC is disposed between the fifth layer and the sixth layer on the back side of integrated circuit 50. Via VT is disposed between the sixth layer and the seventh layer on the back side of integrated circuit 50.

[0137] For illustration, back conductive traces 901-905 extend along the x-direction and are separated from one another in the y-direction. Back conductive traces 1001-1007 extend in the y-direction and are separated from one another in the x-direction.

[0138] In some embodiments, back conductive traces 1001-1007 are used to transmit supply voltages VDD and VSS to back conductive lines 706-709, 707', 708', 708" and 709' via back conductive traces 803-809 and back conductive traces 901-905. For example, back conductive trace 1002 provides supply voltage VDD to back conductive trace 902 via via VT. Back conductive trace 902 is coupled to back conductive line 807 via via VC. Back conductive line 807 is further coupled to 706 via via VF. Therefore, supply voltage VDD is transmitted from back conductive trace 1002 to back conductive line 706 and further to the active device.

[0139] Taking another example, along line EE', back conductive trace 1003 is coupled to back conductive trace 901 via via VT, and back conductive trace 901 is coupled to back conductive line 803 via via VC. Figure 3C and Figure 5 In both cases, the back conductive line 803 is coupled to the back conductive line 707 via the via VF7. The back conductive line 707 is coupled to the flip-flop unit FFCELL1 via the via VB11. Therefore, the supply voltage VSS is transmitted from the back conductive trace 1003 to the flip-flop unit FFCELL1. The configuration of the back conductive traces 901-905 and the back conductive traces 1001-1007 is similar to the configuration of the back conductive traces 902 and the back conductive traces 1003. Therefore, repeated descriptions are omitted here.

[0140] In some methods, although the clock signal is shared with multiple flip-flop units through metal wiring on the front side of the integrated circuit, it leads to great complexity and area penalty in the circuit design. Figure 4 and Figure 5 As shown, because the power supply voltage and clock signal are transmitted through the metal lines on the back side, improved flexibility and wiring utilization are provided, and thus the circuit design is optimized and the manufacturing cost is reduced.

[0141] Figure 5 The configuration is given for illustrative purposes. Various implementations are within the scope of an embodiment of the present invention. For example, in some embodiments, the number of through holes VC and VT is greater than Figure 5 The number shown in .

[0142] Figure 6 FIG. 1 is a flowchart of a method 1100 for manufacturing an integrated circuit according to some embodiments of the present invention, wherein the integrated circuit includes the integrated circuit 10, 40 or 50. It should be understood that in Figure 6 Additional operations may be provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchanged. Throughout the various views and illustrative embodiments, like reference numbers are used to represent like elements. Method 1100 includes operations 1110-1150, which are referred to below. FIG. 3B to FIG. 3C The flip-flop circuit 200 is described.

[0143] In operation 1110, a device for operating the scan flip-flop circuit 200 is formed on the front side of the integrated circuit 10. Figure 3B The active device includes active components, such as transistors P1-P5, P7-P13, P15-P18, P20, N1-N5, N7-N13, N15-N18 and N20.

[0144] In some embodiments, after forming the functional device, the integrated circuit is flipped over to perform backside processing.

[0145] In operation 1120, back-side conductive lines (including, for example, back-side conductive lines 701-705 and 710) are formed to extend in the x-direction in the fourth layer on the back side of the integrated circuit 10 (i.e., as mentioned above, a layer below the first layer on the front side of the scan flip-flop circuit 200) to transmit the clock signals clk and clkb to the scan flip-flop circuit 200. Figure 3C shown.

[0146] In operation 1130, other backside conductive lines (including, for example, backside conductive lines 706-709) are formed in the fourth layer on the backside of the integrated circuit 10 to transmit the supply voltages VSS and VDD to the scan flip-flop circuit 200. Figure 3CAs shown, for example, back conductive lines 701 and 705 are between back conductive lines 707 and 709. Back conductive lines 702 and 704 are surrounded by back conductive line 706.

[0147] In some embodiments, at least one of the back conductive lines 706 - 709 includes a first portion extending in the x-direction and a second portion extending in the y-direction, for example, the back conductive line 707 has an L-shape.

[0148] In operation 1140, back side conductive lines (including, for example, back side conductive lines 801-802) are formed to extend in the y direction in the fifth layer on the back side of the integrated circuit 10 (i.e., the layer below the fourth layer on the back side of the scan flip-flop circuit 200 as mentioned above), as shown in FIG. Figure 3C The fourth layer is between the fifth layer on the back side and the front side of the integrated circuit 10. The back side conductive lines 801-802 are used to transmit the clock signals clk and clkb between the back side conductive lines 701-705 and 710.

[0149] In operation 1150, back conductive lines 803-805 extending parallel to back conductive lines 801-802 are formed in the fifth layer on the back side of the integrated circuit 10 to transmit the supply voltages VSS and VDD to the back conductive lines 706-709. Figure 3C In some embodiments, the back conductive lines 801 - 802 are located between the back conductive lines 804 and 805 .

[0150] In some embodiments, Figure 5 As shown, the method 1100 further includes forming back conductive traces 901-905 extending in the x-direction in the sixth layer (i.e., the layer below the fifth layer on the back side of the scan flip-flop circuit 200 as mentioned above) and back conductive traces 1001-1007 extending in the y-direction in the seventh layer (i.e., the layer below the sixth layer on the back side of the scan flip-flop circuit 200 as mentioned above). For example, the back conductive traces 901-905 and the back conductive traces 1001-1007 are used to transmit the supply voltages VSS and BDD to the back conductive lines 803-804.

[0151] In some embodiments, there are no conductive lines for transmitting the clock signals clk and clkb in the sixth and seventh layers on the back side of the integrated circuit 10. Figure 5 shown in a cross-sectional view.

[0152] Reference now Figure 7 . Figure 7FIG. 1 is a block diagram of an electronic design automation (EDA) system 1200 for designing integrated circuit layout design according to some embodiments of the present invention. The EDA system 1200 is used to implement Figure 6 Revealed and combined Figures 1A to 5 One or more operations of method 1100 are further explained. In some embodiments, EDA system 1200 includes an APR system.

[0153] In some embodiments, EDA system 1200 is a general purpose computing device including a hardware processor 1202 and a non-transitory computer readable storage medium 1204. Storage medium 1204 is encoded with (i.e., stores) computer program code (instructions) 1206 (i.e., an executable instruction set), among other things. Hardware processor 1202 executes instructions 1206 (at least in part) to represent an EDA tool that implements, for example, a portion or all of method 1100.

[0154] The processor 1202 is electrically coupled to the computer readable storage medium 1204 via the bus 1208. The processor 1202 is also electrically coupled to the I / O interface 1210 and the manufacturing tool 1216 via the bus 1208. The network interface 1212 is also electrically coupled to the processor 1202 via the bus 1208. The network interface 1212 is connected to the network 1214, so that the processor 1202 and the computer readable storage medium 1204 can be connected to external components via the network 1214. The processor 1202 is used to execute the computer program code 1206 encoded in the computer readable storage medium 1204 so that the EDA system 1200 can be used to perform part or all of the process and / or method. In one or more embodiments, the processor 1202 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0155] In one or more embodiments, the computer-readable storage medium 1204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1204 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1204 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0156] In one or more embodiments, the storage medium 1204 stores computer program code 1206 for causing the EDA system 1200 (where such execution (at least in part) represents an EDA tool) to be used to perform a portion or all of the processes and / or methods. In one or more embodiments, the storage medium 1204 also stores information that facilitates the performance of a portion or all of the processes and / or methods. In one or more embodiments, the storage medium 1204 stores an IC layout 1220 of a standard cell, including such a standard cell as disclosed herein, for example, corresponding to the above referenced Figures 1A to 5 The cells of the integrated circuits 10, 40 and 50 are discussed.

[0157] The EDA system 1200 includes an I / O interface 1210. The I / O interface 1210 is coupled to an external circuit. In one or more embodiments, the I / O interface 1210 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touch screen, and / or cursor arrow keys for communicating information and commands to the processor 1202.

[0158] The EDA system 1200 also includes a network interface 1212 coupled to the processor 1202. The network interface 1212 allows the EDA system 1200 to communicate with a network 1214 to which one or more other computer systems are connected. The network interface 1212 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1264. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 1200.

[0159] The EDA system 1200 also includes a fabrication tool 1216 coupled to the processor 1202. The fabrication tool 1216 is used to fabricate an integrated circuit according to the design file processed by the processor 1202, for example, as described above with reference to FIG. Figures 1A to 5 Integrated circuits 10, 40, and 50 are discussed.

[0160] The EDA system 1200 is configured to receive information via an I / O interface 1210. The information received via the I / O interface 1210 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing performed by the processor 1202. The information is passed to the processor 1202 via a bus 1208. The EDA system 1200 is configured to receive information related to the UI via the I / O interface 1210. The information is stored in the computer-readable medium 1204 as a design specification 1222.

[0161] In some embodiments, part or all of the process and / or method is implemented as an independent software application for execution by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as a part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in for a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as a part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 1200. In some embodiments, the layout diagram including the standard cell is generated using a suitable layout generation tool.

[0162] In some embodiments, the processor is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical disks, such as DVDs; magnetic disks, such as hard disks; semiconductor memories, such as ROM, RAM, memory cards, etc.

[0163] Figure 8 1 is a block diagram of an IC manufacturing system 1300 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the IC manufacturing system 1300 is used to manufacture at least one of the following: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit.

[0164] exist Figure 8In the embodiment of the present invention, the IC manufacturing system 1300 includes entities that interact with each other in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 1360, such as a design organization 1320, a mask organization 1330, and an IC manufacturer / fab ("fab") 1350. The entities in the IC manufacturing system 1300 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design organization 1320, the mask organization 1330, and the IC fab 1350 are owned by a single entity. In some embodiments, two or more of the design organization 1320, the mask organization 1330, and the IC fab 1350 coexist in a common facility and use common resources.

[0165] The design organization (or design team) 1320 generates an IC design layout 1322. The IC design layout 1322 includes various geometric patterns, for example, Figure 1A and Figures 3A to 5 The IC layout design depicted in FIG. 1 is designed for use with an IC device 1360, such as the IC layout design depicted in FIG. Figure 1A and Figures 3A to 5 The integrated circuits 10, 40, and 50 discussed. The geometric pattern corresponds to the pattern of metal, oxide, or semiconductor layers that make up the various components of the IC device 1360 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 1322 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate, such as active regions, gate electrodes, source and drain, conductive segments or vias for interconnecting between layers. The design mechanism 1320 implements an appropriate design program to form the IC design layout 1322. The design program includes one or more of a logical design, a physical design, or a location and route. The IC design layout 1322 is presented in one or more data files having information of the geometric pattern. For example, the IC design layout 1322 can be expressed in a GDSII file format or a DFII file format.

[0166] The mask mechanism 1330 includes data preparation 1332 and mask manufacturing 1344. The mask mechanism 1330 uses the IC design layout drawing 1322 to manufacture one or more masks 1345, which will be used to manufacture various layers of the IC device 1360 according to the IC design layout drawing 1322. The mask mechanism 1330 performs mask data preparation 1332, wherein the IC design layout drawing 1322 is translated into a representative data file ("RDF"). The mask data preparation 1332 provides the RDF to the mask manufacturing 1344. The mask manufacturing 1344 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1345 or a semiconductor wafer 1353. The IC design layout drawing 1322 is manipulated by the mask data preparation 1332 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1350. In Figure 8 In FIG. 1 , data preparation 1332 and mask manufacturing 1344 are illustrated as separate elements. In some embodiments, data preparation 1332 and mask manufacturing 1344 may be collectively referred to as mask data preparation.

[0167] In some embodiments, data preparation 1332 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, crosstalk, other process effects, etc. OPC adjusts IC design layout 1322. In some embodiments, data preparation 1332 includes additional resolution enhancement techniques (RET), such as off-axis illumination, secondary resolution assist features, phase shift masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0168] In some embodiments, data preparation 1332 includes a mask rule checker (MRC) that checks the IC design layout 1322 that has undergone processing in OPC using a set of mask creation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1322 to compensate for the constraints during mask creation 1344, which may undo portions of the modifications performed by the OPC in order to satisfy the mask creation rules.

[0169] In some embodiments, data preparation 1332 includes lithography process checking (LPC), which simulates the processing to be performed by IC fab 1350 to manufacture IC device 1360. LPC simulates this processing based on IC design layout 1322 to create a simulated manufactured device, such as IC device 1360. Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after LPC has created the simulated manufactured device, if the shape of the simulated device is not sufficient to meet the design rules, OPC and / or MRC will be repeated to further improve IC design layout 1322.

[0170] It should be understood that the above description of data preparation 1332 has been simplified for the purpose of clarity. In some embodiments, data preparation 1332 includes additional features, such as logic operations (LOPs), to modify IC design layout 1322 according to manufacturing rules. In addition, the processes applied to IC design layout 1322 during data preparation 1332 can be performed in a variety of different orders.

[0171] After data preparation 1332 and during mask fabrication 1344, a mask 1345 or a set of masks 1345 are fabricated based on the modified IC design layout 1322. In some embodiments, mask fabrication 1344 includes performing one or more lithographic exposures based on the IC design layout 1322. In some embodiments, an electron-beam (e-beam) or multiple e-beam mechanisms are used to form a pattern on a mask (mask or reticle) 1345 based on the modified IC design layout 1322. Mask 1345 can be formed using various techniques. In some embodiments, mask 1345 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, is used to expose an image-sensitive material layer (e.g., photoresist) that has been coated on a wafer, is blocked by the opaque areas and is transmitted through the transparent areas. In one example, a binary mask version of mask 1345 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1345 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 1345, various features in a pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. Masks produced by mask manufacturing 1344 are used in a variety of processes. For example, such mask(es) are used in an ion implantation process to form various doped regions in semiconductor wafer 1353, in an etching process to form various etched regions in semiconductor wafer 1353, and / or in other suitable processes.

[0172] IC fab 1350 includes wafer fabrication 1352. IC fab 1350 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 1350 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line, FEOL) manufacturing) of multiple IC products, while a second manufacturing facility may provide back-end manufacturing (back-end-of-line, BEOL) manufacturing) for interconnecting and packaging IC products, and a third manufacturing facility may provide other services for the foundry enterprise.

[0173] IC fab 1350 uses mask 1345 manufactured by mask mechanism 1330 to manufacture IC device 1360. Therefore, IC fab 1350 at least indirectly uses IC design layout 1322 to manufacture IC device 1360. In some embodiments, IC fab 1350 uses mask 1345 to manufacture semiconductor wafer 1353 to form IC device 1360. In some embodiments, IC manufacturing includes performing one or more lithography exposures based on IC design layout 1322 at least indirectly. Semiconductor wafer 1353 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 1353 further includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0174] As described above, an integrated circuit in one embodiment of the present invention includes back conductive lines for transmitting clock signals and power supply voltage signals. With the configuration of one embodiment of the present invention, noise interference caused by data signals transmitted on the front side of the integrated circuit is eliminated, and the conductive lines for clock signals are not adjacent to the data signals, and the conductive lines for power supply voltage signals shield the conductive lines for clock signals from interference. Therefore, enhanced noise immunity of the integrated circuit is provided.

[0175] In some embodiments, an integrated circuit is disclosed, which includes a first latch circuit, a second latch circuit, and a clock circuit. The first latch circuit transmits a plurality of data signals to the second latch circuit via a plurality of first conductive lines, and the plurality of first conductive lines are disposed on the front side of the integrated circuit. The clock circuit transmits a first clock signal and a second clock signal to the first latch circuit and the second latch circuit via a plurality of second conductive lines, and the plurality of second conductive lines are disposed on the back side of the integrated circuit opposite to the front side. In some embodiments, the clock circuit includes a first inverter for generating a first clock signal. Each transistor in the first inverter includes a first number of fin structures. The clock circuit also includes a second inverter for generating a second clock signal. Each transistor in the second inverter includes a second number of fin structures. The first number and the second number are different from each other. In some embodiments, the second conductive lines include: a first group of conductive lines disposed in a first layer on the back side of the integrated circuit; and a second group of conductive lines disposed in a second layer on the back side of the integrated circuit. The first layer is closer to the front side of the integrated circuit than the second layer. In some embodiments, the integrated circuit further includes: at least one first via coupled between at least one of the first group of conductive lines and at least one of the second group of conductive lines; and at least one second via coupled between the at least one of the first group of conductive lines and at least one gate included in the first latch circuit. In some embodiments, the integrated circuit further includes a plurality of power rails disposed in the first layer. The first group of conductive lines is between the power rails. In some embodiments, the integrated circuit further includes a plurality of first power rails. The first power rail and the second conductive line are disposed in the first layer on the back side of the integrated circuit. At least one of the first power rails includes a first portion extending in a first direction and a second portion extending in a second direction different from the first direction. The at least one of the first power rails surrounds at least one of the second conductive lines in a layout view. In some embodiments, the integrated circuit further includes: a plurality of second power rails extending in the second direction and separated from each other in the first direction; and a plurality of vias coupled between the first power rail and the second power rail. In some embodiments, the integrated circuit further includes a plurality of power rails disposed in the first layer on the back side of the integrated circuit. At least one of the power rails is L-shaped. The power rails are used to transmit the first supply voltage and the second supply voltage to the first latch circuit and the second latch circuit. In some embodiments, the integrated circuit further includes a plurality of first power rails to a plurality of fourth power rails disposed in the first to fourth layers on the back side of the integrated circuit. The first layer is one of the first to fourth layers closest to the front side of the integrated circuit, and the fourth layer is one of the first to fourth layers farthest from the front side of the integrated circuit. The first power rails to the fourth power rails are used to transmit at least one supply voltage to the first latch circuit, the second latch circuit, and the clock circuit.In some embodiments, the second conductive lines include: a first set of conductive lines disposed in the first layer and between the first power rails in the layout view; and a second set of conductive lines disposed in the second layer and between the second power rails in the layout view.

[0176] An integrated circuit is also disclosed, which includes a flip-flop circuit, the flip-flop circuit including a first unit having a first unit height and a second unit having a second unit height. The flip-flop circuit includes a first transistor in the first unit and a second transistor in the second unit. The first transistor includes a first gate and a first active region. The first gate receives a first signal from a first conductive line disposed on the front side of the integrated circuit. The first active region transmits a first clock signal to a second conductive line according to the first signal, the second conductive line being in a first layer on the back side of the integrated circuit opposite to the front side. The flip-flop circuit further includes a third conductive line disposed in a second layer below the first layer on the back side of the integrated circuit and coupled to the second conductive line. The second transistor includes a second gate and a second active region. The second gate receives a first clock signal via a fourth conductive line, the fourth conductive line being disposed in a first layer on the back side of the integrated circuit and coupled to the third conductive line. The second active region transmits a second clock signal to a fifth conductive line in the first layer on the back side of the integrated circuit according to the first clock signal, wherein the second clock signal is generated by inverting the first clock signal. In some embodiments, the first unit height and the second unit height are different from each other. In some embodiments, the integrated circuit further includes a first power rail and a second power rail disposed in a first layer on the back side of the integrated circuit. The first power rail couples the third active region included in the first transistor to the first supply voltage. The second power rail couples the fourth active region included in the second transistor to the first supply voltage. The second conductive line is between the first power rail and the second power rail. In some embodiments, the integrated circuit further includes a plurality of flip-flop circuits in a plurality of flip-flop units. The flip-flop units are adjacent to each other along a direction. The integrated circuit further includes a third power rail and a fourth power rail disposed in a second layer on the back side of the integrated circuit and passing through the flip-flop units in the direction. The third power rail and the fourth power rail are used to couple the first power rail and the second power rail to the first supply voltage, respectively. In some embodiments, the third conductive line extends across the first unit to the second unit. In some embodiments, the integrated circuit further includes a third transistor in the first unit. The third transistor includes a third gate for receiving a first clock signal via a sixth conductive line, which is disposed in the first layer on the back side of the integrated circuit and coupled to the third conductive line.

[0177] A method is also disclosed, which includes the following operations: forming an active device operating as a scan flip-flop circuit on the front side of an integrated circuit; forming a plurality of first conductive lines extending in a first direction in a first layer on the back side of the integrated circuit to transmit a first clock signal and a second clock signal to the active device; forming a plurality of second conductive lines in the first layer on the back side of the integrated circuit to transmit a first power supply voltage and a second power supply voltage to the active device, wherein the first conductive lines are interposed between the second conductive lines; forming a plurality of third conductive lines extending in a second direction different from the first direction in a second layer on the back side of the integrated circuit to transmit the first clock signal and the second clock signal between the first conductive lines, wherein the first layer is disposed between the second layer and the front side of the integrated circuit; and forming a plurality of fourth conductive lines extending parallel to the third conductive lines in the second layer on the back side of the integrated circuit to transmit the first power supply voltage and the second power supply voltage to the second conductive lines, wherein the third conductive lines are interposed between the fourth conductive lines. In some embodiments, at least one of the second conductive lines includes a first portion extending in the first direction and a second portion extending in the second direction. In some embodiments, the method further includes: forming a plurality of fifth conductive lines extending in the first direction and a plurality of sixth conductive lines extending in the second direction in the third layer and the fourth layer on the back side of the integrated circuit, respectively, to transmit the first supply voltage and the second supply voltage to the fourth conductive lines. In some embodiments, the third layer is sandwiched between the second layer and the fourth layer.

[0178] The foregoing content summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of an embodiment of the present invention. Those skilled in the art should understand that they can easily use an embodiment of the present invention as a basis to design or modify other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also be aware that such equivalent constructions do not depart from the spirit and scope of an embodiment of the present invention, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of an embodiment of the present invention.

Claims

1. An integrated circuit, characterized in that: Include: a first latch circuit and a second latch circuit, wherein the first latch circuit is used to transmit a plurality of data signals to the second latch circuit via a plurality of first conductive lines, wherein the plurality of first conductive lines are disposed on a front surface of the integrated circuit; as well as a clock circuit for transmitting a first clock signal and a second clock signal to the first latch circuit and the second latch circuit via a plurality of second conductive lines, wherein the plurality of second conductive lines are disposed on a back side of the integrated circuit opposite to the front side, The clock circuit includes: a first inverter comprising a plurality of first transistors, wherein the plurality of first transistors comprises a first number of fin structures; and A second inverter includes a plurality of second transistors, wherein the plurality of second transistors include a second number of fin structures different from the first number.

2. The integrated circuit according to claim 1, characterized in that The first inverter is used to generate the first clock signal, and The second inverter is used to generate the second clock signal. The first number is smaller than the second number.

3. The integrated circuit according to claim 1, characterized in that The plurality of second conductive lines include: a first set of conductive lines disposed in a first layer on the back side of the integrated circuit; and A second set of conductive lines is disposed in a second layer on the back side of the integrated circuit, wherein the first layer is closer to the front side of the integrated circuit than the second layer.

4. The integrated circuit according to claim 3, characterized in that Also includes: at least one first via coupled between at least one of the first set of conductive lines and at least one of the second set of conductive lines; and At least one second via is coupled between the at least one of the first set of conductive lines and at least one gate included in the first latch circuit.

5. The integrated circuit according to claim 3, characterized in that: Also includes: A plurality of power rails are disposed in the first layer, wherein the first set of conductive lines are interposed between the plurality of power rails.

6. The integrated circuit according to claim 1, characterized in that Also includes: a plurality of first power rails, wherein the plurality of first power rails and the plurality of second conductive lines are disposed in a first layer on a back side of the integrated circuit, At least one of the plurality of first power rails includes a first portion extending in a first direction and a second portion extending in a second direction different from the first direction, wherein the at least one of the plurality of first power rails surrounds at least one of the plurality of second conductive lines in a layout view.

7. The integrated circuit according to claim 6, characterized in that Also includes: a plurality of second power rails extending in the second direction and separated from each other in the first direction; as well as A plurality of through-holes are coupled between the plurality of first power rails and the plurality of second power rails.

8. The integrated circuit according to claim 1, characterized in that Also includes: a plurality of power rails disposed in a first layer on the back side of the integrated circuit, wherein at least one of the plurality of power rails is L-shaped, The plurality of power rails are used to transmit a first power supply voltage and a second power supply voltage to the first latch circuit and the second latch circuit.

9. The integrated circuit according to claim 1, characterized in that: Also includes: A plurality of first power rails to a plurality of fourth power rails are disposed in a first to a fourth layer on the back side of the integrated circuit, The first plurality of power rails to the fourth plurality of power rails are used to transmit at least one supply voltage to the first latch circuit, the second latch circuit and the clock circuit.

10. The integrated circuit according to claim 9, characterized in that The plurality of second conductive lines include: a first set of conductive lines disposed in a first layer and between the first power rails in a layout view; and A second set of conductive lines is disposed in a second layer and between the second power rails in the layout view.

11. An integrated circuit, characterized in that: Include: A flip-flop circuit includes a first unit having a first unit height and a second unit having a second unit height, and comprises: A first transistor in the first unit comprises: a first gate for receiving a first signal from a first conductive line disposed on a front side of the integrated circuit; and a first active region for transmitting a first clock signal to a second conductive line according to the first signal, the second conductive line being in a first layer on a back side of the integrated circuit opposite to the front side; a third conductive line disposed in a second layer below the first layer on the back side of the integrated circuit and coupled to the second conductive line; as well as A second transistor in the second unit comprises: a second gate for receiving the first clock signal via a fourth conductive line disposed in the first layer on the back side of the integrated circuit and coupled to the third conductive line; as well as A second active region is used to transmit a second clock signal to a fifth conductive line according to the first clock signal. The fifth conductive line is in the first layer on the back side of the integrated circuit, wherein the second clock signal is generated by inverting the first clock signal.

12. The integrated circuit according to claim 11, characterized in that The first unit height and the second unit height are different from each other.

13. The integrated circuit according to claim 11, characterized in that Also includes: a first power rail and a second power rail disposed in the first layer on the back side of the integrated circuit, wherein the first power rail is used to couple a third active region included in the first transistor to a first supply voltage, and the second power rail is used to couple a fourth active region included in the second transistor to the first supply voltage, The second conductive line is between the first power rail and the second power rail.

14. The integrated circuit according to claim 13, characterized in that Also includes: a plurality of flip-flop circuits in a plurality of flip-flop units, wherein the plurality of flip-flop units are adjacent to each other along a direction; and A third power rail and a fourth power rail are disposed in the second layer on the back side of the integrated circuit and pass through the plurality of flip-flop units in the direction, wherein the third power rail and the fourth power rail are used to couple the first power rail and the second power rail to the first supply voltage, respectively.

15. The integrated circuit according to claim 11, characterized in that The third conductive line extends across the first unit to the second unit.

16. The integrated circuit according to claim 11, characterized in that Also includes: A third transistor in the first unit comprises: A third gate is used to receive the first clock signal via a sixth conductive line, wherein the sixth conductive line is disposed in the first layer on the back side of the integrated circuit and is coupled to the third conductive line.

17. A method for manufacturing an integrated circuit, characterized in that: Include: forming an active device operating as a scan flip-flop circuit on a front side of an integrated circuit; A plurality of first conductive lines extending in a first direction are formed in a first layer on a back surface of the integrated circuit to transmit a first clock signal and a second clock signal to the active device; forming a plurality of second conductive lines in the first layer on the back side of the integrated circuit to transmit a first supply voltage and a second supply voltage to the active device, wherein the plurality of first conductive lines are interposed between the plurality of second conductive lines; forming a plurality of third conductive lines extending in a second direction different from the first direction in a second layer on the back side of the integrated circuit to transmit the first clock signal and the second clock signal between the plurality of first conductive lines, wherein the first layer is disposed between the second layer and the front side of the integrated circuit; as well as A plurality of fourth conductive lines extending parallel to the plurality of third conductive lines are formed in the second layer on the back side of the integrated circuit to transmit the first supply voltage and the second supply voltage to the plurality of second conductive lines, wherein the plurality of third conductive lines are interposed between the plurality of fourth conductive lines.

18. The method for manufacturing an integrated circuit according to claim 17, characterized in that: At least one of the second conductive lines includes a first portion extending in the first direction and a second portion extending in the second direction.

19. The method for manufacturing an integrated circuit according to claim 17, characterized in that: Also includes: A plurality of fifth conductive lines extending in the first direction and a plurality of sixth conductive lines extending in the second direction are respectively formed in a third layer and a fourth layer on the back side of the integrated circuit to transmit the first supply voltage and the second supply voltage to the plurality of fourth conductive lines.

20. The method for manufacturing an integrated circuit according to claim 19, characterized in that: The third layer is sandwiched between the second layer and the fourth layer.

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