Memory device

Abstract

A memory device includes a stack structure, a memory element, a passage element, and a semiconductor layer. The stack structure includes a source layer, an insulating layer, and a gate electrode layer. The insulating layer is on the source layer. The gate electrode layer is on the insulating layer. The memory element is on an electrode sidewall surface of the gate electrode layer. A memory cell is defined in the memory element between the passage element and the gate electrode layer. The semiconductor layer is electrically connected between the source layer and the passage element. An interface is between the semiconductor layer and the source layer. The interface is laterally offset inside an insulating sidewall surface of the insulating layer.

Description

TECHNICAL FIELD

[0001] The present invention relates to a memory device. BACKGROUND

[0002] As critical dimensions of elements in integrated circuits are scaled down to the limits perceived by fabrication processes, designers have begun to seek techniques that can achieve greater memory density, thereby achieving lower costs per bit. SUMMARY

[0003] The present invention relates to a memory device.

[0004] According to an aspect of the present invention, a memory device includes a stack structure, a storage element, a channel element, and a semiconductor layer. The stack structure includes a source layer, an insulating layer, and a gate electrode layer. The insulating layer is on the source layer. The gate electrode layer is on the insulating layer. The storage element is on an electrode sidewall surface of the gate electrode layer. A storage cell is defined in the storage element between the channel element and the gate electrode layer. The semiconductor layer is electrically connected between the source layer and the channel element. The semiconductor layer has an interface with the source layer. The interface is laterally offset inside an insulating sidewall surface of the insulating layer.

[0005] According to another aspect of the present invention, a memory device includes a stack structure, a storage element, a channel element, and a semiconductor layer. The stack structure includes a source layer and a plurality of gate electrode layers. The gate electrode layers are on the same side of the source layer. The storage element is on an electrode sidewall surface of the gate electrode layers. A storage cell is defined in the storage element between the channel element and the gate electrode layers. The semiconductor layer is electrically connected between the channel element and the source layer. The semiconductor layer includes a first semiconductor portion and a second semiconductor portion. The second semiconductor portion is electrically connected between the first semiconductor portion and the channel element. A semiconductor sidewall surface of the first semiconductor portion is laterally offset outside a semiconductor sidewall surface of the second semiconductor portion.

[0006] According to yet another aspect of the present invention, a memory device includes a stack structure, a storage element, a channel element, and a semiconductor layer. The stack structure includes a source layer and a gate electrode layer. The gate electrode layer is on the same side of the source layer. The storage element is on an electrode sidewall surface of the gate electrode layer. A storage cell is defined in the storage element between the channel element and the gate electrode layer. The semiconductor layer includes a first semiconductor portion and a second semiconductor portion. The second semiconductor portion is electrically connected between the first semiconductor portion and the channel element. A lateral dimension of the first semiconductor portion is greater than a lateral dimension of the second semiconductor portion.

[0007] For a better understanding of the present invention, reference will be made to the following examples and accompanying drawings: BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A cross-sectional schematic of a memory device of one embodiment is depicted.

[0009] Figure 2 A cross-sectional schematic of a memory device of another embodiment is depicted.

[0010] Figures 3A to 3O A method of fabricating a memory device of one embodiment is depicted.

[0011] Figures 4A to 4E A method of fabricating a memory device of another embodiment is depicted.

[0012]

Symbol Explanation

[0013] 102: semiconductor substrate

[0014] 102S: upper semiconductor surface

[0015] 204: stack structure

[0016] 306: storage element

[0017] 306L: laterally-extending storage portion

[0018] 306V: vertically-extending storage portion

[0019] 408: channel element

[0020] 420, 432, 434: channel layer

[0021] 510: semiconductor layer

[0022] 510A: first semiconductor portion

[0023] 510AS: semiconductor sidewall surface

[0024] 510B: second semiconductor portion

[0025] 510BS: semiconductor sidewall surface

[0026] 510C: third semiconductor portion

[0027] 510CU: upper semiconductor surface

[0028] 510CS: semiconductor sidewall surface

[0029] 612: insulating layer

[0030] 612U: upper insulating surface

[0031] 612S: insulating sidewall surface

[0032] 714: source layer

[0033] 714S: electrode side wall surface

[0034] 816: insulating layer

[0035] 816B: lower insulating surface

[0036] 816S: insulating side wall surface

[0037] 918: insulating film

[0038] 918S: insulating side wall surface

[0039] 922: dielectric film

[0040] 923: air gap

[0041] 924: pad element

[0042] 926: dielectric layer

[0043] 928: conductive source element

[0044] 930: dielectric element

[0045] 1036: layer of material

[0046] 1038: opening

[0047] 1040: layer of material

[0048] 1042: stack structure

[0049] 1044: layer of material

[0050] 1046: notch

[0051] 1048: recess

[0052] 1050: oxide layer

[0053] 1052: slit

[0054] CI: interface

[0055] D1: first direction

[0056] D2: second direction

[0057] ES: electrode side wall surface

[0058] GSL, SSL, WL: gate electrode layer DETAILED DESCRIPTION

[0059] In order to make the aims, technical solutions and advantages of the present application clearer, the present application will be further described in details below with reference to specific embodiments and the accompanying drawings.

[0060] The following description is presented to enable any person skilled in the art to make and use the application. Descriptions of specific embodiments are provided only as examples. Other embodiments can be used, and structural or procedural modifications can be made without departing from the scope of the present application. The steps and structures of the embodiments are not limited to the order shown but can be performed in other orders. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims. Like reference numerals are used to indicate like elements in the figures.

[0061] Referring to FIG. 1, a cross-sectional schematic view of a memory device is shown. The memory device can include a semiconductor substrate 102, a stack structure 204, a storage element 306, a channel element 408, and a semiconductor layer 510. Figure 1 The stack structure 204 can include an insulating layer 612, a source layer 714, an insulating layer 816, a gate electrode layer SSL, a gate electrode layer GSL, a gate electrode layer WL, and an insulating film 918. The insulating layer 612 can be on the semiconductor substrate 102. The source layer 714 can be on the insulating layer 612. The insulating layer 816 can be on the source layer 714. The gate electrode layers (including the gate electrode layer SSL, the gate electrode layer GSL, and the gate electrode layer WL) and the insulating film 918 can be interleaved and stacked on the insulating layer 816. The source layer 714 and the gate electrode layers (including the gate electrode layer SSL, the gate electrode layer GSL, and the gate electrode layer WL) can be electrically isolated from each other by the insulating layer 816 and the insulating film 918.

[0062] The semiconductor layer 510 can be electrically connected between the source layer 714 and the channel element 408. The semiconductor layer 510 can include a first semiconductor portion 510A, a second semiconductor portion 510B, and a third semiconductor portion 510C. The first semiconductor portion 510A can be electrically connected between the second semiconductor portion 510B and the third semiconductor portion 510C. The second semiconductor portion 510B can be electrically connected between the first semiconductor portion 510A and the channel element 408. The third semiconductor portion 510C can be adjacent to an upper semiconductor surface 102S of the semiconductor substrate 102 and to an insulating sidewall surface 612S of the insulating layer 612.

[0063] The semiconductor layer 510 can be electrically connected between the source layer 714 and the channel element 408. The semiconductor layer 510 can include a first semiconductor portion 510A, a second semiconductor portion 510B, and a third semiconductor portion 510C. The first semiconductor portion 510A can be electrically connected between the second semiconductor portion 510B and the third semiconductor portion 510C. The second semiconductor portion 510B can be electrically connected between the first semiconductor portion 510A and the channel element 408. The third semiconductor portion 510C can be adjacent to an upper semiconductor surface 102S of the semiconductor substrate 102 and to an insulating sidewall surface 612S of the insulating layer 612.

[0064] An interface CI can be between the source layer 714 and the first semiconductor portion 510A of the semiconductor layer 510. The interface CI includes an adjoining portion between the electrode sidewall surface 714S of the source layer 714 and the semiconductor sidewall surface 510AS of the first semiconductor portion 510A. The interface CI can be a longitudinal crystalline interface. The interface CI is laterally offset inward of the insulating sidewall surface 816S of the insulating layer 816. The interface CI is laterally offset inward of the insulating sidewall surface 612S of the insulating layer 612. In the present disclosure, the term "laterally" can be a direction parallel to the first direction Dl as shown in the figures. The first direction Dl can be, for example, the X direction. The first semiconductor portion 510A of the semiconductor layer 510 can be adjoined between the lower insulating surface 816B of the insulating layer 816 and the upper insulating surface 612U of the insulating layer 612. The first semiconductor portion 510A and the third semiconductor portion 510C of the semiconductor layer 510 can be adjoined between the source layer 714 and the semiconductor substrate 102.

[0065] For example, the semiconductor sidewall surface 510AS of the first semiconductor portion 510A, the semiconductor sidewall surface 510BS of the second semiconductor portion 510B, and the semiconductor sidewall surface 510CS of the third semiconductor portion 510C are on the same side of the semiconductor layer 510. The semiconductor sidewall surface 510AS of the first semiconductor portion 510A can be laterally offset outward of the semiconductor sidewall surface 510BS of the second semiconductor portion 510B. The semiconductor sidewall surface 510AS of the first semiconductor portion 510A can be laterally offset outward of the semiconductor sidewall surface 510CS of the third semiconductor portion 510C. The semiconductor sidewall surface 510BS of the second semiconductor portion 510B can be substantially aligned with the semiconductor sidewall surface 510CS of the third semiconductor portion 510C.

[0066] As shown, the lateral dimension of the first semiconductor portion 510A can be greater than the lateral dimension of the second semiconductor portion 510B. The lateral dimension of the first semiconductor portion 510A can be greater than the lateral dimension of the third semiconductor portion 510C. In one embodiment, the lateral dimension of the second semiconductor portion 510B can be the same as the lateral dimension of the third semiconductor portion 510C.

[0067] The conductive property of the source layer 714 can be different from the conductive property of the first semiconductor portion 510A, the second semiconductor portion 510B, and the third semiconductor portion 510C. The conductivity type of the semiconductor substrate 102 can be opposite to the conductivity type of the source layer 714. In one embodiment, the semiconductor substrate 102 has a P conductivity type material. The source layer 714 has an N conductivity type material. The semiconductor layer 510 has an undoped or P type impurity doped material.

[0068] The storage element 306 can include a laterally-extending storage portion 306L and a longitudinally-extending storage portion 306V. The laterally-extending storage portion 306L is on the upper semiconductor surface 510CU of the third semiconductor portion 510C. The longitudinally-extending storage portion 306V can be on the electrode side wall surfaces ES of the gate electrode layers (including the gate electrode layers SSL, GSL, WL), the insulating side wall surfaces 918S of the insulating film 918, and the insulating side wall surfaces 816S of the insulating layer 816. In the present invention, the so-called longitudinal direction can be a direction parallel to the second direction D2 as shown in the figure. The second direction D2 can be the Z direction.

[0069] In this embodiment, the passage element 408 includes a passage layer 420 which can extend on the upper semiconductor surface 510CU of the third semiconductor portion 510C, the storage side wall surfaces and the upper storage surface of the laterally-extending storage portion 306L, and the storage side wall surfaces of the longitudinally-extending storage portion 306V.

[0070] A dielectric film 922 can be on the passage layer 420. A pad element 924 can be on the dielectric film 922 and electrically connected to the passage element 408. In this embodiment, the pad element 924 can be electrically connected to an overlying bit line contact (not shown) and to a bit line. A dielectric layer 926 can be on the stack structure 204. A conductive source element 928 can extend through the gate electrode layers SSL, GSL, WL, the insulating film 918, and the insulating layer 816. The conductive source element 928 is electrically connected to the source layer 714. The conductive source element 928 can electrically isolate the gate electrode layers SSL, GSL, WL from each other through a dielectric element 930. The source layer 714 and the first and second semiconductor portions 510A, 510B of the semiconductor layer 510 are electrically connected between the conductive source element 928 and the passage element 408.

[0071] The memory device includes 3D vertical channel NAND strings. The uppermost gate electrode layer SSL can be used as a string select line, the lowermost gate electrode layer GSL can be used as a ground select line, and the other intermediate gate electrode layers WL between the two can be used as word lines. A memory cell can be defined in a memory element 306 between a channel element 408 and a gate electrode layer WL. A NAND string includes the memory cells electrically connected in series. In one embodiment, a method of operating the memory device includes controlling formation of an inversion channel in the semiconductor layer 510 by providing a voltage to the gate electrode layer GSL, such that there is no PN junction between the source layer 714 and the semiconductor layer 510, and a current path from a bit line can flow in sequence through the pad element 924, the channel element 408, the semiconductor layer 510, the source layer 714, and out through the conductive source element 928. The source layer 714 (e.g., heavily doped N-type material) and the conductive source element 928 (e.g., metal material) provided in the vertical direction from bottom to top can have low resistive properties, thus reducing the overall resistance of the current path and improving the operating efficiency of the memory device. Current does not flow into the semiconductor substrate 102 of the opposite conductivity type (e.g., P-type). Because there is no PN junction between the source line and the semiconductor substrate 102, there is no junction capacitance. This can reduce resistance-capacitance delay (RC delay) and higher speed operation.

[0072] Please refer to Figure 2 , which shows a cross-sectional schematic view of a memory device of another embodiment. Figure 2 The memory device of Figure 1 is different from the memory device of . In this embodiment, the channel element 408 includes a channel layer 432 and a channel layer 434. The channel layer 432 can be located on the upper storage surface of the laterally extending storage portion 306L and the storage sidewall surface of the vertically extending storage portion 306V. The channel layer 434 can extend on the upper semiconductor surface 510CU of the third semiconductor portion 510C, the storage sidewall surface of the laterally extending storage portion 306L, and the channel sidewall surface of the channel layer 432. The dielectric film 922 can be on the channel layer 434.

[0073] In one embodiment, the memory device as shown in Figure 1 may be manufactured using the steps shown in Figures 3A to 3O .

[0074] Please refer to Figure 3AA semiconductor substrate 102 is provided. The semiconductor substrate 102 can include, for example, a silicon substrate, or other suitable semiconductor material. The semiconductor substrate 102 can include a first conductivity type material, for example, a material doped with a first conductivity type impurity, such as a P-type well region. A stack structure 1042 can be formed on the semiconductor substrate 102. In one embodiment, an insulating layer 612 can be formed on the semiconductor substrate 102. A source layer 714 can be formed on the insulating layer 612. The source layer 714 can include a second conductivity type material, for example, a material doped with a second conductivity type impurity. In one embodiment, the source layer 714 includes an N-type material, for example, a heavily doped N-type material. An insulating layer 816 can be formed on the source layer 714. Interleaved insulating films 918 and material layers 1036 can be formed on the insulating layer 816. The insulating layer 612, the insulating layer 816, and the insulating films 918 can include a different material than the material layers 1036. In one embodiment, the insulating layer 612, the insulating layer 816, and the insulating films 918 can include an oxide, such as silicon oxide. The material layers 1036 can include a nitride, such as silicon nitride. However, the present application is not limited to this.

[0075] Referring to Figure 3B The patterning step can be performed using a photolithography and etching process to form openings 1038 through the insulating films 918, the material layers 1036, the insulating layer 816, the source layer 714, and the insulating layer 612, and expose the semiconductor substrate 102. The semiconductor substrate 102 can act as an etch stop layer. In one embodiment, the sidewall surfaces of the layers exposed by the openings 1038 can be aligned with each other.

[0076] Referring to Figure 3C A material layer 1040 can be formed at the bottom of the openings 1038. The material layer 1040 can be formed using a deposition process. In one embodiment, the material layer 1040 can be grown using a selective epitaxy process from the electrode sidewall surfaces 714S of the source layer 714 and the upper semiconductor surface 102S of the semiconductor substrate 102 exposed by the openings 1038. In one embodiment, the material layer 1040 is not limited to the profile shown in the figure, but can include any possible profile that can be grown epitaxially from the electrode sidewall surfaces 714S and the upper semiconductor surface 102S. For example, the upper surface of the material layer 1040 can be a flat surface or a non-flat surface. In one embodiment, the material layer 1040 can be a semiconductor layer, and the material can include, for example, SiGe x However, the present application is not limited to this. In one embodiment, a thermal annealing step can be performed to, for example, eliminate voids in the material.

[0077] Referring to Figure 3DThe storage element 306 can be formed in the opening 1038 and on the upper surface of the stacked structure 1042 using a deposition method. The storage element 306 may include any charge trapping structure, such as an oxide-nitride-oxide (ONO) structure, an ONONO structure, an ONONONO structure, or an oxide-nitride-oxide-nitride-oxide (BE-SONOS) structure, etc. For example, the charge trapping layer may use nitrides such as silicon nitride, or other similar high dielectric constant materials including metal oxides, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), etc.

[0078] Please refer to Figure 3E A material layer 1044 can be formed on the memory element 306. In one embodiment, the material layer 1044 may include undoped polysilicon. However, the invention is not limited thereto, and other suitable materials may also be used for the material layer 1044.

[0079] Please refer to Figure 3F Anisotropic etching can be used to remove the bottom portion of material layer 1044 in aperture 1038 and the portion on the upper surface of stacked structure 1042, leaving the portion of material layer 1044 located on the sidewall of aperture 1038. Then, a suitable etching method can be used to remove the portion of memory element 306 not covered by material layer 1044, thereby exposing material layer 1040.

[0080] Please refer to Figure 3G It can be removed using a suitable etching method. Figure 3F Material layer 1044 is shown. In one embodiment, the etching step may be performed using a wet etching method, such as using an etching solution like NH4OH. In another embodiment, the etching step may include a standard cleaning 1 (SC1) process, which may use, for example, a cleaning solution containing water, NH3, and H2O2. However, the invention is not limited thereto.

[0081] Please refer to Figure 3H It can be removed using a suitable etching method. Figure 3G The material layer 1040 is shown. In one embodiment, the selected etching method may be selective for etching the material layer 1040, while not substantially etching other components, such as the source layer 714, the semiconductor substrate 102, etc.

[0082] Please refer to Figure 3I The source layer 714 can be etched back to form a notch 1046 communicating with the opening 1038, and the electrode sidewall surface of the .... Figure 3HThe positions of the insulating sidewall surfaces 816S and 612S of the insulating layer 816 and 612S, respectively, are laterally shifted into the source layer 714 to become the electrode sidewall surface 714S. The electrode sidewall surface 714S is offset inside the insulating sidewall surface 816S of the insulating layer 816 and inside the insulating sidewall surface 612S of the insulating layer 612. In one embodiment, the lateral dimension of the portion of the source layer 714 etched away (or the lateral offset dimension of the electrode sidewall surface 714S, or the lateral dimension of the notch 1046) can be, for example, 5 nm to 50 nm, such as 20 nm, but the invention is not limited thereto. The selected etch-back method can selectively etch the source layer 714 while substantially not etching other components, such as the insulating layers 816 and 612. In one embodiment, the etch-back can be performed using a wet etching method, such as using an etching solution like NH4OH. In one embodiment, the back etching step may include a standard cleaning 1 (SC1) process, which may, for example, use a cleaning solution containing water, NH3, and H2O2.

[0083] Please refer to Figure 3J A semiconductor layer 510 can be formed at the bottom of the opening 1038 and in the recess 1046. The semiconductor layer 510 may include silicon, such as polycrystalline silicon or monocrystalline silicon. The semiconductor layer 510 can be formed by deposition. In one embodiment, a selective epitaxial growth method can be used to grow a semiconductor layer 510 adjacent to the source layer 714, the semiconductor substrate 102, and the memory element 306 from the electrode sidewall surface 714S of the source layer 714 exposing the recess 1046 and the upper semiconductor surface 102S of the semiconductor substrate 102. The semiconductor layer 510 and the source layer 714 may have an interface CI, and the semiconductor layer 510 and the semiconductor substrate 102 may also have an interface, such as a crystal interface. In the embodiments, the semiconductor layer 510 is not limited to the contour shown in the figure, but may include any possible contour epitaxially grown from the electrode sidewall surface 714S and the upper semiconductor surface 102S. For example, the upper surface of the semiconductor layer 510 may be a flat surface or a non-flat surface.

[0084] In one embodiment, the semiconductor layer 510 and the source layer 714 adjacent thereto are formed with different doping states. For example, the semiconductor layer 510 is formed of an undoped semiconductor material or a P-type impurity-doped semiconductor material, and the source layer 714 adjacent to the semiconductor layer 510 is formed of an N-type impurity-doped semiconductor material, such as a heavily doped N-type semiconductor material. In this embodiment, the semiconductor layer 510 is formed after the memory element 306, and thus does not undergo the high-temperature process used to form the memory element 306, which can limit diffusion of the N-type doping impurities of the source layer 714 into the semiconductor layer 510. In addition, the first semiconductor portion 510A of the semiconductor layer 510 formed in the portion within the recess 1046 (i.e., the portion extending between the upper insulating surface 612U of the insulating layer 612 and the lower insulating surface 816B of the insulating layer 816, or the portion extending beyond the insulating sidewall surface 816S of the insulating layer 816 and the insulating sidewall surface 612S of the insulating layer 612) can also provide an acceptable diffusion range of the N-type impurities from the source layer 714, thereby avoiding the problem of excessive diffusion of the N-type impurities (e.g., diffusion beyond the insulating sidewall surface 816S of the insulating layer 816 / the insulating sidewall surface 612S of the insulating layer 612) that can degrade the operational efficiency of the memory device.

[0085] Referring to Figure 3K The channel layer 420 can be formed on the memory element 306, the semiconductor layer 510, and the upper surface of the stack structure 1042. In one embodiment, the channel layer 420 includes an undoped polysilicon material. However, the present application is not limited thereto, and other suitable materials can also be used for the channel layer 420.

[0086] Referring to Figure 3LA dielectric film 922 can be formed in the opening 1038. The dielectric film 922 can be formed using suitable deposition methods. The dielectric film 922 can be, for example, a non-conformal film of material and have an air gap 923 therein. In one embodiment, the dielectric film 922 can comprise an oxide such as silicon oxide, but is not limited thereto, and other suitable dielectric materials can be used. The dielectric film 922 on the upper surface of the stack structure 1042 can be removed using a chemical mechanical polishing process. The chemical mechanical polishing process can stop on the channel layer 420. Then, a recess can be formed in the dielectric film 922 and the channel layer 420 by a back etching step. A pad element 924 can be formed in the recess. In one embodiment, the pad element 924 can comprise a conductive material or a semiconductor material such as an N-type semiconductor material, for example, a heavily doped N-type semiconductor material. The pad element 924 can be formed using deposition methods and the deposited material on the upper surface of the stack structure 1042 can be removed using a chemical mechanical polishing process. The chemical mechanical polishing step can stop on the topmost insulating film 918 (used as a hard mask) in the stack structure 1042. In one embodiment, the pad element 924 will provide a landing area for an overlying bit line contact and be electrically connected to the bit line.

[0087] Referring to Figure 3M A dielectric layer 926 can be formed. The dielectric layer 926 can be used as a cap layer to protect the pad element 924. In one embodiment, the dielectric layer 926 can comprise an insulating material including an oxide such as silicon oxide or other suitable material. A recess 1048 can be formed through the dielectric layer 926, the insulating film 918, the material layer 1036 and the insulating layer 816 and expose the source layer 714 using photolithography and etching processes. In one embodiment, the etching step can use the source layer 714 as an etch stop layer. Then, an oxidation step can be performed on the source layer 714 exposed by the recess 1048 to form an oxide layer 1050 on the upper electrode surface of the source layer 714.

[0088] Referring to Figure 3N An etching step can be performed to remove the material layer 1036 exposed by the recess 1048 as shown in Figure 3M to form a slit 1052. The slit 1052 can expose the upper / lower insulating surfaces of the insulating film 918, the upper insulating surface of the insulating layer 816 and the storage sidewall surfaces of the storage element 306. In one embodiment, the structure as shown in Figure 3M can be immersed in an etching solution (e.g., containing phosphoric acid (H3PO4) or the like) that is selective to the material layer 1036 (e.g., silicon nitride) to remove the material layer 1036.

[0089] Referring to Figure 3OThe gate electrode layers SSL, GSL, and WL can fill the slots 1052. In one embodiment, a dielectric film (not shown) can be formed on the exposed device surfaces in the slots 1052 prior to forming the gate electrode layers SSL, GSL, and WL, and then the gate electrode layers SSL, GSL, and WL can be formed on the dielectric film and fill the slots 1052. The dielectric film can include, for example, a high-k material, or other suitable dielectric material. In one embodiment, the gate electrode material / dielectric material formed in the recesses 1048 and the oxide layer 1050 can be removed using a suitable etching process.

[0090] Referring back to Figure 1 A dielectric element 930 can be formed on the exposed device sidewall surfaces in the recesses 1048. In one embodiment, the dielectric element 930 can be formed by a deposition process that forms a dielectric film in the recesses 1048 and on the upper surface of the dielectric layer 926, and then a non-isotropic etching process can be used to remove portions of the dielectric film on the bottom of the recesses 1048 and on the upper surface of the dielectric layer 926, leaving the dielectric film in the recesses 1048 as the dielectric element 930. In one embodiment, the dielectric element 930 can include an oxide such as silicon oxide, although the application is not limited in this respect. A conductive source element 928 can then be formed to fill the recesses 1048 and electrically connect to the source layer 714. In one embodiment, the conductive source element 928 can be formed by a suitable deposition process that forms a conductive material in the recesses 1048 and on the upper surface of the dielectric layer 926, and then a chemical mechanical polishing process can be used to remove the conductive material on the upper surface of the dielectric layer 926. The conductive material can include an alloy or a metal such as titanium nitride (TiN) or tungsten (W), among others.

[0091] In another embodiment, a memory device as shown in Figure 2 may be fabricated using a process flow as shown in Figures 4A to 4E . For example, after performing the fabrication process described with reference to Figures 3A to 3B , the steps shown in Figure 4A may be performed.

[0092] Referring to Figure 4A , a back etching step can be performed on the source layer 714 to form notches 1046 that communicate with the openings 1038, and to cause the electrode sidewall surfaces of the source layer 714 to substantially align with the locations of the insulating sidewall surfaces 816S of the insulating layer 816 and the insulating sidewall surfaces 612S of the insulating layer 612, and to laterally shift inwardly into the source layer 714 to become the electrode sidewall surfaces 714S.

[0093] Referring to Figure 4BA semiconductor layer 510 can be formed in the bottom of the opening 1038 and in the recess 1046. The semiconductor layer 510 can comprise silicon, such as polysilicon, monocrystalline silicon, etc. The semiconductor layer 510 can be formed using deposition. In one embodiment, the semiconductor layer 510 can be grown between the source layer 714 and the semiconductor substrate 102 adjacent to the electrode sidewall surface 714S of the source layer 714 and the upper semiconductor surface 102S of the semiconductor substrate 102 using a selective epitaxy process. In embodiments, the semiconductor layer 510 is not limited to the profile shown, but can include any possible profile that can be grown epitaxially from the electrode sidewall surface 714S and the upper semiconductor surface 102S. For example, the upper surface of the semiconductor layer 510 can be a flat surface or a non-flat surface. In one embodiment, a thermal anneal step can be performed to, for example, eliminate voids in the material.

[0094] Referring to Figure 4C A memory element 306 can be formed in the opening 1038 and on the upper surface of the stack structure 1042. A channel layer 432 can then be formed on the memory element 306. The channel layer 432 can comprise, for example, undoped polysilicon formed using a deposition process, although the application is not limited in this regard.

[0095] Referring to Figure 4D The channel layer 432 can be removed from the bottom of the opening 1038 and from the upper surface of the stack structure 1042 using an anisotropic etch, leaving the channel layer 432 on the sidewalls of the opening 1038. The memory element 306 can then be removed from the portions of the memory element 306 not covered by the channel layer 432 using a suitable etch, thereby exposing the semiconductor layer 510.

[0096] Referring to Figure 4E A channel layer 434 can be formed in the opening 1038 and on the upper surface of the stack structure 1042. The channel layer 434 can comprise, for example, undoped polysilicon formed using a deposition process, although the application is not limited in this regard.

[0097] The process can then continue similarly to that described with reference to Figures 3L to 3O and Figure 1 The fabrication concept forms a dielectric film 922, a pad element 924, a dielectric layer 926, a gate electrode layer SSL, a gate electrode layer GSL, a gate electrode layer WL, a dielectric element 930, and a conductive source element 928 to form a memory device as shown in Figure 2 .

[0098] The memory device of the application is not limited to the fabrication method described above and can be adapted as appropriate. In one embodiment, for example, the process can continue with reference to Figure 3DAfter the formation of the memory element 306, portions of the memory element 306 at the bottom of the opening 1038 and on the upper surface of the stack structure 1042 are removed using a non-isotropic etching method, and the steps of forming / removing the material layer 1044 described with reference to Figure 3E With Figure 3F the formation / removal steps of the material layer 1044 described with reference to Figure 3G and the related manufacturing steps thereafter, a memory device similar to that shown in Figure 1 may also be formed.

[0099] The above-described specific embodiments have further detailed the purposes, technical solutions and beneficial effects of the present application, and it should be understood that the above-described is only a specific embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A memory device, comprising: A stacked structure, comprising: One source pole layer; A first insulating layer is disposed on the source layer; and Multiple gate electrode layers are disposed on the first insulating layer; A storage element on the electrode sidewall surface of the gate electrode layers; A channel element, wherein a plurality of memory cells are defined in the memory element between the channel element and the gate electrode layers; and A semiconductor layer is electrically connected between the source layer and the channel element. The semiconductor layer and the source layer have an interface that is laterally offset inside an insulating sidewall surface of the first insulating layer. The semiconductor layer includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion is electrically connected between the second semiconductor portion and the third semiconductor portion. A semiconductor sidewall surface of the first semiconductor portion is laterally offset outside a semiconductor sidewall surface of the second semiconductor portion, and the semiconductor sidewall surface of the first semiconductor portion is laterally offset outside a semiconductor sidewall surface of the third semiconductor portion.

2. The memory device of claim 1, wherein the semiconductor layer is adjacent to a lower insulating surface of the first insulating layer.

3. The memory device of claim 1, wherein the stacked structure further comprises a second insulating layer, wherein the source layer is between the first insulating layer and the second insulating layer, and the interface is laterally offset inside an insulating sidewall surface of the second insulating layer.

4. A memory device, comprising: A stacked structure includes a source layer and a plurality of gate electrode layers, the gate electrode layers being on the same side of the source layer; A storage element on the electrode sidewall surface of the gate electrode layers; A channel element, wherein a plurality of memory cells are defined in the memory element between the channel element and the gate electrode layers; and A semiconductor layer electrically connected between the channel element and the source layer includes a first semiconductor portion and a second semiconductor portion, the second semiconductor portion being electrically connected between the first semiconductor portion and the channel element, and a semiconductor sidewall surface of the first semiconductor portion being laterally offset to the outside of a semiconductor sidewall surface of the second semiconductor portion; the semiconductor layer also includes a third semiconductor portion, wherein the first semiconductor portion is electrically connected between the second semiconductor portion and the third semiconductor portion, and the semiconductor sidewall surface of the first semiconductor portion is laterally offset to the outside of a semiconductor sidewall surface of the third semiconductor portion.

5. A memory device, comprising: A stacked structure includes a source layer and a plurality of gate electrode layers, the gate electrode layers being on the same side of the source layer; A storage element on the electrode sidewall surface of the gate electrode layers; A channel element, wherein a plurality of memory cells are defined in the memory element between the channel element and the gate electrode layers; and A semiconductor layer includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion, wherein the first semiconductor portion is electrically connected between the second semiconductor portion and the third semiconductor portion, a semiconductor sidewall surface of the first semiconductor portion is laterally offset to the outside of a semiconductor sidewall surface of the second semiconductor portion, the semiconductor sidewall surface of the first semiconductor portion is laterally offset to the outside of a semiconductor sidewall surface of the third semiconductor portion, the second semiconductor portion is electrically connected between the first semiconductor portion and the channel element, wherein a lateral dimension of the first semiconductor portion is larger than a lateral dimension of the second semiconductor portion.

6. The memory device of claim 5, wherein the semiconductor layer further comprises a third semiconductor portion, wherein the first semiconductor portion is electrically connected between the second semiconductor portion and the third semiconductor portion, and the lateral dimension of the first semiconductor portion is larger than a lateral dimension of the third semiconductor portion.

7. The memory device according to any one of claims 1, 4 or 5, further comprising a semiconductor substrate, wherein the semiconductor layer is adjacent to an upper semiconductor surface of the semiconductor substrate, wherein the conductivity type of the semiconductor substrate is opposite to the conductivity type of the source layer.

8. The memory device according to any one of claims 1, 4 or 5, further comprising a power supply element extending in the stacked structure, wherein the semiconductor layer and the source layer are electrically connected between the power supply element and the channel element.

9. The memory device according to claim 4 or 5, wherein the conductivity of the source layer is different from the conductivity of the first semiconductor portion and the second semiconductor portion.

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