Three-dimensional ferroelectric memory array including integrated gate selector and method of forming the same

Abstract

The present invention discloses a ferroelectric field effect transistor (FeFET), which includes: a semiconductor channel; a source region, which contacts one end of the semiconductor channel; a drain region, which contacts the second end of the semiconductor channel; a gate electrode; a ferroelectric gate dielectric layer, which is located between the semiconductor channel and the gate electrode; and a bidirectional selector material layer, which is located between the gate electrode and the ferroelectric gate dielectric layer.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. non-provisional patent application serial number 16 / 694,340, filed on November 25, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to a three-dimensional ferroelectric memory array including an integrated gate selector and a method of manufacturing the same. Background Art

[0004] Ferroelectric materials are materials that show spontaneous polarization of charge in the absence of an applied electric field. In the minimum energy state, the net polarization P of the charge within the ferroelectric material is non-zero. Therefore, the material undergoes spontaneous ferroelectric polarization, and the ferroelectric material accumulates surface charges of opposite polarity types on two opposing surfaces. The polarization P of the ferroelectric material shows hysteresis as a function of the voltage V applied across the ferroelectric material. The product of the remnant polarization and the coercive field of the ferroelectric material is a measure used to characterize the effectiveness of the ferroelectric material.

[0005] A ferroelectric memory device is a memory device that includes a ferroelectric material for storing information. The ferroelectric material acts as a memory material for the memory device. Depending on the polarity of the electric field applied to the ferroelectric material, the dipole moment of the ferroelectric material is programmed in two different orientations (e.g., "up" or "down" polarization positions, based on the atomic positions in the lattice, such as oxygen atom positions and / or metal atom positions) to store information in the ferroelectric material. The different orientations of the dipole moment of the ferroelectric material can be detected by the electric field generated by the dipole moment of the ferroelectric material. For example, the orientation of the dipole moment can be detected by measuring the current flowing through a semiconductor channel disposed adjacent to the ferroelectric material in a field effect transistor ferroelectric memory device. Summary of the invention

[0006] According to one aspect of the present disclosure, a ferroelectric field effect transistor (FeFET) includes: a semiconductor channel; a source region, the source region contacts one end of the semiconductor channel; a drain region, the drain region contacts a second end of the semiconductor channel; a gate electrode; a ferroelectric gate dielectric layer, the ferroelectric gate dielectric layer is located between the semiconductor channel and the gate electrode; and a bidirectional selector material layer, the bidirectional selector material layer is located between the gate electrode and the ferroelectric gate dielectric layer.

[0007] According to another aspect of the present disclosure, a method for forming a semiconductor device is provided, the method comprising: forming a channel level insulating layer above a substrate; forming a vertical stack of semiconductor channels at the level of the channel level insulating layer; forming a stack directly on the vertical stack of semiconductor channels, the stack comprising a ferroelectric gate dielectric layer, a bidirectional selector material layer and a gate electrode from one side to the other; and providing a source region on one end of each semiconductor channel in the semiconductor channel and providing a drain region on the other end of each semiconductor channel in the semiconductor channel, wherein each of the semiconductor channel, the source region and the drain region contacts the ferroelectric gate dielectric layer, and each channel layer insulating layer in the channel level insulating layer contacts a corresponding one of the source regions and a corresponding one of the drain regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic vertical cross-sectional view of a first exemplary structure after forming at least one peripheral device and a semiconductor material layer according to the first embodiment of the present disclosure.

[0009] Figure 2 is a schematic vertical cross-sectional view of a first exemplary structure after forming alternating stacks of insulating layers and sacrificial material layers according to the first embodiment of the present disclosure.

[0010] Figure 3 is a schematic vertical cross-sectional view of a first exemplary structure after forming a stepped terrace and a backward stepped dielectric material portion according to the first embodiment of the present disclosure.

[0011] Figure 4A is a schematic vertical cross-sectional view of a first exemplary structure after forming a storage opening and a support opening according to the first embodiment of the present disclosure.

[0012] Figure 4B for Figure 4A A top view of the first exemplary structure of FIG. The vertical plane A-A' is Figure 4A The plane of the section.

[0013] Figure 5 is a schematic vertical cross-sectional view of the first exemplary structure after the channel-level insulating layer is laterally recessed selectively with respect to the inter-transistor-level insulating layer and the sacrificial material layer according to the first embodiment of the present disclosure.

[0014] Figure 6 is a schematic vertical cross-sectional view of a first exemplary structure after forming a semiconductor channel having a tubular configuration according to the first embodiment of the present disclosure.

[0015] Fig. 7Ais a schematic vertical cross-sectional view of a first exemplary structure after forming a layer stack including a gate dielectric layer, a selector material layer, and a word line in each memory opening from one side to the other according to the first embodiment of the present disclosure.

[0016] Figure 7B for Fig. 7A A top view of the first exemplary structure of FIG. The vertical plane A-A' is Fig. 7A The plane of the section.

[0017] Fig. 8A is a schematic vertical cross-sectional view of the first exemplary structure after forming a contact-level dielectric layer and backside trenches according to the first embodiment of the present disclosure.

[0018] Figure 8B for Fig. 8A A partial perspective top view of the first exemplary structure. The vertical plane A-A' is Fig. 8A A schematic vertical cross-sectional view of a plane.

[0019] Fig. 9 is a schematic vertical cross-sectional view of a first exemplary structure after forming a backside recess according to the first embodiment of the present disclosure.

[0020] Fig.10 is a schematic vertical cross-sectional view of a first exemplary structure after forming a doped semiconductor layer according to the first embodiment of the present disclosure.

[0021] Fig.11 is a schematic vertical cross-sectional view of the first exemplary structure after laterally recessing the doped semiconductor layer according to the first embodiment of the present disclosure.

[0022] Fig.12 is a schematic vertical cross-sectional view of a first exemplary structure after conformal deposition of a metallic material according to a first embodiment of the present disclosure.

[0023] Fig.13A is a schematic vertical cross-sectional view of the first exemplary structure after removing metal material from the backside trench and from above the contact-level dielectric layer according to the first embodiment of the present disclosure.

[0024] Fig. 13B for Fig.13A A partial perspective top view of the first exemplary structure. The vertical plane A-A' is Fig.13A A schematic vertical cross-sectional view of a plane.

[0025] Fig.14 is a schematic vertical cross-sectional view of the first exemplary structure after forming a dielectric trench fill structure according to the first embodiment of the present disclosure.

[0026] Fig.15A is a schematic vertical cross-sectional view of a first exemplary structure after forming a contact via structure according to the first embodiment of the present disclosure.

[0027] Fig. 15B for Fig.15A A top view of the first exemplary structure of FIG. The vertical plane A-A' is Fig.15A A schematic vertical cross-sectional view of a plane.

[0028] Fig.16 is a schematic vertical cross-sectional view of a second exemplary structure after forming an insulating layer, a doped semiconductor layer, and a sacrificial material layer according to the second embodiment of the present disclosure.

[0029] Fig.17 is a schematic vertical cross-sectional view of a second exemplary structure after forming a stepped terrace and a backward stepped dielectric material portion according to a second embodiment of the present disclosure.

[0030] Fig.18 is a schematic vertical cross-sectional view of a second exemplary structure after forming a storage opening and a support opening according to the second embodiment of the present disclosure.

[0031] Fig.19 is a schematic vertical cross-sectional view of a second exemplary structure after forming a semiconductor channel having a tubular configuration according to the second embodiment of the present disclosure.

[0032] Fig. 20 is a schematic vertical cross-sectional view of a second exemplary structure after forming a layer stack including a gate dielectric layer, a selector material layer, and a word line in each memory opening from one side to the other according to the second embodiment of the present disclosure.

[0033] Fig.21 is a schematic vertical cross-sectional view of a second exemplary structure after forming a contact-level dielectric layer and backside trenches according to the second embodiment of the present disclosure.

[0034] Fig. 22 is a schematic vertical cross-sectional view of a second exemplary structure after forming a backside recess according to a second embodiment of the present disclosure.

[0035] Fig.23 is a schematic vertical cross-sectional view of a second exemplary structure after forming a metal material layer according to the second embodiment of the present disclosure.

[0036] Fig.24 is a schematic vertical cross-sectional view of a second exemplary structure after forming a dielectric trench filling structure and a contact via structure according to the second embodiment of the present disclosure.

[0037] Fig.25 is a schematic circuit diagram of a three-dimensional array of memory elements according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] As discussed above, the present disclosure is directed to a three-dimensional ferroelectric memory array including an integrated gate selector and a method of manufacturing the same, various aspects of which are described below.

[0039] The drawings are not drawn to scale. Multiple instances of elements can be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of elements. Serial numbers such as "first", "second" and "third" are only used to identify similar elements, and different serial numbers can be used throughout the specification and claims of the present disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements that provide an edge or surface shared by the elements. As used herein, a first element "on" a second element can be located on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0040] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0041] As used herein, a first surface and a second surface "vertically coincide" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from the vertical direction at an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or a substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0042] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed on a single substrate such as a semiconductor wafer without a substrate intervening therebetween. The term "monolithic" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory levels before bonding, but since the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays.

[0043] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board by a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded therein, for example, by flip chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of planes therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some restrictions. In the case where the die is a memory die (i.e., a die including a memory element), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple storage blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

[0044] refer to Figure 1, shows a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 9, which may be a semiconductor substrate. The substrate may include a substrate semiconductor layer 9 and an optional semiconductor material layer. The substrate semiconductor layer 9 may be a semiconductor wafer or a semiconductor material layer, and may include at least one elemental semiconductor material (e.g., a single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate may have a main surface 7, which may be, for example, the topmost surface of the substrate semiconductor layer 9. The main surface 7 may be a semiconductor surface. In one embodiment, the main surface 7 may be a single crystal semiconductor surface, such as a single crystal semiconductor surface.

[0045] As used herein, "semiconductor material" refers to a semiconductor material having a -5 S / m to 1.0×10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m, and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 5 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 S / m. As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state) (i.e., having a conductivity greater than 1.0×10 5 S / m) of a semiconductor material. A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 5S / m in the range of 1000 s / m. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Therefore, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. Doped semiconductor materials can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that includes at least one metal element. All conductivity measurements are performed under standard conditions.

[0046] In one embodiment, at least one semiconductor device 700 of a peripheral circuit may be formed on a portion of the substrate semiconductor layer 9. The at least one semiconductor device may include, for example, a field effect transistor. If the at least one semiconductor device is used for a peripheral circuit, the at least one semiconductor device is referred to herein as at least one peripheral device. For example, at least one shallow trench isolation structure 720 may be formed by etching a portion of the substrate semiconductor layer 9 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer may be formed over the substrate semiconductor layer 9, and may then be patterned to form at least one gate structure (750, 752, 754, 758), each of which may include a gate dielectric 750, a gate electrode (752, 754), and a gate cap dielectric 758. The gate electrode (752, 754) may include a stack of a first gate electrode portion 752 and a second gate electrode portion 754. At least one gate spacer 756 may be formed around the at least one gate structure (750, 752, 754, 758) by depositing and anisotropically etching a dielectric liner. An active region 730 may be formed in the upper portion of the substrate semiconductor layer 9, for example, by introducing electrical dopants using at least one gate structure (750, 752, 754, 758) as a mask structure. Additional masks may be used as needed. The active region 730 may include a source region and a drain region of a field effect transistor. A first dielectric liner 761 and a second dielectric liner 762 may be optionally formed. Each of the first dielectric liner and the second dielectric liner (761, 762) may include a silicon oxide layer, a silicon nitride layer, and / or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide and non-stoichiometric silicon oxide having more or less than two oxygen atoms for each silicon atom. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner 761 may be a silicon oxide layer, and the second dielectric liner 762 may be a silicon nitride layer. At least one semiconductor device of the peripheral circuit may include a driver circuit of a memory device to be formed subsequently.

[0047] A dielectric material such as silicon oxide may be deposited over at least one semiconductor device and may then be planarized to form a planarized dielectric layer 770. In one embodiment, the planarized top surface of the planarized dielectric layer 770 may be coplanar with the top surface of the dielectric liner (761, 762). Subsequently, the planarized dielectric layer 770 and the dielectric liner (761, 762) may be removed from a certain area to physically expose the top surface of the substrate semiconductor layer 9. As used herein, a surface is "physically exposed" if the surface is in physical contact with a vacuum or a gaseous material (such as air).

[0048] A bottom insulating layer 31 may be formed over the top surface 7 of the substrate 9 by depositing an insulating material, such as silicon oxide, before, during, or after forming the at least one semiconductor device 700 .

[0049] The region (i.e., area) of at least one semiconductor device 700 is referred to herein as the peripheral device region 200. The region in which the memory array is subsequently formed is referred to herein as the memory array region 100. A staircase region 300 for subsequently forming a stepped platform of a conductive layer may be provided between the memory array region 100 and the peripheral device region 200. In an alternative embodiment, at least one semiconductor device 700 is formed below the memory array region 100 in a CMOS array under ("CUA") configuration. In this case, the peripheral device region 200 may be omitted or used in conjunction with the CUA configuration. In another alternative embodiment, at least one semiconductor device 700 may be formed on a separate substrate and then bonded to the substrate 9 containing the memory array region 100.

[0050] refer to Figure 2 , a material layer sequence including two or more repeating bodies of a unit layer stack (42, 32A, 42, 32B) may be formed above the bottom insulating layer 31. The unit layer stack may include, from bottom to top, a first instance of a sacrificial material layer 42, a channel-level insulating layer 32A, a second instance of a sacrificial material layer 42, and an inter-transistor-level insulating layer 32B. The channel-level insulating layer 32A and the inter-transistor-level insulating layer 32B are collectively referred to herein as insulating layers 32.

[0051] Thus, an alternating plurality of insulating layers 32 and sacrificial material layers 42 are provided. As used herein, an alternating plurality of first and second elements refers to a structure in which instances of the first element and instances of the second element are alternating. In this case, the insulating layers 32 and sacrificial material layers 42 are alternating within the alternating plurality of insulating layers 32 and sacrificial material layers. The alternating plurality of insulating layers 32 and sacrificial material layers 42 are referred to herein as alternating stacks (32, 42).

[0052] The channel-level insulating layer 32A includes a first insulating material. In one embodiment, the first insulating material may include a doped silicate glass material, such as borosilicate glass (BSG), borophosphosilicate glass (BPSG), or fluorosilicate glass or an organic silicate glass material. The first insulating material may have a higher etching rate in 100:1 diluted hydrofluoric acid than undoped silicate glass. In one embodiment, the etching rate of the doped silicate glass material or the combination of organic silicate glass materials in the channel-level insulating layer 32A in 100:1 diluted hydrofluoric acid may be at least 3 times and / or at least 10 times greater than the etching rate of undoped silicate glass in 100:1 diluted hydrofluoric acid. The thickness of each channel-level insulating layer 32A may be in the range of 10nm to 60nm, but smaller and larger thicknesses may also be used.

[0053] The inter-transistor level insulating layer 32B includes a second insulating material. In one embodiment, the second insulating material may include a silicate glass material having a different composition than the dielectric material of the channel level insulating layer 32A. In one embodiment, the second insulating material may include undoped silicate glass (i.e., undoped silicon oxide, such as silicon dioxide). In one embodiment, the first insulating material of the channel level insulating layer 32A may have an etching rate in a 100:1 diluted hydrofluoric acid solution at 20 degrees Celsius that is at least three times the etching rate of the silicate glass material of the inter-transistor level insulating layer 32B in a 100:1 diluted hydrofluoric acid solution at 20 degrees Celsius. The thickness of each inter-transistor level insulating layer 32B may be in the range of 10 nm to 60 nm, but smaller and larger thicknesses may also be used.

[0054] The sacrificial material layer 42 includes a sacrificial material that is selectively removable for the material of the insulating layer 32. Generally speaking, the material of the sacrificial material layer 42 is a sacrificial material that is selectively removable for the material of the channel level insulating layer 32A and for the material of the inter-transistor level insulating layer 32B. As used herein, if the removal process removes the first material at a rate at least twice the removal rate of the second material, the removal of the first material is "selective" for the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material. For example, the sacrificial material layer 42 may include silicon nitride, amorphous silicon, polycrystalline silicon, or a silicon-germanium alloy. In one embodiment, the sacrificial material layer 42 includes silicon nitride and / or is substantially composed of silicon nitride. The thickness of each sacrificial material layer 42 may be in the range of 15nm to 60nm, but smaller and larger thicknesses may also be used.

[0055] The channel-level insulating layers 32A are a first subset of insulating layers 32 on which vertical semiconductor channels are subsequently formed. The inter-transistor-level insulating layers 32B are a second subset of insulating layers 32 disposed between vertically adjacent pairs of vertical field effect transistors.

[0056] In the illustrated example, the alternating stack (32, 42) of insulating layers 32 and sacrificial material layers 42 may begin with a bottommost sacrificial layer 42, which is located below the bottommost channel-level insulating layer 32A, and may terminate with a topmost sacrificial layer 42, which overlies the topmost channel-level insulating layer 32A. However, an alternative bottommost layer and / or an alternative topmost layer may be used for the alternating stack (32, 42). The number of channel-level insulating layers 32A in the alternating stack (32, 42) may be in the range of 2 to 1024, typically 8 to 256, but a greater number of repeating bodies may also be used. In one embodiment, the alternating stack (32, 42) may include multiple repeating bodies of the unit layer stack (42, 32A, 42, 43B) to provide a periodic structure that repeats along the vertical direction.

[0057] An insulating capping layer 70 may be formed over the alternating stack (32, 42). The insulating capping layer 70 includes a dielectric material different from the material of the sacrificial material layer 42. In one embodiment, the insulating capping layer 70 may include a dielectric material that may be used for the insulating layer 32 as described above. The insulating capping layer 70 may have a greater thickness than each insulating layer 32. The insulating capping layer 70 may be deposited by, for example, chemical vapor deposition. In one embodiment, the insulating capping layer 70 may be a silicon oxide layer.

[0058] Generally speaking, the group of all insulating layers 32 within the alternating stack (32, 42) includes a vertical alternating sequence of channel-level insulating layers 32A and inter-transistor-level insulating layers 32B. In other words, if all insulating layers 32 are selected from the alternating stack (32, 42), the insulating layers 32 include a vertical alternating sequence of channel-level insulating layers 32A and inter-transistor-level insulating layers 32B. Each instance of the channel-level insulating layer 32A is formed as a horizontally extended layer having a corresponding top surface and a corresponding bottom surface, and each instance of the inter-transistor-level insulating layer 32B is formed as a horizontally extended layer having a corresponding top surface and a corresponding bottom surface. In one embodiment, each sacrificial material layer 42 except the bottommost sacrificial material layer in the sacrificial material layer 42 and except the topmost sacrificial material layer in the sacrificial material layer 42 contacts the corresponding overlying insulating layer in the insulating layer 32 and the corresponding underlying insulating layer in the insulating layer 32.

[0059] refer to Figure 3, forming a stepped surface at a peripheral region of the alternating stack (32, 42), which peripheral region is referred to herein as a platform region. As used herein, "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface, and adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, and a portion of the alternating stack (32, 42) is removed from the volume by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0060] A platform area is formed in the staircase area 300, which is located between the memory array area 100 and the peripheral device area 200, and the peripheral device area contains at least one semiconductor device for a peripheral circuit. The stepped cavity may have various stepped surfaces so that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the substrate 9. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the cavity depth by one or more levels, and the second type of etching process laterally extending the area to be vertically etched in the subsequent etching process of the first type. As used herein, a "level" of a structure including a plurality of alternating levels is defined as the relative position of a pair of first material layers and a second material layer within the structure.

[0061] Each sacrificial material layer 42 except a topmost sacrificial material layer 42 in the alternating stack (32, 42) extends laterally further than any overlying sacrificial material layer 42 in the alternating stack (32, 42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32, 42) that extend continuously from a bottommost layer in the alternating stack (32, 42) to a topmost layer in the alternating stack (32, 42).

[0062] Each vertical step of the stepped surface may have a height of one or more pairs of insulating layers 32 and sacrificial material layers. In one embodiment, each vertical step may have a height of a single pair of insulating layers 32 and sacrificial material layers 42. In another embodiment, multiple "columns" of steps may be formed along the first horizontal direction hd1, so that each vertical step has a height of multiple pairs of insulating layers 32 and sacrificial material layers 42, and the number of columns may be at least the number of the multiple pairs. Each column of stairs may be vertically offset from each other, so that each of the sacrificial material layers 42 has a physically exposed top surface in the stairs of the corresponding column. In an exemplary example, two columns of stairs are formed for each block of the memory stack structure to be subsequently formed, so that one column of stairs provides a physically exposed top surface for odd-numbered sacrificial material layers 42 (as counted from the bottom) and the other column of stairs provides a physically exposed top surface for even-numbered sacrificial material layers (as counted from the bottom). A configuration of three, four, or more columns of stairs with a corresponding set of vertically offset physically exposed surfaces of sacrificial material layers 42 may also be adopted. Each sacrificial material layer 42 has a greater lateral extent than any covering sacrificial material layer 42 in at least one direction, such that each physically exposed surface of any sacrificial material layer 42 has no overhang. In one embodiment, the vertical steps within each column of steps may be arranged along a first horizontal direction hd1, and the columns of steps may be arranged along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1 may be perpendicular to a boundary between the memory array region 100 and the staircase region 300.

[0063] A backward stepped dielectric material portion 65 (i.e., an insulating filling material portion) may be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from above the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the backward stepped dielectric material portion 65. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the backward stepped dielectric material portion 65, the silicon oxide of the backward stepped dielectric material portion 65 may be doped with a dopant or may not be doped with a dopant, such as B, P, and / or F.

[0064] refer to Figure 4A and Figure 4BA photolithographic material stack (not shown) including at least a photoresist layer may be formed over the insulating cap layer 70 and the backward stepped dielectric material portion 65, and may be photolithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the staircase region 300. The pattern in the photolithographic material stack may be transferred through the insulating cap layer 70 or the backward stepped dielectric material portion 65 and through the alternating stack (32, 42) by at least one anisotropic etching using the patterned photolithographic material stack as an etching mask. Portions of the alternating stack (32, 42) below the openings in the patterned photolithographic material stack are etched to form memory openings 49 and support openings 19. As used herein, a "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed. As used herein, a "support opening" refers to a structure in which a support structure (such as a support column structure) that mechanically supports other elements is subsequently formed. Memory opening 49 is formed through insulating capping layer 70 and the entirety of alternating stacks (32, 42) in memory array region 100. Support opening 19 is formed through rearward stepped dielectric material portion 65 and portions of alternating stacks (32, 42) below the stepped surface in staircase region 300.

[0065] The memory opening 49 extends through the entirety of the alternating stack (32, 42). The support opening 19 extends through a subset of the layers within the alternating stack (32, 42). The chemistry of the anisotropic etching process used to etch the material through the alternating stack (32, 42) can be alternating to optimize the etching of the first material and the second material in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of the memory opening 49 and the support opening 19 can be substantially vertical, or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0066] The memory openings 49 and the support openings 19 may extend from the top surface of the alternating stack (32, 42) to the corresponding bottom surface located within the bottom insulating layer 31. Each of the memory openings 49 and the support openings 19 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings 49 may be formed in the memory array area 100. A two-dimensional array of support openings 19 may be formed in the staircase area 300.

[0067] refer to Figure 5, an isotropic etching process may be performed to laterally recess the physically exposed cylindrical sidewalls of the channel-level insulating layer 32A selectively to the materials of the sacrificial material layer 42 and the inter-transistor-level insulating layer 32B. For example, if the sacrificial material layer 42 includes silicon nitride, the inter-transistor-level insulating layer 32B includes undoped silicate glass, and the channel-level insulating layer includes doped silicate glass or organosilicate glass, a wet etching process using dilute hydrofluoric acid with a dilution of 100:1 or higher may be performed to laterally recess the physically exposed sidewalls of the channel-level insulating layer 32A. The lateral recess distance of the sidewalls of the channel-level insulating layer 32A may be at least three times greater than the lateral recess distance of the sidewalls of the inter-transistor-level insulating layer 32B, and / or at least 10 times greater, such as 100 times greater or greater.

[0068] Optionally, another isotropic etching process may be performed to recess the sidewalls of the sacrificial material layer 42 so that the recessed sidewalls of the sacrificial material layer 42 substantially vertically coincide with the sidewalls of the inter-transistor level insulating layer 32B. A vertical stack of annular cylindrical cavities 47 may be formed around each memory opening 49 in the memory array region 100. Each annular cylindrical cavity 47 may have an outer boundary that coincides with the recessed sidewalls of the channel level insulating layer 32A, and an inner boundary that coincides with a cylindrical vertical plane that includes the sidewalls of the sacrificial material layer 42 surrounding the corresponding memory opening 49. The lateral recess distance between the sidewalls of the channel level insulating layer 32A and the sidewalls of the sacrificial material layer 42 may be in the range of 3 nm to 40 nm, such as 5 nm to 20 nm, although smaller and larger recess distances may also be employed.

[0069] refer to Figure 6 , a semiconductor material such as amorphous silicon or polycrystalline silicon may be conformally deposited in an annular cylindrical cavity 47 formed by a lateral recess of the channel level insulating layer 32A. The semiconductor material may have a doping of a first conductivity type, which may be p-type or n-type. The atomic concentration of the dopant of the first conductivity type in the semiconductor material may be between 1.0×10 14 / cm 3 to 1.0×10 18 / cm 3 , but smaller and larger dopant concentrations may also be used. The thickness of the conformally deposited semiconductor material may be selected so that the entire volume of each annular cylindrical cavity 47 is filled with semiconductor material. An anisotropic etch may be performed to remove portions of the semiconductor material that are not masked by the insulating cap layer 70, the anisotropic etch selectively etching the semiconductor material with respect to the insulating cap layer 70 and the insulating material of the bottom insulating layer 31. Each remaining tubular portion of the semiconductor material filling the corresponding annular cylindrical cavity 47 constitutes a semiconductor channel 60. Each semiconductor channel 60 may have a tubular shape.

[0070] Each instance of semiconductor channel 60 may be formed on the sidewalls of a corresponding instance of channel-level insulating layer 32A. In one embodiment, each semiconductor channel 60 may have a cylindrical outer sidewall and a cylindrical inner sidewall that is laterally offset inwardly from the cylindrical outer sidewall by a uniform lateral offset distance that may be the same as the sidewalls of the channel-level insulating layer 32A. Figure 5 The lateral offset distance of the isotropic etching process for forming the recessed sidewall of the channel-level insulating layer 32A at the processing step of the semiconductor channel 60 is the same. In one embodiment, each semiconductor channel 60 may have an annular flat top surface and an annular flat bottom surface. The outer peripheries of the annular flat top surface and the annular flat bottom surface of the semiconductor channel 60 are adjacent to the upper periphery and the lower periphery of the cylindrical outer sidewall of the semiconductor channel 60. The inner peripheries of the annular flat top surface and the annular flat bottom surface of the semiconductor channel 60 are adjacent to the upper periphery and the lower periphery of the cylindrical inner sidewall of the semiconductor channel 60. The height of each semiconductor channel 60 may be the same as the thickness of the channel-level insulating layer 32A contacting the cylindrical outer sidewall of the semiconductor channel 60.

[0071] refer to Fig. 7A and Figure 7B , a gate dielectric layer 54 is formed on the inner sidewall of each semiconductor channel 60 within the vertical stack of semiconductor channels surrounding each memory opening 49. The gate dielectric layer 54 may be formed directly on the physically exposed cylindrical sidewalls of the sacrificial material layer 42 and the inter-transistor level insulating layer 32B. The gate dielectric layer 54 extends vertically as a continuous material layer from the bottommost sacrificial material layer in the sacrificial material layer 42 to the topmost sacrificial material layer in the sacrificial material layer 42 within each memory opening 49, and directly contacts the sidewall of each inter-transistor level insulating layer in the inter-transistor level insulating layer 32B. The gate dielectric layer 54 is laterally spaced apart from each channel-level insulating layer in the channel-level insulating layer 32 by the corresponding vertical stack of semiconductor channels 54 located around each memory opening 49.

[0072] The gate dielectric layer 54 includes a ferroelectric material. In one embodiment, the gate dielectric layer 54 consists essentially only of a ferroelectric material. In another embodiment, the gate dielectric layer 54 includes a multi-film stack of a ferroelectric material film and a non-ferroelectric dielectric material film (e.g., a silicon oxide film). As used herein, "ferroelectric material" refers to a crystalline material that exhibits spontaneous electric polarization in the absence of an external electric field. The ferroelectric material in the gate dielectric layer 54 may be an insulating ferroelectric material. In one embodiment, the gate dielectric layer 54 includes a hafnium oxide layer that contains at least one dopant selected from Al, Zr, and Si and has a ferroelectric non-centrosymmetric orthorhombic phase. Alternatively, other ferroelectric materials such as barium titanate, bismuth ferrite, lead titanate, lead zirconate titanate, etc. may be used. The gate dielectric layer 54 may have a thickness in the range of 1.5 nm to 15 nm, such as from 3 nm to 10 nm, but smaller and larger thicknesses may also be used. In one embodiment, the gate dielectric layer 54 may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0073] A bipolar selector material layer 56 is then formed on the gate dielectric layer 54 as a conformal material layer. As used herein, "bipolar selector material" refers to any material that can be used as an on / off switch without switching bias polarity dependence depending on the magnitude of the bias voltage applied across it (i.e., if the absolute value of the voltage is greater than a threshold, the material switches at a positive voltage or a negative voltage). The selector material layer may include a non-ohmic material that provides an electrically isolated electrical connection, depending on the magnitude of the voltage bias applied across it. In one embodiment, the selector material layer includes at least one threshold switch material layer. At least one threshold switch material layer includes any suitable threshold switch material that exhibits nonlinear electrical behavior, such as a bidirectional threshold switch (OTS) material.

[0074] As used herein, a bidirectional threshold switch is a device that does not crystallize in a low resistivity state at voltages above a threshold voltage, and returns to a high resistivity state when a voltage above a critical holding voltage is not applied across the OTS material layer. As used herein, a "bidirectional threshold switch material" refers to a material that exhibits a nonlinear resistivity curve under an applied external bias voltage, such that the resistivity of the material decreases with the magnitude of the applied external bias voltage. In other words, the bidirectional threshold switch material is non-ohmic and becomes more conductive at a higher external bias voltage than at a lower external bias voltage.

[0075] A bidirectional threshold switch material (OTS material) may be amorphous (e.g., amorphous) in a high resistivity state and may remain amorphous (e.g., amorphous) in a low resistivity state during application of a voltage above its threshold voltage across the OTS material. The OTS material may return to a high resistivity state when the high voltage above its threshold voltage is reduced to below a critical holding voltage. The bidirectional threshold switch material may remain amorphous (e.g., amorphous) throughout the resistivity state change.

[0076] In one embodiment, the bidirectional threshold switch material may include a chalcogenide material that exhibits hysteresis in both the write current polarity and the read current polarity. The chalcogenide material may be a GeTe compound or a Ge-Se compound doped with a dopant selected from As, N and C, such as a Ge-Se-As compound semiconductor material. The bidirectional threshold switch material layer may include any bidirectional threshold switch material. In one embodiment, the bidirectional threshold switch material layer may include a compound of at least one Group 14 element and at least one Group 16 element. In one embodiment, the bidirectional threshold switch material layer may include a material selected from GeSeAs alloy, GeTeAs, GeSeTeSe alloy, GeSe alloy, SeAs alloy, GeTe alloy and SiTe alloy and / or may be substantially composed of the material.

[0077] In one embodiment, the material of the selector material layer may be selected such that the resistivity of the selector material therein is reduced by at least two orders of magnitude (i.e., more than 100 times) upon application of an external bias voltage that exceeds a critical bias voltage magnitude (also referred to as a threshold voltage). In one embodiment, the composition and thickness of the selector material layer may be selected such that the critical bias voltage magnitude may be in the range of 1V to 6V, although smaller and larger critical bias voltage magnitudes may also be employed. The thickness of the selector material layer may be, for example, in the range of 1nm to 50nm, such as 5nm to 25nm, although smaller and larger thicknesses may also be employed.

[0078] Conductive material may be deposited in each remaining unfilled volume of the memory opening 49 and the support opening. The conductive material may include at least one metallic material and / or heavily doped semiconductor material. For example, the conductive material may include an optional conductive metal nitride liner (such as a TiN liner, a TaN liner, or a WN liner) and a metal filling material (such as tungsten).

[0079] Excess portions of the conductive material, the selector material layer 56, and the gate dielectric layer 54 may be removed from above a horizontal plane including the top surface of the insulating cap layer 70 by a planarization process, which may employ at least one recess etching process and / or a chemical mechanical planarization (CMP) process. The top surface of the insulating cap layer 70 may serve as a stop layer for at least one recess etching process and / or a CMP process. Each remaining portion of the conductive material in the memory opening 49 and the support opening 19 constitutes a word line 62. The portion of each word line 62 at the level of each semiconductor channel includes a gate electrode 62G of a corresponding vertical field effect transistor 80.

[0080] A layer stack (which includes, from one side to the other, a gate dielectric layer 54, a selector material layer 56, and a word line 62) may be formed on a corresponding vertical stack of semiconductor channels 60 within each memory opening 49. Each vertical stack of semiconductor channels 60 surrounds a corresponding one of the memory openings 49 and contacts each of the channel-level insulating layers 32A. The gate dielectric layer 54 includes a ferroelectric dielectric material, and the selector material layer 56 includes a bipolar switching material that provides a voltage magnitude-dependent switching characteristic.

[0081] Each gate dielectric layer 54 includes a tubular gate dielectric portion extending through each layer of the alternating stack (32, 42), and a bottom gate dielectric base portion adjacent to the bottom periphery of the tubular gate dielectric portion. Each selector material layer 56 is laterally surrounded by the tubular gate dielectric portion and includes a tubular selector material portion extending through each layer of the alternating stack (32, 42) and a bottom selector material base portion adjacent to the bottom periphery of the tubular selector material portion. Each word line 62 is laterally surrounded by the tubular selector material portion of the corresponding selector material layer 56 and extends through each layer in the alternating stack (32, 42). Each of the semiconductor channel 60, the gate dielectric layer 54, the selector material layer 56 and the word line 62 extends in a vertical direction.

[0082] Each combination of the gate dielectric layer 54, the selector material layer 56, and the word line 62 filling the memory opening 49 and the adjacent vertical stack of the semiconductor channel 60 together constitutes a memory opening filling structure 58. Each combination of the adjacent vertical stack of all material portions filling the support opening 19 and the semiconductor channel 60 constitutes a support pillar structure. A two-dimensional array of memory opening filling structures 58 can be formed in the memory array area 100. An array of support pillar structures 20 can be formed in the staircase area 300. There is no semiconductor channel 60 on the portion of the support pillar structure 20 extending through the rear stepped dielectric material portion 65.

[0083] refer to Fig. 8A and Figure 8B, a contact level dielectric layer 73 may be formed over the alternating stack {(32A, 32B), 42} of insulating layers (32A, 32B) and sacrificial material layers 42 and over the memory opening filling structure 58 and the support pillar structure 20. The contact level dielectric layer 73 includes a dielectric material different from the dielectric material of the sacrificial material layer 42. For example, the contact level dielectric layer 73 may include silicon oxide. The contact level dielectric layer 73 may have a thickness in the range of 50 nm to 500 nm, but smaller and larger thicknesses may also be used.

[0084] A photoresist layer (not shown) may be applied over the contact level dielectric layer 73 and photolithographically patterned to form openings in the regions between the clusters of memory opening fill structures 58. The pattern in the photoresist layer may be transferred using anisotropic etching through the contact level dielectric layer 73, the alternating stacks {(32A, 32B), 42} and / or the back stepped dielectric material portions 65 to form backside trenches 79 extending vertically downward from the top surface of the contact level dielectric layer 73 to the bottom insulating layer 31 and extending laterally through the memory array region 100 and the staircase region 300.

[0085] In one embodiment, the backside trenches 79 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The memory opening filling structures 58 may be arranged in a row extending along the first horizontal direction hd1. Each backside trench 79 may have a uniform width that is constant along the longitudinal direction (i.e., along the first horizontal direction hd1). The photoresist layer may be removed, for example, by ashing.

[0086] refer to Fig. 9 , an etchant that selectively etches the sacrificial material layer 42 relative to the insulating layer (32A, 32B) may be introduced into the backside trench 79, for example, using an etching process. The backside recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The sacrificial material layer 42 may be removed selectively to the insulating layer (32A, 32B), the material of the backward stepped dielectric material portion 65, and the material of the gate dielectric layer 54. In one embodiment, the sacrificial material layer 42 may include silicon nitride, and the materials of the insulating layer (32A, 32B) and the backward stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxide.

[0087] The etching process for selectively removing the sacrificial material layer 42 for the insulating layer (32A, 32B) and the gate dielectric layer 54 can be a wet etch using a wet etching solution or can be a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in the vapor phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process in which the first exemplary structure is immersed in a wet etching tank including phosphoric acid, which selectively etches silicon nitride for silicon oxide, silicon, and various other materials used in the art. When the backside recess 43 exists in the volume previously occupied by the sacrificial material layer 42, the support pillar structure 20, the rear stepped dielectric material portion 65, and the memory opening filling structure 58 provide structural support.

[0088] Each backside recess 43 may be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess 43 may be greater than the height of the backside recess 43. Multiple backside recesses 43 may be formed in the volume from which the sacrificial material layer 42 is removed. The memory opening 49 in which the memory opening filling structure 58 is formed is referred to herein as a frontside opening or a frontside cavity, in contrast to the backside recess 43.

[0089] Each of the plurality of backside recesses 43 may extend substantially parallel to the top surface of the substrate 9. The backside recesses 43 may be vertically defined by the top surface of the lower insulating layer (32A, 32B) and the bottom surface of the overlying insulating layer (32A, 32B). In one embodiment, each backside recess 43 may have a uniform height throughout.

[0090] refer to Fig.10 , a doped semiconductor material may be deposited in the back recess 43. The semiconductor material may be doped with a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The atomic concentration of the dopant of the second conductivity type in the semiconductor material may be 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 The doping concentration of the semiconductor layer 60 is within the range of , but smaller and larger dopant concentrations may also be used. A plurality of doped semiconductor layers (44, 46) may be formed in the plurality of backside recesses. The plurality of doped semiconductor layers (44, 46) include a source layer 44 contacting a first annular horizontal surface of the semiconductor channel 60 and a drain layer 46 contacting a second annular horizontal surface of the semiconductor channel 60. The source layer 44 serves as a source doping region of a corresponding vertical field effect transistor, and the drain layer 46 serves as a drain doping region of a corresponding vertical field effect transistor.

[0091] Generally speaking, the doped semiconductor regions of the source layer and the drain layer contacting the end portions of the semiconductor channel 60 can be used as the source region or the drain region of each vertical field effect transistor 80, depending on the voltage biasing scheme and the polarity of the minority charge carriers flowing through the semiconductor channel. Therefore, although the present disclosure is described using an embodiment in which the source layer 44 is formed at the bottom end of each semiconductor channel 60 and the drain layer 46 is formed at the top end of each semiconductor channel, it should be understood that the positions of the source layer 44 and the drain layer 46 contacting any semiconductor channel 60 can be reversed, depending on the voltage biasing scheme adopted across the source layer 44 and the drain layer 46.

[0092] In the illustrated example, each annular bottom surface of the semiconductor channel 60 is contacted by the source layer 44, and each annular top surface of the semiconductor channel 60 is contacted by the drain layer 46. Each source layer 44 contacts the annular bottom surface of the two-dimensional array of semiconductor channels 60 having corresponding cylindrical sidewalls, which contact a corresponding one of the channel-level insulating layers 32A. Each drain layer 46 contacts the annular top surface of the two-dimensional array of semiconductor channels 60 having corresponding cylindrical sidewalls, which contact a corresponding one of the channel-level insulating layers 32A. The end portion of the source layer 44 that contacts the semiconductor channel 60 and / or each portion near the end portion constitutes a source region. The end portion of the drain layer 46 that contacts the semiconductor channel 60 and / or each portion near the end portion constitutes a drain region. Each sacrificial material layer 42 can be replaced with a source layer 44 or a drain layer 46.

[0093] A continuous doped semiconductor layer 46L may be formed on the sidewalls of each backside trench 79 and over the contact-level dielectric layer 73. The continuous doped semiconductor layer 46L includes a continuous extension of doped semiconductor material deposited in the backside trench 79 or over the contact-level dielectric layer 73. A backside cavity 79' exists within the portion of each backside trench 79 that is not filled with the continuous metal material layer 46L.

[0094] refer to Fig.11, the continuous doped semiconductor layer 46L is etched back from the sidewalls of each backside trench 79 and from above the contact-level dielectric layer 73, such as by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the doped semiconductor material in the backside recess 43 constitutes a source layer 44 or a drain layer 46. In one embodiment, the doped semiconductor material of the source layer 44 and the drain layer 46 can be isotropically etched back, for example, using a wet etching process that etches the doped semiconductor material selectively to the materials of the insulating layer (32A, 32B), the bottom insulating layer 31, the insulating capping layer 70, and the contact-level dielectric layer 73. In an illustrative example, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH) can be performed to laterally recess the sidewalls of the source layer 44 and the drain layer 46 from the backside trench 79. Alternatively, the doped semiconductor material of the source layer 44 and the drain layer 46 is not isotropically etched back.

[0095] The lateral recess distance of the sidewalls of the source layer 44 and the drain layer 46 may be controlled so that the surface of the semiconductor channels 60 is not physically exposed and each semiconductor channel 60 is separated from the volume of the recess around the backside trench 79 by at least the corresponding source region (region of the source layer 44) and the corresponding drain region (region of the drain layer 46). In one embodiment, the lateral recess distance of the sidewalls of the source layer 44 and the drain layer 46 around each backside trench 79 may be in the range of 20 nm to 100 nm, although smaller and larger lateral recess distances may also be used.

[0096] refer to Fig.12, at least one metal material may be deposited in the lateral recess around the backside trench 79, at the peripheral region of the backside trench 79, and above the contact level dielectric layer 73. The at least one metal material may include a metal barrier liner material and a metal filler material. The metal barrier liner material may include a conductive metal nitride material, such as TiN, TaN, WN, or a stack thereof. In one embodiment, the metal barrier liner material may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier liner material may be in the range of 1 nm to 5 nm, such as 2 nm to 3 nm, but smaller and larger thicknesses may also be used. In one embodiment, the metal barrier liner material may consist essentially of a conductive metal nitride such as TiN. The metal filler material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal filler material may consist essentially of at least one elemental metal. The at least one elemental metal of the metal fill material may be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal fill material may consist essentially of a single elemental metal.

[0097] Multiple metal material layers (64, 66) may be formed in the multiple lateral recesses, and a continuous metal material layer 66L may be formed on the sidewalls of each backside trench 79 and over the contact-level dielectric layer 73. Each metal material layer (64, 66) includes a portion of a metal barrier layer (which includes a metal barrier liner material) and a portion of a metal fill material layer (which includes a metal fill material). The continuous metal material layer 66L includes a continuous portion of the metal barrier layer and a continuous portion of the metal fill material layer located in the backside trench 79 or over the contact-level dielectric layer 73.

[0098] Each metal material layer 64 contacting the source layer 44 constitutes a source contact layer 64, and each metal material layer 66 contacting the drain layer 46 constitutes a drain contact layer 66. Each of the source contact layer 64 and the drain contact layer 66 may have a uniform width (the uniform width is Fig.11 The formation of the metal material layer (64, 66) is optional. If the doped semiconductor material of the source layer 44 and the drain layer 46 is Fig.11 In the illustrated step, no isotropic etching is performed, and the metal material layer (64, 66) is omitted. In this case, the source layer 44 fills the entire backside recess 43 at the source level, and the drain layer 46 fills the entire backside recess 43 at the drain level.

[0099] refer to Fig.13A and Fig. 13B, for example, by etching back the deposited metal material of the continuous metal material layer 66L from the sidewalls of each backside trench 79 and from above the contact level dielectric layer 73 by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of at least one deposited metal material in the backside recess 43 constitutes a source contact layer 64 or a drain contact layer 66. Therefore, each sacrificial material layer 42 is replaced with a corresponding replacement material layer {(44, 46), (64, 66)}. Each replacement material layer includes a combination of a source layer 44 and a source contact layer 64 or a combination of a drain layer 46 and a drain contact layer 66. The source contact layer 64 and the drain contact layer 66 may include corresponding metal material layers.

[0100] Generally, a source region 44S (including a portion of the source layer 44) is formed on one end of each semiconductor channel 60, and a drain region 46D (including a portion of the drain layer 46) is formed on the other end of each semiconductor channel 60. At least one contiguous combination (which may be a plurality of contiguous combinations) of a semiconductor channel 60, a source region 44S, and a drain region 46D may be formed on each gate dielectric layer 54. The total number of contiguous combinations of semiconductor channels 60, source regions 44S, and drain regions 46D contacting each gate dielectric layer 54 in each memory opening 49 may be the same as the total number of channel-level insulating layers 32A within the alternating stack of insulating layers (32A, 32B) and conductive layers {(44, 64), (46, 66)}.

[0101] Each of the replacement material layers {(44, 46), (64, 66)} includes a corresponding source layer 44 including a source region 44S or a corresponding drain layer 46 including a drain region 46D. The source layer 44 and the drain layer 46 are formed on each of the gate dielectric layers 54 located in the memory opening 49. The metal material layer (64, 66) is formed on the sidewall of the corresponding one of the source layer 44 and the drain layer 46 and is laterally spaced apart from the gate dielectric layer 54. Each of the metal material layers (64, 66) contacts the sidewall of the corresponding one of the source layer 44 and the drain layer 46 and does not contact the gate dielectric layer 54. In one embodiment, each metal material layer (64, 66) except the topmost metal material layer among the metal material layers (64, 66) and except the bottommost metal material layer among the metal material layers (64, 66) contacts a corresponding one of the channel level insulating layers 32A and a corresponding one of the transistor inter-level insulating layers 32B.

[0102] Each combination of the source layer 44 and the source contact layer 64 constitutes a source-side conductive layer (44, 64). Each combination of the drain layer 46 and the drain contact layer 66 constitutes a drain-side conductive layer (46, 66). The source-side conductive layer (44, 64) and the drain-side conductive layer (46, 66) are collectively referred to as conductive layers {(44, 46), (64, 66)}.

[0103] Multiple adjacent combinations of corresponding semiconductor channels 60, corresponding source regions 44S, and corresponding drain regions 46D may be arranged on the sidewalls of the corresponding gate dielectric layer 54 along the vertical direction around each memory opening 49. Multiple inter-transistor level insulating layers 32B may be disposed above the substrate 9 within an alternating stack of insulating layers (32A, 32B) and conductive layers {(44, 64), (46, 66)} such that vertically adjacent pairs of combinations of semiconductor channels 60, source regions 44S, and drain regions 46D are vertically spaced apart by corresponding inter-transistor level insulating layers 32B.

[0104] refer to Fig.14 , a dielectric material such as silicon oxide may be deposited in the backside trench to form a dielectric wall structure 76. Each dielectric wall structure 76 may contact the sidewall of each insulating layer (32A, 32B) within the alternating stack of insulating layers (32A, 32B) and conductive layers {(44, 64), (46, 66)}, and may contact each metallic material layer (64, 66) within the alternating stack. Each dielectric wall structure 76 is laterally spaced apart from the source layer 44 and the drain layer 46. The top surface of each dielectric wall structure 76 may be coplanar with the top surface of the contact level dielectric layer 73. Alternatively, as in Fig.13A and Fig. 13B The horizontal portions of the dielectric material overlying the top surface of the contact-level dielectric layer 73 provided at the processing step of can be incorporated into the contact-level dielectric layer 73 .

[0105] Each ferroelectric material portion of the gate dielectric layer 54 that contacts a corresponding one of the semiconductor channels constitutes a memory element that can store a polarization direction as a data bit. The polarization of each ferroelectric material portion determines the threshold voltage of a vertical field effect transistor 80, which includes a corresponding ferroelectric material portion and an adjacent semiconductor channel 60. If the polarization direction in the ferroelectric material portion causes the ferroelectric material portion to attract minority charge carriers in the adjacent semiconductor channel 60, the field effect transistor 80 has a low threshold voltage. If the polarization direction in the ferroelectric material portion causes the ferroelectric material portion to repel minority charge carriers in the adjacent semiconductor channel 60, the field effect transistor 80 has a high threshold voltage.

[0106] refer to Fig.15A and Fig. 15B, a contact via structure (88, 86, 8P) may be formed through the contact level dielectric layer 73 and optionally through the backward stepped dielectric material portion 65. For example, a gate contact via structure 88 may be formed through the contact level dielectric layer 73 on the top surface of the corresponding word line 62 in the memory array region 100. A source / drain contact via structure 86 may be formed through the contact level dielectric layer 73 on a corresponding one of the source layer 44 and the drain layer 46, and through the backward stepped dielectric material portion 65 in the staircase region 300. A peripheral device contact via structure 8P may be formed directly through the backward stepped dielectric material portion 65 on a corresponding node of the peripheral device 700 in the peripheral region 200. In an alternative embodiment, the peripheral device 700 is formed on a separate substrate and then bonded to the memory device. In this case, the peripheral device contact via structure 8P may be omitted. In another alternative embodiment, the peripheral device 700 may be formed between the bottom insulating layer 31 and the substrate 9, and the peripheral device contact via structures 8P may connect various nodes of the peripheral device 700 to various nodes of the three-dimensional array of ferroelectric memory elements.

[0107] refer to Fig.16 , showing a second exemplary structure according to a second embodiment of the present disclosure, which can be obtained by forming a bottom insulating layer 31 and a periodic sequence of material layers including a plurality of repeating bodies of a unit layer stack. Figure 1 The second exemplary structure is obtained by converting the first exemplary structure of the cell layer stack into the second exemplary structure. The cell layer stack may include a first instance of a sacrificial material layer 42, a first instance of a doped semiconductor layer (which may be a source layer 44), a channel-level insulating layer 32A, a second instance of a doped semiconductor layer (which may be a drain layer 46), a second instance of a sacrificial material layer 42, and an inter-transistor-level insulating layer 32B. The inter-transistor-level insulating layer 32B of the topmost repeat of the cell layer stack may be replaced with an insulating cap layer 70.

[0108] The semiconductor channel to be formed subsequently has a doping of a first conductivity type. The doped semiconductor layer (44, 46) has a doping of a second conductivity type opposite to the first conductivity type. The atomic concentration of the dopant of the second conductivity type in the doped semiconductor layer (44, 46) may be within 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 The thickness of each doped semiconductor layer (44, 46) may be in the range of 10 nm to 50 nm, but smaller and larger atomic concentrations may also be used.

[0109] Each doped semiconductor layer (44, 46) is formed between and contacts a vertically adjacent pair of one of the channel-level insulating layers 32A and one of the sacrificial material layers 42. Each of the doped semiconductor layers (44, 46) may include a source layer 44 or a drain layer 44. Each source layer 44 includes a two-dimensional array of source regions for a two-dimensional array of semiconductor channels to be formed subsequently, and each drain layer 46 includes a two-dimensional array of drain regions for a two-dimensional array of semiconductor channels to be formed subsequently.

[0110] refer to Fig.17 , which can be executed by modifying Figure 3 The processing steps of the anisotropic etching process for forming vertical steps extending through the combination of the sacrificial material layer 42 and the insulating layer 32 are modified to provide vertical steps extending through the adjacent combination of the sacrificial material layer 42, the drain layer 46, and the transistor-level insulating layer 32A, or through the adjacent combination of the source layer 44, the sacrificial material layer 42, and the transistor-level insulating layer 32B. In this case, the terminal step of each anisotropic etching process for forming vertical steps of each layer in the layer stack including a plurality of repeating bodies of the unit layer stack (42, 44, 32A, 46, 42, 32B) can be performed selectively to the material of the sacrificial material layer 42 or selectively to the material of the source layer 44. The backward stepped dielectric material portion 65 can be formed in the stepped cavity to form the backward stepped dielectric material portion 65.

[0111] refer to Fig.18 , which can be performed by modifying the etch chemistry of the anisotropic etch process Figure 4A and Figure 4B The processing steps are performed to etch through the insulating cap layer 70 and the unmasked portion of the layer stack including the multiple repeats of the cell layer stack (42, 44, 32A, 46, 42, 32B). The bottom insulating layer 31 can be used as an etch stop structure. The memory opening 49 is formed in the memory array region 100, and the support opening 19 is formed in the staircase region 300.

[0112] refer to Fig.19 , an isotropic etching process may be performed to laterally recess the physically exposed cylindrical sidewalls of the channel-level insulating layer 32A, which is selective to the materials of the sacrificial material layer 42, the doped semiconductor layer (44, 46), and the inter-transistor-level insulating layer 32B, as described above with respect to FIG. 4. Then, a semiconductor channel 60 is formed in the recessed portion, as described above with respect to FIG. Figure 5 described.

[0113] One end of each semiconductor channel 60 contacts the horizontal surface of the source layer 44, and the other end of each semiconductor channel 60 contacts the horizontal surface of the drain layer 46. Each portion of the source layer 44 that contacts the semiconductor channel 60 and / or is near the semiconductor channel constitutes a source region 44S, and each portion of the drain layer 46 that contacts the semiconductor channel 60 and / or is near the semiconductor channel constitutes a drain region 46D. The cylindrical inner sidewall of the semiconductor channel 60 may vertically coincide with the overlying sidewall or the underlying sidewall of the insulating layer 32 and the doped semiconductor layer (44, 46).

[0114] refer to Fig. 20 , executable Fig. 7A and Figure 7B The processing steps of FIG. 1 and FIG. 2 are performed to form a layer stack including a gate dielectric layer 54, a selector material layer 56, and a word line 62 in each of the memory opening 49 and the support opening 19. No semiconductor channel 60 is present on the portion of the support pillar structure 20 extending through the rear stepped dielectric material portion 65.

[0115] refer to Fig.21 , a contact level dielectric layer 73 may be formed over the insulating cap layer 70, the memory opening fill structure 58, and the support pillar structure 20. A photoresist layer (not shown) may be applied over the contact level dielectric layer 73 and photolithographically patterned to form openings in the regions between the clusters of the memory opening fill structures 58. The pattern in the photoresist layer may be transferred using anisotropic etching through the contact level dielectric layer 73, multiple repeats of the cell layer stack (42, 44, 32A, 46, 42, 32B), and / or the back stepped dielectric material portion 65 to form a backside trench 79 that extends vertically downward from the top surface of the contact level dielectric layer 73 to the bottom insulating layer 31, and extends laterally through the memory array region 100 and the staircase region 300.

[0116] In one embodiment, the backside trenches 79 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The memory opening filling structures 58 may be arranged in a row extending along the first horizontal direction hd1. Each backside trench 79 may have a uniform width that is constant along the longitudinal direction (i.e., along the first horizontal direction hd1). The photoresist layer may be removed, for example, by ashing.

[0117] refer to Fig. 22, an etchant that selectively etches the sacrificial material layer 42 relative to the insulating layer (32A, 32B) and the doped semiconductor layer (44, 46) may be introduced into the backside trench 79, for example, using an etching process. A backside recess 63 is formed in the volume from which the sacrificial material layer 42 is removed. The sacrificial material layer 42 may be removed selectively to the material of the insulating layer (32A, 32B), the material of the doped semiconductor layer (44, 46), the material of the backward stepped dielectric material portion 65, and the material of the gate dielectric layer 54. In one embodiment, the sacrificial material layer 42 may include silicon nitride, and the materials of the insulating layer (32A, 32B) and the backward stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxide.

[0118] The etching process for selectively removing the sacrificial material layer 42 for the insulating layer (32A, 32B), the doped semiconductor layer (44, 46), and the gate dielectric layer 54 can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in the vapor phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process in which the first exemplary structure is immersed in a wet etching tank including phosphoric acid, which selectively etches silicon nitride for silicon oxide, silicon, and various other materials used in the art. When the backside recess 63 exists in the volume previously occupied by the sacrificial material layer 42, the support pillar structure 20, the rear stepped dielectric material portion 65, and the memory opening filling structure 58 provide structural support.

[0119] Each backside recess 63 can be a laterally extending cavity whose lateral dimension is greater than the vertical extent of the cavity. A plurality of backside recesses 63 can be formed in the volume from which the sacrificial material layer 42 is removed. The memory opening 49 in which the memory opening filling structure 58 is formed is referred to herein as a frontside opening or frontside cavity, in contrast to the backside recess 63.

[0120] Each of the plurality of backside recesses 63 may extend substantially parallel to the top surface of the substrate 9. The backside recess 63 may be vertically defined by the top surface of the underlying insulating layer (such as the inter-transistor level insulating layer 32B) and the bottom surface of the overlying doped semiconductor layer (such as the source layer 44), or may be vertically defined by the top surface of the underlying doped semiconductor layer (such as the drain layer 46) and the bottom surface of the overlying insulating layer (such as the inter-transistor level insulating layer 32B). In one embodiment, each backside recess 63 may have a uniform height throughout.

[0121] refer to Fig.23, at least one metal material may be deposited in the backside recess 63, at the peripheral region of the backside trench 79, and above the contact level dielectric layer 73. The at least one metal material may include a metal barrier liner material and a metal filler material. The metal barrier liner material may include a conductive metal nitride material, such as TiN, TaN, WN, or a stack thereof. In one embodiment, the metal barrier liner material may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier liner material may be in the range of 1nm to 5nm, such as 2nm to 3nm, but smaller and larger thicknesses may also be used. In one embodiment, the metal barrier liner material may be substantially composed of a conductive metal nitride such as TiN. The metal filler material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, or a combination thereof. In one embodiment, the metal filler material may be substantially composed of at least one elemental metal. The at least one elemental metal of the metal filler material may be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic filler material may consist essentially of a single elemental metal.

[0122] A plurality of metal material layers (64, 66) may be formed in the plurality of backside recesses 63, and a continuous metal material layer may be formed on the sidewalls of each backside trench 79 and over the contact-level dielectric layer 73. Each metal material layer (64, 66) includes a portion of a metal barrier layer (which includes a metal barrier liner material) and a portion of a metal fill material layer (which includes a metal fill material). The continuous metal material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal fill material layer located in the backside trench 79 or over the contact-level dielectric layer 73.

[0123] Each metal material layer 64 contacting source layer 44 constitutes a source contact layer 64, and each metal material layer 66 contacting drain layer 46 constitutes a drain contact layer 66. The area of ​​each source contact layer 64 may be the same as the area of ​​the overlying source layer 44, and the area of ​​each drain contact layer 66 may be the same as the area of ​​the underlying drain layer 46.

[0124] The deposited metal material of the continuous metal material layer is etched back from the sidewalls of each back contact trench 79 and from above the contact level dielectric layer 73, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of at least one deposited metal material in the back side recess 63 constitutes a source contact layer 64 or a drain contact layer 66. Thus, each sacrificial material layer 42 is replaced with a corresponding replacement material layer, which includes and / or consists of one of the source contact layer 64 and the drain contact layer 66. The source contact layer 64 and the drain contact layer 66 may include a corresponding metal material layer. Each adjacent combination of the source layer 44 and the source contact layer 64 constitutes a source side conductive layer (44, 64), and each adjacent combination of the drain layer 46 and the drain contact layer 66 constitutes a drain side conductive layer (46, 66). The source side conductive layer (44, 64) and the drain side conductive layer (46, 66) are collectively referred to as conductive layers {(44, 64), (46, 66)}.

[0125] Generally, a source region 44S (including a portion of the source layer 44) is formed on one end of each semiconductor channel 60, and a drain region 46D (including a portion of the drain layer 46) is formed on the other end of each semiconductor channel 60. At least one contiguous combination (which may be a plurality of contiguous combinations) of the semiconductor channel 60, the source region 44S, and the drain region 46D may be formed on each gate dielectric layer 54. An alternating stack of insulating layers (32A, 32B) and conductive layers {(44, 64), (46, 66)} may be formed over the substrate 9. The total number of contiguous combinations of semiconductor channels 60, source regions 44S, and drain regions 46D contacting each gate dielectric layer 54 may be the same as the total number of channel-level insulating layers 32A within the alternating stack [(32A, 32B), {(44, 64), (46, 66)}].

[0126] The source layer 44 and the drain layer 46 are formed on each of the gate dielectric layers 54 located in the memory opening 49 and contact the horizontal surface of the semiconductor channel 60. The metal material layer (64, 66) is directly formed on each of the gate dielectric layers 54 and is vertically spaced apart from the semiconductor channel 60 by a corresponding one of the source layer 44 and the drain layer 46. Each of the metal material layers (64, 66) contacts the sidewall of each of the gate dielectric layers 54 laterally surrounded by the metal material layer (64, 66).

[0127] Multiple adjacent combinations of corresponding semiconductor channels 60, corresponding source regions 44S, and corresponding drain regions 46D may be arranged on the sidewalls of the corresponding gate dielectric layer 54 along the vertical direction around each memory opening 49. Multiple inter-transistor level insulating layers 32B may be disposed above the substrate 9 within an alternating stack of insulating layers (32A, 32B) and conductive layers {(44, 64), (46, 66)} such that vertically adjacent pairs of combinations of semiconductor channels 60, source regions 44S, and drain regions 46D are vertically spaced apart by corresponding inter-transistor level insulating layers 32B.

[0128] refer to Fig.24 , executable Fig.14 , Fig.15A and Fig. 15B The processing steps are to form the dielectric wall structure 76 and various contact via structures (88, 86, 8P). For example, the gate contact via structure 88 may be formed through the contact level dielectric layer 73 on the top surface of the corresponding word line 62 in the memory array area 100. The source / drain contact via structure 86 may be formed through the contact level dielectric layer 73 on the corresponding one of the source layer 44 and the drain layer 46, and through the backward stepped dielectric material portion 65 in the staircase area 300. During the formation of the via cavity for forming the source / drain contact via structure 86, the metal material layer (64, 66) may be used as an etch stop structure. In this case, each of the source / drain contact via structures 86 may contact a corresponding one of the source contact layer 44 and the drain contact layer 46. A peripheral device contact via structure 8P may be formed directly through the backward stepped dielectric material portion 65 on the corresponding nodes of the peripheral device 700 in the peripheral region 200. In an alternative embodiment, the peripheral device 700 is formed on a separate substrate and then bonded to the memory device. In this case, the peripheral device contact via structure 8P may be omitted. In another alternative embodiment, the peripheral device 700 may be formed between the bottom insulating layer 31 and the substrate 9, and the peripheral device contact via structure 8P may connect the various nodes of the peripheral device 700 to the various nodes of the three-dimensional array of ferroelectric memory elements.

[0129] refer to Fig.25, a schematic circuit diagram of a three-dimensional array of memory elements according to an embodiment of the present disclosure is shown. Each field effect transistor (i.e., ferroelectric field effect transistor, FeFET) 80A includes: a semiconductor channel 60; a source region 44S, the source region contacts one end of the semiconductor channel 60; a drain region 46D, the drain region contacts the opposite end of the semiconductor channel 60; a gate electrode 62G, the gate electrode is positioned adjacent to each semiconductor channel 60; a ferroelectric gate dielectric layer 54, the ferroelectric gate dielectric layer is located between the semiconductor channel 60 and the gate electrode 62G; and a bidirectional selector material layer 56, the bidirectional selector material layer is located between the gate electrode 62G and the ferroelectric gate dielectric layer 54. The gate electrode 62G can be part of a vertical word line 62 (WL1, WL2).

[0130] Source region 44S may include a portion of source layer 44, and drain region 46D may include a portion of drain layer 46. Each source layer 44 may include at least a portion of a source line (44, 64) (SL1, SL2), and each drain layer 46 may include at least a portion of a bit line (46, 66) (BL1, BL2).

[0131] Each word line 62 (WL1, WL2) controls the gate electrode 62G of a corresponding vertical stack of vertical field effect transistors 80, such as a stack of a first vertical field effect transistor 80A and a second vertical field effect transistor 80B, or a stack of a third vertical field effect transistor 80C and a fourth field effect transistor 80D, as shown in FIG. Fig.25 shown.

[0132] In a FeFET without a bidirectional selector material layer 56, the programming or erasing interference voltage may be half of the programming and erasing voltage. By adding a bidirectional selector material layer 56 between the gate electrode 62G and the semiconductor channel 60 of the FeFET 80 of the embodiment of the present disclosure, there is no programming or erasing interference on the FeFET 80. In one embodiment, the switching threshold voltage of the bidirectional selector material layer 56 may be greater than half of the programming and erasing voltage required to program and erase the FeFET 80. If the voltage difference between the word line voltage and the bit line voltage is greater than the switching threshold voltage of the bidirectional selector material layer 56, the semiconductor channel may be activated by the word line voltage. If the voltage difference between the word line voltage and the bit line voltage is less than the switching threshold voltage of the bidirectional selector material layer 56, the semiconductor channel 60 is deactivated (i.e., the gate electrode to semiconductor channel bias is about 0V).

[0133] With reference to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a ferroelectric field effect transistor (FeFET) 80 (e.g., 80A) includes: a semiconductor channel 60; a source region 44S contacting one end of the semiconductor channel; a drain region 46D contacting a second end of the semiconductor channel; a gate electrode 62G; a ferroelectric gate dielectric layer 54 located between the semiconductor channel and the gate electrode; and a bidirectional selector material layer 56 located between the gate electrode and the ferroelectric gate dielectric layer.

[0134] In one embodiment, the FeFET further comprises a substrate 9 having a horizontal surface 7, wherein the semiconductor channel, the ferroelectric gate dielectric layer, the bidirectional selector material layer and the gate electrode extend along a vertical direction perpendicular to the horizontal surface 7. The gate electrode 62G comprises a portion of a vertical word line 62 extending perpendicular to the horizontal surface.

[0135] In one embodiment, source region 44S includes a portion of source layer 44, drain region 46D includes a portion of drain layer 46, source layer 44 includes at least a portion of source line (44, 64), and drain layer 46 includes at least a portion of bit line (46, 66). In one embodiment, channel-level insulating layer 32A is located between source region 44S and drain region 46D.

[0136] In one embodiment, a three-dimensional FeFET array includes: FeFET 80A; additional FeFET 80B, which is located below FeFET 80A; and an inter-transistor level insulating layer 32B, which is located between the source line (44, 64) of FeFET 80A and the bit line (46, 66) of the additional FeFET 80B.

[0137] In one embodiment, the FeFET array includes an alternating stack of insulating layers (32A, 32B) and conductive layers {(44, 64), (46, 66)} alternating along the vertical direction; a group of all insulating layers (32A, 32B) within the alternating stack includes a vertical alternating sequence of channel-level insulating layers 32A and inter-transistor-level insulating layers 32B; and a group of all conductive layers {(44, 64), (46, 66)} within the alternating stack includes a vertical alternating sequence of source layers 44 and drain layers 46.

[0138] In one embodiment, each of the metal material layers (64, 66) contacts the sidewall of a corresponding one of the source layer 44 and the drain layer 46, and does not contact the ferroelectric gate dielectric layer 54. In one embodiment, each of the metal material layers (64, 66) contacts the horizontal surface of a corresponding one of the source layer 44 and the drain layer 46, and contacts the ferroelectric gate dielectric layer 54.

[0139] In one embodiment, a plurality of memory openings 49 may extend vertically through the alternating stack of insulating layers (32A, 32B) and conductive layers {(44, 64), (46, 66)}. A ferroelectric gate dielectric layer 54, a bidirectional selector material layer 56, and a vertical word line 62 are located within a memory opening 49 of the plurality of memory openings 49.

[0140] In one embodiment, the ferroelectric gate dielectric layer 54 includes a tubular gate dielectric portion extending through each of the conductive layers {(44, 64), (46, 66)} and a bottom gate dielectric base portion adjacent to the bottom periphery of the tubular gate dielectric portion; the bidirectional selector material layer 56 is laterally surrounded by the tubular gate dielectric portion and includes a tubular selector material portion extending through each of the conductive layers {(44, 64), (46, 66)} and a bottom selector material base portion adjacent to the bottom periphery of the tubular selector material portion; and the vertical word line 62 is laterally surrounded by the tubular selector material portion and extends through each of the conductive layers {(44, 64), (46, 66)}.

[0141] In one embodiment, the bidirectional selector material layer 54 includes a bidirectional threshold switch material.

[0142] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A ferroelectric field effect transistor, comprising: Semiconductor channel; a source region, the source region contacting one end of the semiconductor channel; a drain region, the drain region contacting the second end of the semiconductor channel; a gate electrode; a ferroelectric gate dielectric layer located between the semiconductor channel and the gate electrode; and A bipolar selector material layer is located between the gate electrode and the ferroelectric gate dielectric layer.

2. The ferroelectric field effect transistor according to claim 1, further comprising a substrate having a horizontal surface, wherein: The semiconductor channel, the ferroelectric gate dielectric layer, the bipolar selector material layer, and the gate electrode extend along a vertical direction perpendicular to the horizontal surface; and The gate electrode includes a portion of a vertical word line extending perpendicular to the horizontal surface.

3. The ferroelectric field effect transistor according to claim 2, wherein: The source region includes a portion of the source layer; The drain region includes a portion of the drain layer; The source layer includes at least a portion of a source line; and The drain layer includes at least a portion of a bit line. 4 . The ferroelectric field effect transistor according to claim 3 , further comprising a channel-level insulating layer, wherein the channel-level insulating layer is located between the source region and the drain region.

5. The ferroelectric field effect transistor of claim 1, wherein the bipolar selector material layer comprises a bipolar threshold switching material.

6. A three-dimensional ferroelectric field effect transistor array, the three-dimensional ferroelectric field effect transistor array include: The ferroelectric field effect transistor according to claim 4; an additional ferroelectric field effect transistor, the additional ferroelectric field effect transistor being located below the ferroelectric field effect transistor; and An inter-transistor level insulating layer is located between the source line of the ferroelectric field effect transistor and the bit line of the additional ferroelectric field effect transistor.

7. The three-dimensional ferroelectric field effect transistor array according to claim 6, wherein: The array comprises an alternating stack of insulating layers and conductive layers alternating along the vertical direction; a set of all insulating layers within the alternating stack comprises a vertically alternating sequence of the channel level insulating layers and inter-transistor level insulating layers; and A set of all conductive layers within the alternating stack includes a vertically alternating sequence of the source layers and the drain layers.

8. The three-dimensional ferroelectric field effect transistor array according to claim 7, further comprising a metal material layer contacting a corresponding one of the source layer and the drain layer and being located between vertically adjacent pairs of the insulating layers. 9 . The three-dimensional ferroelectric field effect transistor array according to claim 8 , wherein each of the metal material layers contacts a sidewall of a corresponding one of the source layer and the drain layer and does not contact the ferroelectric gate dielectric layer.

10. The three-dimensional ferroelectric field effect transistor array according to claim 8, wherein each of the metal material layers contacts a horizontal surface of a corresponding one of the source layer and the drain layer, and contacts the ferroelectric gate dielectric layer.

11. The three-dimensional ferroelectric field effect transistor array according to claim 7, further comprising a plurality of memory openings extending vertically through the alternating stack of the insulating layer and the conductive layer, wherein the ferroelectric gate dielectric layer, the bipolar selector material layer and the vertical word line are located within a memory opening among the plurality of memory openings.

12. The three-dimensional ferroelectric field effect transistor array according to claim 11, wherein: the ferroelectric gate dielectric layer comprising a tubular gate dielectric portion extending through each of the conductive layers and a bottom gate dielectric base portion adjacent to a bottom periphery of the tubular gate dielectric portion; The bipolar selector material layer is laterally surrounded by the tubular gate dielectric portion and includes a tubular selector material portion extending through each of the conductive layers and a bottom selector material base portion adjacent to a bottom periphery of the tubular selector material portion; and The vertical word line is laterally surrounded by a tubular selector material portion and extends through each of the conductive layers.

13. A method of forming a semiconductor device, the method comprising: forming a channel level insulating layer over the substrate; forming a vertical stack of semiconductor channels at the level of the channel-level insulating layer; forming a stack directly on the vertical stack of semiconductor channels, the stack comprising, from one side to the other, a ferroelectric gate dielectric layer, a bipolar selector material layer, and a gate electrode; and A source region is provided on one end of each of the semiconductor channels and a drain region is provided on the other end of each of the semiconductor channels, wherein each of the semiconductor channel, the source region and the drain region contacts the ferroelectric gate dielectric layer, and each of the channel-level insulating layers contacts a corresponding one of the source regions and a corresponding one of the drain regions.

14. The method according to claim 13, wherein: Each of the ferroelectric gate dielectric layer, the bipolar selector material layer, and the gate electrode is formed over the substrate and extends in a vertical direction perpendicular to a top surface of the substrate; Each of the channel-level insulating layers is formed as a horizontal extension layer having a top surface and a bottom surface; and Each of the semiconductor channels is formed as a tubular structure on a sidewall of a corresponding one of the channel-level insulating layers.

15. The method according to claim 14, further comprising forming an inter-transistor level insulating layer over the substrate such that the inter-transistor level insulating layer interfaces with the channel level insulating layer, wherein: Each of the semiconductors contacts a sidewall of the ferroelectric gate dielectric layer; and Vertically adjacent pairs of combinations of respective semiconductor channels, respective source regions, and respective drain regions are vertically spaced apart by respective ones of the inter-transistor level insulating layers.

16. The method according to claim 15, further comprising: forming an alternating stack of insulating layers and sacrificial material layers alternating along the vertical direction above the top surface of the substrate, wherein a set of all insulating layers within the alternating stack comprises a vertically alternating sequence of the channel level insulating layers and the inter-transistor level insulating layers; as well as The sacrificial material layer is replaced with replacement material layers, each of the replacement material layers comprising a respective metal material layer, wherein: each sacrificial material layer except a bottommost sacrificial material layer among the sacrificial material layers and except a topmost sacrificial material layer among the sacrificial material layers contacts a corresponding overlying insulating layer among the insulating layers and a corresponding underlying insulating layer among the insulating layers; Each of the replacement material layers includes a corresponding source layer including one of the source regions or a corresponding drain layer including one of the drain regions.

17. The method of claim 16, wherein: The source electrode layer and the drain electrode layer are formed on the ferroelectric gate dielectric layer; and The metallic material layer is formed on a sidewall of a respective one of the source layer and the drain layer and is laterally spaced apart from the ferroelectric gate dielectric layer.

18. The method according to claim 15, further comprising: forming doped semiconductor layers over the substrate, such that each doped semiconductor layer is formed between and contacts vertically adjacent pairs of one of the channel-level insulating layers and one of the sacrificial material layers, wherein each of the doped semiconductor layers includes a corresponding source layer containing one of the source regions or a corresponding drain layer containing one of the drain regions; as well as The sacrificial material layer is replaced with a metal material layer that contacts a horizontal surface of a corresponding one of the doped semiconductor layers.

19. The method of claim 18, wherein the metal material layer is formed on a sidewall of the ferroelectric gate dielectric layer.

20. The method of claim 15, further comprising forming a plurality of memory openings extending vertically through the alternating stack, wherein the ferroelectric gate dielectric layer, the bipolar selector material layer, and the gate electrode are located within a memory opening of the plurality of memory openings.

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