Method for forming a semiconductor structure and semiconductor structure

Abstract

A method of forming a semiconductor structure and a semiconductor structure. Forming a plurality of semiconductor-on-insulator (SOI) field effect transistors including a plurality of substrate regions having different thicknesses can be achieved by selectively thinning a region of the top semiconductor layer while avoiding thinning an additional region of the top semiconductor layer. An oxidation process or an etching process can be used to thin this region of the top semiconductor layer, and a patterned oxidation barrier mask or an etching mask can be used to prevent oxidation or etching of the additional portion of the top semiconductor layer. A plurality of shallow trench isolation structures can be formed before or after the selective thinning process step. Forming a plurality of field effect transistors having different depletion region configurations can use multiple thicknesses of multiple patterned portions of the top semiconductor layer. For example, partially depleted SOI field effect transistors and fully depleted SOI field effect transistors can be provided.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a plurality of semiconductor-on-insulator field effect transistors, and to a method of forming such a semiconductor device. Background Art

[0002] A semiconductor-on-insulator (SOI) field effect transistor is formed by providing a semiconductor-on-insulator substrate including a stack from bottom to top of a handle substrate, an insulating layer, and a top semiconductor layer, and by forming a plurality of shallow trench isolation structures, various doped semiconductor regions, and a plurality of gate stack structures within or above the top semiconductor layer. In this way, each semiconductor-on-insulator field effect transistor has the same thickness. The device characteristics of these semiconductor-on-insulator field effect transistors can be determined by the thickness of these semiconductor-on-insulator field effect transistors. For example, if a depletion region within a floating body region does not extend throughout the floating body region, a partially depleted semiconductor-on-insulator field effect transistor can be formed. Alternatively, if a depletion region within a floating body region extends throughout the floating body region, a fully depleted semiconductor-on-insulator field effect transistor can be formed. Partially depleted semiconductor-on-insulator field effect transistors and fully depleted field effect transistors provide different device characteristics, and it may be desirable to employ partially depleted semiconductor-on-insulator field effect transistors and fully depleted semiconductor-on-insulator field effect transistors within the same semiconductor wafer. However, it is difficult to provide both partially depleted semiconductor-on-insulator field effect transistors and fully depleted semiconductor-on-insulator field effect transistors within a semiconductor-on-insulator substrate in which the top semiconductor layer is of uniform thickness throughout. Summary of the Invention

[0003] Some embodiments of the present disclosure provide a method of forming a semiconductor structure, comprising: providing a semiconductor-on-insulator substrate including a processing substrate, an insulating layer, and a top semiconductor layer; covering a first region of the top semiconductor layer with at least one first diffusion barrier layer and physically exposing a second region of the top semiconductor layer; thinning the second region of the top semiconductor layer by performing an oxidation process that oxidizes a surface portion of the second region of the top semiconductor layer while the at least one first diffusion barrier layer impedes oxidation of the first region of the top semiconductor layer, wherein after the oxidation process, the second region of the top semiconductor layer has a thickness thinner than that of the first region of the top semiconductor layer; forming a plurality of shallow trenches that penetrate the top semiconductor layer, wherein the top semiconductor layer is divided into a plurality of separated portions including: a first substrate region patterned from the first region of the top semiconductor layer and a second substrate region patterned from the second region of the top semiconductor layer; forming a shallow trench isolation structure by filling the shallow trenches with a dielectric fill material and recessing portions of the dielectric fill material, wherein the shallow trench isolation structure includes a first shallow trench isolation portion that is located between the first substrate region and the second substrate region and has a non-planar inclined top surface; and forming a first semiconductor-on-insulator field effect transistor including the first substrate region and a second semiconductor-on-insulator field effect transistor including the second substrate region.

[0004] Some other embodiments of the present disclosure provide a method of forming a semiconductor structure, comprising: providing a semiconductor-on-insulator substrate including a processing substrate, an insulating layer, and a top semiconductor layer; forming a shallow trench isolation structure that penetrates the top semiconductor layer, wherein the trench isolation structure laterally surrounds a plurality of patterned portions of the top semiconductor layer including a first substrate region and a second substrate region; thinning the second substrate region by vertically recessing the second substrate region while protecting the first substrate region with a first etch mask layer; and forming a first semiconductor-on-insulator field effect transistor including the first substrate region and a second semiconductor-on-insulator field effect transistor including the second substrate region.

[0005] Some embodiments of the present disclosure provide a semiconductor structure, comprising: a semiconductor-on-insulator substrate, a first semiconductor-on-insulator field-effect transistor, and a second semiconductor-on-insulator field-effect transistor. The semiconductor-on-insulator substrate includes a processing substrate, an insulating layer, and a plurality of substrate regions laterally surrounded by a shallow trench isolation structure. The plurality of substrate regions include a first substrate region having a first thickness and a second substrate region having a second thickness less than the first thickness. The first semiconductor-on-insulator field-effect transistor includes the first substrate region, a first source region and a first drain region embedded in the first substrate region, and a first gate stack structure. The second semiconductor-on-insulator field-effect transistor includes the second substrate region, a second source region and a second drain region embedded in the second substrate region, and a second gate stack structure. Wherein: a portion of the shallow trench isolation structure located between the first substrate region and the second substrate region has a height difference between an upper edge of a first sidewall contacting the first substrate region and an upper edge of a second sidewall contacting the second substrate region; and the upper edges of the first sidewall and the second sidewall are connected via a continuous top surface of the portion of the shallow trench isolation structure including a non-horizontal surface section. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A is a top view of a first exemplary structure after the formation of a first semiconductor oxide layer on the top surface of a semiconductor-on-insulator substrate according to a first embodiment of the present disclosure;

[0008] Figure 1B is along Figure 1A a vertical cross-sectional view of the first exemplary structure along plane B-B' of

[0009] Figure 2A is a top view of a first exemplary structure after the formation of a first diffusion barrier layer, the application and patterning of a first photoresist layer, and the transfer of a pattern in the first photoresist layer through the first diffusion barrier layer and the first semiconductor oxide layer according to a first embodiment of the present disclosure;

[0010] Figure 2B is along Figure 2A a vertical cross-sectional view of the first exemplary structure along plane B-B' of

[0011] Figure 3Ais a top view of a first exemplary structure after an oxidation process for forming a second semiconductor oxide layer according to a first embodiment of the present disclosure;

[0012] Figure 3B is along Figure 3A a vertical cross-sectional view of the first exemplary structure taken along plane B-B' of;

[0013] Figure 4A is a top view of a first exemplary structure after the formation of a second diffusion barrier layer, the application and patterning of a second photoresist layer, and the transfer of a pattern in the second photoresist layer through the second diffusion barrier layer and the second semiconductor oxide layer according to a first embodiment of the present disclosure;

[0014] Figure 4B is along Figure 4A a vertical cross-sectional view of the first exemplary structure taken along plane B-B' of;

[0015] Figure 4C is at Figure 4A and Figure 4B a vertical cross-sectional view of an alternative embodiment of the first exemplary structure during the process steps of;

[0016] Figure 5A is a top view of a first exemplary structure after an oxidation process for forming a third semiconductor oxide layer according to a first embodiment of the present disclosure;

[0017] Figure 5B is along Figure 5A a vertical cross-sectional view of the first exemplary structure taken along plane B-B' of;

[0018] Figure 5C is at Figure 5A and Figure 5B a vertical cross-sectional view of an alternative embodiment of the first exemplary structure during the process steps of;

[0019] Figure 6A is a top view of a first exemplary structure after the formation of a planarization termination dielectric layer according to a first embodiment of the present disclosure;

[0020] Figure 6B is along Figure 6A a vertical cross-sectional view of the first exemplary structure taken along plane B-B' of;

[0021] Figure 6C is at Figure 6A and Figure 6B a vertical cross-sectional view of an alternative embodiment of the first exemplary structure during the process steps of;

[0022] Figure 7Ais a top view of a first exemplary structure after the formation of the shallow trench according to a first embodiment of the present disclosure;

[0023] Figure 7B is a vertical cross-sectional view of the first exemplary structure along plane B-B' of Figure 7A ;

[0024] Figure 7C is a vertical cross-sectional view of an alternative embodiment of the first exemplary structure during the process steps of Figure 7A and Figure 7B ;

[0025] Figure 8A is a top view of a first exemplary structure after the formation of the dielectric filling material layer according to a first embodiment of the present disclosure;

[0026] Figure 8B is a vertical cross-sectional view of the first exemplary structure along plane B-B' of Figure 8A ;

[0027] Figure 8C is a vertical cross-sectional view of an alternative embodiment of the first exemplary structure during the process steps of Figure 8A and Figure 8B ;

[0028] Figure 9A is a top view of a first exemplary structure after the planarization of the dielectric filling material layer according to a first embodiment of the present disclosure;

[0029] Figure 9B is a vertical cross-sectional view of the first exemplary structure along plane B-B' of Figure 9A ;

[0030] Figure 9C is a vertical cross-sectional view of an alternative embodiment of the first exemplary structure during the process steps of Figure 9A and Figure 9B ;

[0031] Figure 10A is a top view of a first exemplary structure after the removal of the planarization termination dielectric layer, the second diffusion barrier layer, and the first diffusion barrier layer, and the recessing of the dielectric filling material layer according to a first embodiment of the present disclosure;

[0032] Figure 10B is a vertical cross-sectional view of the first exemplary structure along plane B-B' of Figure 10A ;

[0033] Figure 11Ais a top view of a first exemplary structure after the formation of a gate dielectric layer according to a first embodiment of the present disclosure;

[0034] Figure 11B is along Figure 11A a vertical cross-sectional view of the first exemplary structure taken along plane B-B' of;

[0035] Figure 12A is a top view of a first exemplary structure after the formation of a plurality of gate stack structures and a plurality of extension regions according to a first embodiment of the present disclosure;

[0036] Figure 12B is along Figure 12A a vertical cross-sectional view of the first exemplary structure taken along plane B-B' of;

[0037] Figure 13A is a top view of a first exemplary structure after the formation of a plurality of semiconductor-on-insulator field effect transistors according to a first embodiment of the present disclosure;

[0038] Figure 13B is along Figure 13A a vertical cross-sectional view of the first exemplary structure taken along plane B-B' of;

[0039] Figure 14A is a top view of a first exemplary structure after the formation of a contact layer dielectric and a plurality of contact via structures according to a first embodiment of the present disclosure;

[0040] Figure 14B is along Figure 14A a vertical cross-sectional view of the first exemplary structure taken along plane B-B' of;

[0041] Figure 15A is a top view of a second exemplary structure after the formation of a silicon oxide cushion layer and a silicon nitride cushion layer on the top surface of a semiconductor-on-insulator substrate according to a second embodiment of the present disclosure;

[0042] Figure 15B is along Figure 15A a vertical cross-sectional view of the second exemplary structure taken along plane B-B' of;

[0043] Figure 16A is a top view of a second exemplary structure after the formation of shallow trenches according to a second embodiment of the present disclosure;

[0044] Figure 16B is along Figure 16A a vertical cross-sectional view of the second exemplary structure taken along plane B-B' of;

[0045] Figure 17AIt is a top view of a second exemplary structure after the formation of a shallow trench isolation structure according to a second embodiment of the present disclosure;

[0046] Figure 17B It is a Figure 17A vertical cross-sectional view of the second exemplary structure along plane B-B';

[0047] Figure 18A It is a top view of a second exemplary structure after the removal of a silicon nitride cushion layer and a silicon oxide cushion layer according to a second embodiment of the present disclosure;

[0048] Figure 18B It is a Figure 18A vertical cross-sectional view of the second exemplary structure along plane B-B';

[0049] Figure 19A It is a top view of a second exemplary structure after the formation of a first gate dielectric layer according to a second embodiment of the present disclosure;

[0050] Figure 19B It is a Figure 19A vertical cross-sectional view of the second exemplary structure along plane B-B';

[0051] Figure 20A It is a top view of a second exemplary structure after vertically recessing a second substrate region and a third substrate region while protecting a first substrate region with a first patterned photoresist layer according to a second embodiment of the present disclosure;

[0052] Figure 20B It is a Figure 20A vertical cross-sectional view of the second exemplary structure along plane B-B';

[0053] Figure 21A It is a top view of a second exemplary structure after the formation of a second gate dielectric layer according to a second embodiment of the present disclosure;

[0054] Figure 21B It is a Figure 21A vertical cross-sectional view of the second exemplary structure along plane B-B';

[0055] Figure 22A It is a top view of a second exemplary structure after vertically recessing a third substrate region while protecting a first substrate region and a second substrate region with a second patterned photoresist layer according to a second embodiment of the present disclosure;

[0056] Figure 22B It is a Figure 22A vertical cross-sectional view of the second exemplary structure along plane B-B';

[0057] Figure 23A is a top view of a second exemplary structure after the formation of a third gate dielectric layer, according to a second embodiment of the present disclosure;

[0058] Figure 23B is along Figure 23A a vertical cross-sectional view of the second exemplary structure along plane B-B' of;

[0059] Figure 24A is a top view of a second exemplary structure after the formation of a plurality of gate stack structures and a plurality of extension regions, according to a second embodiment of the present disclosure;

[0060] Figure 24B is along Figure 24A a vertical cross-sectional view of the second exemplary structure along plane B-B' of;

[0061] Figure 25A is a top view of a second exemplary structure after the formation of a semiconductor-on-insulator field effect transistor, according to a second embodiment of the present disclosure;

[0062] Figure 25B is along Figure 25A a vertical cross-sectional view of the second exemplary structure along plane B-B' of;

[0063] Figure 26A is a top view of a second exemplary structure after the formation of a contact layer dielectric layer and a plurality of contact via structures, according to a second embodiment of the present disclosure;

[0064] Figure 26B is along Figure 26A a vertical cross-sectional view of the second exemplary structure along plane B-B' of;

[0065] Figure 27 is a first flowchart illustrating a plurality of steps for forming a first exemplary structure of the present disclosure according to an embodiment of the present disclosure;

[0066] Figure 28 is a second flowchart illustrating a plurality of steps for forming a second exemplary structure of the present disclosure according to an embodiment of the present disclosure.

[0067]

Symbol Description

[0068] 4: Processing substrate

[0069] 6: Insulating layer

[0070] 8: Semiconductor-on-insulator substrate

[0071] 10A: First matrix region

[0072] 10A’: Additional substrate region

[0073] 10A”: Additional substrate region

[0074] 10B: Second substrate region

[0075] 10C: Third substrate region

[0076] 10L: Top semiconductor layer

[0077] 11: Shallow trench

[0078] 12: Shallow trench isolation structure

[0079] 12A: First shallow trench isolation part (part of the shallow trench isolation structure)

[0080] 12B: Second shallow trench isolation part (part of the shallow trench isolation structure)

[0081] 12C: Third shallow trench isolation part (part of the shallow trench isolation structure)

[0082] 12D: Fourth shallow trench isolation part (additional part of the shallow trench isolation structure)

[0083] 12L: Dielectric fill material layer

[0084] 14: Silicon oxide cushion layer

[0085] 16: Planarization termination dielectric layer

[0086] 17: Photoresist layer

[0087] 100: First device region (first region)

[0088] 116: Silicon nitride cushion layer

[0089] 141: First diffusion barrier layer

[0090] 142: Second semiconductor oxide layer

[0091] 143: Third semiconductor oxide layer

[0092] 161: First diffusion barrier layer

[0093] 162: Second diffusion barrier layer

[0094] 167A: First photoresist layer

[0095] 167B: Second photoresist layer

[0096] 200: Second device region (second region)

[0097] 2710: Step

[0098] 2720: Step

[0099] 2730: Step

[0100] 2740: Step

[0101] 2750: Step

[0102] 2760: Step

[0103] 2810: Step

[0104] 2820: Step

[0105] 2830: Step

[0106] 2840: Step

[0107] 31A: Source extension region

[0108] 31A”: Source extension region

[0109] 31B: Source extension region

[0110] 31C: Source extension region

[0111] 32A: Source region

[0112] 32A”: Source region

[0113] 32B: Source region

[0114] 32C: Source region

[0115] 38A: Drain region

[0116] 38A’: Drain region

[0117] 38B: Drain region

[0118] 38C: Drain region

[0119] 39A: Drain extension region

[0120] 39A’: Drain extension region

[0121] 39B: Drain extension region

[0122] 39C: Drain extension region

[0123] 300: Third device region (second region, third region)

[0124] 42A: Source-side metal-semiconductor alloy region

[0125] 42B: Source-side metal-semiconductor alloy region

[0126] 42C: Source-side metal-semiconductor alloy region

[0127] 48A: Drain-side metal-semiconductor alloy region

[0128] 48B: Drain-side metal-semiconductor alloy region

[0129] 48C: Drain-side metal-semiconductor alloy region

[0130] 50A: Gate stack structure

[0131] 50B: Gate stack structure

[0132] 50C: Gate stack structure

[0133] 52A: Gate dielectric layer

[0134] 52B: Gate dielectric layer

[0135] 52C: Gate dielectric layer

[0136] 54A: Gate electrode

[0137] 54B: Gate electrode

[0138] 54C: Gate electrode

[0139] 56A: Gate spacer

[0140] 56B: Gate spacer

[0141] 56C: Gate spacer

[0142] 58A: Gate capping dielectric

[0143] 58B: Gate capping dielectric

[0144] 58C: Gate capping dielectric

[0145] 67A: First photoresist layer (first etch mask layer)

[0146] 67B: Second photoresist layer

[0147] 70: Contact-level dielectric layer

[0148] 72A: Contact via structure

[0149] 72B: Contact via structure

[0150] 72C: Contact via structure

[0151] 75A: Contact via structure

[0152] 75B: Contact via structure

[0153] 75C: Contact hole structure of the contact

[0154] 78A: Contact hole structure of the contact

[0155] 78B: Contact hole structure of the contact

[0156] 78C: Contact hole structure of the contact

[0157] B - B’: Plane

[0158] α: Average tilt angle

[0159] β: Average tilt angle

[0160] γ: Average tilt angle Detailed implementation manners

[0161] The following disclosure provides many different implementation manners or embodiments to implement different features of the provided subject matter. The following describes specific embodiments of components and configurations to simplify the present disclosure. Of course, these are only embodiments and are not intended to limit. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the purpose of simplicity and clarity, and the repetition itself does not imply a relationship between the various embodiments and / or configurations discussed.

[0162] In addition, spatially relative terms such as "below", "beneath", "lower", "above", "higher" and the like may be used herein to facilitate the description of the relationship between one element or feature and other elements or features as depicted in the drawings. In addition to covering the directions depicted in the drawings, spatially relative terms are intended to cover different directions of the device during use or operation. The device may have other directions (rotated 90 degrees or other directions), and the spatially relative terms used herein may be interpreted accordingly. Unless otherwise explicitly stated, it is assumed that each element with the same reference numeral has the same material composition and has a thickness within the same thickness range.

[0163] The present disclosure generally relates to semiconductor devices, and more particularly to semiconductor devices including multiple semiconductor-on-insulator (SOI) field-effect transistors, and to methods of forming such semiconductor devices. These SOI field-effect transistors are located on a same SOI substrate and have different thicknesses for multiple substrate regions. The top semiconductor layer of the SOI substrate can be patterned into multiple substrate regions laterally surrounded by a shallow trench isolation structure. Different substrate regions can be selectively thinned using a combination of a patterned oxidation mask structure and an oxidation process that oxidizes multiple upper portions of the multiple unmasked substrate regions, or using a combination of a patterned etching mask structure and an etching process that etches multiple upper portions of the multiple unmasked substrate regions. Each of the above embodiments is discussed in detail below.

[0164] Referring to Figure 1A and Figure 1B , there is shown a first exemplary structure in accordance with a first embodiment of the present disclosure, which includes a semiconductor-on-insulator substrate 8 that includes a top semiconductor layer 10L. The semiconductor-on-insulator substrate 8 includes, from bottom to top: a handle substrate 4, an insulating layer 6 (which is also referred to as a buried insulating layer), and a top semiconductor layer 10L. The handle substrate 4 can include any material that can provide mechanical support for multiple overlying layers and can have a thickness in the range from 60 nm (nanometers) to 2 mm (millimeters), such as from 120 nm to 800 microns, but smaller and larger thicknesses can also be used. The handle substrate 4 can include a semiconductor material (such as silicon), an insulating material, or a conductive material. For example, the handle substrate 4 can include a semiconductor material. The insulating layer 6 includes an insulating material such as silicon oxide and can have a thickness in the range from 50 nm to 600 nm, such as from 100 nm to 300 nm, but smaller and larger thicknesses can also be used. For example, the semiconductor-on-insulator substrate 8 can be a commercially available single-crystalline semiconductor-on-insulator substrate.

[0165] The top semiconductor layer 10L can include a single-crystalline semiconductor material or a polycrystalline semiconductor material. In one embodiment, the entirety of the top semiconductor layer 10L can include a single-crystalline semiconductor layer material such as single-crystalline silicon. The thickness of the top semiconductor layer 10L can be in the range from 300 nm to 600 nm, but smaller and larger thicknesses can also be used. In one embodiment, the thickness of the top semiconductor layer 10L can be selected to be thick enough to form a partially depleted semiconductor-on-insulator field-effect transistor (SOI FET) thereon. The semiconductor material of the top semiconductor layer 10L can be doped with a first conductivity type, which can be p-type or n-type. The atomic concentration of the dopant of the first conductivity type in the top semiconductor layer 10L can be in the range from 1.0x10 14 / cm 3to 3.0x10 17 / cm 3 within the range, but smaller and larger atomic concentrations may also be used. In one embodiment, the top semiconductor layer 10L may include silicon and a dopant of a first conductivity type.

[0166] The first semiconductor oxide layer 141 may be formed on the top surface of the top semiconductor layer 10L. The first semiconductor oxide layer 141 may be deposited via a conformal or non-conformal deposition process, or may be formed by oxidation of a surface portion of the top semiconductor layer 10L. In an embodiment where the first semiconductor oxide layer 141 is formed by oxidation of a surface portion of the top semiconductor layer 10L, the initially provided thickness of the top semiconductor layer 10L may be thicker such that the thickness of the top semiconductor layer 10L after the oxidation process may be within the range from 200 nm to 500 nm, but smaller and larger thicknesses may also be used. The thickness of the first semiconductor oxide layer 141 may be within the range from 20 nm to 400 nm, for example within the range from 40 nm to 200 nm, but smaller and larger thicknesses may also be used. The first semiconductor oxide layer 141, if present, may function as a stress reliever that reduces stress on the top semiconductor layer 10L during subsequent process steps such as oxidation processes and chemical mechanical planarization processes.

[0167] The first exemplary structure may include a plurality of regions for forming a plurality of devices (e.g., a plurality of field effect transistors). For example, the first exemplary structure may include a first device region 100 for forming a first semiconductor-on-insulator field effect transistor, a second device region 200 for forming a second semiconductor-on-insulator field effect transistor, and a third device region 300 for forming a third semiconductor-on-insulator field effect transistor. The region (portion) of the top semiconductor layer 10L within the first device region 100 is referred to herein as the first region of the top semiconductor layer 10L, the region of the top semiconductor layer 10L within the second device region 200 is referred to herein as the second region of the top semiconductor layer 10L, and the region of the top semiconductor layer 10L within the third device region 300 is referred to as the third region of the top semiconductor layer 10L. The top semiconductor layer 10L may include a plurality of additional regions in which a plurality of additional devices may be subsequently formed.

[0168] See Figure 2A and Figure 2B, a first diffusion barrier layer 161 may be disposed over a top surface of the first semiconductor oxide layer 141. The first diffusion barrier layer 161 includes a material that blocks or impedes the diffusion of oxygen atoms through this layer. For example, the first diffusion barrier layer 161 may include silicon nitride or silicon carbide. The first diffusion barrier layer 161 may be deposited via a conformal or non-conformal deposition process and may have a thickness in the range from 10 nm to 40 nm, although smaller and larger thicknesses may also be used.

[0169] A first photoresist layer 167A may be applied over the first diffusion barrier layer 161 and may be lithographically patterned to cover portions of the first diffusion barrier layer 161 in the first device region 100 but not cover portions of the first diffusion barrier layer 161 in the second device region 200 or in the third device region 300. Depending on whether thinning of multiple portions of the top semiconductor layer 10L within each additional device region is desired, multiple additional portions of the first diffusion barrier layer 161 in multiple additional device regions may or may not be covered.

[0170] Using an etching process, through the first diffusion barrier layer 161 and the first semiconductor oxide layer 141, the pattern in the first photoresist layer 167A may be transferred. The etching process may include an isotropic etching process (e.g., a wet etching process) or may include an anisotropic etching process (e.g., a reactive ion etching process). During the etching process, portions of the first diffusion barrier layer 161 and portions of the first semiconductor oxide layer 141 may be removed from the second region 200 and the third region 300 above the top semiconductor layer 10L. Thus, the first region 100 of the top semiconductor layer 10L is covered by the first diffusion barrier layer 161, and the second region 200 and the third region 300 of the top semiconductor layer 10L are physically exposed. Subsequently, the first photoresist layer 167A may be removed, e.g., via ashing.

[0171] Subsequently, the first diffusion barrier layer 161 may be used to prevent or impede the oxidation of multiple portions of the underlying top semiconductor layer 10L. Silicon nitride or silicon carbide is effective as a diffusion barrier material. Thus, the first diffusion barrier layer 161 in the first region 100 may provide a significant thickness difference between different regions of the top semiconductor layer 10L through subsequent oxidation processes.

[0172] See Figure 3A and Figure 3B, an oxidation process is performed to convert multiple uncovered surface portions of the top semiconductor layer 10L into a semiconductor oxide layer, which is referred to herein as the second semiconductor oxide layer 142. The oxidation process may include a thermal oxidation process or a plasma oxidation process. Multiple surface portions of the second region 200 and the third region 300 of the top semiconductor layer 10L are converted into the second semiconductor oxide layer 142. As a result, the second region 200 and the third region 300 of the top semiconductor layer 10L are thinned via the oxidation process. During the oxidation process, the first diffusion barrier layer 161 impedes and / or prevents the oxidation of the first region 100 of the top semiconductor layer 10L. After the oxidation process, the thicknesses of the second region 200 and the third region 300 of the top semiconductor layer 10L are less than the thickness of the first region 100 of the top semiconductor layer 10L. The thicknesses of the second region 200 and the third region 300 of the top semiconductor layer 10L may be in the range of 20% to 80% of the thickness of the top semiconductor layer 10L provided at the process steps such as Figure 1A and Figure 1B . For example, the thicknesses of the second region 200 and the third region 300 of the top semiconductor layer 10L may be in the range from 30 nm to 150 nm, such as from 50 nm to 100 nm, but smaller and larger thicknesses may also be used. The first diffusion barrier layer 161 minimizes the reduction in the thickness of the top semiconductor layer 10L in the first region 100, thereby providing a significant thickness difference between multiple portions of the top semiconductor layer 10L in the second region 200 and the third region 300 and the portion of the top semiconductor layer 10L in the first region 100. Alternatively, in embodiments where at least one first diffusion barrier layer includes only the first semiconductor oxide layer 141, the thickness of the first region 100 of the top semiconductor layer 10L may be reduced in parallel to an extent less than the reduced thicknesses in the second and third regions (200, 300) of the top semiconductor layer 10L. The second semiconductor oxide layer 142 is adjacent to the first semiconductor oxide layer 141 at its periphery.

[0173] Referring to Figure 4A and Figure 4B , a second diffusion barrier layer 162 may be deposited on the top surface of the first diffusion barrier layer 161 and above the second semiconductor oxide layer 142. The second diffusion barrier layer 162 includes a material that blocks the diffusion of oxygen atoms through this layer. For example, the second diffusion barrier layer 162 may include silicon nitride or silicon carbide. The deposition of the second diffusion barrier layer 162 may be via a conformal or non-conformal deposition process and may have a thickness in the range from 10 nm to 40 nm, but smaller and larger thicknesses may also be used.

[0174] The second photoresist layer 167B can be applied over the second diffusion barrier layer 162 and can be lithographically patterned to cover portions of the second diffusion barrier layer 162 in the first device region 100 and in the second device region 200, without covering portions of the second diffusion barrier layer 162 in the third device region 300. Depending on whether subsequent thinning of portions of the top semiconductor layer 10L within each additional device region is desired, additional portions of the second diffusion barrier layer 162 in the plurality of additional device regions may or may not be covered.

[0175] Using an etching process, the pattern in the second photoresist layer 167B can be transferred through the second diffusion barrier layer 162 and the second semiconductor oxide layer 142. The etching process can include an isotropic etching process (e.g., a wet etching process), or can include an anisotropic etching process (e.g., a reactive ion etching process). During the etching process, portions of the second diffusion barrier layer 162 and portions of the second semiconductor oxide layer 142 are removed from a third region 300 that is above the top semiconductor layer 10L. Thus, the first region 100 and the second region 200 of the top semiconductor layer 10L are covered by the second diffusion barrier layer 162, and the third region 300 of the top semiconductor layer 10L is physically exposed. The second photoresist layer 167B can then be removed, e.g., via ashing.

[0176] Typically, the third region 300 of the top semiconductor layer 10L can be physically exposed while the first region 100 of the top semiconductor layer 10L is covered by the first diffusion barrier layer 161 and while the second region of the top semiconductor layer 10L is covered by a semiconductor oxide portion (which is formed via oxidation of a surface portion of the second region 200 of the top semiconductor layer 10L, i.e., the second semiconductor oxide layer 142) and by the second diffusion barrier layer 162.

[0177] See Figure 4C , which illustrates an alternative embodiment of the first exemplary structure, which can be obtained from the first exemplary structure of Figure 4A and Figure 4B by removing the first diffusion barrier layer 161 after the process steps of Figure 3A and Figure 3B (i.e., before the formation of the second diffusion barrier layer 162). In such an embodiment, the first diffusion barrier layer 161 can be removed with selectivity with respect to the top semiconductor layer 10L, the second semiconductor oxide layer 142, and the first semiconductor oxide layer 141. For example, a wet etching process can be used to remove the first diffusion barrier layer 161. In such an embodiment, the second diffusion barrier layer 162 can be formed directly on the top surface of the second semiconductor oxide layer 142 and on the first semiconductor oxide layer 141.

[0178] SeeFigure 5A and Figure 5B ,an oxidation process is performed to convert the unmasked surface portion of the top semiconductor layer 10L into a semiconductor oxide layer, which is herein referred to as the third semiconductor oxide layer 143. The oxidation process may include a thermal oxidation process or a plasma oxidation process. The surface portion of the third region 300 of the top semiconductor layer 10L is converted into the third semiconductor oxide layer 143. As a result, the third region 300 of the top semiconductor layer 10L is thinned via the oxidation process. The first and second diffusion barrier layers (161, 162) impede the oxidation of the first region 100 and the second region 200 of the top semiconductor layer 10L during the oxidation process. After the oxidation process, the thickness of the third region 300 of the top semiconductor layer 10L is less than the thickness of the second region 200 of the top semiconductor layer 10L. The thickness of the third region 300 of the top semiconductor layer 10L may be in the range of 2% to 50% of the thickness of the top semiconductor layer 10L as provided in the process steps such as in Figure 1A and Figure 1B . For example, the thicknesses of the second region 200 and the third region 300 of the top semiconductor layer 10L may be in the range from 30 nm to 150 nm, such as from 50 nm to 100 nm, but smaller and larger thicknesses may also be used. The second diffusion barrier layer 162 minimizes the reduction in the thickness of multiple portions of the top semiconductor layer 10L located in the first region 100 and the second region 200, thereby increasing the thickness difference between the portion of the top semiconductor layer 10L in the third region 300 and the multiple portions of the top semiconductor layer 10L with respect to the first region 100 and the second region 200. Alternatively, in embodiments where the second diffusion barrier layer 162 is not used as at least one of the second diffusion barrier layers, the thickness of the second region 200 of the top semiconductor layer 10L may be reduced to a lesser extent in parallel, less than the extent of the thickness reduction in the third region 300 of the top semiconductor layer 10L. The third semiconductor oxide layer 143 is adjacent to the second semiconductor oxide layer 142 at a first portion of its periphery and may be adjacent to the first semiconductor oxide layer 141 at a second portion of its periphery.

[0179] Referring to Figure 5C , an alternative embodiment of the first exemplary structure is illustrated, which may be obtained from the structure of Figure 4C by performing the process steps of Figure 5A and Figure 5B .

[0180] Referring to Figure 6A and Figure 6B, a planarization termination dielectric layer 16 may be formed over the second diffusion barrier layer 162 and the third semiconductor oxide layer 143. The planarization termination dielectric layer 16 includes a dielectric material that functions as a termination layer during a subsequent planarization process that planarizes a dielectric fill material for a shallow trench isolation structure. For example, the planarization termination dielectric layer 16 may include silicon nitride. Forming the planarization termination dielectric layer 16 may occur after thinning a second region 200 of the top semiconductor layer 10L and a third region 300 of the top semiconductor layer 10L. Generally, the planarization termination dielectric layer 16 may be formed over the second diffusion barrier layer 162, which includes over the first diffusion barrier layer 161 and a semiconductor oxide portion (formed by oxidation of a surface portion of the second region 200 of the top semiconductor layer 10L, i.e., the second semiconductor oxide layer 142). The top surface of the planarization termination dielectric layer 16 may include a plurality of horizontal surface segments and a plurality of non-horizontal surface segments, the plurality of horizontal surface segments being separated from the insulating layer 6 by different vertical separation distances, and the plurality of horizontal surface segments connecting adjacent pairs of the plurality of horizontal surface segments. In other words, the top surface of the planarization termination dielectric layer 16 includes topographical features that include a plurality of horizontal surfaces and a plurality of non-horizontal surfaces that connect these horizontal surfaces to each other. The non-horizontal surfaces may be tapered or vertical and may include a plurality of curved surface segments. The height of the topographical variation in the top surface of the planarization termination dielectric layer 16 may be in the range from 50 nm to 300 nm, although smaller and larger thicknesses may also be used.

[0181] According to an embodiment of the present disclosure, by selecting the thickness of the first semiconductor oxide layer 141, the height of the topographical variation in the top surface of the planarization termination dielectric layer 16 can be minimized such that the height of the top surface of the first semiconductor oxide layer 141 is approximately at the height of the top surface of the third semiconductor oxide layer 143. Generally, silicon oxide derived from single crystal silicon undergoes a volume expansion of about 117%. In other words, the volume of the silicon oxide material portion after oxidation of the single crystal silicon portion is about 217% of the volume of the single crystal silicon portion. Thus, the thickness of the first semiconductor oxide layer 141 can be selected such that the height of the top surface of the third semiconductor oxide layer 143 is within 100 nm and / or 50 nm of the height of the top surface of the first semiconductor oxide layer 141. In one embodiment, the top surface of the second semiconductor oxide layer 142 can be within 150 nm and / or 75 nm of the top surface of the first semiconductor oxide layer 141. According to an embodiment of the present disclosure, the total topographical variation in the top surface of the planarization termination dielectric layer 16 along the vertical direction can be less than 50% of the initial thickness of the top semiconductor layer 10L and / or less than 25%. For example, the total topographical variation in the top surface of the planarization termination dielectric layer 16 along the vertical direction can be in the range from 1% to 50% of the initial thickness of the top semiconductor layer 10L, such as from 3% to 25%.

[0182] See Figure 6C , which illustrates an alternative embodiment of the first exemplary structure, which can be obtained from Figure 5C the structure by removing the second diffusion barrier layer 162 before performing the process steps of Figure 6A and Figure 6B , or by removing the second diffusion barrier layer 162 and the first diffusion barrier layer 161 from the structure of Figure 6A and Figure 6B before performing the process steps of Figure 5A and Figure 5B . In such an embodiment, the planarization termination dielectric layer 16 can be formed directly on the top surface of the first semiconductor oxide layer 141 and on the top surface of the second semiconductor oxide layer 142.

[0183] See Figure 7A and Figure 7B, a photoresist layer 17 may be applied over the top surface of the planarization stop dielectric layer 16 and may be lithographically patterned to cover multiple discrete regions of the top semiconductor layer 10L. For example, a first region of the top semiconductor layer 10L within the region of the first device region 100 may be covered, a second region of the top semiconductor layer 10L within the region of the second device region 200 may be covered, a third region of the top semiconductor layer 10L within the region of the third device region 300 may be covered, and so on. In one embodiment, the regions covered by the multiple patterned portions of the photoresist layer 17 may include multiple rectangular regions.

[0184] An anisotropic etching process may be performed to transfer the pattern in the photoresist layer 17 through the planarization stop dielectric layer 16, the respective diffusion barrier layers (161, 162), the respective semiconductor oxide layers (141, 142, 143), and the top semiconductor layer 10L. The anisotropic etching process may include an etching step that etches each of the underlying material layers without selectivity, and / or may include multiple etching steps that etch a material of a particular material layer selectively with respect to a material of an underlying material layer. In an illustrative embodiment, the anisotropic etching process may include: a first etching step that etches a plurality of materials of the planarization stop dielectric layer 16 and the respective diffusion barrier layers (161, 162) selectively with respect to the respective semiconductor oxide layers (141, 142, 143); a second etching step that etches the materials of the respective semiconductor oxide layers (141, 142, 143) selectively with respect to the top semiconductor layer 10L, or non-selectively with respect to the material of the top semiconductor layer 10L (i.e., at approximately the same etching rate); and a third etching step that etches the material of the top semiconductor layer 10L selectively with respect to the material of the insulating layer 6.

[0185] Shallow trenches 11 are formed in a plurality of volumes from which a plurality of materials including the planarization termination dielectric layer 16, the respective diffusion barrier layers (161, 162), and the respective semiconductor oxide layers (141, 142, 143) are removed. The shallow trenches 11 divide the remaining portions of the planarization termination dielectric layer 16, the respective diffusion barrier layers (161, 162), the respective semiconductor oxide layers (141, 142, 143), and the top semiconductor layer 10L into a plurality of separated layer stacks that are laterally spaced apart from each other. The patterned portions of the top semiconductor layer 10L may include a plurality of substrate regions (10A, 10B, 10C, 10A’, 10A”), which can be used to form a plurality of semiconductor-on-insulator (SOI) field-effect transistors (FETs). For example, the patterned portion of the top semiconductor layer 10L in the first device region 100 may include a first substrate region 10A, the patterned portion of the top semiconductor layer 10L in the second device region 200 may include a second substrate region 10B, and the patterned portion of the top semiconductor layer 10L in the third device region 300 may include a third substrate region 10C. Further, a plurality of additional substrate regions (10A’, 10A”) may be formed in a plurality of additional device regions. For example, a first additional substrate region 10A’ and a second additional substrate region 10A” are illustrated in Figure 7A and Figure 7B . Depending on the patterns of the first diffusion barrier layer 161 and the second diffusion barrier layer 162 used during the oxidation process, such additional substrate regions (10A’, 10A”) may have the same thickness as any one of the first substrate region 10A, the second substrate region 10B, or the third substrate region 10C.

[0186] Each of the first substrate region 10A, the second substrate region 10B, and the third substrate region 10C may have respective sets of tapered sidewalls that are exposed to the shallow trenches 11. The taper angle of the tapered sidewalls of the substrate regions (10A, 10B, 10C, 10A’, 10A”) in the vertical direction may be in the range from 0.1 degrees to 10 degrees, for example, in the range from 0.2 degrees to 5 degrees. Subsequently, the photoresist layer 17 may be removed, for example, via ashing.

[0187] Referring to Figure 7C , an alternative embodiment of the first exemplary structure during the process steps illustrated in Figure 7A and Figure 7B . This alternative embodiment of the first exemplary structure may be derived from the structure of Figure 6C by performing the process steps of Figure 7A and Figure 7B .

[0188] Referring to Figure 8A andFigure 8B The dielectric fill material may be conformally deposited in the shallow trench 11 and over the planarization stop dielectric layer 16 to form a dielectric fill material layer 12L. The dielectric fill material includes a planarizable dielectric material, such as undoped silicate glass or doped silicate glass. Optionally, a reflow process (e.g., annealing at an elevated temperature) may be performed to cause the dielectric fill material to reflow in the shallow trench 11 without voids or with a minimum void volume. The profile of the top surface of the dielectric fill material layer 12L generally replicates the profile of the top surface of the planarization stop dielectric layer 16.

[0189] Refer to Figure 8C which shows an alternative embodiment of the first exemplary structure during the process steps of Figure 8A and Figure 8B An alternative embodiment of the first exemplary structure can be obtained from the structure of Figure 8B by performing the process steps of FIG. 8A and Figure 7C .

[0190] Refer to Figure 9A and Figure 9B A chemical mechanical planarization process may be performed to remove portions of the dielectric fill material layer 12L from above the top surface of the planarization stop dielectric layer 16. A high down pressure may be used to cause dishing of the polished surface of the dielectric fill material layer 12L and to remove portions of the dielectric fill material layer 12L from multiple bottommost regions above the top surface of the planarization stop dielectric layer 16. In some embodiments, multiple surface portions of the planarization stop dielectric layer 16 may be removed during the planarization process. After the planarization process, the top surface of the planarization stop dielectric layer 16 may be physically exposed in each device region (100, 200, 300). After the chemical mechanical planarization process, multiple remaining portions of the dielectric fill material may extend over multiple first segments of the top surface of the planarization stop dielectric layer 16 adjacent to the shallow trench 11, and multiple second segments of the top surface of the planarization stop dielectric layer 16 that are laterally spaced from the shallow trench 11 may be physically exposed.

[0191] Refer to Figure 9C which shows an alternative embodiment of the first exemplary structure during the process steps of Figure 9A and Figure 9B An alternative embodiment of the first exemplary structure can be obtained from the structure of Figure 9A by performing the process steps of Figure 9B and Figure 8C .

[0192] Refer to Figure 10A and Figure 10B, a first isotropic etching process can be performed to isotropically etch the planarization termination dielectric layer 16, which is selective with respect to the dielectric filling material. During the first isotropic etching process, the second diffusion barrier layer 162 and the first diffusion barrier layer 161 can be removed. In an illustrative embodiment, the planarization termination dielectric layer 16 can include silicon nitride, and the first isotropic etching process can include a wet etching process using hot phosphoric acid.

[0193] Subsequently, by performing a second isotropic etching process, each semiconductor oxide layer (141, 142, 143) (i.e., multiple semiconductor oxide portions formed above the top semiconductor layer 10L during the Figure 1A and Figure 1B , Figure 3A and Figure 3B , and Figure 5A and Figure 5B process steps) and the dielectric filling material of the dielectric filling material layer 12L can be simultaneously and isotropically removed, which is selective with respect to the substrate regions (10A, 10B, 10C, 10A', 10A"). For example, a wet etching process using dilute hydrofluoric acid can be performed to isotropically etch multiple portions of each semiconductor oxide layer (141, 142, 143) and the dielectric filling material layer 12L. Through the second isotropic etching process, each semiconductor oxide layer (142, 142, 143) can be completely removed. The dielectric filling material layer 12L can be isotropically recessed such that multiple remaining portions of the dielectric filling material are located between adjacent pairs of substrate regions (10A, 10B, 10C, 10A', 10A"). The remaining portions of the dielectric filling material constitute the shallow trench isolation structure 12. Generally, forming the shallow trench isolation structure 12 can be achieved by filling the shallow trenches 11 with the dielectric filling material, planarizing the main portion of the dielectric filling material above the planarization termination dielectric layer 16, removing the planarization termination dielectric layer 16 and any diffusion barrier layers (161, 162), and by recessing the dielectric filling material layer 12L and simultaneously removing each semiconductor oxide layer (141, 142, 143).

[0194] Multiple portions of the shallow trench isolation structure 12 can be located between a pair of substrate regions in the substrate regions (10A, 10B, 10C, 10A', 10A") having a height difference. For example, a first shallow trench isolation portion 12A located between the first substrate region 10A and the second substrate region 10B can have a height difference between the upper edge of the first sidewall contacting the first substrate region 10A and the upper edge of the second sidewall contacting the second substrate region 10B.

[0195] Via a continuous top surface of a first shallow trench isolation portion 12A that includes a non-horizontal surface section, upper edges on a first sidewall and upper edges on a second sidewall may be connected. In one embodiment, the first shallow trench isolation portion 12A may have a non-planar, slanted top surface that continuously extends between an upper edge of the first sidewall of the first shallow trench isolation portion 12A that contacts a first substrate region 10A and an upper edge of the second sidewall of the first shallow trench isolation portion 12A that contacts a second substrate region 10B. In one embodiment, the continuous top surface of the first shallow trench isolation portion 12A may include a curved, tapered surface that has no horizontal steps or vertical steps.

[0196] The first substrate region 10A may have a first thickness, the second substrate region 10B may have a second thickness that is less than the first thickness, and the third substrate region 10C may have a third thickness that is less than the second thickness. The shallow trench isolation structure 12 may include a second shallow trench isolation portion 12B that is located between the second substrate region 10B and the third substrate region 10C and that has a curved, tapered surface. The shallow trench isolation structure may include a third shallow trench isolation portion 12C that is located between the third substrate region 10C and an additional substrate region 10A'' that has the first thickness and that has a curved, tapered surface.

[0197] In one embodiment, a plurality of substrate regions (10A, 1B, 10C, 10A', 10A") may include an additional substrate region 10A' that is located adjacent to the first substrate region 10A and has a first thickness. An additional portion of the shallow trench isolation structure 12, such as a fourth shallow trench isolation portion 12D, may be located between the first substrate region 10A and the additional substrate region 10A' and may have a curved top surface that connects the upper edge of the first sidewall of the additional portion of the shallow trench isolation that contacts the first substrate region 10A and the upper edge of the second sidewall of the additional portion of the shallow trench isolation structure 12 (such as the fourth shallow trench isolation portion 12D) that contacts the additional substrate region 10A'. In one embodiment, the first substrate region 10A and the additional substrate region 10A' may have the same thickness (e.g., the first thickness), and the upper edge of the first sidewall of the additional portion of the shallow trench isolation structure 12 and the upper edge of the second sidewall of the additional portion of the shallow trench isolation structure 12 may be located at the same distance from the insulating layer 6. In one embodiment, the central region of the curved top surface may be elevated relative to the upper edge of the first sidewall of the first portion of the additional portion of the shallow trench isolation structure 12 (such as the fourth shallow trench isolation portion 12D). Generally, the plurality of top surfaces of the plurality of portions of the shallow trench isolation structure 12 located between substrate regions (10A, 10B, 10C, 10A', 10A") having different thicknesses may be tapered and curved, and due to the isotropic nature of the etching process of the recessed dielectric fill material 12L, the plurality of top surfaces of the plurality of portions of the shallow trench isolation structure 12 located between a plurality of substrate regions (10A, 10B, 10C, 10A', 10A") having the same thickness may be curved.

[0198] See Figure 11A and Figure 11B , gate dielectric layers (52A, 52B, 52C) are formed on the plurality of top surfaces of the respective substrate regions (10A, 10B, 10C, 10A', 10A"). The formation of the gate dielectric layers (52A, 52B, 52C) may be via thermal oxidation of the plurality of surface portions of the semiconductor material in the respective substrate regions (10A, 10B, 10C, 10A', 10A") and / or via deposition of a gate dielectric material layer (such as an aluminum oxide layer and / or a hafnium oxide layer). In one embodiment, the formation of the gate dielectric layers (52A, 52B, 52C) may be via the same set of process steps and may generally have the same material composition and the same thickness.

[0199] See Figure 12A and Figure 12B, a gate electrode material layer may subsequently be deposited over the gate dielectric layer (52A, 52B, 52C). The gate electrode material layer includes at least one conductive material. For example, the gate electrode material layer may include a metal, an intermetallic alloy, a metal-semiconductor alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal carbide, and a doped semiconductor material (which includes p-type or n-type dopants having an average atomic concentration in the range from 5.0x10 19 / cm 3 to 2.0x10 21 / cm 3 ). The gate electrode material layer may be composed of a single conductive material or a stack of multiple conductive materials. The bottommost material within the gate electrode material layer may be selected to provide a suitable work function for the gate electrode subsequently formed by patterning the gate electrode material layer. Forming the gate electrode material layer may be via chemical vapor deposition, physical vapor deposition, vacuum evaporation, and / or atomic layer deposition. The thickness of the gate electrode material layer may be in the range from 50 nm to 300 nm, although smaller and larger thicknesses may also be used.

[0200] A gate cap dielectric layer may be formed over the gate electrode material layer. The gate cap dielectric layer includes a diffusion barrier layer material, such as silicon nitride. Other suitable materials are within the scope of the concept of the present disclosure. The thickness of the gate cap dielectric layer may be in the range from 20 nm to 60 nm, although smaller and larger thicknesses may also be used.

[0201] A photoresist layer (not shown) may be applied over the gate electrode material layer and may be lithographically patterned to form a plurality of line patterns that extend over a respective region in each of the plurality of device regions. An anisotropic etching process (such as a reactive ion etching process) may be performed to transfer the pattern in the photoresist layer through the layer stack of the gate cap dielectric layer, the gate electrode material layer, and the gate dielectric layer (52A, 52B, 52C). The substrate regions (10A, 10B, 10C, 10A’, 10A”) and the shallow trench isolation structure 12 may be used as etching stop structures.

[0202] Multiple remaining portions of the layer stack of the gate cap dielectric layer, the gate electrode material layer, and the gate dielectric layers (52A, 52B, 52C) include multiple gate stack structures {(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)}. Each gate stack structure {(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)} may include: a first gate stack structure (52A, 54A, 58A) formed in a first device region 100 and including a first gate dielectric layer 52A, a first gate electrode 54A, and a first gate cap dielectric 58A; a second gate stack structure (52B, 54B, 58B) formed in a second device region 200 and including a second gate dielectric layer 52B, a second gate electrode 54B, and a second gate cap dielectric 58B; and a third gate stack structure (52C, 54C, 58C) formed in a third device region 300 and including a third gate dielectric layer 52C, a third gate electrode 54C, and a third gate cap dielectric 58C.

[0203] An extension ion implantation process may be performed to implant dopants of a second conductivity type into multiple unmasked surface portions of multiple substrate regions (10A, 10B, 10C, 10A', 10A"). The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. Multiple implanted surface portions of the multiple substrate regions (10A, 10B, 10C, 10A', 10A") may be converted into multiple doped semiconductor regions doped with the second conductivity type. Source extension regions (31A, 31B, 31C) and drain extension regions (39A, 39B, 39C) may be formed within each device region (100, 200, 300) via the conversion of multiple surface portions of the multiple substrate regions (10A, 10B, 10C, 10A', 10A") into multiple portions of doped semiconductor material doped with the second conductivity type. The average atomic concentration of the dopants of the second conductivity type in the multiple source extension regions (31A, 31B, 31C) and the multiple drain extension regions (39A, 39B, 39C) may be in the range from 1.0x10 19 / cm 3 to 1.0x10 21 / cm 3within a range, but smaller and larger dopant concentrations can also be used. The depths of the multiple source extension regions (31A, 31B, 31C) and the multiple drain extension regions (39A, 39B, 39C) can be within a range from 5 nm to 50 nm, but smaller and larger depths can also be used. Below the gate stack structures {(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)} and located between adjacent pairs of source extension regions (31A, 31B, 31C) and drain extension regions (39A, 39B, 39C), each surface portion of the multiple substrate regions (10A, 10B, 10C, 10A', 10A") contains a semiconductor channel. Each semiconductor channel extends between a source extension region (31A, 31B, 31C) and a drain extension region (39A, 39B, 39C) and can be doped with a dopant of a first conductivity type. Optionally, halo implantation can be performed to implant dopants of the first conductivity type into multiple regions below the multiple gate stack structures {(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)}. Subsequently, the photoresist layer can be removed, for example, via ashing.

[0204] See Figure 13A and Figure 13B, at least one dielectric material (e.g., silicon nitride and / or silicon oxide) can be conformally deposited over multiple gate stack structures 50A, 50B, 50C{(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)}, multiple source extension regions (31A, 31B, 31C), multiple drain extension regions (39A, 39B, 39C), and shallow trench isolation structure 12. At least one dielectric material can be anisotropically etched (e.g., via a reactive ion etching process) to remove multiple horizontal portions. Each remaining vertical portion that laterally surrounds respective gate stack structures{(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)} includes gate spacers (56A, 56B, 56C) that comprise the at least one dielectric material. Although only a single gate spacer (56A, 56B, 56C) is shown around each gate stack structure{(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)}, multiple embodiments are explicitly contemplated herein in which multiple gate spacers are formed on gate stack structures{(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)} by sequentially depositing and anisotropically etching multiple dielectric materials. In one embodiment, gate spacers (56A, 56B, 56C) can laterally surround gate stack structures{(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)} and can be topologically homeomorphic to a torus, i.e., can be continuously deformed into a torus without forming new openings or breaking existing openings. The width of each gate spacer (56A, 56B, 56C) at its base (i.e., the lateral distance between the inner and outer walls) can be in the range from 5 nm to 100 nm, although smaller and larger widths can also be used.

[0205] Dopants of a second conductivity type can be implanted into multiple unmasked portions of multiple source extension regions (31A, 31B, 31C), multiple drain extension regions (39A, 39B, 39C), and multiple portions of underlying multiple substrate regions (10A, 10B, 10C, 10A’, 10A”). The implanted multiple portions of source extension regions (31A, 31B, 31C), drain extension regions (39A, 39B, 39C), and multiple portions of underlying multiple substrate regions (10A, 10B, 10C, 10A’, 10A”) form multiple deep source regions and multiple deep drain regions. The average atomic concentration of dopants of the second conductivity type in the multiple deep source regions and multiple deep drain regions can be from 5.0x10 19 / cm3 to 2.0 x 10 21 / cm 3 within the range, but smaller and larger dopant concentrations can also be used. The average atomic concentration of the dopant of the second conductivity type in the plurality of deep source regions and the plurality of deep drain regions is higher than the average atomic concentration of the dopant of the second conductivity type in the plurality of remaining portions of the plurality of source extension regions (31A, 31B, 31C) and the plurality of drain extension regions (39A, 39B, 39C). The depth of the plurality of deep source regions and the plurality of deep drain regions can be in the range from 5 nm to 300 nm, for example from 10 nm to 100 nm, but smaller and larger depths can also be used. The depth of the plurality of deep source regions and the plurality of deep drain regions can be greater than the depth of the plurality of source extension regions (31A, 31B, 31C) and the plurality of drain extension regions (39A, 39B, 39C).

[0206] The deep source regions and the deep drain regions can be formed within each device region. Each combination of a source extension region (31A, 31B, 31C) and a deep source region constitutes a source region (32A, 32B, 32C), which can include a first source region 32A formed in the first device region 100, a second source region 32B formed in the second device region 200, and a third source region 32C formed in the third device region 300. Each combination of a drain extension region (39A, 39B, 39C) and a deep drain region constitutes a drain region (38A, 38B, 38C), which can include a first drain region 38A formed in the first device region 100, a second drain region 38B formed in the second device region 200, and a third drain region 38C formed in the third device region 300. Generally, the source regions (32A, 32B, 32C) and the drain regions (38A, 38B, 38C) can be formed in each substrate region (10A, 10B, 10C, 10A', 10A") laterally surrounded by the shallow trench isolation structure 12. The semiconductor channel extends between the source regions (32A, 32B, 32C) and the drain regions (38A, 38B, 38C) under the respective gate stack structures {(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)}.

[0207] A semiconductor-on-insulator (SOI) field-effect transistor (FET) can be formed within each device region (100, 200, 300). For example, a first semiconductor-on-insulator field-effect transistor can be formed within and above the first substrate region 10A, a second semiconductor-on-insulator field-effect transistor can be formed within and above the second substrate region 10B, and a third semiconductor-on-insulator field-effect transistor can be formed within and above the third substrate region 10C.

[0208] Refer to Figure 14A and Figure 14B Figure 14B , a dielectric material can be deposited over multiple gate stack structures {(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)}, source regions (32A, 32B, 32C), drain regions (38A, 38B, 38C), and shallow trench isolation structure 12. The dielectric material can include a planarizable dielectric material, such as undoped silicate glass or doped silicate glass, or a self-planarizing dielectric material, such as flowable oxide (FOX). The deposition of the dielectric material can be via a chemical vapor deposition process (e.g., a plasma enhanced chemical vapor deposition process), or via spin coating. The top surface of the dielectric material can be planarized during or after the deposition process. A dielectric material layer having a flat (i.e., horizontal) top surface is formed, and then multiple contact via structures are formed through this dielectric material layer. Thus, the dielectric material layer is referred to herein as the contact level dielectric layer 70. The top surface of the contact level dielectric layer 70 can be flat and can be located above the top surface of the gate capping dielectrics (58A, 58B, 58C). The vertical distance between the top surface of the contact level dielectric layer 70 and the top surface of the gate capping dielectrics (58A, 58B, 58C) can be in the range from 30 nm to 400 nm, but smaller and larger thicknesses can also be used.

[0209] A photoresist layer (not shown) can be applied over the contact level dielectric layer 70 and can be lithographically patterned to form multiple separate openings through this layer. The multiple openings in the photoresist layer can be formed over the source regions (32A, 32B, 32C), drain regions (38A, 38B, 38C), and gate electrodes (54A, 54B, 54C). An anisotropic etching process can be performed to form multiple contact via cavities through the contact level dielectric layer 70. These contact via cavities include: source contact via cavities that extend from the top surface of the contact level dielectric layer 70 to the top surface of a corresponding one of the multiple source regions (32A, 32B, 32C); drain contact via cavities that extend from the top surface of the contact level dielectric layer 70 to the top surface of a corresponding one of the multiple drain regions (38A, 38B, 38C); and gate contact via cavities that extend from the top surface of the contact level dielectric layer 70 to the top surface of a corresponding one of the multiple gate electrodes (54A, 54B, 54C).

[0210] Via a conformal or non-conformal deposition method, a metal that forms a metal semiconductor alloy can be deposited into a plurality of contact via cavities. If the substrate regions (10A, 10B, 10C, 10A’, 10A”) comprise doped silicon and / or consist essentially of doped silicon, the metal can be a material that forms a metal silicide. For example, the metal can include nickel, titanium, tungsten, molybdenum, platinum, or other metals that form metal silicides. An annealing process can be performed at an elevated temperature to induce the formation of the metal silicide material. The elevated temperature can be in the range from 500 degrees Celsius to 750 degrees Celsius. A plurality of unreacted portions of the metal can be removed via a wet etching process that etches the metal selectively with respect to the metal silicide material. The plurality of remaining portions of the metal silicide material include source-side metal semiconductor alloy regions (42A, 42B, 42C) contacting respective source regions (32A, 32B, 32C), drain-side metal semiconductor alloy regions (48A, 48B, 48C) contacting respective drain regions (38A, 38B, 38C), and gate-side metal semiconductor alloy regions (not explicitly shown) contacting respective gate electrodes (54A, 54B, 54C).

[0211] A metal liner including a diffusion barrier material can be deposited at a plurality of peripheral portions of a plurality of remaining volumes of the contact via cavities. The metal liner includes a conductive metal nitride material (such as TiN, TaN, or WN) and / or a metal carbide material (such as TiC, TaC, or WC). The thickness of the metal liner can be in the range from 3 nm to 15 nm, but smaller and larger thicknesses can also be used.

[0212] A metal fill material (such as Cu, W, Mo, Co, Ru, and / or other elemental metals, or intermetallic alloys) can be deposited within the plurality of remaining volumes of the plurality of contact via cavities. Via a planarization process, a plurality of portions of the metal fill material and the metal liner that are located above a horizontal plane including the top surface of the contact level dielectric layer 70 can be removed. Each combination of the remaining portions of the metal fill material and the metal liner that fill a respective one of the plurality of contact via cavities constitutes a contact via structure (72A, 75A, 78A, 72B, 75B, 78B, 72C, 75C, 78C). The contact via structures (72A, 75A, 78A, 72B, 75B, 78B, 72C, 75C, 78C) include: a plurality of source contact via structures (72A, 72B, 72C) that contact respective source side metal semiconductor alloy regions (42A, 42B, 42C); a plurality of drain contact via structures (78A, 78B, 78C) that contact respective drain side metal semiconductor alloy regions (48A, 48B, 48C), and a plurality of gate contact via structures (75A, 75B, 75C) that contact respective gate side metal semiconductor alloy regions or respective gate electrodes (54A, 54B, 54C) (in the case where no gate side metal semiconductor alloy region is formed).

[0213] The average tilt angle α of the top surface of the first shallow trench isolation portion 12A, measured between a horizontal plane and a Euclidean plane (which includes the top edges of the two sidewalls of the first shallow trench isolation portion 12A that respectively contact the first substrate region 10A and the second substrate region 10B), can be in the range from 1 degree to 20 degrees, for example, in the range from 2 degrees to 20 degrees, but smaller and larger angles can also be used. The average tilt angle β of the top surface of the second shallow trench isolation portion 12B, measured between a horizontal plane and a Euclidean plane (which includes the top edges of the two sidewalls of the second shallow trench isolation portion 12B that respectively contact the second substrate region 10B and the third substrate region 10C), can be in the range from 1 degree to 20 degrees, for example, in the range from 2 degrees to 20 degrees, but smaller and larger angles can also be used. The average tilt angle γ of the top surface of the third shallow trench isolation portion 12C, measured between a horizontal plane and a Euclidean plane (which includes the top edges of the two sidewalls of the third shallow trench isolation portion 12C that respectively contact the third substrate region 10C and the additional substrate region 10A''), can be in the range from 1 degree to 20 degrees, for example, in the range from 2 degrees to 20 degrees, but smaller and larger angles can also be used.

[0214] The thickness of the first substrate region 10A and the plurality of additional substrate regions (10A', 10A") can be in the range from 150 nm to 500 nm, for example from 200 nm to 400 nm, but smaller and larger thicknesses can also be used. The thickness of the second substrate region 10B can be in the range from 30 nm to 150 nm, for example from 50 nm to 100 nm, but smaller and larger thicknesses can also be used. The thickness of the third substrate region 10C can be in the range from 10 nm to 70 nm, for example in the range from 30 nm to 50 nm, and smaller and larger thicknesses can also be used.

[0215] See Figures 14A to 14B And in accordance with various embodiments of the present disclosure, a semiconductor structure is provided that includes: a semiconductor-on-insulator substrate 8 that includes a processing substrate 4, an insulating layer 6, and a plurality of substrate regions (10A, 10B, 10C, 10A', 10A") that are laterally surrounded by a shallow trench isolation structure 12, the plurality of substrate regions (10A, 10B, 10C, 10A', 10A") including a first substrate region 10A having a first thickness and a second substrate region 10B having a second thickness that is less than the first thickness; a first semiconductor-on-insulator (SOI) field effect transistor (FET) that includes the first substrate region 10A, a first source region 32A and a first drain region 38A embedded in the first substrate region 10A, and a first gate stack structure (52A, 54A, 58A); and a second semiconductor-on-insulator field effect transistor that includes the second substrate region 10B, a second source region 32B and a second drain region 38B embedded in the second substrate region 10B, and a second gate stack structure (52B, 54B, 58B), wherein: a portion 12A of the shallow trench isolation structure 12 located between the first substrate region 10A and the second substrate region 10B has a height difference between an upper edge of a first sidewall contacting the first substrate region 10A and an upper edge of a second sidewall contacting the second substrate region 10B; and the upper edge of the first sidewall and the upper edge of the second sidewall are connected via a continuous top surface of the portion 12A of the shallow trench isolation structure 12 that includes a non-horizontal surface segment.

[0216] In one embodiment, the continuous top surface of portion 12A of the shallow trench isolation structure 12 includes a tapered surface of the bent region, which has no horizontal steps or vertical steps. In one embodiment, the plurality of substrate regions (10A, 10B, 10C, 10A', 10A") includes an additional substrate region 10' that is located adjacent to the first substrate region 10A and has a first thickness; and an additional portion 12D of the shallow trench isolation structure 12 is located between the first substrate region 10A and the additional substrate region 10A', and has a curved top surface that connects and contacts the upper edge of the first sidewall of the additional portion 12D of the shallow trench isolation structure 12 that contacts the first substrate region 10A and the upper edge of the second sidewall of the additional portion 12D of the shallow trench isolation structure 12 that contacts the additional substrate region 10A'.

[0217] In one embodiment, the upper edge of the first sidewall of the additional portion 12D of the shallow trench isolation structure 12 and the upper edge of the second sidewall of the additional portion 12D of the shallow trench isolation structure 12 are located at the same distance from the insulating layer 6. In one embodiment, the central region of the curved top surface can be elevated relative to the upper edge of the first sidewall of the additional portion 12D of the shallow trench isolation structure 12.

[0218] Multiple types of semiconductor devices (such as multiple field effect transistors) can be formed in the patterned portions of the top semiconductor layer 10L. In one embodiment, the first substrate region 10A, the second substrate region 10B, and the third substrate region 10C have different thicknesses, and multiple different types of field effect transistors can be formed above the first substrate region 10A, the second substrate region 10B, and the third substrate region 10C. In an illustrative embodiment, a first field effect transistor can be formed in the first device region 100 that exhibits device characteristics similar to those of a field effect transistor formed on a bulk semiconductor substrate, a partially depleted silicon-on-insulator (PDSOI) field effect transistor can be formed in the second device region 200, and a fully depleted silicon-on-insulator (FDSOI) field effect transistor can be formed in the third device region 300. Thus, the first exemplary structure of the present disclosure provides for the formation of multiple different types of semiconductor devices on the same substrate.

[0219] See Figure 15A and Figure 15B , according to a second embodiment of the present disclosure, a second exemplary structure can be formed by providing a silicon-on-insulator (SOI) substrate 8, which can be used in Figure 1A and Figure 1Bis the same as the semiconductor-on-insulator substrate 8. A silicon oxide cushion layer 14 and a silicon nitride cushion layer 116 may be formed above the top surface of the semiconductor-on-insulator substrate 8. The silicon oxide cushion layer 14 may include silicon oxide and may have a thickness in the range from 5 nm to 50 nm, but smaller and larger thicknesses may also be used. The silicon nitride cushion layer 116 includes silicon nitride and may have a thickness in the range from 20 nm to 100 nm, but smaller and larger thicknesses may also be used.

[0220] Refer to Figure 16A and Figure 16B , a photoresist layer may be applied above the silicon nitride cushion layer 116 and may be lithographically patterned to cover multiple discrete regions of the top semiconductor layer 10L. For example, a first region of the top semiconductor layer 10L within the region of the first device region 100 may be covered, a second region of the top semiconductor layer 10L within the region of the second device region 200 may be covered, a third region of the top semiconductor layer 10L within the region of the third device region 300 may be covered, and so on. In one embodiment, the multiple regions covered by the multiple patterned portions of the photoresist layer may include multiple rectangular regions.

[0221] An anisotropic etching process may be performed to transfer the pattern in the photoresist layer through the silicon nitride cushion layer 116, the silicon oxide cushion layer 14, and the top semiconductor layer 10L. The anisotropic etching process may include: an etching step that etches each of the underlying material layers without selectivity, and / or multiple etching steps that etch a material of a particular material layer selectively with respect to the material of an underlying material layer. In an illustrative embodiment, the anisotropic etching process may include: a first etching step that etches the material of the silicon nitride cushion layer 116 selectively with respect to the material of the silicon oxide cushion layer 14; a second etching step that etches the silicon oxide cushion layer 14 selectively with respect to the material of the top semiconductor layer 10L or without selectivity with respect to the material of the top semiconductor layer 10L (i.e., at the same etching rate); and a third etching step that etches the material of the top semiconductor layer 10L selectively with respect to the material of the insulating layer 6.

[0222] Shallow trenches 11 are formed in a plurality of volumes from which the silicon nitride liner 116, silicon oxide liner 14, and top semiconductor layer 10L are removed. The shallow trenches 11 divide the remaining portions of the silicon nitride liner 116, silicon oxide liner 14, and top semiconductor layer 10L into a plurality of separated layer stacks that are laterally spaced from each other. The patterned portions of the top semiconductor layer 10L may include a plurality of substrate regions (10A, 10B, 10C, 10A’, 10A”), which can be used to form a plurality of semiconductor-on-insulator (SOI) field-effect transistors (FETs). For example, the patterned portion of the top semiconductor layer 10L in the first device region 100 may include a first substrate region 10A, the patterned portion of the top semiconductor layer 10L in the second device region 200 may include a second substrate region 10B, and the patterned portion of the top semiconductor layer 10L in the third device region 300 may include a third substrate region 10C. Additionally, a plurality of additional substrate regions (10A’, 10A”) may be formed in a plurality of additional device regions. For example, a first additional substrate region 10A’ and a second additional substrate region 10A” may be formed.

[0223] Each of the first substrate region 10A, second substrate region 10B, and third substrate region 10C may have respective sets of tapered sidewalls that are exposed to the shallow trenches 11. The tapered sidewalls of the substrate regions (10A, 10B, 10C, 10A’, 10A”) may have a taper angle in the range from 0.1 degrees to 10 degrees in the vertical direction, for example in the range from 0.2 degrees to 5 degrees. The photoresist layer 17 may then be removed, for example via ashing.

[0224] Referring to Figure 17A and Figure 17B , a dielectric fill material may be conformally deposited in the shallow trenches 11 and over the silicon nitride liner 116 to form a dielectric fill material layer. The dielectric fill material includes a planarizable dielectric material, such as undoped silicate glass or doped silicate glass. Optionally, a reflow process (e.g., annealing at an elevated temperature) may be performed to cause the dielectric fill material to reflow in the shallow trenches 11 without voids or with a minimum void volume.

[0225] An executable recess etching process can be performed to remove multiple portions of the dielectric fill material layer covering the top surface of the silicon nitride cushion layer. In addition, the recess etching process can be continued to vertically recess the top surface of the remaining portion of the dielectric fill material layer below the horizontal plane including the top surface of the silicon nitride cushion layer 116. In one embodiment, the recess etching process can be continued until the top surface of the remaining portion of the dielectric fill material layer is formed between the horizontal plane including the top surface of the silicon nitride cushion layer 116 and the horizontal plane including the bottom surface of the silicon nitride cushion layer 116. The remaining continuous portion of the dielectric fill material includes the shallow trench isolation structure 12.

[0226] Generally, the shallow trench isolation structure 12 can be formed by depositing a dielectric fill material within the shallow trench 11 and above the silicon nitride cushion layer 116, and recessing the dielectric fill material to be below the horizontal plane including the top surface of the silicon nitride cushion layer 116. The remaining portion of the dielectric fill material after recessing the dielectric fill material includes the shallow trench isolation structure 12, which is formed within the shallow trench 11 and contacts the top surface of the insulating layer 6. In one embodiment, the entire top surface of the shallow trench isolation structure 12 can be formed within the same horizontal plane. The shallow trench isolation structure 12 is formed through the top semiconductor layer 10L. The shallow trench isolation structure 12 laterally surrounds multiple patterned portions of the top semiconductor layer 10L including multiple substrate regions (10A, 10B, 10C, 10A', 10A"). The multiple substrate regions (10A, 10B, 10C, 10A', 10A") can include a first substrate region 10A formed in the first device region 100, a second substrate region 10B formed in the second device region 200, and a third substrate region 10C formed in the third device region 300.

[0227] Refer to Figure 18A and Figure 18B Via a first etching process, the silicon nitride cushion layer 116 can be removed. For example, a wet etching process using hot phosphoric acid can be used to remove the silicon nitride cushion layer 116. The silicon oxide cushion layer 14 can subsequently be removed via a second etching process. For example, a wet etching process using dilute hydrofluoric acid can be used to remove the silicon oxide cushion layer 14. Multiple surface portions of the shallow trench isolation structure 12 can be recessed isotropically in parallel during the second etching process. The shallow trench isolation structure 12 can include multiple top surfaces located within the same horizontal plane.

[0228] The shallow trench isolation structure 12 may include a plurality of shallow trench isolation portions (12A, 12B, 12C, 12D) located between a pair of respective adjacent substrate regions (10A, 10B, 10C, 10A', 10A"). For example, the shallow trench isolation structure 12 may include a first shallow trench isolation portion 12A located between the first substrate region 10A and the second substrate region 10B, a second shallow trench isolation portion 12B located between the second substrate region 10B and the third substrate region 10C, a third shallow trench isolation portion 12C located between the third substrate region 10C and the additional substrate region 10A", and an additional shallow trench isolation portion 12D located between the first substrate region 10A and another additional substrate region 10A'.

[0229] See Figure 19A and Figure 19B , a first gate dielectric layer 52A may be formed on the top surfaces of the respective substrate regions (10A, 10B, 10C, 10A', 10A"). The first gate dielectric layer 52A may be formed by thermal oxidation of the surface portions of the semiconductor material in the respective substrate regions (10A, 10B, 10C, 10A', 10A"), and / or by deposition of a gate dielectric material layer (such as an aluminum oxide layer and / or a hafnium oxide layer). In one embodiment, the substrate regions (10A, 10B, 10C, 10A', 10A") may be formed by the same set of process steps and may generally have the same material composition and the same thickness. In one embodiment, the first gate dielectric layer 52A may include a first semiconductor oxide layer formed on the top surfaces of the respective substrate regions (10A, 10B, 10C, 10A', 10A").

[0230] See Figure 20A and Figure 20B, a first photoresist layer 67A may be formed over the second exemplary structure and may be lithographically patterned to form openings in a plurality of regions of the second device region 200 and the third device region 300. A plurality of segments of the first gate dielectric layer 52A located in the second device region 200 and the third device region 300 are physically exposed, while a segment of the first gate dielectric layer 52A located in the first device region 100 is covered by the first photoresist layer 67A. The first photoresist layer 67A is formed over the first substrate region 10A without covering the second substrate region 10B or the third substrate region 10C. An edge of the first photoresist layer 67A may be formed over a part (e.g., the first shallow trench isolation part 12A) of the shallow trench isolation structure 12 located between the first substrate region 10A and the second substrate region 10B. Another edge of the first photoresist layer 67A may be formed over a part (e.g., the third shallow trench isolation part 12C) of the shallow trench isolation structure 12 located between the third substrate region 10C and the additional substrate region 10A".

[0231] An etching process may be performed to remove the plurality of segments of the first gate dielectric layer 52A located in the second device region 200 and the third device region 300, while the segment of the first gate dielectric layer 52A in the first device region 100 is under the first photoresist layer 67A and is protected by the first photoresist layer 67A. For example, a wet process using dilute hydrofluoric acid may be performed to etch the plurality of unmasked segments of the first gate dielectric layer 52A. A plurality of top surfaces of the second substrate region 10B and the third substrate region 10C are physically exposed, while the first substrate region 10A is covered by the first photoresist layer 67A. In such an embodiment, using the first photoresist layer 67A as an etching mask, the second segment of the first gate dielectric layer 52A on the second substrate region 10B and the third segment of the first gate dielectric layer 52A on the third substrate region may be etched. During the etching process, the first segment of the first gate dielectric layer 52A on the first substrate region 10A is covered by the first photoresist layer 67A and is thus not etched during the etching process. The unmasked segments of the part (e.g., the first shallow trench isolation part 12A) of the shallow trench isolation structure 12 are located between the first substrate region 10A and the second substrate region 10B and are etched in parallel during the etching process and may be vertically recessed to provide a recessed vertical surface that vertically offsets the top surface of the non-recessed segment of the part (i.e., the masked segment of the shallow trench isolation part 12A under the first photoresist layer 67A) of the shallow trench isolation structure 12 under the first photoresist layer 67A.

[0232] The second substrate region 10B and the third substrate region 10C can be thinned. Via a subsequent etching process, the second substrate region 10B and the third substrate region 10C can be vertically recessed while protecting the first substrate region 10A with the first etching mask layer. In one embodiment, the first photoresist layer 67A can function as the first etching mask layer. Alternatively, the first photoresist layer 67A can be removed, and the remaining first section of the first gate dielectric layer 52A in the first device region 100 can function as the first etching mask layer. In such an embodiment, the second substrate region 10B and the third substrate region 10C can be vertically recessed using an etching process that etches the materials of the second substrate region 10B and the third substrate region 10C selectively with respect to the first section of the first gate dielectric layer 52A and the materials of the shallow trench isolation structure 12. In an illustrative embodiment, a wet etching process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) can be used to vertically recess the second substrate region 10B and the third substrate region 10C selectively with respect to the first section of the first gate dielectric layer 52A and the materials of the shallow trench isolation structure 12.

[0233] A portion of the shallow trench isolation structure 12 (e.g., the first shallow trench isolation portion 12A) located between the first substrate region 10A and the second substrate region 10B can have a height difference between the upper edge of the first sidewall contacting the first substrate region 10A and the upper edge of the second sidewall contacting the second substrate region 10B. The upper edge of the first sidewall and the upper edge of the second sidewall can be connected via a continuous top surface of the portion of the shallow trench isolation structure 12 that includes a non-horizontal surface section. In one embodiment, the continuous top surface of the portion of the shallow trench isolation structure 12 (e.g., the first shallow trench isolation portion 12A) can include a first horizontal surface section and a second horizontal surface section, the first horizontal surface section adjacent to an edge of the first sidewall of the portion of the shallow trench isolation structure 12 contacting the first substrate region 10A, and the second horizontal surface section adjacent to an edge of the second sidewall of the portion of the shallow trench isolation structure 12 contacting the second substrate region 10B. In various embodiments, in which an anisotropic etching process is used to etch the unmasked portions of the first gate dielectric layer 52A and concurrently etch the unmasked portions of the shallow trench isolation structure 12, a vertical surface section can be adjacent to an edge of the first horizontal surface section and adjacent to an edge of the second horizontal surface section. In various embodiments, in which an isotropic etching process is used to etch the unmasked portions of the first gate dielectric layer 52A and concurrently etch the unmasked regions of the shallow trench isolation structure 12, a tapered concave surface section can be adjacent to an edge of the first horizontal surface section and adjacent to an edge of the second horizontal surface section.

[0234] Refer to Figure 21A and Figure 21B , a second gate dielectric layer 52B may be formed on the top surfaces of a plurality of physically exposed portions of the second substrate region 10B and the third substrate region 10C. The formation of the second gate dielectric layer 52B may be via thermal oxidation of a plurality of surface portions of the semiconductor material in the second substrate region 10B and the third substrate region 10C, and / or via deposition of a gate dielectric material layer (such as an aluminum oxide layer and / or a hafnium oxide layer). Via the addition of dielectric material portions, the first gate dielectric layer 52A may become thicker. In one embodiment, the second gate dielectric layer 52B may include a second semiconductor oxide layer formed on the top surfaces of a plurality of portions of the second substrate region 10B and the third substrate region 10C.

[0235] Refer to Figure 22A and Figure 22B , a second photoresist layer 67B may be formed over the second exemplary structure and may be lithographically patterned to form an opening in a region of the third device region 300. A section of the second gate dielectric layer 52B located in the third device region 300 is physically exposed, while a section of the first gate dielectric layer 52A located in the first device region 100 and a section of the second gate dielectric layer 52B located in the second device region 200 are covered by the second photoresist layer 67B. The second photoresist layer 67B is formed over the first substrate region 10A and the second substrate region 10B without covering the third substrate region 10C. An edge of the second photoresist layer 67B may be formed over a portion of the shallow trench isolation structure 12 (such as the second shallow trench isolation portion 12B) located between the second substrate region 10B and the third substrate region 10C. Another edge of the second photoresist layer 67B may be formed over a portion of the shallow trench isolation structure 12 (such as the third shallow trench isolation portion 12C) located between the third substrate region 10C and an additional substrate region 10A".

[0236] An etch process can be performed to remove multiple segments of the second gate dielectric layer 52B located in the third device region 300, while the first gate dielectric layer 52A and the segments of the second gate dielectric layer 52B in the second device region 200 are under the second photoresist layer 67B and are protected by the second photoresist layer 67B. For example, a wet etch process using dilute hydrofluoric acid can be performed to etch the unmasked segments of the second gate dielectric layer 52B in the third device region 300. The top surface of the third substrate region 10C can be physically exposed while the first substrate region 10A and the second substrate region 10B are covered by the second photoresist layer 67B. In such an embodiment, the second gate dielectric layer 52B on the third substrate region 10C can be etched using the second photoresist layer 67B as an etch mask. During the etch process, the first gate dielectric layer 52A and the segments of the second gate dielectric layer 52B on the second substrate region 10B are covered by the second photoresist layer 67B and thus are not etched during the etch process. During the etch process, the unmasked segments of the portion of the shallow trench isolation structure 12 (e.g., the second shallow trench isolation portion 12B) between the second substrate region 10B and the third substrate region 10C can be etched in parallel and can be vertically recessed to provide a recessed horizontal surface that is vertically offset from the top surface of the non-recessed segments of the portion of the shallow trench isolation structure 12 under the second photoresist layer 67B (i.e., the masked segments of the second shallow trench isolation portion 12B under the second photoresist layer 67B).

[0237] The third substrate region 10C can be thinned via a subsequent etch process that can vertically recess the third substrate region 10C while protecting the first substrate region 10A and the second substrate region 10B using a second etch mask layer. In one embodiment, the second photoresist layer 67B can function as the second etch mask layer. Alternatively, the second photoresist layer 67B can be removed and the remaining segments of the first gate dielectric layer 52A and the second gate dielectric layer 52B in the second device region 200 can function as the second etch mask layer. In such an embodiment, the third substrate region 10C can be vertically recessed using an etch process that etches the material of the third substrate region 10C with selectivity relative to the materials of the first gate dielectric layer 52A, the second gate dielectric layer 52B, and the shallow trench isolation structure 12. In an illustrative example, a wet etch process using hot trimethyl-2-hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethylammonium hydroxide (TMAH) can be used to vertically recess the third substrate region 10C with selectivity relative to the materials of the first gate dielectric layer 52A, the second gate dielectric layer 52B, and the shallow trench isolation structure 12.

[0238] A portion of the shallow trench isolation structure 12 (e.g., the second shallow trench isolation portion 12B) located between the second substrate region 10B and the third substrate region 10C may have a height difference between an upper edge of a third sidewall contacting the second substrate region 10B and an upper edge of a fourth sidewall contacting the third substrate region 10C. The upper edges of the third sidewall and the fourth sidewall may be connected via a continuous top surface of the portion of the shallow trench isolation structure 12 that includes a non-horizontal surface section. In one embodiment, the continuous top surface of the portion of the shallow trench isolation structure 12 (e.g., the second shallow trench isolation portion 12B) may include a third horizontal surface section and a fourth horizontal surface section, the third horizontal surface section adjacent to an edge of the third sidewall of the portion of the shallow trench isolation structure 12 contacting the second substrate region 10B, and the fourth horizontal surface section adjacent to an edge of the fourth sidewall of the portion of the shallow trench isolation structure 12 contacting the third substrate region 10C. In various embodiments, where an anisotropic etching process is used to etch multiple unmasked portions of the second gate dielectric layer 52B and concurrently etch multiple unmasked regions of the shallow trench isolation structure 12, a vertical surface section may be adjacent to an edge of the third horizontal surface section and adjacent to an edge of the fourth horizontal surface section. In various embodiments, where an isotropic etching process is used to etch multiple unmasked portions of the second gate dielectric layer 52B and concurrently etch multiple unmasked regions of the shallow trench isolation structure 12, a tapered concave surface section may be adjacent to an edge of the third horizontal surface section and adjacent to an edge of the fourth horizontal surface section. Generally, the third substrate region 10C may be thinned by vertically recessing the third substrate region 10C while protecting the first substrate region 10A and the second substrate region 10B using the second etch mask layer.

[0239] See Figure 23A and Figure 23B, a third gate dielectric layer 52C may be formed on a physically exposed top surface of the third substrate region 10C. The formation of the third gate dielectric layer 52C may be via thermal oxidation of multiple surface portions of the semiconductor material in the third substrate region 10C, and / or deposition of a gate dielectric material layer (such as an aluminum oxide layer and / or a hafnium oxide layer). Via the addition of dielectric material portions, the first gate dielectric layer 52A and the second gate dielectric layer 52B may become thicker. In one embodiment, the third gate dielectric layer 52C may include a second semiconductor oxide layer formed on multiple top surfaces of the third substrate region 10C. In one embodiment, the first gate dielectric layer 52A may have a greater thickness than the second gate dielectric layer 52B, and the second gate dielectric layer 52B may have a greater thickness than the third gate dielectric layer 52C. The thickness of the first gate dielectric layer 52A may be in the range from 3 nm to 20 nm, the thickness of the second gate dielectric layer 52B may be in the range from 2 nm to 10 nm, and the thickness of the third gate dielectric layer 52C may be in the range from 1 nm to 6 nm, but smaller and larger thicknesses may also be used for each of the first gate dielectric layer 52A, the second gate dielectric layer 52B, and the third gate dielectric layer 52C.

[0240] Refer to Figure 24A and Figure 24B , process steps may be performed Figure 12A and Figure 12B to form multiple gate stack structures {(52A, 54A, 58A), (52B, 54B, 58B), (52C, 54C, 58C)}, multiple source extension regions (31A, 31B, 31C), and multiple drain extension regions (39A, 39B, 39C).

[0241] Refer to Figure 25A and Figure 25B , process steps may be performed Figure 13A and Figure 13B to form multiple gate spacers (56A, 56B, 56C), multiple source regions (32A, 32B, 32C, 32A”), and multiple drain regions (38A, 38B, 38C).

[0242] Refer to Figure 26A and Figure 26B , process steps may be performed Figure 14A and Figure 14B to form a contact layer dielectric 70, source side metal-semiconductor alloy regions (42A, 42B, 42C), drain side metal-semiconductor alloy regions (48A, 48B, 48C), gate side metal-semiconductor alloy regions, and respective contact via structures (72A, 75A, 78A, 72B, 75B, 78B, 72C, 75C, 78C).

[0243] The thicknesses of the first substrate region 10A and the plurality of additional substrate regions (10A', 10A") can be in the range from 150 nm to 500 nm, for example from 200 nm to 400 nm, but smaller and larger thicknesses can also be used. The thickness of the second substrate region 10B can be in the range from 30 nm to 150 nm, for example from 50 nm to 100 nm, but smaller and larger thicknesses can also be used. The thickness of the third substrate region 10C can be in the range from 10 nm to 70 nm, for example in the range from 30 nm to 50 nm, and smaller and larger thicknesses can also be used.

[0244] See Figures 15A to 26B And in accordance with various embodiments of the present disclosure, there is provided a semiconductor structure comprising: a semiconductor-on-insulator substrate 8 including a processing substrate 4, an insulating layer 6, and a plurality of substrate regions (10A, 10B, 10C, 10A', 10A") laterally surrounded by shallow trench isolation structures 12. The plurality of substrate regions (10A, 10B, 10C, 10A', 10A") include a first substrate region 10A having a first thickness and a second substrate region 10B having a second thickness less than the first thickness; a first semiconductor-on-insulator (SOI) field effect transistor (FET) including the first substrate region 10A, a first source region 32A and a first drain region 38A embedded in the first substrate region 10A, and a first gate stack structure (52A, 54A, 58A); and a second semiconductor-on-insulator field effect transistor including the second substrate region 10B, a second source region 32B and a second drain region 38B embedded in the second substrate region 10B, and a second gate stack structure (52B, 54B, 58B), wherein: a portion 12A of the shallow trench isolation structure 12 located between the first substrate region 10A and the second substrate region 10B has a height difference between an upper edge of a first sidewall contacting the first substrate region 10A and an upper edge of a second sidewall contacting the second substrate region 10B; and via a continuous top surface of the portion 12A of the shallow trench isolation structure 12 including a non-horizontal surface section, this upper edge of the first sidewall and this upper edge of the second sidewall are connected.

[0245] In one embodiment, the continuous top surface of portion 12A of the shallow trench isolation structure 12 includes: a first horizontal surface section adjacent to an edge of a first sidewall of portion 12A of the shallow trench isolation structure 12 that contacts the first substrate region 10A; a second horizontal surface section adjacent to an edge of a second sidewall of portion 12A of the shallow trench isolation structure 12 that contacts the second substrate region 10B; and a vertical surface section adjacent to an edge of the first horizontal surface section and adjacent to an edge of the second horizontal section. Alternatively, a tapered concave surface section may be adjacent to an edge of the first horizontal surface section and adjacent to an edge of the second horizontal surface section.

[0246] Multiple types of semiconductor devices (e.g., multiple field effect transistors) may be formed in the multiple patterned portions of the top semiconductor layer 10L. In one embodiment, the first substrate region 10A, the second substrate region 10B, and the third substrate region 10C have different thicknesses, and multiple different types of field effect transistors may be formed above the first substrate region 10A, the second substrate region 10B, and the third substrate region 10C. In an illustrative embodiment, a first field effect transistor may be formed in the first device region 100 that exhibits device characteristics similar to those of a field effect transistor formed on a bulk semiconductor substrate, a partially depleted silicon-on-insulator (PDSOI) field effect transistor may be formed in the second device region 200, and a fully depleted silicon-on-insulator (FDSOI) field effect transistor may be formed in the third device region 300. Thus, the second exemplary structure of the present disclosure provides for the formation of multiple different types of semiconductor devices on the same substrate.

[0247] See Figure 27, the first flowchart depicts a plurality of steps for forming a first exemplary structure of the present disclosure. Referring to step 2710, a semiconductor-on-insulator substrate 8 is provided, which includes a processing substrate 4, an insulating layer 6, and a top semiconductor layer 10L. Referring to step 2720, using a first diffusion barrier layer 161, a first region 100 of the top semiconductor layer 10L can be covered, and a second region 200 of the top semiconductor layer 10L can be physically exposed. Referring to step 2730, the second region 200 of the top semiconductor layer 10L can be thinned by performing an oxidation process that oxidizes a surface portion of the second region 200 of the top semiconductor layer 10L, while the first diffusion barrier layer 161 hinders the oxidation of the first region 100 of the top semiconductor layer 10L. After the oxidation process, the second region 200 of the top semiconductor layer 10L has a thickness less than that of the first region 100 of the top semiconductor layer 10L. Referring to step 2740, a plurality of shallow trenches 11 can be formed through the top semiconductor layer 10L. The top semiconductor layer 10L is divided into a plurality of discrete portions, which include a first substrate region 10A patterned from the first region 100 of the top semiconductor layer 10L and a second substrate region 10B patterned from the second region 200 of the top semiconductor layer 10L. Referring to step 2750, a shallow trench isolation structure 12 can be formed by filling the shallow trenches 11 with a dielectric filling material and recessing a plurality of portions of the dielectric filling material. The shallow trench isolation structure 12 includes a first shallow trench isolation portion 12A located between the first substrate region 10A and the second substrate region 10B and has a non-planar inclined top surface. Referring to step 2760, a first semiconductor-on-insulator (SOI) field-effect transistor (FET) including the first substrate region 10A and a second semiconductor-on-insulator field-effect transistor including the second substrate region 10B can be formed.

[0248] Referring to Figure 28 , the second flowchart depicts a plurality of steps for forming a second exemplary structure of the present disclosure. Referring to step 2810, a semiconductor-on-insulator substrate 8 is provided, which includes a processing substrate 4, an insulating layer 6, and a top semiconductor layer 10L. Referring to step 2820, a shallow trench isolation structure 12 is formed through the top semiconductor layer 10L. The shallow trench isolation structure 12 laterally surrounds a plurality of patterned portions of the top semiconductor layer 10L including the first substrate region 10A and the second substrate region 10B. Referring to step 2830, the second substrate region is thinned by vertically recessing the second substrate region 10B while protecting the first substrate region 10A using a first etch mask layer (67A or 52A). Referring to step 2840, a first semiconductor-on-insulator (SOI) field-effect transistor (FET) including the first substrate region 10A and a second semiconductor-on-insulator field-effect transistor including the second substrate region 10B can be formed.

[0249] Referring to all the figures and various embodiments in accordance with the present disclosure, a method of forming a semiconductor structure is provided, which includes the following operations: providing a semiconductor-on-insulator substrate 8, which includes a processing substrate 4, an insulating layer 6, and a top semiconductor layer 10L. The method further includes the following operations: covering a first region 100 of the top semiconductor layer 10L with at least one first diffusion barrier layer 141, and physically exposing second regions 200, 300 of the top semiconductor layer 10L. The method further includes the following operations: thinning the second regions 200, 300 of the top semiconductor layer 10L by performing an oxidation process that oxidizes surface portions of the second regions 200, 300 of the top semiconductor layer 10L, while at least one first diffusion barrier layer 141 impedes oxidation of the first region 100 of the top semiconductor layer 10L, wherein after the oxidation process, the second regions 200, 300 of the top semiconductor layer 10L have a thickness less than that of the first region 100. The method further includes the following operations: forming a shallow trench 11 that penetrates the top semiconductor layer 10L, wherein the top semiconductor layer 10L is divided into a plurality of separated portions 10A, 10B, 10C, which include a first substrate region 10A patterned from the first region 100 of the top semiconductor layer 10L, and a second substrate region 10B patterned from the second region 200 of the top semiconductor layer 10L. The method further includes the following operations: forming a shallow trench isolation structure 12 by filling the shallow trench 11 with a dielectric filling material and recessing a plurality of portions of the dielectric filling material, wherein the shallow trench isolation structure 12 includes a first shallow trench isolation portion 12A located between the first substrate region 10A and the second substrate region 10B and has a non-planar inclined top surface. This method further includes the following operations: forming a first semiconductor-on-insulator (SOI) field effect transistor (FET) that includes the first substrate region 10A, and a second semiconductor-on-insulator field effect transistor that includes the second substrate region 10B.

[0250] Referring to all the figures and various embodiments in accordance with the present disclosure, a method of forming a semiconductor structure is provided, which includes the following operations: providing a semiconductor-on-insulator substrate 8, which includes a processing substrate 4, an insulating layer 6, and a top semiconductor layer 10L. The method further includes the following operations: forming a shallow trench isolation structure 12 that penetrates the top semiconductor layer 10L, wherein the shallow trench isolation structure 12 laterally surrounds a plurality of patterned portions of the top semiconductor layer 10L that include a first substrate region 10A and a second substrate region 10B. The method further includes the following operations: thinning the second substrate region 10B by vertically recessing the second substrate region 10B while protecting the first substrate region 10A with a first etch mask layer 67A; and forming a first semiconductor-on-insulator (SOI) field effect transistor (FET) that includes the first substrate region 10A and a second semiconductor-on-insulator that includes the second substrate region 10B.

[0251] Referring to all of the figures and in accordance with various embodiments of the present disclosure, a semiconductor structure is provided that includes: a semiconductor-on-insulator substrate 8 that includes a processing substrate 4, an insulating layer 6, and a plurality of substrate regions (10A, 10B, 10C, 10A', 10A") laterally surrounded by a shallow trench isolation structure 12, the plurality of substrate regions (10A, 10B, 10C, 10A', 10A") including a first substrate region 10A having a first thickness and a second substrate region 10B having a second thickness less than the first thickness; a first semiconductor-on-insulator (SOI) field-effect transistor (FET) including the first substrate region 10A, a first source region 32A and a first drain region 38A embedded in the first substrate region 10A, and a first gate stack structure (52A, 54A, 58A); and a second semiconductor-on-insulator field-effect transistor including the second substrate region 10B, a second source region 32B and a second drain region 38B embedded in the second substrate region 10B, and a second gate stack structure (52B, 54B, 58B), wherein a portion 12A of the shallow trench isolation structure 12 located between the first substrate region 10A and the second substrate region 10B has a height difference between an upper edge of a first sidewall contacting the first substrate region 10A and an upper edge of a second sidewall contacting the second substrate region 10B; and the upper edge of the first sidewall and the upper edge of the second sidewall are connected via a continuous top surface of the portion 12A of the shallow trench isolation structure 12 that includes a non-horizontal surface section.

[0252] In one embodiment, the plurality of substrate regions (10A, 10B, 10C, 10A', 10A") includes a third substrate region 10C having a third thickness less than the second thickness. The semiconductor structure includes a third semiconductor-on-insulator field-effect transistor that includes the third substrate region 10C, a third source region 32C and a third drain region 38C embedded in the third substrate region 10C, and a third gate stack structure (52C, 54C, 58C). The first semiconductor-on-insulator field-effect transistor may include a partially depleted semiconductor-on-insulator field-effect transistor. The third semiconductor-on-insulator field-effect transistor may include a fully depleted semiconductor-on-insulator field-effect transistor. The second semiconductor-on-insulator field-effect transistor may include a partially depleted semiconductor-on-insulator field-effect transistor or a fully depleted semiconductor-on-insulator field-effect transistor.

[0253] The various methods and structures of the present disclosure may provide a combination of at least one partially depleted semiconductor-on-insulator field-effect transistor and at least one fully depleted semiconductor-on-insulator field-effect transistor on a same semiconductor-on-insulator substrate, with low production costs and a relatively short process time.

[0254] Some embodiments of the present disclosure provide a method of forming a semiconductor structure, comprising: providing a semiconductor-on-insulator substrate including a processing substrate, an insulating layer, and a top semiconductor layer; covering a first region of the top semiconductor layer with at least one first diffusion barrier layer and physically exposing a second region of the top semiconductor layer; thinning the second region of the top semiconductor layer by performing an oxidation process that oxidizes a surface portion of the second region of the top semiconductor layer while the at least one first diffusion barrier layer impedes oxidation of the first region of the top semiconductor layer, wherein after the oxidation process, the second region of the top semiconductor layer has a thickness thinner than that of the first region of the top semiconductor layer; forming a plurality of shallow trenches that penetrate the top semiconductor layer, wherein the top semiconductor layer is divided into a plurality of separated portions including: a first substrate region patterned from the first region of the top semiconductor layer and a second substrate region patterned from the second region of the top semiconductor layer; forming a shallow trench isolation structure by filling the shallow trenches with a dielectric filling material and recessing portions of the dielectric filling material, wherein the shallow trench isolation structure includes a first shallow trench isolation portion that is located between the first substrate region and the second substrate region and has a non-planar inclined top surface; and forming a first semiconductor-on-insulator field effect transistor including the first substrate region and a second semiconductor-on-insulator field effect transistor including the second substrate region.

[0255] In some embodiments, the method of forming a semiconductor structure further comprises: forming a first semiconductor oxide layer on a top surface of the top semiconductor layer; forming a first diffusion barrier layer above the first semiconductor oxide layer; and removing portions of the first diffusion barrier layer and the first semiconductor oxide layer above the second region of the top semiconductor layer to provide the at least one first diffusion barrier layer.

[0256] In some embodiments, the method of forming a semiconductor structure further comprises: forming a planarization termination dielectric layer above the at least one first diffusion barrier layer and above semiconductor oxide portions formed by oxidation of the surface portion of the second region of the top semiconductor layer after thinning the second region of the top semiconductor layer, wherein the plurality of shallow trenches are formed through the planarization termination dielectric layer and the dielectric filling material is deposited above the planarization termination dielectric layer.

[0257] In some embodiments, in the method of forming a semiconductor structure, a top surface of the planarization termination dielectric layer includes a plurality of horizontal surface segments and a plurality of non-horizontal surface segments that are vertically spaced apart from the insulating layer by different vertical spacing distances, and the non-horizontal surface segments connect adjacent pairs of the plurality of horizontal surface segments.

[0258] In some embodiments, the method of forming a semiconductor structure further includes performing a chemical mechanical planarization process that removes portions of a dielectric fill material from above a top surface of a planarization termination dielectric layer, wherein remaining portions of the dielectric fill material extend beyond a plurality of first sections of the top surface of the planarization termination dielectric layer adjacent to these shallow trenches, and a plurality of second sections of the top surface of the planarization termination dielectric layer that are laterally spaced from these shallow trenches are physically exposed.

[0259] In some embodiments, the method of forming a semiconductor structure further includes: isotropically etching the planarization termination dielectric layer, having selectivity with respect to the dielectric fill material, by performing a first isotropic etching process after performing the chemical mechanical planarization process; and simultaneously isotropically etching a semiconductor oxide portion and the dielectric fill material, having selectivity with respect to materials of a plurality of first substrate regions and second substrate regions, by performing a second isotropic etching process.

[0260] In some embodiments, the method of forming a semiconductor structure further includes: physically exposing a third region of a top semiconductor layer while a first region of the top semiconductor layer is covered with at least one first diffusion barrier layer and while a second region of the top semiconductor layer is covered with a semiconductor oxide portion formed by oxidizing a surface portion of the second region of the top semiconductor layer; and thinning the third region of the top semiconductor layer by performing an additional oxidation process that oxidizes a surface portion of the third region of the top semiconductor layer while the at least one first diffusion barrier layer and the semiconductor oxide portion impede oxidation of the first region of the top semiconductor layer and the second region of the top semiconductor layer, wherein after the additional oxidation process, the thickness of the third region of the top semiconductor layer is less than the thickness of the second region of the top semiconductor layer.

[0261] Some other embodiments of the present disclosure provide a method of forming a semiconductor structure, including: providing a semiconductor-on-insulator substrate including a processing substrate, an insulating layer, and a top semiconductor layer; forming a shallow trench isolation structure that passes through the top semiconductor layer, wherein the trench isolation structure laterally surrounds a plurality of patterned portions of the top semiconductor layer including a first substrate region and a second substrate region; thinning the second substrate region by vertically recessing the second substrate region while protecting the first substrate region with a first etch mask layer; and forming a first semiconductor-on-insulator field effect transistor including the first substrate region and a second semiconductor-on-insulator field effect transistor including the second substrate region.

[0262] In some embodiments, the method of forming a semiconductor structure further includes: forming a silicon oxide cushion layer on the top surface of the top semiconductor layer; forming a silicon nitride cushion layer above the silicon oxide cushion layer; and forming a plurality of shallow trenches that penetrate the silicon nitride cushion layer, the silicon oxide cushion layer, and the top semiconductor layer, wherein shallow trench isolation structures are formed in these shallow trenches.

[0263] In some embodiments, the method of forming a semiconductor structure further includes: depositing a dielectric filling material in the shallow trenches and above the silicon nitride cushion layer; and recessing the dielectric filling material below a horizontal plane including the top surface of the silicon nitride cushion layer. Wherein: the remaining portion of the dielectric filling material after recessing the dielectric filling material includes the shallow trench isolation structure; and the entire top surface of the shallow trench isolation structure is within the same horizontal plane.

[0264] In some embodiments, the method of forming a semiconductor structure further includes: forming a first oxide layer on the top surfaces of a first substrate region and a second substrate region; and removing a second section of the first semiconductor oxide layer covering the second substrate region without removing a first section of the first semiconductor oxide layer covering the first substrate region.

[0265] In some embodiments, in the method of forming a semiconductor structure, an etching process is used to vertically recess the second substrate region, and the etching process etches the material of the second substrate region selectively with respect to the first section of the first semiconductor oxide layer and the materials of the plurality of shallow trench isolation structures.

[0266] In some embodiments, the method of forming a semiconductor structure further includes: forming a patterned photoresist layer above the first substrate region without covering the second substrate region, wherein an edge of the patterned photoresist layer is formed above a part of the shallow trench isolation structure located between the first substrate region and the second substrate region; and using the patterned photoresist layer as an etching mask to etch the second section of the first semiconductor oxide layer, wherein an unmasked section of the part of the shallow trench isolation structure located between the first substrate region and the second substrate region is etched in parallel and vertically recessed to provide a recessed horizontal surface that is vertically offset from the top surface of an undepressed section of the part of the shallow trench isolation structure below the patterned photoresist layer.

[0267] In some embodiments, in the method of forming a semiconductor structure, the patterned portions of the top semiconductor layer include a third substrate region that is laterally surrounded by the shallow trench isolation structure; and the method further includes thinning the third substrate region by vertically recessing the third substrate region while protecting the first substrate region and the second substrate region using a second etching mask layer.

[0268] Some embodiments of the present disclosure provide a semiconductor structure, comprising: a semiconductor-on-insulator substrate, a first semiconductor-on-insulator field-effect transistor, and a second semiconductor-on-insulator field-effect transistor. The semiconductor-on-insulator substrate includes a processing substrate, an insulating layer, and a plurality of substrate regions laterally surrounded by a shallow trench isolation structure. The plurality of substrate regions includes a first substrate region having a first thickness and a second substrate region having a second thickness less than the first thickness. The first semiconductor-on-insulator field-effect transistor includes the first substrate region, a first source region and a first drain region embedded in the first substrate region, and a first gate stack structure. The second semiconductor-on-insulator field-effect transistor includes the second substrate region, a second source region and a second drain region embedded in the second substrate region, and a second gate stack structure. Wherein: a portion of the shallow trench isolation structure located between the first substrate region and the second substrate region has a height difference between an upper edge of a first sidewall contacting the first substrate region and an upper edge of a second sidewall contacting the second substrate region; and the upper edges of the first sidewall and the second sidewall are connected via a continuous top surface of the portion of the shallow trench isolation structure including a non-horizontal surface section.

[0269] In some embodiments, in the semiconductor structure, the continuous top surface of the portion of the shallow trench isolation structure includes a curved conical surface without horizontal or vertical steps.

[0270] In some embodiments, in the semiconductor structure, the plurality of substrate regions includes additional substrate regions located adjacent to the first substrate region and having the first thickness; and additional portions of the shallow trench isolation structure are located between the first substrate region and the additional substrate regions and have a curved top surface connecting an upper edge of a first sidewall of the additional portion of the shallow trench isolation structure contacting the first substrate region and an upper edge of a second sidewall of the additional portion of the shallow trench isolation structure contacting the additional substrate region.

[0271] In some embodiments, in the semiconductor structure, the upper edge of the first sidewall of the additional portion of the shallow trench isolation structure and the upper edge of the second sidewall of the additional portion of the shallow trench isolation structure are located at the same distance from the insulating layer; and a central region of the curved top surface is elevated relative to the upper edge of the first sidewall of the additional portion of the shallow trench isolation structure.

[0272] In some embodiments, in a semiconductor structure, a continuous top surface of a portion of a shallow trench isolation structure includes: a first horizontal surface section, a second horizontal surface section, and a vertical surface section. The first horizontal surface section abuts an edge of a first sidewall of a portion of the shallow trench isolation structure that contacts a first substrate region. The second horizontal surface section abuts an edge of a second sidewall of a portion of the shallow trench isolation structure that contacts a second substrate region. The vertical surface section abuts an edge of the first horizontal surface section and an edge of the second horizontal surface section.

[0273] In some embodiments, in a semiconductor structure, a plurality of substrate regions includes a third substrate region having a third thickness that is less than a second thickness; the semiconductor structure includes a third silicon-on-insulator field-effect transistor that includes: a third substrate region, a third source region and a third drain region embedded in the third substrate region, and a third gate stack structure; a first silicon-on-insulator field-effect transistor includes a partially depleted silicon-on-insulator field-effect transistor; and the third silicon-on-insulator field-effect transistor includes a fully depleted silicon-on-insulator field-effect transistor.

[0274] The foregoing outlines several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for the design and modification of other processes and structures to achieve the same purposes as the embodiments introduced herein, or to achieve the same benefits. Those skilled in the art should also understand that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. A method of forming a semiconductor structure, characterized in that, comprising: providing a semiconductor-on-insulator substrate, which includes a processing substrate, an insulating layer, and a top semiconductor layer; covering a first region of the top semiconductor layer with at least one first diffusion barrier layer and physically exposing a second region of the top semiconductor layer; thinning the second region of the top semiconductor layer by performing an oxidation process to oxidize a surface portion of the second region of the top semiconductor layer, while the at least one first diffusion barrier layer impedes the oxidation of the first region of the top semiconductor layer; forming a planarization termination dielectric layer above the at least one first diffusion barrier layer and above a semiconductor oxide portion, the semiconductor oxide being formed by the oxidation of the surface portion of the second region of the top semiconductor layer, after thinning the second region of the top semiconductor layer; forming a plurality of shallow trenches through the top semiconductor layer, wherein the top semiconductor layer is divided into a plurality of separate portions including: a first substrate region patterned from the first region of the top semiconductor layer, and a second substrate region patterned from the second region of the top semiconductor layer, wherein the plurality of shallow trenches pass through the planarization termination dielectric layer; forming a shallow trench isolation structure by filling the plurality of shallow trenches with a dielectric filling material and recessing portions of the dielectric filling material; and forming a first semiconductor-on-insulator field effect transistor including the first substrate region, and a second semiconductor-on-insulator field effect transistor including the second substrate region.

2. The method of forming the semiconductor structure according to claim 1, characterized in that, further comprising: forming a first semiconductor oxide layer on a top surface of the top semiconductor layer; forming a diffusion barrier layer above the first semiconductor oxide layer; and removing portions of the diffusion barrier layer and the first semiconductor oxide layer from above the second region of the top semiconductor layer to provide the at least one first diffusion barrier layer.

3. The method of forming the semiconductor structure according to claim 1, characterized in that, wherein the plurality of shallow trenches are formed through the planarization termination dielectric layer, and the dielectric filling material is deposited above the planarization termination dielectric layer.

4. The method of forming the semiconductor structure according to claim 3, characterized in that, wherein a top surface of the planarization termination dielectric layer includes a plurality of horizontal surface segments and a plurality of non-horizontal surface segments, the plurality of horizontal surface segments being vertically spaced apart by different vertical spacing distances perpendicular to the insulating layer, and the plurality of non-horizontal surface segments connecting adjacent pairs of the plurality of horizontal surface segments.

5. The method of forming the semiconductor structure according to claim 3, characterized in that, It also includes performing a chemical mechanical planarization process that removes multiple portions of the dielectric fill material from a top surface that is higher than the planarization termination dielectric layer, wherein multiple remaining portions of the dielectric fill material extend beyond multiple first segments of the top surface of the planarization termination dielectric layer near the multiple shallow trenches, and multiple second segments of the top surface of the planarization termination dielectric layer that are laterally spaced from the multiple shallow trenches are physically exposed.

6. The method of forming the semiconductor structure according to claim 5, wherein, it also includes: anisotropically etching the planarization termination dielectric layer, having selectivity with respect to the dielectric fill material, by performing a first anisotropic etching process after performing the chemical mechanical planarization process; and simultaneously anisotropically etching the semiconductor oxide portion and the dielectric fill material, having selectivity with respect to the materials of the multiple first substrate regions and the multiple second substrate regions, by performing a second anisotropic etching process.

7. The method of forming the semiconductor structure according to claim 1, wherein, it also includes: physically exposing a third region of the top semiconductor layer, while the first region of the top semiconductor layer is covered with the at least one first diffusion barrier layer, and while the second region of the top semiconductor layer is covered with a semiconductor oxide portion that is formed by oxidizing a surface portion of the second region of the top semiconductor layer; and thinning the third region of the top semiconductor layer by performing an additional oxidation process that oxidizes a surface portion of the third region of the top semiconductor layer, while the at least one first diffusion barrier layer and the semiconductor oxide portion impede the oxidation of the first region of the top semiconductor layer and the second region of the top semiconductor layer, wherein after the additional oxidation process, the third region of the top semiconductor layer has a thickness that is less than a thickness of the second region of the top semiconductor layer.

8. A method of forming a semiconductor structure, wherein, it includes: providing a substrate that includes a top semiconductor layer; covering a first region of the top semiconductor layer with at least one first diffusion barrier layer and physically exposing a second region of the top semiconductor layer; thinning the second region of the top semiconductor layer without thinning the first region of the top semiconductor layer; forming a planarization termination dielectric layer above the at least one first diffusion barrier layer, after thinning the second region of the top semiconductor layer; forming multiple shallow trenches through the top semiconductor layer, wherein the top semiconductor layer is divided into multiple separate portions that include: a first substrate region patterned from the first region of the top semiconductor layer, and a second substrate region patterned from the second region of the top semiconductor layer; forming a shallow trench isolation structure by filling the multiple shallow trenches with a dielectric fill material and recessing multiple portions of the dielectric fill material; and forming a first semiconductor-on-insulator field effect transistor that includes the first substrate region, and a second semiconductor-on-insulator field effect transistor that includes the second substrate region.

9. The method of forming the semiconductor structure according to claim 8, wherein, further comprising: forming a silicon oxide cushion layer on a top surface of the top semiconductor layer; and forming a silicon nitride cushion layer above the silicon oxide cushion layer.

10. The method of forming the semiconductor structure according to claim 9, wherein, further comprising: depositing the dielectric filling material above the silicon nitride cushion layer, wherein an entirety of a top surface of the shallow trench isolation structure is within a same horizontal plane, and the horizontal plane is lower than the top surface of the silicon nitride cushion layer.

11. The method of forming the semiconductor structure according to claim 8, wherein, further comprising: forming a first semiconductor oxide layer on top surfaces of the first substrate region and the second substrate region; and removing a second section of the first semiconductor oxide layer covering the second substrate region without removing a first section of the first semiconductor oxide layer covering the first substrate region.

12. The method of forming the semiconductor structure according to claim 11, wherein, using an etching process to vertically recess the second substrate region, and the etching process etches a material of the second substrate region selectively with respect to the first section of the first semiconductor oxide layer and materials of the shallow trench isolation structure.

13. The method of forming the semiconductor structure according to claim 11, wherein, further comprising: forming a patterned photoresist layer above the first substrate region without covering the second substrate region, wherein an edge of the patterned photoresist layer is formed above a part of the shallow trench isolation structure located between the first substrate region and the second substrate region; and using the patterned photoresist layer as an etching mask to etch a second section of the first semiconductor oxide layer, wherein an unmasked section of the part of the shallow trench isolation structure located between the first substrate region and the second substrate region is etched in parallel and vertically recessed to provide a recessed horizontal surface which is vertically offset from a top surface of an undepressed section of the part of the shallow trench isolation structure below the patterned photoresist layer.

14. The method of forming the semiconductor structure according to claim 8, wherein, wherein: the plurality of patterned parts of the top semiconductor layer include a third substrate region which is laterally surrounded by the shallow trench isolation structure; and the method further comprises thinning the third substrate region by vertically recessing the third substrate region while protecting the first substrate region and the second substrate region with a second etching mask layer.

15. A semiconductor structure, wherein, comprising: a semiconductor-on-insulator substrate, which includes a processing substrate, an insulating layer, and a plurality of substrate regions which are laterally surrounded by a shallow trench isolation structure, and the plurality of substrate regions include a first substrate region having a first thickness and a second substrate region having a second thickness less than the first thickness; A first semiconductor-on-insulator field-effect transistor, comprising the first substrate region, a first source region and a first drain region embedded in the first substrate region, and a first gate stack structure; and A second semiconductor-on-insulator field-effect transistor, comprising the second substrate region, a second source region and a second drain region embedded in the second substrate region, and a second gate stack structure, wherein: A part of the shallow trench isolation structure located between the first substrate region and the second substrate region has a height difference between an upper edge of a first sidewall contacting the first substrate region and an upper edge of a second sidewall contacting the second substrate region; and The upper edge of the first sidewall and the upper edge of the second sidewall are connected via a continuous top surface of the part of the shallow trench isolation structure including a non-horizontal surface section, wherein the continuous top surface of the part of the shallow trench isolation structure includes a curved tapered surface without a horizontal step or a vertical step.

16. The semiconductor structure according to claim 15, wherein: The plurality of substrate regions includes an additional substrate region located adjacent to the first substrate region and having the first thickness; and An additional part of the shallow trench isolation structure is located between the first substrate region and the additional substrate region, and has a curved top surface connecting an upper edge of a first sidewall of the additional part of the shallow trench isolation structure contacting the first substrate region and an upper edge of a second sidewall of the additional part of the shallow trench isolation structure contacting the additional substrate region.

17. The semiconductor structure according to claim 16, wherein: The upper edge of the first sidewall of the additional part of the shallow trench isolation structure and the upper edge of the second sidewall of the additional part of the shallow trench isolation structure are located at the same distance from the insulating layer; and A central region of the curved top surface is elevated relative to the upper edge of the first sidewall of the additional part of the shallow trench isolation structure.

18. The semiconductor structure according to claim 15, wherein, wherein: The plurality of substrate regions includes a third substrate region having a third thickness less than the second thickness; The semiconductor structure includes a third semiconductor-on-insulator field-effect transistor including the third substrate region, a third source region and a third drain region embedded in the third substrate region, and a third gate stack structure; The first semiconductor-on-insulator field-effect transistor includes a partially depleted semiconductor-on-insulator field-effect transistor; and The third semiconductor-on-insulator field-effect transistor includes a fully depleted semiconductor-on-insulator field-effect transistor.

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