Transistor gate and forming method

Abstract

The present disclosure relates to transistor gates and methods of forming them. A device includes: a first nanostructure; a second nanostructure, above the first nanostructure; a first high-k gate dielectric, around the first nanostructure; a second high-k gate dielectric, around the second nanostructure; and a gate electrode, above the first high-k gate dielectric and the second high-k gate dielectric. The portion of the gate electrode between the first nanostructure and the second nanostructure includes: a first p-type work function metal; a barrier material, above the first p-type work function metal; and a second p-type work function metal, above the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

Description

Technical Field

[0001] The present disclosure relates generally to transistor gates and methods of forming them. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed. Summary of the invention

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a first nanostructure; a second nanostructure above the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode above the first high-k gate dielectric and the second high-k gate dielectric, wherein a portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material above the first p-type work function metal; and a second p-type work function metal above the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

[0005] According to another embodiment of the present disclosure, a transistor is provided, comprising: a first nanostructure on a semiconductor substrate; a second nanostructure on the first nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure; and a gate electrode on the gate dielectric, wherein the gate electrode comprises: a p-type work function metal; a barrier material on the p-type work function metal, the barrier material physically separating a first portion of the p-type work function metal from a second portion of the p-type work function metal in a region between the first nanostructure and the second nanostructure; an adhesion layer on the barrier material; and a filling metal on the adhesion layer.

[0006] According to another embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure being disposed above the second nanostructure; depositing a p-type work function metal above the gate dielectric, wherein, after depositing the p-type work function metal, an opening is retained between a first portion of the p-type work function metal and a second portion of the p-type work function metal, the first portion of the p-type work function metal and the second portion of the p-type work function metal being between the first nanostructure and the second nanostructure; and depositing a barrier material above the p-type work function metal using an atomic layer deposition (ALD) process, wherein the barrier material fills the opening between the first portion of the p-type work function metal and the second portion of the p-type work function metal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 An example of a nanostructured field effect transistor (nanoFET) in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 11C , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig.19C , Fig.19D , Fig. 20A , Fig. 20B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.24C , Fig.25A , Fig.25B and Fig.25C is a cross-sectional view of an intermediate stage in fabricating a nanoFET according to some embodiments.

[0010] Fig.19E is an elemental analysis of materials of a nanoFET according to some embodiments.

[0011] Fig.21 is a cross-sectional view of a nanoFET according to some embodiments.

[0012] Fig.26A , Fig.26B and Fig.26C is a cross-sectional view of a nanoFET according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] The thickness of the work function metal (WFM) layer(s) in the transistor gate stack affects the threshold voltage (V TH ). Therefore, it is desirable that the WFM layer has a relatively uniform thickness to provide reduced threshold voltage variation. Various embodiments provide a gate stack comprising a relatively thin work function metal (WFM) layer and a barrier layer on the WFM layer. The barrier layer physically separates portions of the WFM layer in various regions of the gate stack (e.g., between adjacent nanostructures of a nanoFET). For example, a merged region of the WFM layer may have twice the thickness of an unmerged region of the WFM layer, thereby causing undesirable threshold voltage variation. By separating the WFM layer with a barrier layer, the threshold voltage variation may be advantageously reduced, thereby improving the reliability and performance of the device. In addition, the barrier layer may include tungsten deposited using a fluorine-containing precursor. In such an embodiment, fluorine from the precursor may diffuse into the gate dielectric layer of the transistor, thereby improving device performance.

[0016] Figure 1 An example of a nanoFET (e.g., a nanowire FET, a nanosheet FET, etc.) in a three-dimensional view according to some embodiments is shown. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) on a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 serves as a channel region of the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. An isolation region 68 is disposed between adjacent fins 66, which may protrude above and between adjacent isolation regions 68. Although the isolation region 68 is shown / described as being separated from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and an isolation region. In addition, although the bottom of the fin 66 is shown as a single continuous material with the substrate 50, the bottom of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, the fin 66 refers to the portion extending between adjacent isolation regions 68.

[0017] Gate dielectric 100 is over the top surface of fin 66 and along the top surface, sidewalls and bottom surface of nanostructure 55. Gate electrode 102 is over gate dielectric 100. Epitaxial source / drain regions 92 are disposed on fin 66 on opposite sides of gate dielectric layer 96 and gate electrode 98.

[0018] Figure 1Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction perpendicular to the direction of current flow, e.g., between epitaxial source / drain regions 90 of the nanoFET. Cross section BB' is perpendicular to cross section AA' and parallel to the longitudinal axis of fin 66 of the nanoFET and in the direction of current flow, e.g., between epitaxial source / drain regions 90 of the nanoFET. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source / drain regions of the nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0019] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. In addition, some embodiments contemplate aspects used in planar devices such as planar FETs, or fin field effect transistors (FinFETs).

[0020] Figures 2 to 25C is a cross-sectional view of an intermediate stage in fabricating a nanoFET according to some embodiments. Figures 2 to 5 , Fig. 6A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig.19C , Fig.19D , Fig. 20A , Fig.21 , Fig.22A , Fig.23A , Fig.24A , Fig.25A and Fig.26A Shows Figure 1 Reference cross section AA' is shown. Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 11C , Fig. 12B , Fig.12D , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B and Fig.26B Shows Figure 1 Reference cross section BB' is shown. Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig. 13C , Fig.23C , Fig.24C , Fig.25C and Fig.26C Shows Figure 1 Reference cross section CC' shown.

[0021] exist Figure 2 In the invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide; or combinations thereof.

[0022] The substrate 50 has a region n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, such as an n-type nano FET, and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, such as a p-type nano SFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown in the separator 20), and any number of device features (such as other active devices, doped regions, isolation structures, etc.) can be set between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be provided.

[0023] Further in Figure 2In the embodiment of the present invention, a multilayer stack 64 is formed on a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For the purpose of illustration and as discussed in more detail below, the second semiconductor layer 53 will be removed and the first semiconductor layer 51 will be patterned to form a channel region of a nanoFET in the p-type region 50P. In addition, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of a nanoFET in the n-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in the p-type region 50P.

[0024] In other embodiments, the first semiconductor layer 51 may be removed, and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon, etc.) and may be formed simultaneously. Fig.26A , Fig.26B and Fig.26C The structure resulting from such an embodiment is shown where, for example, the channel regions in both the p-type region 50P and the n-type region 50N include silicon.

[0025] For illustrative purposes, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer in the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nanoFET, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nanoFET, such as silicon, carbon silicon, etc. For illustrative purposes, the multilayer stack 64 is shown as having a bottommost semiconductor layer suitable for a p-type nanoFET. In some embodiments, the multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for an n-type nanoFET.

[0026] The first semiconductor material and the second semiconductor material may be materials having high etching selectivity to each other. Thus, in the n-type region 50N, the first semiconductor layer 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form a channel region of the n-type NSFETS. Similarly, in the p-type region 50P, the second semiconductor layer 53 of the second semiconductor material may be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form a channel region of the p-type NSFETS. In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P may be formed simultaneously and have the same material composition, such as silicon, silicon germanium, etc. Fig.26A , Fig.26B and Fig.26C The structure resulting from such an embodiment is shown where, for example, the channel regions in both the p-type region 50P and the n-type region 50N include silicon.

[0027] Reference now Figure 3 According to some embodiments, fins 66 are formed in substrate 50 and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching grooves in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching can be anisotropic. Forming nanostructure 55 by etching multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and define second nanostructures 54A-C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can be further collectively referred to as nanostructure 55.

[0028] The fins 66 and nanostructures 55 may be patterned by any suitable method. For example, one or more photolithography processes may be used to pattern the fins 66 and nanostructures 55, including a double patterning process or a multi-patterning process. Typically, a double patterning or multi-patterning process combines a photolithography process and a self-alignment process, allowing the creation of patterns having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66.

[0029] For illustrative purposes, Figure 3The fins 66 in the n-type region 50N and the p-type region 50P are shown as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater or less than the width of the fins 66 in the p-type region 50P. Further, although each of the fins 66 and the nanostructures 55 are shown as having a uniform width, in other embodiments, the fins 66 and / or the nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or the nanostructures 55 increases continuously in a direction toward the substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

[0030] exist Figure 4 In the embodiment shown, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material on the substrate 50, the fin 66 and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide (e.g., silicon oxide), a nitride, etc., or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that an excess of insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown separately) can be first formed along the surface of the substrate 50, the fin 66 and the nanostructure 55. Thereafter, a filling material such as described above can be formed on the liner.

[0031] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 55. In some embodiments, a planarization process may be employed, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. The planarization process exposes the nanostructures 55 so that the top surfaces of the nanostructures 55 and the insulating material are flush after the planarization process is completed.

[0032] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of fins 66 in regions 50N and 50P protrude from between adjacent STI regions 68. In addition, the top surface of STI regions 68 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dished), or a combination thereof. The top surface of STI regions 68 may be formed to be flat, convex, and / or concave by appropriate etching. STI regions 68 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fins 66 and nanostructures 55). For example, oxide removal using, for example, diluted hydrofluoric acid (dHF) acid may be employed.

[0033] The above about Figures 2 to 4 The process described is only one example of how the fin 66 and nanostructure 55 can be formed. In some embodiments, the fin 66 and / or nanostructure 55 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. The epitaxial structure can be epitaxially grown in the trench, and the dielectric layer can be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or nanostructure 55. The epitaxial structure can include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments in which the epitaxial structure is epitaxially grown, the epitaxially grown material can be doped in situ during growth, which can avoid previous and / or subsequent implantation, but in situ doping and implantation doping can be used together.

[0034] In addition, for illustrative purposes only, the first semiconductor layer 51 (and the resulting nanostructure 52) and the second semiconductor layer 53 (and the resulting nanostructure 54) are shown and discussed herein as including the same material in the p-type region 50P and the n-type region 50N. Thus, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials or may be formed in a different order in the p-type region 50P and the n-type region 50N.

[0035] Further in Figure 4In the embodiment having different well types, a photoresist or other mask (not shown separately) may be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist may be formed over the fins 66 and the STI region 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration of about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0036] After or before the implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., which is implanted into the region at a concentration of about 10 14 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0037] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implant damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fin may be in-situ doped during growth, which may eliminate implantation, but in-situ doping and implantation doping may be used together.

[0038] exist Figure 5In the embodiment of the present invention, a dummy dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A dummy gate layer 72 is formed on the dummy dielectric layer 760, and a mask layer 74 is formed on the dummy gate layer 72. The dummy gate layer 762 may be deposited on the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 may be deposited on the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material, and may be selected from the group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials with high etch selectivity relative to the etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 70 is shown as covering only the fin 66 and / or the nanostructure 55 for illustration purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited so that the dummy dielectric layer 70 covers the STI region 68, so that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0039] 6A to 16B Various additional steps in fabricating example devices are shown. Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig. 12C , Fig.13A , Fig. 13C , Fig.14A , Fig.15A and Fig.16A Features in either region 50N or region 50P are shown. Fig. 6A and Figure 6B In the embodiment, the mask layer 74 may be patterned using acceptable photolithography and etching techniques (see Figure 5) to form mask 78. The pattern of mask 78 can then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. Dummy gate 76 covers the corresponding channel region of fin 66. The pattern of mask 78 can be used to physically separate each of dummy gates 76 from adjacent dummy gates 76. Dummy gate 76 can also have a length direction substantially perpendicular to the length direction of the corresponding fin 66. .

[0040] exist Fig. 7A and Figure 7B In Fig. 6A and Figure 6B A first spacer layer 80 and a second spacer layer 82 are formed over the structure shown. The first spacer layer 80 and the second spacer layer 82 are then patterned to serve as spacers for forming self-aligned source / drain regions. Fig. 7A and Figure 7B , a first spacer layer 80 is formed on the top surface of the STI region 68; the top surface and sidewalls of the fin 66, the nanostructure 55, and the mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric layer 71. A second spacer layer 82 is deposited on the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation, or may be deposited by CVD, ALD, etc. The second spacer layer 82 may be formed of a material having a different etch rate from the material of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may be deposited by CVD, ALD, etc.

[0041] After forming the first spacer layer 80 and before forming the second spacer layer 82, an implant for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above, Figure 4 As discussed in the implantation, a mask (e.g., photoresist) can be formed over the n-type region 50N while exposing the p-type region 50P, and impurities of an appropriate type (e.g., p-type) can be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. Subsequently, a mask (e.g., photoresist) can be formed over the p-type region 50P while exposing the n-type region 50N, and impurities of an appropriate type (e.g., n-type) can be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the previously discussed n-type impurities, and the p-type impurity can be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have approximately 1×10 15 Atom / cm 3 About 1×10 19 Atom / cm 3Annealing can be used to repair implant damage and activate the implanted impurities.

[0042] exist Fig. 8A and Figure 8B , the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source and drain regions, and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processes. The first spacer layer 80 and the second spacer layer 82 can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer layer 82 has a different etching rate from the material of the first spacer layer 80, so that the first spacer layer 80 can be used as an etching stop layer when the second spacer layer 82 is patterned, and the second spacer layer 82 can be used as a mask when the first spacer layer 80 is patterned. For example, the second spacer layer 82 may be etched using an anisotropic etching process, wherein the first spacer layer 80 serves as an etch stop layer, and wherein the remaining portion of the second spacer layer 82 forms the second spacer 83, as shown in FIG. Fig. 8A Thereafter, the second spacer 83 is used as a mask while etching the exposed portion of the first spacer layer 80, thereby forming Fig. 8A A first spacer 81 is shown.

[0043] like Fig. 8A As shown, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As shown, in some embodiments, the second spacer layer 82 may be removed from above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy dielectric layer 60. In other embodiments, a portion of the second spacer layer 82 may remain above the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0044] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, etc. In addition, different structures and steps may be used to form n-type devices and p-type devices.

[0045] exist Fig.9A and Fig. 9BIn some embodiments, a first recess 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. An epitaxial source / drain region will be subsequently formed in the first recess 86. The first recess 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate. Fig.9A As shown, the top surface of the STI region 58 may be flush with the bottom surface of the first recess 86. In various embodiments, the fin 66 may be etched such that the bottom surface of the first recess 86 is disposed below the top surface of the STI region 68, etc. The first recess 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 86, the first spacer 81, the second spacer 83, and the mask 78 mask portions of the fin 66, the nanostructure 55, and the substrate 50. Each layer of the nanostructure 55 and / or the fin 66 may be etched using a single etching process or multiple etching processes. A timed etching process may be used to stop etching the first recess 86 after the first recess 86 reaches a desired depth.

[0046] exist Fig. 10A and Fig. 10B In the embodiment, the portion of the sidewalls of each layer of the multilayer stack 64 formed of the first semiconductor material (e.g., the first nanostructure 52) exposed by the first groove 86 is etched to form a sidewall groove 88 in the n-type region 50N, and the portion of the sidewalls of each layer of the multilayer stack 64 formed of the second semiconductor material (e.g., the second nanostructure 54) exposed by the first groove 86 is etched to form a sidewall groove 88 in the p-type region 50P. Fig. 10BThe sidewalls of the first nanostructure 52 and the second nanostructure 54 in the groove 88 are shown as straight, but these sidewalls can be concave or convex. The sidewalls can be etched using an isotropic etching process (e.g., wet etching, etc.). A mask (not shown) can be used to protect the p-type region 50P while etching the first nanostructure 52 using an etchant selective to the first semiconductor material, so that in the n-type region 50N, the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52. Similarly, a mask (not shown) can be used to protect the n-type region 50N while etching the second nanostructure 54 using an etchant selective to the second semiconductor material, so that in the p-type region 50P, the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54. In embodiments where the first nanostructure 52 includes, for example, SiGe and the second nanostructure 54 includes, for example, Si or SiC, the sidewalls of the first nanostructure 52 in the n-type region 50N may be etched using a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like, and the sidewalls of the second nanostructure 54 in the p-type region 50P may be etched using a dry etching process using hydrogen fluoride, another fluorine-based gas, or the like.

[0047] exist Figures 11A-11C In the embodiment, a first inner spacer 90 is formed in the sidewall groove 88. Fig. 10A and Fig. 10B An internal spacer layer (not shown separately) is deposited on the structure shown to form a first internal spacer 90. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced with corresponding gate structures.

[0048] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized, for example, a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and flush with the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first inner spacer 90 may extend beyond the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively, or be recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0049] In addition, despite the Fig. 11B The outer sidewall of the first inner spacer 90 is shown as straight, but the outer sidewall of the first inner spacer 90 can be concave or convex. As an example, Fig. 11C An embodiment is shown in which, in the n-type region 50P, the sidewalls of the first nanostructure 52 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer is recessed from the sidewalls of the second nanostructure 54. An embodiment is also shown in which, in the p-type region 50P, the sidewalls of the second nanostructure 54 are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer is recessed from the sidewalls of the first nanostructure 52. The inner spacer layer may be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 may be used to prevent the source / drain regions (e.g., the etching process for forming the gate structure) formed by a subsequent etching process (e.g., an etching process for forming the gate structure) from being etched. FIG. 12A to FIG. 12C Damage to the epitaxial source / drain regions 92) discussed.

[0050] exist Figure 12A-12C In the embodiment, an epitaxial source / drain region 92 is formed in the first recess 86. In some embodiments, the source / drain region 92 may exert stress on the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Fig. 12B As shown, epitaxial source / drain regions 92 are formed in first recesses 86 so that each dummy gate 76 is disposed between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, first spacers 81 are used to separate epitaxial source / drain regions 92 from dummy gates 72 by an appropriate lateral distance, and first inner spacers 90 are used to separate epitaxial source / drain regions 92 from nanostructures 55 by an appropriate lateral distance so that epitaxial source / drain regions 92 do not short-circuit the gate of a subsequently formed resulting nanoFET.

[0051] The epitaxial source / drain region 92 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 may include any acceptable material suitable for n-type nano FETs. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 may include a material that applies tensile strain on the second nanostructure 54, such as silicon, silicon carbide, silicon carbide doped with phosphorus, silicon phosphorus, etc. The epitaxial source / drain region 92 may have a surface protruding from the corresponding upper surface of the nanostructure 55, and may have a small facet.

[0052] The epitaxial source / drain region 92 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). Then, the epitaxial source / drain region 92 is epitaxially grown in the first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can include any acceptable material suitable for p-type nano FETs. For example, if the first nanostructure 52 is silicon germanium, the epitaxial source / drain region 92 can include a material that applies compressive strain on the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The epitaxial source / drain region 92 can also have a surface that protrudes from the corresponding surface of the multilayer stack 64, and can have a small facet.

[0053] The epitaxial source / drain regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, and then annealed. The impurity concentration of the source / drain regions may be about 1×10 19 Atom / cm 3 and about 1×10 21 Atom / cm 3 The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in-situ during growth.

[0054] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in n-type region 50N and p-type region 50P, the upper surfaces of epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same NSFET to merge, such as Fig. 12A In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, such as Fig. 12C As shown. Fig. 12A and Fig. 12C In the illustrated embodiment, the first spacer 81 can be formed at the top surface of the STI region 68 to prevent epitaxial growth. In some other embodiments, the first spacer 81 can cover a portion of the sidewalls of the nanostructure 55 to further prevent epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer 81 can be adjusted to remove the spacer material to allow the epitaxial growth area to extend to the surface of the STI region 58.

[0055] The epitaxial source / drain region 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration that is less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In embodiments where the epitaxial source / drain region 92 includes three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited on the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited on the second semiconductor material layer 92B.

[0056] Fig.12D An embodiment is shown in which the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are concave, the outer sidewalls of the first inner spacer 90 are concave, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Fig.12D As shown, the epitaxial source / drain regions 92 may be formed to contact the first inner spacer 90 and may extend beyond the sidewalls of the second nanostructures 54 in the n-type region 50N and beyond the sidewalls of the first nanostructures 52 in the p-type region 50P.

[0057] exist Figure 13A-13C In the embodiment, the first interlayer dielectric (ILD) 96 is deposited on Fig. 6A , Fig. 12B and Fig. 12A On top of the structure shown ( Figures 7A-12D The process will not change Fig. 6A). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the mask 74, and the first spacer 81. The CESL 94 may include a dielectric material having an etch rate different from that of the material of the first ILD 96 above, for example, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0058] exist Figure 14A-14B In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within process variations. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0059] exist Fig.15A and Fig. 15B In the embodiment of the present invention, the dummy gate 72 and the mask 74 (if present) are removed in one or more etching steps to form a second recess 98. The portion of the dummy gate dielectric 60 in the second recess 98 may also be removed. In some embodiments, the dummy gate 72 and the dummy gate dielectric 60 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using (one or more) reactive gases that selectively etch the dummy gate 72 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and / or overlies portions of the nanostructure 55 that serve as channel regions in the subsequently completed nanoFET. Portions of the nanostructure 55 that serve as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 may then be removed after the dummy gate 72 is removed.

[0060] exist Fig.16A and Fig. 16BIn the embodiment, the second nanostructure 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process (e.g., wet etching, etc.) using an etchant that is selective to the material of the second nanostructure 54, while the first nanostructure 52, the substrate 50, and the STI region 58 remain relatively unetched compared to the second nanostructure 54. In embodiments where the second nanostructure 54 includes, for example, SiGe and the first nanostructure 52 includes, for example, Si or SiC, hydrogen fluoride, another fluorine-based gas, etc. can be used to remove the second nanostructure 54 in the p-type region 50P.

[0061] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P may be formed simultaneously, for example, by removing the first nanostructure 52 in both the n-type region 50N and the p-type region, or by removing the second nanostructure 54 in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type NSFET and the p-type NSFET may have the same material composition, such as silicon, silicon germanium, etc. Fig.26A , Fig.26B and Fig.26C A structure resulting from an embodiment in which the channel regions in both the p-type region 50P and the n-type region 50N are provided by the second nanostructure 54 and comprise, for example, silicon is shown.

[0062] exist FIG. 17A to FIG. 22B In some embodiments, a gate dielectric layer and a gate electrode are formed for a replacement gate in a second recess 98. The gate electrode includes a barrier layer surrounding the WFM layer that physically separates portions of the WFM layer in certain areas of the gate stack (e.g., between nanostructures 52 / 54). Thus, regardless of the location of the WFM layer in the gate stack, the WFM layer can have good thickness uniformity and can advantageously reduce threshold voltage variation. Additionally, in some embodiments, the barrier layer includes tungsten deposited using a fluorine-containing precursor that allows fluorine to diffuse into the underlying gate dielectric. It has been observed that incorporating fluorine into the gate dielectric can improve device reliability.

[0063] The formation of the gate dielectric in the n-type region 50N and the p-type region 50P can occur simultaneously, so that the gate dielectric in each region is formed of the same material, and the formation of the gate electrode can occur simultaneously, so that the gate electrode in each region is formed of the same material. In some embodiments, the gate dielectric in each region can be formed by different processes, so that the gate dielectric can be a different material and / or have a different number of layers, and / or the gate electrode in each region can be formed by different processes, so that the gate electrode can be a different material and / or have a different number of layers. When different processes are used, various mask steps can be used to mask and expose appropriate areas. In the following description, the gate electrode of the n-type region 50N and the gate electrode of the p-type region 50P are formed separately.

[0064] FIG. 17A to FIG. 20B The gate dielectric 100 and the gate electrode 102 are shown formed in the p-type region 50P, and the n-type region 50P may be masked at least when the gate electrode 102 is formed in the p-type region (eg, as follows Figures 18A to 20B described above).

[0065] exist Fig.17A and Fig. 17B In the embodiment of the present invention, the gate dielectric 100 is conformally deposited in the second recess 98 of the p-type region 50P. The gate dielectric 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric 100 may include a first gate dielectric 101 (e.g., including silicon oxide, etc.), and a second gate dielectric 103 (e.g., including metal oxide, etc.) on the first gate dielectric 101. In some embodiments, the second gate dielectric 103 includes a high-k dielectric material, and in these embodiments, the k value of the second gate dielectric 103 may be greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In some embodiments, the first gate dielectric 101 may be referred to as an interfacial layer, and the second gate dielectric 103 may be referred to as a high-k gate dielectric.

[0066] The structure of the gate dielectric 100 may be the same or different in the n-type region 50N and the p-type region 50P. For example, the n-type region 50N may be masked or exposed while forming the gate dielectric 100 in the p-type region 50P. In an embodiment in which the n-type region 50N is exposed, the gate dielectric 100 may be formed simultaneously in the n-type region 50N. The formation method of the gate dielectric 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0067] exist Fig.18A and Fig.18BIn the embodiment of the present invention, the conductive material 105 is conformally deposited on the gate dielectric 100 in the p-type region 50P. In some embodiments, the conductive material 105 is a p-type WFM, including titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, etc. The conductive material 105 can be deposited by CVD, ALD, PECVD, PVD, etc. The conductive material 105 can have a thickness T1 on the surface of the nanostructure 52, and the ratio of the thickness T1 to the distance D1 between adjacent nanostructures 52 can be in the range of about 0.05 to about 0.2. It has been observed that by having a ratio of the thickness T1 to the distance D1 within this range, undesirable merging of the conductive material 105 can be avoided. For example, by keeping the ratio within the above range, the conductive material 105 can remain unmerged. As a result, the thickness of the conductive material 105 in the inner region 50I (e.g., between adjacent nanostructures 52) can be substantially equal to the thickness of the conductive material 105 outside the inner region 50I. As a result, the threshold voltage variation of the resulting device can be advantageously reduced. For example, the opening 130 remains in the inner region 50I between a first portion of the conductive material 105 (eg, a portion on the lower surface of the first nanostructure 52 ) and a second portion of the conductive material 105 (eg, a portion on the upper surface of the first nanostructure 52 ).

[0068] exist Fig.19A , Fig.19B and Fig.19C , the barrier material 107 is conformally deposited on the conductive material 105. In some embodiments, the barrier material 107 includes tungsten and is deposited by a deposition process 109. The deposition process 109 may be an ALD process, etc. In some embodiments, the process temperature of the deposition process 109 may be in the range of about 250°C to about 450°C. It has been observed that a deposition temperature below about 250°C may result in an unacceptably low deposition rate, thereby adversely affecting production yield. It has also been observed that a deposition temperature above 450°C may result in damage to process tools (e.g., damage to the ALD deposition chamber). In some embodiments, the deposition process 109 may be performed at a pressure of about 0.5 Torr to about 20 Torr. It has been observed that a deposition pressure outside this range (e.g., less than about 0.5 Torr or greater than about 20 Torr) may result in an inability to accurately control the deposition process, thereby adversely affecting yield.

[0069] In addition, the deposition process 109 may include flowing one or more precursors into the deposition chamber, and the one or more precursors may include a fluorine-containing precursor. For example, during the deposition process 109, a first precursor (e.g., WF6, etc.) and a second precursor (e.g., SiH4, etc.) may flow into the process chamber in sequence. The first precursor and the second precursor may react with the exposed surface of the wafer to form a monolayer of the barrier material 107. In the deposition process 109, the ratio of the amount of the first precursor (e.g., WF6, etc.) to the amount of the second precursor (e.g., SiH4, etc.) may be in the range of about 0.75 to about 1.25. In the deposition process 109, the first precursor and the second precursor may be alternately provided to the deposition chamber. The first precursor and the second precursor may each flow at a rate of about 30 sccm to about 300 sccm, and each flow at a pulse time of about 0.5 seconds to about 60 seconds. It has been observed that by keeping the precursor ratio, flow rate and / or pulse time within the above range during the deposition process 109, the desired fluorine concentration may be achieved in the gate dielectric layer 103.

[0070] In some embodiments, the deposition process 109 may cause fluorine to diffuse into the underlying gate dielectric 100. For example, Fig.19C A detailed view of region 111 during deposition process 109 is shown. By using a fluorine-containing precursor, fluorine particles 113 diffuse through barrier material 107 and conductive material 105 into gate dielectric 100. As a result, fluorine may be present in conductive material 105 and gate dielectric 100. This is also Fig.19E , which shows that after performing the deposition process 109, along Fig.19A and Fig.19B Energy dispersive X-ray spectroscopy (EDS) line scan curve (linescan) of line 115. Fig.19E As shown, fluorine is present in the conductive material 105 and the gate dielectric 100 .

[0071] For example, as a result of the deposition process 109, the fluorine concentration in the second gate dielectric layer 103 can be in a range of about 0.5% to about 10%. It has been observed that having a fluorine concentration within this range has advantages, such as improved device reliability. For example, when the second gate dielectric layer 103 has a fluorine concentration of less than 0.5%, device reliability may deteriorate. As another example, when the second gate dielectric 103 has a fluorine concentration greater than 10%, the capacitance equivalent thickness (CET) of the second gate dielectric 103 may deteriorate. By controlling the mixture of the first precursor and the second precursor (e.g., in the above-mentioned ratio, flow rate and / or pulse time), a desired fluorine concentration can be achieved in one or more gate dielectrics 100.

[0072] The barrier material 107 may fill the remainder of the inner region 50I between the first nanostructures 52 (eg, fill the openings 130, see Fig.18A and Fig.18B ). For example, the barrier material 107 can be deposited on the conductive material 105 until they are fused and welded together, and in some embodiments, an interface 107I can be formed by a first portion 107A of the barrier material 107 (e.g., the first barrier material 107A) that contacts a second portion 107B of the barrier layer 107 in the region 50I (e.g., the second barrier material 107B).

[0073] Fig.19D A detailed cross-sectional view of the inner region 50I between adjacent nanostructures 52 according to some embodiments is shown. In the resulting structure, the stack of materials in the inner region 50I may include: a first portion of the gate dielectric 100 (e.g., the first gate dielectric 100A), a first portion of the conductive material 105 (e.g., the first conductive material 105A) on the gate dielectric 100A, a first barrier material 107A, a second barrier material 107B on the first barrier material 107A and forming an interface with the first barrier material 107A, a second portion of the conductive material 105 (e.g., the second conductive material 105B) on the second barrier material 107B, and a second portion of the gate dielectric 100 (e.g., the second gate dielectric 100B) on the second conductive material 105B. The first gate dielectric 100A includes an interfacial layer 101A and a high-k gate dielectric 103A, and the second gate dielectric 100B includes an interfacial layer 101B and a high-k gate dielectric 103B. The first barrier material 107A and the second barrier material 107B physically separate the first conductive material 105A and the second conductive material 105B in the inner region 50I and can prevent merging of the conductive materials 105. As a result, the thickness of the conductive material 105 in the region 50I can be substantially equal to the thickness of the conductive material 105 outside the region 50I (e.g., within process variations), and threshold voltage variations can be reduced.

[0074] In other embodiments, the barrier material 107 can include a different material and / or be deposited using a different process. For example, the barrier material 107 includes a conductive material deposited using a process that may or may not use a fluorine-containing precursor.

[0075] exist Fig. 20A and Fig. 20BIn the embodiment of the present invention, the remaining portion of the gate electrode 102 is deposited to fill the remaining portion of the second groove 98. For example, an adhesion layer 117 and a filling metal 119 may be deposited over the barrier material 107. The formed gate electrode 102 is formed to be used as a replacement gate and may include the conductive material 105, the barrier material 107, the adhesion layer 117 and the filling metal 119.

[0076] In some embodiments, adhesion layer 117 is conformally deposited on barrier material 107 in p-type region 50P. In some embodiments, adhesion layer 117 includes titanium nitride, tantalum nitride, etc. Adhesion layer 117 may be deposited by CVD, ALD, PECVD, PVD, etc. Adhesion layer 117 may alternatively be referred to as a glue layer and, for example, improves adhesion between barrier material 107 and an overlying fill metal 119.

[0077] A fill metal 119 may then be deposited over the adhesion layer 117. In some embodiments, the fill metal 119 comprises cobalt, ruthenium, aluminum, tungsten, combinations thereof, and the like, which is deposited by CVD, ALD, PECVD, PVD, and the like. The fill metal 119 may have the same material composition as the barrier material 107. In such embodiments, the fill metal 119 may be deposited using a different process than the barrier material 107. For example, the fill metal 119 may include tungsten deposited using a CVD process, and the barrier material 107 may include tungsten deposited using an ALD process. It has been observed that CVD provides an improved deposition rate for the fill metal 119, while the ALD process provides improved thickness control for the barrier material 107, so that the fill metal 119 may be deposited in small areas (e.g., in the inner area 50I, see FIG. 5 ). Fig.19A ) is precisely deposited. In some embodiments, the CVD process for depositing the fill metal 119 may use the same precursor as the ALD process 109. For example, the CVD process for the fill metal 119 may include supplying a first precursor (e.g., WF6, etc.) and a second precursor (e.g., SiH4, etc.) in a CVD process chamber. In some embodiments, the first precursor and the second precursor may be supplied simultaneously during the CVD process for the fill metal 119, and the first precursor and the second precursor may be supplied alternately during the ALD process 109.

[0078] In the p-type region 50P, the gate dielectric 100, the conductive material 105, the barrier material 107, the adhesion layer 117, and the filling metal 119 may each be formed on the top surface, the sidewall, and the bottom surface of the first nanostructure 52. The gate dielectric 100, the conductive material 105, the barrier material 107, the adhesion layer 117, and the filling metal 119 may also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 58. After filling the second groove 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric 100, the conductive material 105, the barrier material 107, the adhesion layer 117, and the filling metal 119, which are above the top surface of the first ILD 96. The remaining portions of the gate electrode 102 and the gate dielectric 100 material thus form a replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric 100 may be collectively referred to as a "gate structure".

[0079] although Fig. 20A and Fig. 20B The gate dielectric 100 and the gate electrode 102 are shown as having straight sidewalls and right angles, but the gate dielectric 100 and the gate electrode 102 may have different configurations. For example, Fig.21 1 shows a cross-sectional view of a gate dielectric 100 and a gate electrode 102 according to another embodiment. Fig.21 In the drawings, the same reference numerals denote Fig. 20A and Fig. 20B However, in Fig.21 In the embodiment, since the nanostructure 51 has rounded corners, the gate dielectric 100 and the gate electrode 102 may also have rounded corners.

[0080] Fig.22A and Fig. 22B A gate stack in an n-type region 50N is shown. Forming a gate stack in the n-type region 50N may include first removing the first nanostructure 52 in the n-type region 50N. The first nanostructure 52 may be removed by forming a mask (not shown) over the p-type region 50P and performing an isotropic etching process such as a wet etch using an etchant selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 68 remain relatively unetched compared to the first nanostructure 52. In embodiments where the first nanostructure 52A-52C includes, for example, SiGe and the second nanostructure 54A-54C includes, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructure 52 in the n-type region 50N.

[0081] A gate stack is then formed over and around the second nanostructure 54 in the n-type region 50N. The gate stack includes a gate dielectric 100 and a gate electrode 127. In some embodiments, the gate dielectric 100 in the n-type region 50N and the p-type region 50P may be formed simultaneously. In addition, at least a portion of the gate electrode 127 may be formed before or after the gate electrode 102 is formed (see Fig. 20A and Fig. 20B ), and at least a portion of the gate electrode 127 may be formed while masking the p-type region 50P. In this way, the gate electrode 127 may include a material different from that of the gate electrode 102. For example, the gate electrode 127 may include a conductive layer 121, a barrier layer 123, and a fill metal 125. The conductive layer 121 may be an n-type work function metal (WFM) layer, including an n-type metal such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like. The conductive layer 121 may be deposited by CVD, ALD, PECVD, PVD, and the like. The barrier layer 123 may include titanium nitride, tantalum nitride, tungsten carbide, combinations thereof, and the like, and the barrier layer 123 may further serve as an adhesion layer. The barrier layer 123 may be deposited by CVD, ALD, PECVD, PVD, and the like. The fill metal 125 includes cobalt, ruthenium, aluminum, tungsten, combinations thereof, and the like, which are deposited by CVD, ALD, PECVD, PVD, and the like. Fill metal 125 may or may not have the same material composition as fill metal 119 , and may or may not be deposited simultaneously with fill metal 119 .

[0082] After filling the second recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric 100 and the gate electrode 127 that are above the top surface of the first ILD 96. The remaining portions of the gate electrode 127 and the gate dielectric 100 material thus form a replacement gate structure of the resulting nanoFET of the n-type region 50N. The CMP process for removing excess material of the gate electrode 102 in the p-type region 50P and the CMP process for removing excess material of the gate electrode 127 in the n-type region 50N may be performed simultaneously or separately.

[0083] exist Figures 23A-23C In the process, the gate structure (including the gate dielectric 100, the gate electrode 102, and the gate electrode 127) is recessed to form a groove directly above the gate structure and between the opposite portion of the first spacer 81. A gate mask 104 including one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the groove, and then a planarization process is performed to remove the excess portion of the dielectric material extending above the first ILD 96. The gate contact (e.g., as described below) formed subsequently Fig.24A and Fig. 24BThe gate contact 114 discussed here passes through the gate mask 104 to contact the top surface of the recessed gate electrode 102 .

[0084] like Figures 23A-23C As further shown, the second ILD 106 is deposited on the first ILD 96 and on the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0085] exist Figures 24A-24C , the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a third recess 108, exposing the surface of the epitaxial source / drain region 92 and / or the gate structure. The third recess 108 can be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; etched through the gate mask 104 using a second etching process; and then etched through the CESL 94 using a third etching process. A mask (e.g., photoresist) can be formed over the second ILD 106 and patterned to mask portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, so that the third recess 108 extends into the epitaxial source / drain region 92 and / or the gate structure, and the bottom of the third recess 108 may be flush with (e.g., at the same level or having the same distance from the substrate) or lower than (e.g., closer to the substrate) the epitaxial source / drain region 92 and / or the gate structure. Fig. 24B The third recess 108 is shown exposing the epitaxial source / drain regions 92 and the gate structure with the same cross-section, but in various embodiments, the epitaxial source / drain regions 92 and the gate structure may be exposed with different cross-sections to reduce the risk of shorting subsequently formed contacts.

[0086] After forming the third recess 108, a silicide region 110 is formed on the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal capable of reacting with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof, on the exposed portion of the epitaxial source / drain region 92, and then performing a thermal annealing process to form the silicide region 110. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, the silicide region 110 may also be a germanide region, or a silicon germanide region (e.g., a region including silicide and germanide). In an embodiment, the silicide region 110 includes TiSi and has a thickness in a range between about 2 nm and about 10 nm.

[0087] Next, in Fig.25A -C, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. The contacts 112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the contacts 112 and 114 each include a barrier layer and a conductive material, and are electrically coupled to the underlying conductive features (e.g., in the illustrated embodiment, the gate electrode 102, the gate electrode 127, and / or the silicide region 110). The contact 114 is electrically coupled to the gate electrodes 102 and 127 and may be referred to as a gate contact, and the contact 112 is electrically coupled to the silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

[0088] Fig.26A -C shows a cross-sectional view of a device according to some alternative embodiments. Fig.26A Shows Figure 1 Reference section AA' is shown. Fig.26B Shows Figure 1 Reference section BB' is shown. Fig.26C Shows Figure 1 Reference section C-C' is shown. Fig.26A -C, the same reference numerals are used to represent Fig.25A -C structure is formed by the same process as the same components. However, in Fig.26A-C, the channel regions in the n-type region 50N and the p-type region 50P include the same material. For example, the second nanostructure 54 including silicon provides a channel region for a p-type NSFET in the p-type region 50P and provides a channel region for an n-type NSFET in the n-type region 50N. This can be formed, for example, by the following operations: Fig.26A -C structure: the first nanostructure 52 is removed from both the p-type region 50P and the n-type region 50N; the gate dielectric 100 and the gate electrode 102 are deposited around the second nanostructure 54 in the p-type region 50P; and the gate dielectric 100 and the gate electrode 104 are deposited around the first nanostructure 54 in the n-type region 50N.

[0089] Various embodiments provide a gate stack comprising a relatively thin WFM layer and a barrier layer on the WFM layer. The barrier layer physically separates portions of the WFM layer in various regions of the gate stack (e.g., between adjacent nanostructures of a nanoFET). By separating the WFM layer from the barrier layer, threshold voltage variations can be advantageously reduced, thereby improving device reliability and performance. Additionally, the barrier layer can be deposited by a process that provides a fluorine-containing precursor. In such embodiments, fluorine from the precursor can diffuse into the gate dielectric layer of the transistor, thereby improving device performance.

[0090] In some embodiments, a device includes: a first nanostructure; a second nanostructure, above the first nanostructure; a first high-k gate dielectric, around the first nanostructure; a second high-k gate dielectric, around the second nanostructure; and a gate electrode, above the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure includes: a first p-type work function metal; a barrier material, above the first p-type work function metal; and a second p-type work function metal, above the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal. Optionally, in some embodiments, the barrier material includes tungsten. Optionally, in some embodiments, the first p-type work function metal and the second p-type work function metal each include titanium nitride. Optionally, in some embodiments, the first p-type work function metal has a first thickness, the first nanostructure is spaced apart from the second nanostructure by a first distance, and a ratio of the first thickness to the first distance is in a range of 0.05 to 0.2. Optionally, in some embodiments, the first high-k gate dielectric includes fluorine. Optionally, in some embodiments, the fluorine concentration in the first high-k gate dielectric is in the range of 0.5% to 10%. Optionally, in some embodiments, the gate electrode further comprises an adhesion layer above the barrier material, the adhesion layer not extending between the first nanostructure and the second nanostructure. Optionally, in some embodiments, the adhesion layer has the same material composition as the first p-type work function metal.

[0091] In some embodiments, a transistor includes: a first nanostructure on a semiconductor substrate; a second nanostructure on the first nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure; and a gate electrode on the gate dielectric. The gate electrode includes: a p-type work function metal; a barrier material on the p-type work function metal, the barrier material physically separating a first portion of the p-type work function metal from a second portion of the p-type work function metal in a region between the first nanostructure and the second nanostructure; an adhesion layer on the barrier material; and a filler metal on the adhesion layer. Optionally, in some embodiments, the barrier material includes a first barrier material and a second barrier material, the first barrier material and the second barrier material forming an interface, the first barrier material and the second barrier material extending into a region between the first nanostructure and the second nanostructure. Optionally, in some embodiments, the barrier material includes tungsten, and the p-type work function metal includes titanium nitride. Optionally, in some embodiments, the ratio of the thickness of the p-type work function metal to the distance between the first nanostructure and the second nanostructure is in the range of 0.05 to 0.2. Optionally, in some embodiments, the gate dielectric includes fluorine. Optionally, in some embodiments, the p-type work function metal comprises fluorine. Optionally, in some embodiments, the transistor further comprises an interface layer, below the gate dielectric, the interface layer surrounds the first nanostructure and the second nanostructure, and the gate dielectric comprises a high-k material.

[0092] In some embodiments, a method includes: depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure being disposed on the second nanostructure; depositing a p-type work function metal on the gate dielectric, wherein after depositing the p-type work function metal, an opening is retained between a first portion of the p-type work function metal and a second portion of the p-type work function metal, the first portion of the p-type work function metal and the second portion of the p-type work function metal being between the first nanostructure and the second nanostructure; and depositing a barrier material on the p-type work function metal using an atomic layer deposition (ALD) process, wherein the barrier material fills the opening between the first portion of the p-type work function metal and the second portion of the p-type work function metal. Optionally, in some embodiments, the ALD process includes depositing the barrier material using a fluorine-containing precursor. Optionally, in some embodiments, the fluorine-containing precursor is WF6. Optionally, in some embodiments, the ALD process includes flowing the fluorine-containing precursor at a rate of 30 sccm to 300 sccm. Optionally, in some embodiments, the ALD process includes flowing the fluorine-containing precursor with a pulse time in the range of 0.5 seconds to 60 seconds.

[0093] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0094] Example 1 is a semiconductor device comprising: a first nanostructure; a second nanostructure above the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode above the first high-k gate dielectric and the second high-k gate dielectric, wherein a portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material above the first p-type work function metal; and a second p-type work function metal above the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

[0095] Example 2 is the device of Example 1, wherein the barrier material comprises tungsten.

[0096] Example 3 is the device of Example 1, wherein the first p-type work function metal and the second p-type work function metal each include titanium nitride.

[0097] Example 4 is the device of Example 1, wherein the first p-type work function metal has a first thickness, the first nanostructure is separated from the second nanostructure by a first distance, and a ratio of the first thickness to the first distance is in a range of 0.05 to 0.2.

[0098] Example 5 is the device of Example 1, wherein the first high-k gate dielectric comprises fluorine.

[0099] Example 6 is the device of Example 5, wherein the fluorine concentration in the first high-k gate dielectric is in a range of 0.5% to 10%.

[0100] Example 7 is the device of Example 1, wherein the gate electrode further includes an adhesion layer over the barrier material, the adhesion layer not extending between the first nanostructure and the second nanostructure.

[0101] Example 8 is the device of Example 7, wherein the adhesion layer has a same material composition as the first p-type work function metal.

[0102] Example 9 is a transistor comprising: a first nanostructure on a semiconductor substrate; a second nanostructure on the first nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure; and a gate electrode on the gate dielectric, wherein the gate electrode comprises: a p-type work function metal; a barrier material on the p-type work function metal, the barrier material physically separating a first portion of the p-type work function metal from a second portion of the p-type work function metal in a region between the first nanostructure and the second nanostructure; an adhesion layer on the barrier material; and a fill metal on the adhesion layer.

[0103] Example 10 is the transistor described in Example 9, wherein the blocking material includes a first blocking material and a second blocking material, the first blocking material forms an interface with the second blocking material, and the first blocking material and the second blocking material extend into the region between the first nanostructure and the second nanostructure.

[0104] Example 11 is the transistor of Example 9, wherein the barrier material comprises tungsten and the p-type work function metal comprises titanium nitride.

[0105] Example 12 is the transistor of Example 9, wherein a ratio of a thickness of the p-type work function metal to a distance between the first nanostructure and the second nanostructure is in a range of 0.05 to 0.2.

[0106] Example 13 is the transistor of Example 9, wherein the gate dielectric comprises fluorine.

[0107] Example 14 is the transistor of Example 9, wherein the p-type work function metal includes fluorine.

[0108] Example 15 is the transistor of Example 9, further comprising: an interface layer below the gate dielectric, the interface layer surrounding the first nanostructure and the second nanostructure, and the gate dielectric comprising a high-k material.

[0109] Example 16 is a method for forming a semiconductor device, comprising: depositing a gate dielectric around a first nanostructure and a second nanostructure, the first nanostructure being disposed above the second nanostructure; depositing a p-type work function metal above the gate dielectric, wherein, after depositing the p-type work function metal, an opening is retained between a first portion of the p-type work function metal and a second portion of the p-type work function metal, the first portion of the p-type work function metal and the second portion of the p-type work function metal being between the first nanostructure and the second nanostructure; and depositing a barrier material above the p-type work function metal using an atomic layer deposition (ALD) process, wherein the barrier material fills the opening between the first portion of the p-type work function metal and the second portion of the p-type work function metal.

[0110] Example 17 is the method of Example 16, wherein the ALD process includes depositing the barrier material using a fluorine-containing precursor.

[0111] Example 18 is the method described in Example 17, wherein the fluorine-containing precursor is WF6.

[0112] Example 19 is the method of Example 17, wherein the ALD process includes flowing the fluorine-containing precursor at a rate of 30 sccm to 300 sccm.

[0113] Example 20 is the method of Example 17, wherein the ALD process includes flowing the fluorine-containing precursor with a pulse time in a range of 0.5 seconds to 60 seconds.

Claims

1. A semiconductor device, comprising: First nanostructure; a second nanostructure, on top of the first nanostructure; a first high-k gate dielectric surrounding the first nanostructure; a second high-k gate dielectric surrounding the second nanostructure; as well as a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric, wherein a portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material on the first p-type work function metal; and a second p-type work function metal above the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal, and wherein the combination of the first p-type work function metal, the barrier material, and the second p-type work function metal extend continuously from the upper surface of the first high-k gate dielectric to the lower surface of the second high-k gate dielectric.

2. The device according to claim 1, wherein The barrier material includes tungsten.

3. The device according to claim 1, wherein The first p-type work function metal and the second p-type work function metal each include titanium nitride.

4. The device according to claim 1, wherein The first p-type work function metal has a first thickness, the first nanostructure is spaced apart from the second nanostructure by a first distance, and a ratio of the first thickness to the first distance is in a range of 0.05 to 0.

2.

5. The device according to claim 1, wherein The first high-k gate dielectric includes fluorine.

6. The device according to claim 5, wherein The fluorine concentration in the first high-k gate dielectric is in the range of 0.5% to 10%.

7. The device according to claim 1, wherein The gate electrode also includes an adhesion layer over the barrier material, the adhesion layer not extending between the first nanostructure and the second nanostructure.

8. The device according to claim 7, wherein The adhesion layer has a same material composition as the first p-type work function metal.

9. A transistor comprising: A first nanostructure, on a semiconductor substrate; a second nanostructure, on top of the first nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure; as well as a gate electrode on the gate dielectric, wherein the gate electrode comprises: p-type work function metal; a barrier material on the p-type work function metal, the barrier material physically separating a first portion of the p-type work function metal from a second portion of the p-type work function metal in a region between the first nanostructure and the second nanostructure, wherein the barrier material comprises a first barrier material and a second barrier material, the first barrier material and the second barrier material forming an interface, the first barrier material and the second barrier material extending into the region between the first nanostructure and the second nanostructure; an adhesion layer on the barrier material; and A filler metal is formed on top of the adhesion layer.

10. The transistor according to claim 9, wherein The barrier material includes tungsten and the p-type work function metal includes titanium nitride.

11. The transistor according to claim 9, wherein A ratio of a thickness of the p-type work function metal to a distance between the first nanostructure and the second nanostructure is in a range of 0.05 to 0.

2.

12. The transistor according to claim 9, wherein The gate dielectric includes fluorine.

13. The transistor according to claim 9, wherein: The p-type work function metal includes fluorine.

14. The transistor according to claim 9, further comprising: An interface layer is provided below the gate dielectric, the interface layer surrounds the first nanostructure and the second nanostructure, and the gate dielectric comprises a high-k material.

15. A method of forming a semiconductor device, comprising: depositing a first gate dielectric around a first nanostructure and depositing a second gate dielectric around a second nanostructure, the first nanostructure being disposed over the second nanostructure; depositing a p-type work function metal over the first gate dielectric and the second gate dielectric, wherein, after depositing the p-type work function metal, an opening remains between a first portion of the p-type work function metal surrounding the first gate dielectric and a second portion of the p-type work function metal surrounding the second gate dielectric, the first portion of the p-type work function metal and the second portion of the p-type work function metal being between the first nanostructure and the second nanostructure; and A barrier material is deposited over the p-type work function metal using an atomic layer deposition (ALD) process, wherein the barrier material fills the opening between the first portion of the p-type work function metal and the second portion of the p-type work function metal.

16. The method according to claim 15, wherein: The ALD process includes depositing the barrier material using a fluorine-containing precursor.

17. The method according to claim 16, wherein: The fluorine-containing precursor is WF6.

18. The method according to claim 16, wherein: The ALD process includes flowing the fluorine-containing precursor at a rate of 30 sccm to 300 sccm.

19. The method according to claim 16, wherein: The ALD process includes flowing the fluorine-containing precursor with a pulse time in a range of 0.5 seconds to 60 seconds.

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