Method for operating device, semiconductor structure and image sensor

Abstract

A method of operating a device, a semiconductor structure, and an image sensor, the device including a photodetector circuit, the photodetector circuit including a photodetector and a sensing circuit, the photodetector and the sensing circuit being located above a substrate semiconductor layer doped with a first conductivity type. The photodetector includes: a pinned photodiode layer of a second conductivity type, which forms a p-n junction with the substrate semiconductor layer; at least one floating diffusion region, the floating diffusion region being laterally spaced from a periphery of the pinned photodiode layer of the second conductivity type; and at least one transfer gate. At least two different operations can be performed by applying at least two different pulse patterns to the at least one transfer gate. The at least two different pulse patterns differ from each other in at least one of the following: pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and a pulse initiation at a corresponding one of the at least one transfer gate.

Description

Technical Field

[0001] The present disclosure relates to a method of operating a device, a semiconductor structure, and a complementary metal oxide semiconductor image sensor. Background Art

[0002] Semiconductor image sensors are used to sense electromagnetic radiation, such as light in the visible range, infrared radiation, and / or ultraviolet light. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in various applications such as digital cameras or embedded cameras in mobile devices. These devices use an array of pixels (which may include photodiodes and transistors) to detect radiation using photogeneration of electron-hole pairs. In the prior art, each pixel in the array is designed for a corresponding dedicated single function. Summary of the invention

[0003] In some embodiments of the present disclosure, a method of operating a device includes the following operations: providing a device including a photodetector circuit, wherein the photodetector circuit includes a photodetector and a sensing circuit, the photodetector and the sensing circuit being located above a substrate semiconductor layer doped with a first conductivity type, wherein the photodetector includes: a pinned photodiode layer of a second conductivity type forming a pn junction with the substrate semiconductor layer; at least one floating diffusion region, the floating diffusion region being laterally spaced from a periphery of the pinned photodiode layer of the second conductivity type; and at least one transfer gate. At least two different operations are performed in the photodetector circuit by applying at least two different pulse patterns to the at least one transfer gate, wherein the at least two different pulse patterns differ from each other in at least one of the following: pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and a pulse activation at a corresponding one of the at least one transfer gate.

[0004] In some embodiments of the present disclosure, a semiconductor structure includes a substrate semiconductor layer having a doping of a first conductivity type; and a photodetector circuit located on the substrate semiconductor layer and including a photodetector and a sensing circuit. The photodetector includes: a pinned photodiode layer of a second conductivity type, which forms a pn junction with the substrate semiconductor layer; at least one floating diffusion region, the floating diffusion region being laterally spaced from a periphery of the pinned photodiode layer of the second conductivity type; and at least one transfer gate. The photodetector circuit is configured to perform at least two different operations by applying at least two different pulse patterns to the at least one transfer gate. The at least two different pulse patterns differ from each other in at least one of the following: pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and a pulse activation at a corresponding one of the at least one transfer gate.

[0005] In some embodiments of the present disclosure, a complementary metal oxide semiconductor image sensor includes an array of multiple pixels located on a substrate semiconductor layer having a first conductivity type doping. Each of the pixels includes at least one sub-pixel, and each sub-pixel includes a photodetector circuit, the photodetector circuit including a photodetector and a sensing circuit. The photodetector includes: a pinned photodiode layer of a second conductivity type, which forms a pn junction with the substrate semiconductor layer; a plurality of floating diffusion regions, the floating diffusion regions are electrically isolated from each other or from each other and are laterally spaced from the periphery of the pinned photodiode layer of the second conductivity type; and a plurality of transfer gates. The photodetector circuit is used to perform at least two different operations by applying at least two different pulse patterns to the transfer gates. The at least two different pulse patterns differ from each other or from each other in one of the following: pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and a pulse start at a corresponding one of the transfer gates. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A is a plan view of a first configuration of a pixel array for an image sensor according to an embodiment of the present disclosure;

[0008] Figure 1B is a plan view of a second configuration of a pixel array for an image sensor according to another embodiment of the present disclosure;

[0009] Figure 2Ais a plan view of a front-side sensor component within the region of a sub-pixel in a first configuration of a first exemplary structure according to an embodiment of the present disclosure;

[0010] Figure 2B is along Figure 2A A vertical cross-sectional view of a first exemplary structure of an articulated vertical plane B–B′–B″–B″′;

[0011] Figure 2C is a plan view of a front-side sensor component within the region of a sub-pixel in a second configuration of the first exemplary structure according to an embodiment of the present disclosure;

[0012] Figure 2D is a plan view of a front-side sensor component within the region of a sub-pixel in a third configuration of the first exemplary structure according to an embodiment of the present disclosure;

[0013] Figure 2E is a plan view of a front-side sensor component within the region of a sub-pixel in a fourth configuration of the first exemplary structure according to an embodiment of the present disclosure;

[0014] Figure 3A is a plan view of a front-side sensor component within the region of a sub-pixel in a first configuration of a second exemplary structure according to an embodiment of the present disclosure;

[0015] Figure 3B is a plan view of a front-side sensor component within the region of a sub-pixel in a second configuration of a second exemplary structure according to an embodiment of the present disclosure;

[0016] Figure 3C yes Figure 3B an enlarged plan view of a second configuration of a second exemplary structure;

[0017] Figure 4 is a vertical cross-sectional view of an exemplary structure after formation of a metal interconnect structure formed within an interconnect-level dielectric layer and attachment of a carrier substrate according to an embodiment of the present disclosure;

[0018] Figure 5 is a vertical cross-sectional view of an exemplary structure after thinning a semiconductor substrate according to an embodiment of the present disclosure;

[0019] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming a deep trench on the back side of a semiconductor substrate according to an embodiment of the present disclosure;

[0020] Figure 7 is a vertical cross-sectional view of an exemplary structure after removal of a hard mask layer and a liner dielectric layer according to an embodiment of the present disclosure;

[0021] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming a dielectric metal oxide liner and a dielectric isolation layer according to an embodiment of the present disclosure;

[0022] Fig. 9 is a vertical cross-sectional view of an exemplary structure after forming a deep trench isolation structure according to an embodiment of the present disclosure;

[0023] Fig.10 is a vertical cross-sectional view of an exemplary structure after forming an antireflective coating (ARC) layer, an optical refractive layer, a dielectric grid material layer, a metal reflective material layer, and a patterned photoresist layer according to an embodiment of the present disclosure;

[0024] Fig.11A is a vertical cross-sectional view of an exemplary structure after forming a composite grid structure according to an embodiment of the present disclosure;

[0025] Fig. 11B yes Fig.11A Plan view of an exemplary structure of; the hinged vertical plane A-A' corresponds to Fig.11A The plane of the vertical cross-section;

[0026] Fig.12 is a vertical cross-sectional view of an exemplary structure after forming an optically transparent layer, a color filter, and a lens according to an embodiment of the present disclosure;

[0027] Fig.13 is a vertical cross-sectional view of an exemplary structure after removal of a carrier substrate according to an embodiment of the present disclosure;

[0028] Fig.14 is a circuit diagram of a first configuration of a first photodetector circuit according to an embodiment of the present disclosure;

[0029] Fig.15 is a circuit diagram of a second configuration of a first photodetector circuit according to an embodiment of the present disclosure;

[0030] Fig.16 is a circuit diagram of a second photodetector circuit according to an embodiment of the present disclosure;

[0031] Fig.17 A schematic diagram of a CMOS image sensor incorporating the photodetector circuit and control circuit of the present disclosure;

[0032] Fig.18 is a timing diagram illustrating an exemplary set of voltage signals as a function of time during operation of a first exemplary photodetector circuit according to an embodiment of the present disclosure;

[0033] Fig.19 is a timing diagram illustrating exemplary pulse patterns for two transfer gates in a first exemplary photodetector circuit according to an embodiment of the present disclosure;

[0034] Fig. 20 is a timing diagram illustrating an exemplary set of voltages as a function of time during operation of a second exemplary photodetector circuit according to an embodiment of the present disclosure;

[0035] Fig.21 is a timing diagram illustrating an exemplary pulse pattern for a transfer gate in a second photodetector circuit according to an embodiment of the present disclosure;

[0036] Fig. 22 is a process flow diagram illustrating an exemplary process sequence for forming an image sensor according to an embodiment of the present disclosure.

[0037]

Explanation of symbols

[0038] 500:Semiconductor substrate

[0039] 510:Semiconductor substrate

[0040] 600:Front sensor component

[0041] 601: substrate semiconductor layer

[0042] 602: Pinned photodiode layer of the second conductivity type

[0043] 603: Pinning layer of the first conductivity type

[0044] 605: transfer gate

[0045] 605A: first transfer gate

[0046] 605B: Second transfer gate

[0047] 605C: third transfer gate

[0048] 606: embedded second conductivity type pinned photodiode layer

[0049] 607: Well of the first conductivity type

[0050] 608: floating diffusion area

[0051] 608A: First floating diffusion region

[0052] 608B: Second floating diffusion region

[0053] 608C: Third floating diffusion region

[0054] 609: front surface

[0055] 611: Transfer transistor body region

[0056] 612: Active area

[0057] 614: Gate dielectric

[0058] 614T: Transfer Gate Dielectric

[0059] 615: Gate

[0060] 620: Shallow Trench Isolation Structure

[0061] 630: Transfer transistor

[0062] 630A: Transfer transistor

[0063] 630B: Transfer transistor

[0064] 640: Reset transistor

[0065] 650: Source follower transistor

[0066] 660: Select transistor

[0067] 670:Interconnect level dielectric layer

[0068] 680:Metal Interconnect Structure

[0069] 682:Metal through hole structure

[0070] 684: Metal wire structure

[0071] 689: Bonding buffer layer

[0072] 690: Carrier substrate

[0073] 709: back surface

[0074] 711: liner dielectric layer

[0075] 712: Hard mask layer

[0076] 719: Deep Groove

[0077] 720: Deep trench isolation structure

[0078] 721: Dielectric Metal Oxide Liner

[0079] 721L: Dielectric Metal Oxide Liner

[0080] 722: Dielectric isolation layer

[0081] 722L: Dielectric isolation layer

[0082] 732: Anti-reflective coating (ARC) layer

[0083] 734: Optical buffer layer

[0084] 740: Grid structure

[0085] 742: Dielectric grid structure

[0086] 742L: Dielectric grid material layer

[0087] 744:Metal Grid Structure

[0088] 744L: Metal reflective material layer

[0089] 747: Photoresist layer

[0090] 770: Optically transparent layer

[0091] 780: Color filter

[0092] 781: Type 1 color filter

[0093] 782: Second type of color filter

[0094] 790: Optical lens

[0095] 800: Sub-pixel

[0096] 801(800): first sub-pixel

[0097] 801D: First Detector Area

[0098] 801S: First sensing circuit area

[0099] 802(800): second sub-pixel

[0100] 802D: Second Detector Area

[0101] 802S: Second sensing circuit area

[0102] 803(800): third sub-pixel

[0103] 803D: Third Detector Area

[0104] 803S: Third sensing circuit area

[0105] 900: Pixels

[0106] 1000: Array

[0107] 2000: Control Circuit

[0108] 2210: Steps

[0109] 2220: Steps DETAILED DESCRIPTION

[0110] The following disclosure provides many different embodiments or examples to implement the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in each example. This repetition is for simplification and clarity purposes, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0111] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0112] The present disclosure relates to semiconductor devices, and more particularly to photodetectors including at least one multifunctional transfer gate and methods of operating the same.

[0113] In general, the structures and methods of the present disclosure can be used to provide multiple functions for a sub-pixel including a photodiode circuit. The photodetector circuit includes a photodetector and a sensing circuit. The photodetector includes: a pinned photodiode layer of a second conductivity type, the layer forming a pn junction with a substrate semiconductor layer; at least one floating diffusion region, the floating diffusion region being laterally spaced from a periphery of the pinned photodiode layer of the second conductivity type; and at least one transfer gate. At least two different operations can be performed in the photodetector circuit by applying at least two different pulse patterns to the at least one transfer gate. The at least two different pulse patterns differ from each other in at least one of the following: pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and a pulse initiation at a corresponding one of the at least one transfer gate.

[0114] The at least two different operations may provide at least two different functions for the photodetector. One of the at least two different operations may include an image capture operation that operates the self-sensing circuit to generate an electrical output. The electrical output has a magnitude proportional to the amount of charge accumulated in the pinned photodiode layer of the second conductivity type. In some embodiments, the photodetector may continue to perform typical operations as an image sensor. Another of the at least two different operations may include additional operations for enhancing the quality of an image captured by the CMOS image sensor.

[0115] In one embodiment, the additional operation is related to the internal operation of the individual sub-pixels, such as a pinning operation, which accumulates charge carriers of the first conductivity type in a pinning layer of the first conductivity type, and the pinning layer of the first conductivity type forms another pn junction with a pinned photodiode layer of the second conductivity type. In another embodiment, the additional function may be related to an overflow discharge operation, in which the charge in the pinned photodiode layer of the second conductivity type is discharged before performing an image capture operation. In another embodiment, the additional function may be related to the global operation of the CMOS image sensor and is independent of the image generation of any particular sub-pixel. For example, the additional function or additional operation may include a single operation or multiple operations selected from a list, the list including but not limited to phase detection autofocus operation, time-of-flight detection operation, single-photon avalanche diode operation, and near-infrared operation. Various aspects of the embodiments of the present disclosure are described below with respect to the various figures of the present application.

[0116] Reference Figure 1A and Figure 1B , a first configuration of an array 1000 of pixels 900 for an image sensor and a second configuration of an array 1000 of pixels 900 for an image sensor are illustrated in corresponding plan views. The image sensor may be a backside illuminated (BSI) image sensor device. However, it should be understood that embodiments of the present disclosure may be used in front side illuminated (FSI) image sensors.

[0117] To generate an image from an image sensor, each pixel 900 represents a minimum unit area. The area of ​​array 1000 including pixels 900 is referred to herein as a pixel array area. The pixels 900 in the pixel array area may be arranged in rows and columns. For example, the pixel array area may include M rows and N columns, where M and N are from 1 to 2. 16 , such as from 2 8 to 2 14 The rows of pixels 900 may be numbered consecutively using integers ranging from 1 to M, and the columns of pixels 900 may be numbered consecutively using integers ranging from 1 to N. ij It refers to the pixel 900 in the i-th row and the j-th column.

[0118] Each pixel 900 includes at least one photodetector that detects radiation in a given wavelength range. Each pixel 900 may include a plurality of photodetectors that detect radiation in a corresponding wavelength range, which may be different from each of the plurality of photodetectors. In one embodiment, each pixel 900 may include a plurality of sub-pixels, each of which includes a corresponding combination of a photodetector and electronic circuitry that detects radiation incident on the photodetector. For example, a pixel 900 may include a sub-pixel that detects radiation in a red wavelength range (such as a range from 635 nm to 700 nm), a sub-pixel that detects radiation in a green wavelength range (such as a range from 520 nm to 560 nm), and a sub-pixel that detects radiation in a blue wavelength range (such as a range from 450 nm to 490 nm). Such sub-pixels are referred to as red sub-pixels, green sub-pixels, and blue sub-pixels, respectively.

[0119] In general, the pixel 900 generates information about incident radiation per unit detection area. The sub-pixel generates information about the intensity of incident radiation within a specific wavelength range detected within the area of ​​the unit detection area. A monochrome pixel 900 may include only a single sub-pixel. A pixel 900 for detecting a spectral distribution of incident radiation includes a plurality of sub-pixels having at least two different detection wavelength ranges. The photodetectors in the pixel array area may include photodiodes, complementary metal-oxide-semiconductor (CMOS) image sensors, charge coupled device (CCD) sensors, active sensors, passive sensors, other applicable sensors, or combinations thereof.

[0120] Reference Figure 2A and Figure 2B, a first configuration of a photodetector circuit in a first exemplary structure is illustrated according to an embodiment of the present disclosure. The photodetector circuit includes a collection of front-side sensor components 600 in the region of a sub-pixel. The front-side sensor components 600 refer to all components of an image sensor that may be formed on the front surface 609 of the semiconductor substrate 500 or may be formed in the substrate semiconductor layer 601. The photodetector circuit includes a photodetector (including a transfer transistor 630) and a sensing circuit (640, 650, 660), which includes a plurality of reset transistors 640, a plurality of source follower transistors 650, and a plurality of select transistors 660.

[0121] Each sub-pixel may include a respective photodetector circuit including a subset of the front-side sensor components 600 that may be located within the region of the sub-pixel. Various configurations of the photodetectors may be derived from one another by changing the layout of the pinned photodiode layer, which includes a pinned photodiode layer 602 of the second conductivity type, at least two floating diffusion regions 608, and at least two transfer gate stack structures (614T, 605). Various configurations for the sensing circuits (640, 640, 650) may be derived from one another by changing the total number of interconnected sets of reset transistors 640, source-follower transistors 650, and selector transistors 650 and / or by rearranging the layout of the interconnected sets of reset transistors 640, source-follower transistors 650, and selector transistors 650.

[0122] A collection of sub-pixels can be used as a pixel, and the array 1000 of pixels can be as shown. Figure 1A or Figure 1B The front sensor component 600 may be arranged as shown, or arranged in any other suitable array configuration to provide an image sensor. Each sub-pixel may include a unit cell UC, which may be repeated along at least one horizontal direction to provide a front sensor component 600 for a single pixel, and a single pixel may include a single sub-pixel, two sub-pixels, or three or more sub-pixels. In one embodiment, multiple instances of the unit cell UC may be repeated along at least one horizontal direction. For example, the unit cell UC may be repeated as a two-dimensional array of unit cells UC, which are replicated with a first period along a first horizontal direction hd1 and a second period along a second horizontal direction hd2. As described above with reference to Figure 1A and Figure 1B As discussed, the two-dimensional array may be a rectangular array or a hexagonal array. Thus, the second horizontal direction hd2 may or may not be perpendicular to the first horizontal direction hd1.

[0123] Figure 2B is along Figure 2A A vertical cross-sectional view of a first exemplary structure of a hinged vertical plane B-B'. Figure 2B, the semiconductor substrate 500 includes a substrate semiconductor layer 601. Each sub-pixel can be formed on or in the substrate semiconductor layer 601, which has a front surface 609 and a back surface. The substrate semiconductor layer 601 includes a semiconductor material such as silicon, germanium, silicon-germanium alloy, compound semiconductor material, or any other semiconductor material with a band gap that does not exceed the energy of the photons to be detected. The material within the substrate semiconductor layer 601 can be selected based on the energy range of the photons to be detected by the sub-pixels. In one embodiment, the substrate semiconductor layer 601 can include single crystal silicon. A commercially available single crystal semiconductor substrate can be used as the semiconductor substrate 500. The semiconductor substrate 500 provided in this processing step has a sufficiently high thickness to withstand standard complementary metal-oxide-semiconductor (CMOS) processing steps. For example, the thickness of the semiconductor substrate 500 can be in the range from 200 microns to 1 mm, but smaller and larger thicknesses can also be used.

[0124] The top portion of the substrate semiconductor layer 601 may be appropriately doped to have a first conductivity type, which may be a p-type or an n-type. For example, an epitaxial semiconductor deposition process may be performed to form a single crystal epitaxial semiconductor material layer at the upper portion of the substrate semiconductor layer so that the atomic concentration of the dopant of the first conductivity type is in the range of 1.0×10 13 / cm 3 to 1.0×10 16 / cm 3 The thickness of the single crystal epitaxial semiconductor material layer may be in the range of from 1 micron to 10 microns, but lesser and greater thicknesses may also be used.

[0125] The first conductivity type well 607 may be formed by ion implantation around a region where a shallow trench isolation structure 620 is subsequently formed. The atomic concentration of the first conductivity type dopant in the first conductivity type well 607 may be in the range of 1.0×10 15 / cm 3 to 1.0×10 18 / cm 3 The range of , but smaller and larger atomic concentrations may also be used. A shallow trench isolation structure 620 may be formed to provide electrical isolation to and from various components within the sub-pixel.

[0126] At least one mask ion implantation process may be used to implant a dopant of a second conductivity type through the front surface 609 of the semiconductor substrate 500. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. Each doped region having a doping of the second conductivity type is formed by at least one mask ion implantation process. A pinned photodiode layer 602 of the second conductivity type may be formed below the front surface 609 of the semiconductor substrate 500 so that the periphery of the pinned photodiode layer 602 of the second conductivity type overlaps the edge of the transfer gate 605 in a plan view. The lateral extension of the pinned photodiode layer 602 of the second conductivity type may be limited to one side of the transfer gate formed subsequently. Therefore, at least one edge of the pinned photodiode layer 602 of the second conductivity type may be laterally spaced apart from the shallow trench isolation structure 620 by an area in which the transfer gate and the floating diffusion region may be subsequently formed.

[0127] A buried second conductivity type pinned photodiode layer 606 may be formed below the second conductivity type pinned photodiode layer 602 at a depth of a bottom portion of the first conductivity type well 607 by implanting a second conductivity type dopant using a higher implantation energy than during an implantation process for forming the second conductivity type pinned photodiode layer 602. The buried second conductivity type pinned photodiode layer 606 may abut the first conductivity type well 607. In one embodiment, each buried second conductivity type pinned photodiode layer 606 may have a perimeter abutting the first conductivity type well 607.

[0128] In one embodiment, the pn junction between the buried second conductivity type pinned photodiode layer 606 and the first conductivity type well 607 may extend continuously around the entire area of ​​the sub-pixel to form a substantially cylindrical surface without any openings therethrough. The pn junction may extend continuously under the portion of the shallow trench isolation structure 620 that laterally surrounds the sub-pixel. The top portion of the buried second conductivity type pinned photodiode layer 606 may abut the bottom portion of the second conductivity type pinned photodiode layer 602 within each sub-pixel. The area of ​​the second conductivity type pinned photodiode layer 602 may be completely within the area of ​​the underlying buried second conductivity type pinned photodiode layer 606 in each sub-pixel.

[0129] In one embodiment, the depth of the top surface of the buried second conductivity type pinned photodiode layer 606 can be in the range of 400 nm to 1,500 nm, although lesser and greater depths can also be used. In one embodiment, the depth of the bottom surface of the buried second conductivity type pinned photodiode layer 606 can be in the range of 800 nm to 2,500 nm, although lesser and greater depths can also be used.

[0130] The unimplanted portion of the substrate semiconductor layer 601 covering the embedded second conductivity type pinned photodiode layer 606 has a doping of the first conductivity type and may subsequently be used as a body region of a transfer transistor. Therefore, the unimplanted portion of the substrate semiconductor layer 601 covering the embedded second conductivity type pinned photodiode layer 606 is referred to herein as a transfer transistor body region 611. In one embodiment, the embedded second conductivity type pinned photodiode layer 606 may have the same lateral extension as a subsequently formed transfer transistor 630 and may overlap a portion of a shallow trench isolation structure 620 surrounding the combination of the second conductivity type pinned photodiode layer 602 and the transfer transistor body region 611.

[0131] The gate stack structures (614, 605, 615) may be formed above the front surface 609 of the semiconductor substrate 500 by depositing and patterning a layer stack including a gate dielectric layer and a gate layer. Each patterned portion of the layer stack constitutes a gate stack structure (614, 605, 615), which may be a transfer gate stack structure (614T, 605) and a control gate stack structure (614, 615). Each transfer gate stack structure (614T, 605) includes a gate dielectric and a gate, the gate dielectric is referred to herein as a transfer gate dielectric 614T, and the gate is referred to herein as a transfer gate 605. Each transfer gate stack structure (614T, 605) is located between the pinned photodiode layer 602 of the second conductivity type and a corresponding one of the floating diffusion regions 608. Each control gate stack structure (614, 615) includes a gate dielectric 614 and a gate 615.

[0132] Reference Figure 2C , illustrating a second configuration of the first exemplary structure, which can be automatically configured by changing the layout of the first floating diffusion region 608A, the second floating diffusion region 608B, the first transfer gate 605A and the second transfer gate 605B. Figure 2A and Figure 2B Specifically, the first floating diffusion region 608A and the second floating diffusion region 608B may be Figure 2C The second configuration is formed adjacent to each other, rather than in Figure 2A and Figure 2B The first configuration of the first exemplary structure adopts a diagonal arrangement.

[0133] Reference Figure 2D , illustrating a third configuration of the first exemplary structure, which can be automatically configured by changing the layout of the first floating diffusion region 608A, the second floating diffusion region 608B, the first transfer gate 605A and the second transfer gate 605B. Figure 2Aand Figure 2B Specifically, the first floating diffusion region 608A and the second floating diffusion region 608B may be Figure 2D The third configuration is formed with a shape or arc, rather than in Figure 2A and Figure 2B The first configuration of the first exemplary structure adopts a diagonal arrangement.

[0134] Reference Figure 2E , illustrating a fourth configuration of the first exemplary structure, which can be self-contained by forming three or more floating diffusion regions and three or more transfer gates. Figure 2A and Figure 2B The first configuration of the first exemplary structure is obtained. For example, the floating diffusion region may include a first floating diffusion region 608A, a second floating diffusion region 608B, and a third floating diffusion region 608C. The transfer gate may include a first transfer gate 605A, a second transfer gate 605B, and a third transfer gate 605C.

[0135] FIG. 2A to FIG. 2E Each floating diffusion region (608A, 608B, 608C) in each configuration of the first exemplary structure shown can be connected to a corresponding combination of a reset transistor 640, a source follower transistor 650, and a select transistor 660. In each configuration, the transfer gate dielectric 614T has the same horizontal cross-sectional shape as the transfer gate 605.

[0136] According to the present disclosure, if FIG. 2A to FIG. 2E As shown, multiple transfer gate stack structures (614T, 605) can be formed in each photodetector circuit. Each transfer gate stack structure (614T, 605) is a gate stack structure of a transfer transistor 630 and includes a stack of a gate dielectric 614 and a transfer gate 605. The transfer gate 605 of the photodetector circuit may include a first transfer gate 605A and a second transfer gate 605B. In embodiments where three or more transfer gates 605 are provided (e.g., as shown in FIG. 1 ), the transfer gates 605 may be provided as a plurality of transfer gates. Figure 2E ), the transfer gate 605 may include a third transfer gate 605C. In embodiments where four or more transfer gates 605 are provided, at least one additional transfer gate (not explicitly shown) may be provided.

[0137] Generally speaking FIG. 2A to FIG. 2EAnd according to embodiments of the present disclosure, each of the transfer gates 605 may be individually controlled by a corresponding control signal provided by control circuitry external to the array of pixels 900. In other words, the transfer gates 605 may be individually operated to perform multiple operations or functions, which may or may not be related to each other or to each other. Further, the operations performed by multiple transfer gates 605 may be performed sequentially or simultaneously.

[0138] Each of the control gate stack structures (614, 615) includes a corresponding layer stack of gate dielectric 614 and gate 615 for other transistors in the sensing circuit, which may include a reset transistor 640, a source follower transistor 650, a select transistor 660, and other suitable transistors that can be used to amplify the signal generated by the photodetector of the sub-pixel.

[0139] Each active region (608, 612) may be formed with a doping of the second conductivity type. According to an embodiment of the present disclosure, each active region (608, 612) may include a plurality of floating diffusion regions 608, which may be used as drain regions of the transfer transistor 630. For example, the floating diffusion region 608 may include a first floating diffusion region 608A and a second floating diffusion region 608B. If three or more floating diffusion regions 608 are provided, the floating diffusion region 608 may include a third floating diffusion region 608C (see, for example, Figure 2E If four or more floating diffusion regions 608 are provided, the floating diffusion region 608 may include at least one additional floating diffusion region (not explicitly shown).

[0140] The current between the second conductivity type pinned photodiode layer 602 and each of the plurality of floating diffusion regions 608 can be controlled by a corresponding one of the plurality of transfer gates 605. Since the transfer gates 605 can be individually controlled by different signals, the current between the second conductivity type pinned photodiode layer 602 and each of the plurality of floating diffusion regions 608 can be individually controlled so that each of the floating diffusion regions 608 can perform different functions and can be at different voltages. The plurality of floating diffusion regions 608 are not in contact with each other or with each other, and can be electrically isolated from each other under appropriate bias conditions for the transfer gates 605.

[0141] In the illustrative example, the first transfer gate 605A can control the current between the pinned photodiode layer 602 of the second conductivity type and the first floating diffusion region 608A, the second transfer gate 605B can control the current between the pinned photodiode layer 602 of the second conductivity type and the second floating diffusion region 608B, and the third transfer gate 605C can control the current between the pinned photodiode layer 602 of the second conductivity type and the third floating diffusion region 608C.

[0142] The pinned photodiode layer 602 of the second conductivity type accumulates charge (such as electrons in the embodiment where the second conductivity type is n-type) during sensing (i.e., when the sub-pixel actively detects photons incident thereon, for example, for the purpose of capturing a frame or taking a photo) and serves as the source region of the transfer transistor 630. The active region 612 includes the source and drain regions of each transistor (640, 650, 660) in the sensing circuit. The floating diffusion region 608 can be vertically separated from the embedded pinned photodiode layer 606 of the second conductivity type by the transfer transistor body region 611.

[0143] The floating diffusion region 608 and the active region 612 may be formed by ion implanting a second conductivity type dopant using a masked ion implantation process. The combination of the corresponding patterned photoresist layer and the gate stack structure (614, 605, 615) may be used as an ion implantation barrier structure (i.e., a mask structure) during the ion implantation process. The depth of the bottom surface of the floating diffusion region 608 may be in the range of 100 nm to 400 nm, such as from 150 nm to 250 nm, but smaller and larger depths may also be used. The depth of the bottom surface of the active region 612 may be in the range of 100 nm to 600 nm, such as from 150 nm to 400 nm, but smaller and larger depths may also be used.

[0144] The pinning layer 603 of the first conductivity type may be formed directly on top of the pinning photodiode layer 602 of the second conductivity type by ion implantation of a dopant of the first conductivity type. The pinning layer 603 of the first conductivity type suppresses depletion of the interface between the pinning photodiode layer 602 of the second conductivity type and the pinning layer 603 of the first conductivity type, and electrically stabilizes the pinning photodiode layer 602 of the second conductivity type. The pinning layer 603 of the first conductivity type is omitted in all top views of the various exemplary structures of the present disclosure in order to clearly illustrate the lateral extension of the pinning photodiode layer 602 of the second conductivity type located below the pinning layer 603 of the first conductivity type. The depth of the pn junction between the pinning layer 603 of the first conductivity type and the pinning photodiode layer 602 of the second conductivity type may be in the range of 5 nm to 100 nm, but smaller and larger depths may also be used. In addition to the pn junction between the pinning photodiode layer 602 of the second conductivity type and the substrate semiconductor layer 601, the pinning layer 603 of the first conductivity type forms an additional pn junction with the pinning photodiode layer 602 of the second conductivity type.

[0145] An interconnect-level dielectric layer 670 may be formed over the front surface 609 of the semiconductor substrate 500, and a metal interconnect structure 680 connecting various nodes of the transistors (630, 640, 650, 660) may be formed within each sub-pixel. The interconnect-level dielectric layer 670 may include a respective dielectric material, such as undoped silica glass, doped silica glass, organosilicate glass, porous dielectric material, or a combination thereof. Dielectric liners including various dielectric materials, such as silicon nitride, silicon oxynitride, silicon oxycarbide, and / or dielectric metal oxides, may be used in the interconnect-level dielectric layer 670 as appropriate. The metal interconnect structure 680 may include various metal via structures 682 and various metal line structures 684. For example, each of the floating diffusion regions 608 may be connected to the gate 615 of the respective source-follower transistor 650 through a subset of the metal interconnect structures 680. The photodetector may include a transfer transistor 630 and may be connected to a sensing circuit including additional transistors ( 640 , 650 , 660 ).

[0146] The sensing circuit (640, 650, 660) includes at least two interconnected sets of reset transistors 640, source follower transistors 650, and select transistors 660. In general, the control signals for the gates 615 of the transistors in different interconnected sets of transistors (640, 650, 660) can be independent, but circuit modifications are possible where the gates 615 within different interconnected sets of transistors (640, 650, 660) share the same control signal or the complement of the signal (i.e., one is the inverse of the other).

[0147] The plurality of floating diffusion regions 608 may be formed by pinning the photodiode layer 602 (eg, Figure 2A , Figure 2C and Figure 2D as shown) or by Figure 2E The shallow trench isolation structures 620 are shown to be laterally spaced apart from each other. The layout of the interconnected set of transfer gate stack structures (614T, 605), floating diffusion regions 608, and transistors (640, 650, 660) of the sensing circuit can have rotational symmetry (e.g. Figure 2A and Figure 2D ), or may have mirror symmetry about a vertical plane (as shown Figure 2C or, Figure 2E As shown, there may not be any rotational symmetry or mirror symmetry in the layout of the unit cells UC.

[0148] In one embodiment, a plurality of floating diffusion regions 608 (eg, Figure 2A , Figure 2C and Figure 2D In one embodiment, as shown in Figure 2D As shown, the plurality of floating diffusion regions 608 can partially surround a region of the second conductivity type pinned photodiode layer 602 with a gap therein.

[0149] In general, the sensing circuit (640, 650, 660) of each sub-pixel may be provided within the area of ​​the unit cell UC. In one embodiment, each interconnected set of transistors (640, 650, 660) of the sensing circuit may be arranged side by side within the area of ​​a corresponding strip located near an edge of the unit cell UC and extending along the entire length of a side of the unit cell UC or along at least 30% of the length of a side of the unit cell UC. In another embodiment, each interconnected set of transistors (640, 650, 660) of the sensing circuit may be arranged around a corresponding floating diffusion region 608 of the transfer transistor 630 within the area of ​​a square located near a corner of the unit cell UC.

[0150] The first exemplary structure includes at least one instance of a sub-pixel. The first exemplary structure may include an image sensor including a pixel array located on a semiconductor substrate 500. The first exemplary structure may include a plurality of sub-pixels located within corresponding pixels in the pixel array. In one embodiment, each pixel within the pixel array includes a corresponding instance of a sub-pixel.

[0151] Reference Figure 3A , illustrates a first configuration of a second exemplary structure, which may be derived from the first exemplary structure by providing a single transfer gate stack structure (614T, 605) instead of multiple transfer gate stack structures (614T, 605) and by providing a single floating diffusion region 608 instead of multiple floating diffusion regions 608. Thus, a single interconnected set of transistors (640, 650, 660) may be used for the sensing circuit of the second exemplary structure.

[0152] The first configuration of the second exemplary structure may include a pinned photodiode layer 602 of the second conductivity type, which forms at least one pn junction with the substrate semiconductor layer 601. The first configuration of the second exemplary structure may include a floating diffusion region 608, which is laterally spaced apart from the pinned photodiode layer 602 of the second conductivity type. A transfer gate stack structure (614T, 605) including a transfer gate dielectric 614T and a transfer gate 605 may be located between the at least one pinned photodiode layer 602 of the second conductivity type and the floating diffusion region 608. Although the transfer gate dielectric 614T is not located in the substrate semiconductor layer 601, the transfer gate stack structure (614T, 605) may be located between the at least one pinned photodiode layer 602 of the second conductivity type and the floating diffusion region 608. Figure 3A605. Although not explicitly shown in the figure, it should be understood that in each configuration, the transfer gate dielectric 614T has the same horizontal cross-sectional shape as the transfer gate 605. The transfer gate stack structure (614T, 605) is located between the floating diffusion region 608 and each of the at least one second conductivity type pinned photodiode layer 602. In one embodiment, the gate length of the transfer gate stack structure (614T, 605), that is, the width of the transfer gate stack structure (614T, 605) along the horizontal direction connecting each second conductivity type pinned photodiode layer 602 and the floating diffusion region 608, can be always consistent.

[0153] Reference Figure 3B and Figure 3C The second configuration of the second exemplary structure can be self-contained by forming the transfer gate 605 in a ring configuration so that the transfer gate 605 surrounds the region of the pinned photodiode layer 602 of the second conductivity type. Figure 3A A first configuration of a first exemplary structure results.

[0154] Reference Figure 4 , additional interconnect-level dielectric layers 670 and additional metal interconnect structures 680 may be formed on the front side of the semiconductor substrate 500. The front side of the components of the semiconductor substrate 500, the interconnect-level dielectric layers 670, and the structures formed therein may be bonded to a carrier substrate 690. The carrier substrate 690 is temporarily attached to the components of the semiconductor substrate 500 and the interconnect-level dielectric layers 670 to provide for subsequent thinning of the semiconductor substrate 500, and for subsequent processing of the components of the thinned semiconductor substrate 500 and the interconnect-level dielectric layers 670. The carrier substrate 690 may include a semiconductor material, an insulating material, or a metal material, and may have a thickness ranging from 300 microns to 1 mm, although lesser and greater thicknesses may also be used.

[0155] Any suitable bonding method may be used to bond the carrier substrate 690 to the front side of the interconnect-level dielectric layer 670. Exemplary bonding methods that may be used to bond the carrier substrate 690 to the interconnect-level dielectric layer 670 include, but are not limited to, oxide-to-oxide bonding, oxide-to-semiconductor bonding, fusion bonding, hybrid bonding, anodic bonding, direct bonding, other suitable bonding processes, and / or combinations thereof. Optionally, an adhesion buffer layer 689 including an intermediate bonding material (e.g., silicon oxide, silicon nitride, or a semiconductor material) may be used to provide adhesion between the interconnect-level dielectric layer 670 and the carrier substrate 690.

[0156] Reference Figure 5, the back side of the semiconductor substrate 500 may be thinned, for example, by grinding, polishing, an isotropic etching process, and / or an anisotropic etching process. During the thinning process, the carrier substrate 690 may provide mechanical support to the semiconductor substrate 500. In one embodiment, the semiconductor substrate 500 may be thinned to a thickness in a range from 1 micron to 12 microns, such as from 1.5 microns to 8 microns, although lesser and greater thicknesses may also be used. The thinned semiconductor substrate 500 after the thinning process is referred to herein as a thinned semiconductor substrate 510, or as semiconductor substrate 510. The thickness of the thinned semiconductor substrate 510 may be determined by the maximum depth of the deep trenches subsequently formed on the back side of the thinned semiconductor substrate 510. In one embodiment, the thickness of the thinned semiconductor substrate 510 may be selected so that the deep trenches subsequently formed on the back side of the semiconductor substrate 510 reach the proximal surface of the shallow trench isolation structure 620. The backside surface 709 of the thinned semiconductor substrate 510 may be polished to provide a flat horizontal surface parallel to the front surface 609 of the thinned semiconductor substrate 510. The exemplary structure may then be turned upside down for further processing.

[0157] Reference Figure 6 , an optional pad dielectric layer 711 and a hard mask layer 712 may be formed over the backside surface 709 of the semiconductor substrate 510. The optional pad dielectric layer 711, if present, may include a silicon oxide layer and may have a thickness in a range from 5 nm to 50 nm, although lesser and greater thicknesses may also be used. The hard mask layer 712 includes an etch mask material that may subsequently be selectively removed from the pad dielectric layer 711 and / or from the semiconductor substrate 510. For example, the hard mask layer 712 may include silicon nitride, borosilicate glass, or a metal material. The hard mask layer 712 may have a thickness in a range from 50 nm to 800 nm, although lesser and greater thicknesses may also be used.

[0158] A photoresist layer (not shown) may be applied over the hard mask layer 712 and may be lithographically patterned to form openings that substantially replicate the pattern of the shallow trench isolation structures 620 located below. A first etching process may be performed to transfer the pattern in the photoresist layer through the hard mask layer 712 and the optional liner dielectric layer 711. Unmasked portions of the semiconductor substrate 510 may be etched by performing a second anisotropic etching process that transfers the pattern of the openings in the photoresist layer and the hard mask layer 712 through the semiconductor substrate 510. The depth of the deep trench 719 may be in a range from 1 micron to 10 microns, such as from 1.5 microns to 8 microns. The photoresist layer may be completely depleted during the second anisotropic etching process. The deep trench 719 may be formed through the semiconductor substrate 510.

[0159] The deep trenches 719 may define areas for the sub-pixels 800. Each sub-pixel 800 may be located within a corresponding sub-pixel area, which is located within an area of ​​a pixel, i.e., a pixel area. For example, the area of ​​a pixel may include an area for a first sub-pixel 801 (800), an area for a second sub-pixel 802 (800), and an area for a third sub-pixel 803 (800). In an illustrative example, the first sub-pixel 801 may be formed in an area including a photodetector for detecting green light, the second sub-pixel 802 may be formed in an area including a photodetector for detecting red light, and the third sub-pixel 803 may be formed in an area including a photodetector for detecting blue light. Each sub-pixel 800 may include a volume containing a patterned columnar portion of the semiconductor substrate 510, which volume is laterally surrounded by a connected set of deep trenches 719. The pixel area of ​​a pixel includes all sub-pixel areas for the set of sub-pixels 800 contained within the pixel.

[0160] Reference Figure 7 , the hard mask layer 712 may be selectively removed from the semiconductor substrate 510, the liner dielectric layer 711, and the shallow trench isolation structure 620. In the illustrative example, if the hard mask layer 712 includes silicon nitride, a wet etching process using hot phosphoric acid may be performed to remove the hard mask layer 712. Subsequently, the liner dielectric layer 711 may be selectively removed from the semiconductor substrate 510.

[0161] Reference Figure 8 , the dielectric metal oxide liner 721L may be conformally deposited over the physically exposed surface of the semiconductor substrate 510. In embodiments where the shallow trench isolation structure 620 is physically exposed in the deep trench 719, the dielectric metal oxide liner 721L may be formed on the sidewalls of the deep trench 719, on the backside surface 709 of the semiconductor substrate 510, and on the surface of the shallow trench isolation structure 620. The dielectric metal oxide liner 721L includes a dielectric metal oxide material having a dielectric constant greater than 7.9 (i.e., a "high dielectric constant" dielectric material). Exemplary dielectric metal oxide materials that may be used for the dielectric metal oxide liner 721L include hafnium oxide, aluminum oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, titanium oxide, lanthanum oxide, barium oxide, or combinations thereof. Other suitable metal materials are within the scope of the present disclosure. The dielectric metal oxide liner 721L may be deposited using a chemical vapor deposition process or atomic layer deposition (ALD). The thickness of the dielectric metal oxide liner 721L may be in a range from 2 nm to 6 nm, although lesser and greater thicknesses may also be used.

[0162] The dielectric metal oxide liner 721L may be formed to provide negative charge trapping. For example, the dielectric metal oxide liner 721L may be deposited using a non-stoichiometric oxygen-rich composition, or may be surface treated, such as using a plasma, to have a non-stoichiometric oxygen-rich surface compression. In such embodiments, the dielectric metal oxide liner 721L may include an oxygen-rich dielectric metal oxide material having negatively charged interstitial oxygen atoms and / or dangling or broken metal oxide bonds, thereby providing an accumulation of negative charge within the dielectric metal oxide liner 721L. In an illustrative example, the surface density of the accumulated negative charge within the dielectric metal oxide liner 721 may be in the range of 5.0×10 9 Electron / cm 2 to 1.0×10 14 Electron / cm 2 In the range of 1.0×10 10 Electron / cm 2 Up to 2.0×10 13 Electron / cm 2 The dielectric metal oxide material used in the dielectric metal oxide liner 721L can accumulate more negative charges than other dielectric materials such as silicon nitride or silicon oxide. The negative charges in the dielectric metal oxide liner 721L increase hole accumulation within the interface portion of the first conductivity type well 607 and the substrate semiconductor layer 601 of the semiconductor substrate 510. A depletion region can be formed within the first conductivity type well 607 and the portion of the substrate semiconductor layer 601 of the semiconductor substrate 510 near the dielectric metal oxide liner 721L. The depletion region reduces dark current and / or white pixels of the image sensor.

[0163] The dielectric isolation layer 722L may be formed by conformally depositing a dielectric material in the remaining volume of the deep trench 719. The dielectric isolation layer 722L includes a dielectric material such as undoped silica glass, doped silica glass (such as borosilicate glass), or a combination thereof. The combination of the dielectric metal oxide liner 721L and the dielectric isolation layer 722L may fill the deep trench 719 (with or without a seam and / or encapsulated cavity).

[0164] Reference Fig. 9, the dielectric isolation layer 722L and the horizontal portion of the dielectric metal oxide liner 721L may be removed from above the backside surface 709 of the semiconductor substrate 510 by a planarization process. The dielectric isolation layer 722L and the horizontal portion of the dielectric metal oxide liner 721L may be removed using a recess etch and / or chemical mechanical planarization process. In one embodiment, the resulting dielectric metal oxide liner 721 may be used as an etch stop layer during the recess etch process to remove the horizontal portion of the resulting dielectric isolation layer 722, or as a stop layer during the chemical mechanical planarization process to remove the horizontal portion of the dielectric isolation layer 722. The horizontal portion of the dielectric metal oxide liner 721 covering the backside surface 709 of the semiconductor substrate 510 may then be removed by performing an isotropic etching process, such as a wet etching process, which etches the material of the dielectric metal oxide liner 721 selectively to the semiconductor material of the semiconductor substrate 510. The dielectric metal oxide liner 721 and the remaining vertical extension of the dielectric isolation layer 722 fill the deep trench 719 and are referred to herein as deep trench isolation structure 720 .

[0165] Reference Fig.10 , an optional anti-reflective coating (ARC) layer 732 , an optical buffer layer 734 , a dielectric grid material layer 742L, and a metal reflective material layer 744L may be sequentially deposited over the backside surface 709 of the semiconductor substrate 510 .

[0166] The optional ARC layer 732 includes an anti-reflective coating that reduces reflections between the semiconductor material of the semiconductor substrate 510 and the cover material layer (i.e., the optical buffer layer 734). The optional ARC layer 732, if present, may have a refractive index between the refractive index of the semiconductor material of the semiconductor substrate 510 and the refractive index of the optical buffer layer 734. The optional ARC layer 732 may include a single material layer or a layer stack of multiple layers with gradually changing refractive indices. The optional ARC layer 732 includes an optically transparent material and may include a semiconductor material, an insulating material, a conductive material, and / or a polymeric material. The ARC layer 732 may have a thickness ranging from 50 nm to 300 nm, although lesser and greater thicknesses may also be used.

[0167] The optical buffer layer 734 includes a semiconductor material (such as silicon, germanium, a silicon-germanium alloy, or a III-V compound semiconductor material) or a dielectric material (such as silicon oxide, silicon oxynitride, silicon nitride, or a dielectric metal oxide (e.g., aluminum oxide). The optical buffer layer 734 includes a material that facilitates the formation of trenches with a high aspect ratio during a subsequent anisotropic etching process. The optical buffer layer 734 can be formed as an unpatterned (blanket) material layer having two horizontal flat surfaces, which are parallel to the backside surface 709 of the semiconductor substrate 510. The distal surface of the optical buffer layer 734 is one of the two horizontal flat surfaces of the optical buffer layer 734, which is farther from the semiconductor substrate 510 (i.e., the top surface of the optical buffer layer 734).

[0168] The dielectric grid material layer 742L may include a dielectric material such as silicon oxide, a porous dielectric material, a polyimide, or another dielectric material. The thickness of the dielectric grid material layer may be in the range of from 50 nm to 500 nm, although lesser and greater thicknesses may also be used. The metal reflective material layer 744L may include a metal material that may provide high reflectivity. For example, the metal reflective material layer 744L may include silver, aluminum, copper, gold, or any other highly reflective metal material. The thickness of the metal reflective material layer 744L may be in the range of from 50 nm to 500 nm, although lesser and greater thicknesses may also be used.

[0169] The photoresist layer 747 may be coated over the metal reflective material layer 744L and may be lithographically patterned to form an opening in the region of the pinned photodiode layer 602 of the second conductivity type, that is, in the region of the photodetector including the corresponding pn junction between the pinned photodiode layer 602 of the second conductivity type and the well 607 of the first conductivity type. The region of the transistors of the sensing circuit (such as the reset transistor 640, the source follower transistor 650, and the select transistor 660) may or may not be covered by the photoresist layer 747.

[0170] Reference Fig.11A and Fig. 11B , portions of the dielectric grid material layer 742L and the metal reflective material layer 744L that are not masked by the patterned portions of the photoresist layer 747 can be etched to form openings therethrough. The remaining portion of the dielectric grid material layer 742L forms a dielectric grid structure 742, and the remaining portion of the metal reflective material layer 744L forms a metal grid structure 744. The stack of the dielectric grid structure 742 and the metal grid structure 744 constitutes a grid structure 740, which is also referred to as a composite grid structure.

[0171] The grid structure 740 may cover the perimeter of the second conductivity type pinned photodiode layer 602 and define a light collection area for each photodetector located within a corresponding sub-pixel 800. The pixel 900 may include a set of sub-pixels for detecting light of different wavelengths. Each pixel 900 may be located in a corresponding pixel area, which includes a set of sub-pixels 800. For example, the pixel 900 may include at least one instance of a first sub-pixel 801, at least one instance of a second sub-pixel 802, and at least one instance of a third sub-pixel 803. In the illustrated example, the pixel may include a first sub-pixel 801 located in a first sub-pixel area (such as a green sub-pixel), two second sub-pixels 802 located in two second sub-pixel areas (such as two red sub-pixels), and a third sub-pixel 803 located in a third sub-pixel area (such as a blue sub-pixel). In general, the pixel 900 may include various combinations of at least two types of sub-pixels 800 for detecting light of different wavelength ranges. Alternatively, the image sensor may be a monochrome image sensor including a single type of sub-pixel 800. In this embodiment, each pixel 900 may include only a single sub-pixel 800 .

[0172] In general, the grid structure 740 includes at least a metal grid structure 744 having reflective sidewalls. The grid structure 740 may include a composite grid structure including a vertical stack of the metal grid structure 744 having reflective sidewalls and the dielectric grid structure 742. The grid structure 740 may be formed over a distal surface of the optical buffer layer 734. The grid structure 740 includes openings that overlie a respective one of the photodetectors including the transfer transistor 630. The portion of the distal surface of the optical buffer layer 734 that is in contact with the bottom surface of the grid structure is a flat distal surface portion of the distal surface of the optical buffer layer 734. During an anisotropic etching process for patterning the grid structure, the portion of the distal surface of the optical buffer layer 734 that is not in contact with the grid structure 740 may be recessed vertically and parallel to a horizontal plane including the bottom surface of the grid structure.

[0173] The grid structure 740 can divide each sub-pixel 800 into a detector region and a sensing circuit region. For example, the first sub-pixel 801 may include a first detector region 801D and a first sensing circuit region 801S, the first detector region 801D covers the second conductivity type pinned photodiode layer 602 of the first sub-pixel 801, and the first sensing circuit region 801S covers the sensing circuit (640, 650, 660) of the first sub-pixel 801. The second sub-pixel 802 may include a second detector region 802D and a second sensing circuit region 802S, the second detector region 802D covers the second conductivity type pinned photodiode layer 602 of the second sub-pixel 802, and the second sensing circuit region 802S covers the sensing circuit (640, 650, 660) of the second sub-pixel 802. The third sub-pixel 803 may include a third detector region 803D covering the second conductivity type pinned photodiode layer 602 of the third sub-pixel 803 and a third sensing circuit region 803S covering the sensing circuit (640, 650, 660) of the third sub-pixel 803. In general, the set of all sub-pixels 800 within a pixel 900 may be arranged in any pattern that facilitates periodic repetition of pixels 900 within the array 1000 of pixels 900.

[0174] Reference Fig.12 , an optically transparent layer 770 having a flat top surface may be formed over the grid structure 740. The optically transparent layer 770 may be formed by depositing a self-planarizing dielectric material such as flowable oxide (FOX). Alternatively, a transparent dielectric material may be deposited and planarized (e.g., by chemical mechanical planarization) to provide the optically transparent layer 770.

[0175] The optically transparent layer 770 vertically extends through the opening in the grid structure 740 and has a second refractive index different from the first refractive index. The optically transparent layer 770 is formed on the optical buffer layer 734.

[0176] Various color filter materials may be coated over the optically transparent layer 770 and may be patterned to form respective color filters 780. The color filters 780 may include a first type color filter 781 formed in the region of the first sub-pixel 801, a second type color filter 782 formed in the region of the second sub-pixel 802, and a third type color filter 783 formed in the region of the third sub-pixel 803. The composition of each color filter material may be selected so that light within a target wavelength range passes through the color filter material, while light outside the target wavelength range is absorbed by the color filter material.

[0177] Optical lens 790 may be formed over color filter 780 by coating an optically transparent material over color filter 780 and by patterning the optically transparent material into material portions having convex surfaces centered about a respective one of the underlying openings within grid structure 740 .

[0178] Reference Fig.13 , the carrier substrate 690 and the adhesion buffer layer 689 (if present) may be separated from the interconnect-level dielectric layer 670. The semiconductor substrate 510 and the device structures thereon may be separated into discrete image sensors before or after the carrier substrate 690 is separated from the semiconductor substrate 510.

[0179] In general, an array 1000 of pixels may be formed on a semiconductor substrate 510. Each pixel within the array 1000 of pixels includes at least one sub-pixel, and each sub-pixel includes a corresponding photodetector (including a transfer transistor 630) and corresponding sensing circuits (640, 650, 660) located on a front surface 609 of the semiconductor substrate 510.

[0180] Reference Fig.14 , a circuit diagram for a first configuration of a first photodetector circuit is shown according to an embodiment of the present disclosure. The first configuration of the first photodetector circuit includes a transfer transistor 630 and two interconnected sets of transistors (640, 650, 660). FIG. 2A to FIG. 2D As shown, a first configuration of a first photodetector circuit may be implemented using a configuration of a first exemplary structure. The photodetector may include a transfer transistor 630 (630A, 630B). The transfer transistor 630 may include a pn junction between a combination of a pinned photodiode layer 602 of the second conductivity type and a buried pinned photodiode layer 606 of the second conductivity type and a substrate semiconductor layer 601 doped with the first conductivity type. A pinned layer 603 of the first conductivity type may be provided on the top side of the pinned photodiode layer 602 of the second conductivity type to provide charge pinning and thereby reduce dark current and white pixel effect. The set of the substrate semiconductor layer 601, the buried pinned photodiode layer 606 of the second conductivity type, the pinned photodiode layer 602 of the second conductivity type, and the pinned layer 603 of the first conductivity type serves as a pinned photodiode PPD. The pinned photodiode layer 602 of the second conductivity type serves as a source region of the transfer transistor 630.

[0181] A first floating diffusion region 608A (labeled as “FD1”) and a second floating diffusion region 608B (labeled as “FD2”) may be provided. The first floating diffusion region 608A may be used as a first drain region of a transfer transistor 630A, and the second floating diffusion region 608B may be used as a second drain region of the transfer transistor 630B. The first transfer gate 605A (labeled as “TG1”) controls the transfer of charges accumulated in the pinned photodiode layer 602 of the second conductivity type to the floating diffusion region 608 through a first semiconductor channel located below the first transfer gate 605A. The second transfer gate 605B (labeled as “TG2”) controls the transfer of charges accumulated in the pinned photodiode layer 602 of the second conductivity type to the floating diffusion region 608 through a second semiconductor channel located below the second transfer gate 605B. The transfer transistor 630 (630A or 630B) may be used as a photodetector.

[0182] The sensing circuit may include two interconnect components of field effect transistors (640, 650, 660). Each interconnect component of the field effect transistors (640, 650, 660) is connected to a corresponding one of the first floating diffusion region and the second floating diffusion region (608A, 608B). The first interconnect component of the field effect transistors (640, 650, 660) includes a first reset transistor RST1, a first source follower transistor SF1, and a first selection transistor SEL1. The second interconnect component of the field effect transistors (640, 650, 660) includes a second reset transistor RST2, a second source follower transistor SF2, and a second selection transistor SEL2. Each reset transistor 640 (i.e., RST1 and RST2) is used to discharge the charge in the floating diffusion region 608 immediately before sensing, so that the charge accumulated in the corresponding floating diffusion region (608A or 608B) during sensing is linearly proportional to the charge accumulated in the pinned photodiode layer 602 of the second conductivity type. The gate of each source follower transistor 650 (i.e., SF1 and ST2) is electrically connected to the corresponding floating diffusion region (608A or 608B) via a set of metal interconnect structures. Therefore, the voltage at the gate of each source follower transistor 650 is proportional to the charge in the corresponding floating diffusion region (608A or 608B). Each select transistor 660 (i.e., SEL1 and SEL2) can be turned on during a read operation to output a voltage (modulated by the voltage at the gate of the corresponding source follower transistor 650) to a column output bus (labeled as "V_out") at a common node of the corresponding source follower transistor and the select transistor 660. In one embodiment, the output node of the first select transistor SEL1 and the output node of the second select transistor SEL2 can be connected, and the gate voltage applied to the gates of the first select transistor SEL1 and the second select transistor SEL2 can be used to output a single output voltage from only one of the two select transistors (SEL1, SEL2). By providing additional interconnect components of field effect transistors (640, 650, 660) within the sensing circuit, Figure 2E The configuration of the first exemplary structure illustrated in results in a similar circuit diagram.

[0183] Reference Fig.15, illustrates a second configuration of the first photodetector circuit according to an embodiment of the present disclosure. The second configuration of the first photodetector circuit can be derived from the first photodetector circuit by connecting the output voltage from the first selection transistor SEL1 to the first column output bus (labeled as "V_out1") and by connecting the output voltage from the second selection transistor SEL2 to the second column output bus (labeled as "V_out2"). In this embodiment, the gate voltages applied to the gates of the first selection transistor SEL1 and the second selection transistor SEL2 can be independent of each other. The output voltage from the first selection transistor SEL1 and the output voltage from the second selection transistor SEL2 can be provided to the first column output bus and the second column output bus at the same time. The configuration of the first photodetector circuit can be obtained by connecting the output voltage from the first selection transistor SEL1 to the first column output bus (labeled as "V_out1") and by connecting the output voltage from the second selection transistor SEL2 to the second column output bus (labeled as "V_out2"). In this embodiment, the gate voltages applied to the gates of the first selection transistor SEL1 and the second selection transistor SEL2 can be independent of each other. The output voltage from the first selection transistor SEL1 and the output voltage from the second selection transistor SEL2 can be provided to the first column output bus and the second column output bus at the same time. FIG. 2A to FIG. 2D The configuration of the first exemplary structure shown implements the second configuration of the first photodetector circuit.

[0184] Reference Fig.16 , a circuit diagram for a second photodetector circuit is shown according to an embodiment of the present disclosure. The second photodetector circuit includes a transfer transistor 630 and an interconnected set of transistors (640, 650, 660). FIG. 3A to FIG. 3C The configuration of the second exemplary structure shown implements a second photodetector circuit. The transfer transistor 630 includes a pn junction between a combination of a pinned photodiode layer 602 of the second conductivity type and a buried pinned photodiode layer 606 of the second conductivity type and a substrate semiconductor layer 601 doped with a first conductivity type. A pinned layer 603 of the first conductivity type is provided on the top side of the pinned photodiode layer 602 of the second conductivity type to provide charge pinning and thereby reduce dark current and white pixel effect. The set of the substrate semiconductor layer 601, the buried pinned photodiode layer 606 of the second conductivity type, the pinned photodiode layer 602 of the second conductivity type, and the pinned layer 603 of the first conductivity type serves as a pinned photodiode PPD. The pinned photodiode layer 60 of the second conductivity type serves as a source region of the transfer transistor 630, and the floating diffusion region 608 labeled "FD" serves as a drain region of the transfer transistor 630. The transfer gate 605 labeled "TG" controls the transfer of charges accumulated in the pinned photodiode layer 602 of the second conductivity type to the floating diffusion region 608. Transfer transistor 630 ( 630A or 630B) may be used as a photodetector.

[0185] The sensing circuit (640, 650, 660) may include a reset transistor 640 (labeled "RST") to discharge the charge in the floating diffusion region 608 immediately before sensing so that the charge accumulated in the floating diffusion region 608 during sensing is linearly proportional to the charge accumulated in the pinned photodiode layer 602 of the second conductivity type. The gate of the source follower transistor 650 (labeled "SF") is electrically connected to the floating diffusion region 608 via a set of metal interconnect structures. Therefore, the voltage at the gate of the source follower transistor 650 is proportional to the charge in the floating diffusion region 608. The select transistor (labeled "SEL") 660 is turned on during a read operation to output a voltage (modulated by the voltage at the gate of the source follower transistor 650) at a common node of the source follower transistor and the select transistor 660 to a column output bus (labeled "COLBUS").

[0186] Reference Fig.17 , illustrates a CMOS image sensor incorporating the photodetector circuitry and control circuitry of the present disclosure. The CMOS image sensor includes an array 1000 of pixels 900, the array of pixels including the respective structures of sub-pixels 800 as described above. Further, the CMOS image sensor includes a control circuit 2000 for generating respective control signals applied to transfer gates 605 within array 1000 and gates 615 of field effect transistors of sensing circuits (640, 650, 660) of array 1000.

[0187] Each sub-pixel 800 includes an instance of a photodetector circuit (630, 640, 650, 660). The photodetector circuit includes a photodetector (including a transfer transistor 630) and a sensing circuit (640, 650, 660) located above a substrate semiconductor layer 601 doped with a first conductivity type. The photodetector includes: a pinned photodiode layer 602 of a second conductivity type, which forms a pn junction with the substrate semiconductor layer 601; at least one floating diffusion region 608, which is laterally spaced from the periphery of the pinned photodiode layer 602 of the second conductivity type; and at least one transfer gate 605.

[0188] According to an embodiment of the present disclosure, at least two different operations may be performed in at least one instance and / or each instance of a photodetector circuit (630, 640, 650, 660) by applying at least two pulse patterns to at least one transfer gate 605. The at least two different pulse patterns differ from one another in at least one of the following: pulse duration, pulse amplitude, and delay time between a control signal applied to the sensing circuit (640, 650, 660) and the initiation of a pulse at a corresponding one of the at least one transfer gate 605.

[0189] In one embodiment, the Fig.17 The at least two different operations performed by the CMOS image sensor may include an image capture operation and an additional operation, wherein the image capture operation generates an electrical output from the sensing circuit (640, 650, 660) having a magnitude proportional to the amount of charge accumulated in the pinned photodiode layer 602 of the second conductivity type, and the additional operation does not generate a two-dimensional image of the intensity of the detected photons. In an illustrative example, the additional operation may include a single operation or multiple operations selected from the following: a phase detection autofocus operation, a time of flight detection operation, a single photon avalanche diode operation, and a near infrared operation.

[0190] Phase detection autofocus operation is an operation that can be performed with the CMOS image sensor of the present disclosure. Pairs of masked pixels, referred to as phase detection pixels, are provided in the CMOS image sensor. The pairs of masked pixels can be physically spaced apart from each other to provide detection of phase information after taking two low-resolution photos. Two different lower resolution images can be taken using phase detection pixels, and can be compared to find the best settings for the lens to obtain the best possible image for the high-resolution image. Specifically, the phase information generated from the phase detection pixels can be used to determine the focal length of the best high-resolution image. After the general processing unit for the image sensor receives the focal length information, the general processing unit can drive the lens to move to a position with the best focus. The phase detection autofocus operation can provide speed adjustment of the focal length of the lens of the CMOS image sensor.

[0191] The time-of-flight detection operation uses time-of-flight technology to resolve the distance between the CMOS image sensor of the present disclosure and the target for each point of the image captured by the CMOS image sensor by measuring the round-trip time of an artificial light signal, the artificial light signal being provided by a laser or light emitting diode emitting light of a predetermined wavelength. Each pixel of the CMOS image sensor may include and / or be composed of sub-pixels for detecting light of the predetermined wavelength. The laser-based time-of-flight detection operation can be used as part of a scannerless light detection and ranging (LIDAR) operation, where the entire scene is captured with each laser pulse, rather than capturing the entire scene point by point using a laser beam such as in a scanning LIDAR system. The time-of-flight detection operation can be used to determine distances in the range of a few centimeters to multiple kilometers. Currently, the distance resolution is about 1 cm. During the time-of-flight detection operation, each pixel (and / or each sub-pixel) can measure the time it takes for light to propagate from an illumination unit (which can be a laser source or a light emitting diode) to an object and back to the CMOS image sensor. Fast operation of each gate (615, 605) can be used.

[0192] Single photon avalanche diode operation is the operation of photogenerated carriers triggering a short-duration large avalanche current via the photoelectric effect. Charge carriers (such as electrons and holes) are accelerated in high electric fields to have high kinetic energy via collision ionization. The high kinetic energy of the charge carriers generates additional charge carriers by ionizing bulk materials. In the presence of a high electric field from a single charge carrier, the number of charge carriers can increase exponentially. In single photon avalanche operation, the pn junction of a pixel of a CMOS image sensor is reverse biased. The pixel can be designed to operate at a reverse bias voltage that is much higher than the breakdown voltage. Single photon avalanche diode operation can be effectively performed by providing a circuit in the control circuit system to sense the leading edge of the avalanche current to generate a standard output pulse synchronized with the avalanche accumulation, terminating the avalanche by reducing the bias voltage to the breakdown voltage, and restoring the photodiode to the operating level. The signal strength can be obtained by counting the number of output pulses within the measurement time slot. The time-dependent waveform of the signal can be obtained by measuring the time distribution of the output pulses.

[0193] Near infrared operation is operation that uses a sub-pixel array that includes a near infrared filter to capture near infrared light. The timing of control pulses for near infrared operation can be different from the timing of control pulses used to generate images based on light in the visible spectrum. In particular, due to the low sensitivity of photodetectors in the near infrared range, the exposure time for the photodetectors (including transfer transistor 630) can be extended, and the pulse pattern of each gate (605, 615) for the photodetectors can be modified compared to conventional operation for capturing images in the visible spectrum.

[0194] The additional operation may be related to enhancing the quality of an image captured by the CMOS image sensor by suppressing background noise. In one embodiment, the photodetector includes a pinned layer 603 of the first conductivity type, which forms another pn junction with a pinned photodiode layer 602 of the second conductivity type, and the additional operation includes a pinning operation to accumulate charge carriers of the first conductivity type in the pinned layer 603 of the first conductivity type. In one embodiment, the additional operation includes an overflow discharge operation in which the charge in the pinned photodiode layer 602 of the second conductivity type is discharged before performing an image capture operation.

[0195] Reference Fig.18 , illustrating an exemplary set of voltages as Fig.14 or Fig.15 V_PPD is a function of time during operation of the first exemplary photodetector circuit. Fig.14 or Fig.15 , and V_TG2. The pinned photodetector PPD of FIG. 6 is a pinned photodetector circuit ( 630 , 640 , 650 , 660 ). V_TG1 refers to the voltage applied to the first transfer gate TG1, and V_TG2 refers to the voltage applied to the second transfer gate TG2. V_SEL1 refers to the voltage applied to the gate of the first selector transistor SEL1, and V_SEL2 refers to the voltage applied to the gate of the second selector transistor SEL2. Different pulse patterns (illustrated by V_TG1 and V_TG2) can be simultaneously applied to multiple transfer gates 605 within the same sub-pixel (i.e., within the same photodetector circuit ( 630 , 640 , 650 , 660)). In addition, each transfer gate ( TG1 , TG2) can be electrically biased using a corresponding string of pulse patterns including at least two different pulse patterns. In general, the different pulse patterns applied to the multiple transfer gates 605 can enable Fig.14 or Fig.15 The simultaneous multiple operations of the first exemplary photodetector circuit may include an image acquisition operation and at least one additional operation, such as a phase detection autofocus operation, a time of flight detection operation, a single photon avalanche diode operation, and / or a near infrared operation.

[0196] Reference Fig.19 , an exemplary pulse pattern for two transfer gates (TG1, TG2) in a first exemplary photodetector circuit is illustrated according to an embodiment of the present disclosure. In this example, four different pulse patterns may be sequentially applied to each of the two transfer gates (TG1, TG2) to provide four different operations for each of the two transfer gates (TG1, TG2). Furthermore, the operations performed by the two transfer gates (TG1, TG2) may be of the same type or of different types.

[0197] Common Reference Fig.14 , Fig.15 , Fig.18 and Fig.19 , the at least one transfer gate 605 of each sub-pixel may include a plurality of transfer gates 605. At least two different pulse patterns may be applied to at least two different transfer gates 605 within the plurality of transfer gates 605. In one embodiment, the at least one floating diffusion region 608 may include a plurality of floating diffusion regions 608 that are electrically isolated from one another or from one another. In one embodiment, the plurality of floating diffusion regions 608 include a first floating diffusion region 608A and a second floating diffusion region 608B, and the plurality of transfer gates 605 include a first transfer gate 605A that covers a first channel region between the second conductivity type pinned photodiode layer 602 and the first floating diffusion region 608A, and a second transfer gate 605B that covers a second channel region between the second conductivity type pinned photodiode layer 602 and the second floating diffusion region 608B.

[0198] In one embodiment, the sensing circuit (640, 650, 660) includes a first source follower transistor SF1 and a second source follower transistor SF2, wherein the first source follower transistor SF1 is used to generate a first output voltage proportional to the charge accumulated in the first floating diffusion region 608A, and the second source follower transistor SF2 is used to generate a second output voltage proportional to the charge accumulated in the second floating diffusion region 608B. In one embodiment, as Fig.15 As shown, the sensing circuit (640, 650, 660) includes two output nodes (such as nodes V_out1 and V_out2), which are used to separately output a first output voltage from the first source follower transistor SF1 and a second output voltage from the second source follower transistor SF2. Fig.14 As shown, the sensing circuit (640, 650, 660) includes two output nodes (such as nodes V_out1 and V_out2), which are used to output one voltage at a time selected from the following: a first output voltage from the first source follower transistor SF1 and a second output voltage from the second source follower transistor SF2.

[0199] Reference Fig. 20 , illustrating an exemplary set of voltages as Fig.16 V_SEL is a function of time during operation of the second exemplary photodetector circuit. Fig.16 V_PPD is the voltage at the gate of the select transistor SEL. Fig.16605. The pinned photodetector PPD of FIG. 604 is a pinned photodetector 605. V_TG refers to the voltage applied to the transfer gate TG. V_RST refers to the voltage applied to the gate of the reset transistor RST (i.e., reset transistor 640). V_FD refers to the voltage at the floating diffusion region 608. Different pulse patterns, such as pulse pattern 1 and pulse pattern 2, may be applied to the transfer gate 605 simultaneously. In other words, the transfer gate 605 may be electrically biased using a respective train of pulse patterns including at least two different pulse patterns. The at least two different pulse patterns may be selected to sequentially enable an image capture operation and at least one additional operation, such as a phase detection autofocus operation, a time of flight detection operation, a single photon avalanche diode operation, and / or a near infrared operation.

[0200] Reference Fig.21 , illustrates exemplary pulse patterns for transfer gate 605 in a second exemplary photodetector circuit according to embodiments of the present disclosure. In this example, four different pulse patterns may be sequentially applied to transfer gate 605 to provide four different operations for transfer gate 605. In general, any sequential combination of different pulse patterns may be applied to transfer gate 605 to enable Fig.16 The sequential multiple operations in the second exemplary photodetector circuit of the present invention may include an image acquisition operation and at least one additional operation, such as a phase detection autofocus operation, a time of flight detection operation, a single photon avalanche diode operation, and / or a near infrared operation.

[0201] Common Reference Fig.16 , Fig. 20 and Fig.21 , at least one transfer gate 605 of each sub-pixel may consist of a single transfer gate 605 , and at least two different pulse patterns are sequentially applied to the single transfer gate 605 .

[0202] Reference Fig. 22, a general method of operating a device such as an image sensor is provided according to an embodiment of the present disclosure. Referring to step 2210, a device including an example of a photodetector circuit (630, 640, 650-660) is provided. The photodetector circuit (630, 640, 650-660) includes a photodetector (including a transfer transistor 630) and a sensing circuit (640, 650, 660). The photodetector and the sensing circuit (640, 650, 660) are located above a substrate semiconductor layer 601 doped with a first conductivity type. The photodetector includes: a pinned photodiode layer 602 of a second conductivity type, which forms a pn junction with the substrate semiconductor layer 601; at least one floating diffusion region 608, which is laterally spaced from a periphery of the pinned photodiode layer 602 of the second conductivity type; and at least one transfer gate 605. Referring to step 2220 , at least two different operations may be performed in an instance of the photodetector circuit ( 630 , 640 , 650 660 ) ​​by applying at least two pulse patterns to at least one transfer gate 605 .

[0203] In general, the photodetector circuits of embodiments of the present disclosure may include instances of sub-pixels within a CMOS image sensor that includes array 1000 of pixels 900. Each of pixels 900 may include at least one sub-pixel.

[0204] With reference to all figures and in accordance with various embodiments of the present disclosure, a method of operating a device is provided, wherein the method includes providing operation of a device including an example of a photodetector circuit 630, 640, 650, 660, wherein the photodetector circuit 630, 640, 650, 660 includes a photodetector 630 and a sensing circuit 640, 650, 660 located above a substrate semiconductor layer 601 doped with a first conductivity type, wherein the photodetector 630 includes: a pinned photodiode layer 602 of a second conductivity type, the layer forming a pn junction with the substrate semiconductor layer 601; at least one floating diffusion region 608, the floating diffusion region being laterally spaced apart from a perimeter of the pinned photodiode layer 602 of the second conductivity type; and at least one transfer gate 605. The method further includes an operation of performing at least two different operations in the instance of the photodetector circuit by applying at least two pulse patterns to the at least one transfer gate 605, wherein the at least two different pulse patterns differ from each other in at least one of pulse duration, pulse amplitude, and delay time between a control signal applied to the sensing circuit 640, 650, 660 and a pulse initiation at a corresponding one of the at least one transfer gate 605.

[0205] In one embodiment, a semiconductor device is provided, the semiconductor device including a substrate semiconductor layer 601 doped with a first conductivity type and a photodetector circuit (630, 640, 650, 660), the photodetector circuit being located on the substrate semiconductor layer 601 and including a photodetector (including a transfer transistor 630) and a sensing circuit (640, 650, 660). The photodetector includes: a pinned photodiode layer 602 of a second conductivity type, the layer forming a pn junction with the substrate semiconductor layer 601; at least one floating diffusion region 608, the floating diffusion region being laterally spaced apart from the periphery of the pinned photodiode layer 602 of the second conductivity type; and at least one transfer gate 605. The photodetector circuit (630, 640, 650, 660) is configured to perform at least two different operations by applying at least two different pulse patterns to at least one transfer gate 605 simultaneously and / or sequentially. At least two different pulse patterns differ from each other in at least one of: pulse duration, pulse amplitude, and delay time between a control signal applied to a sensing circuit (640, 650, 660) (which may include a gate control voltage to any transistor in the sensing circuit) and a pulse initiation at a corresponding one of at least one transfer gate 605.

[0206] In one embodiment, at least one transfer gate 605 is composed of a single transfer gate (eg, FIG. 3A to FIG. 3C and Fig.16 ), and at least two different pulse patterns may be applied sequentially to a single transfer gate 605 (eg Fig. 20 and Fig.21 shown).

[0207] In one embodiment, the at least one transfer gate 605 includes a plurality of transfer gates 605 (eg, FIG. 2A to FIG. 2E , Fig.14 and Fig.15 ), and at least two different pulse patterns are applied to at least two different transfer gates 605 (such as Fig.18 and Fig.19 shown).

[0208] In one embodiment, the at least one floating diffusion region 608 includes a plurality of floating diffusion regions 608 that are electrically isolated from each other or from each other (eg, FIG. 2A to FIG. 2E , Fig.14 and Fig.15). In one embodiment, the plurality of floating diffusion regions 608 include a first floating diffusion region 608A and a second floating diffusion region 608B, and the plurality of transfer gates 605 include a first transfer gate 605A, the first transfer gate covering a first channel region between the second conductivity type pinned photodiode layer 602 and the first floating diffusion region 608A, and a second transfer gate 605B, the second transfer gate covering a second channel region between the second conductivity type pinned photodiode layer 602 and the second floating diffusion region 608B. In one embodiment, the sensing circuit (640, 650, 660) includes a first source follower transistor SF1 and a second source follower transistor SF2, the first source follower transistor SF1 is used to generate a first output voltage proportional to the charge accumulated in the first floating diffusion region 608A (i.e., FD1), and the second source follower transistor SF2 is used to generate a second output voltage proportional to the charge accumulated in the second floating diffusion region 608B (i.e., FD2).

[0209] According to an embodiment of the present disclosure, a CMOS image sensor is provided, including an array 1000 of pixels 900 located on a substrate semiconductor layer 601 doped with a first conductivity type. Each of the pixels 900 includes at least one sub-pixel 800, and each sub-pixel 800 includes a photodetector circuit (630, 640, 650, 660), which includes a photodetector including a transfer transistor 630 and a sensing circuit (640, 650, 660). The photodetector includes: a pinned photodiode layer 602 of a second conductivity type, which forms a pn junction with the substrate semiconductor layer 601; a plurality of floating diffusion regions 608, which are electrically isolated from each other or from each other and laterally spaced from the periphery of the pinned photodiode layer 602 of the second conductivity type; and a plurality of transfer gates 605. The photodetector circuit (640, 650, 660) can be used to perform at least two different operations by applying at least two pulse patterns to the plurality of transfer gates 605 simultaneously and / or sequentially. The at least two different pulse patterns differ from each other in one of pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and the initiation of a pulse at a corresponding one of the plurality of transfer gates 605 .

[0210] In one embodiment, the plurality of floating diffusion regions 608 include a first floating diffusion region 608A and a second floating diffusion region 608B. The plurality of transfer gates 605 include a first transfer gate 605A, which covers a first channel region between the pinned photodiode layer 602 of the second conductivity type and the first floating diffusion region 608A, and a second transfer gate 605B, which covers a second channel region between the pinned photodiode layer 602 of the second conductivity type and the second floating diffusion region 608B. The sensing circuit includes a first source follower transistor SF1 and a second source follower transistor SF2, the first source follower transistor SF1 is used to generate a first output voltage proportional to the charge accumulated in the first floating diffusion region 608A, and the second source follower transistor SF2 is used to generate a second output voltage proportional to the charge accumulated in the second floating diffusion region 608B.

[0211] Various methods and structures of the present disclosure may be used to provide a photodetector circuit that may include a subpixel of a CMOS image sensor and may perform multiple functions using a common pinned photodiode PPD. The multiple functions may include a typical image capture operation and at least one additional operation that may provide additional functionality to the CMOS image sensor and / or may enhance the quality of the captured image.

[0212] In some embodiments of the present disclosure, a method of operating a device includes the following operations: providing a device including a photodetector circuit, wherein the photodetector circuit includes a photodetector and a sensing circuit, the photodetector and the sensing circuit being located above a substrate semiconductor layer doped with a first conductivity type, wherein the photodetector includes: a pinned photodiode layer of a second conductivity type forming a pn junction with the substrate semiconductor layer; at least one floating diffusion region, the floating diffusion region being laterally spaced from a periphery of the pinned photodiode layer of the second conductivity type; and at least one transfer gate. At least two different operations are performed in the photodetector circuit by applying at least two different pulse patterns to the at least one transfer gate, wherein the at least two different pulse patterns differ from each other in at least one of the following: pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and a pulse activation at a corresponding one of the at least one transfer gate.

[0213] In some embodiments, the at least two different operations include: an image capture operation and an additional operation. The image capture operation generates an electrical output from the sensing circuit, the electrical output having a magnitude proportional to the amount of charge accumulated in the pinned photodiode layer of the second conductivity type. The additional operation enhances the quality of the two-dimensional image of the detected photon intensity.

[0214] In some embodiments, the additional operation includes a single operation or a plurality of operations selected from the group consisting of: phase detection autofocus operation, time of flight detection operation, single photon avalanche diode operation, and near infrared operation.

[0215] In some embodiments, the photodetector includes a pinned layer of the first conductivity type forming another pn junction with a pinned photodiode layer of the second conductivity type. Additional operations include a pinning operation that accumulates charge carriers of the first conductivity type in the pinned layer of the first conductivity type.

[0216] In some embodiments, the additional operation includes an overflow discharge operation in which charges in the pinned photodiode layer of the second conductivity type are discharged before performing the image capture operation.

[0217] In some embodiments, the at least one transfer gate is composed of a single transfer gate. At least two different pulse patterns are sequentially applied to the single transfer gate.

[0218] In some embodiments, the at least one transfer gate comprises a plurality of transfer gates. At least two different pulse patterns are applied to at least two different transfer gates among the plurality of transfer gates.

[0219] In some embodiments, the at least one floating diffusion region includes a plurality of floating diffusion regions that are electrically isolated from one another.

[0220] In some embodiments, the floating diffusion regions include a first floating diffusion region and a second floating diffusion region. The transfer gates include a first transfer gate covering a first channel region between the second conductivity type pinned photodiode layer and the first floating diffusion region, and a second transfer gate covering a second channel region between the second conductivity type pinned photodiode layer and the second floating diffusion region.

[0221] In some embodiments, the sensing circuit includes a first source-follower transistor for generating a first output voltage proportional to the charge accumulated in the first floating diffusion region and a second source-follower transistor for generating a second output voltage proportional to the charge accumulated in the second floating diffusion region.

[0222] In some embodiments, the sensing circuit includes two output nodes, and the output nodes are used to separately output a first output voltage from the first source-follower transistor and a second output voltage from the second source-follower transistor.

[0223] In some embodiments, a device comprises a CMOS image sensor comprising an array of a plurality of pixels, each of which comprises at least one sub-pixel.

[0224] In some embodiments of the present disclosure, a semiconductor structure includes a substrate semiconductor layer having a doping of a first conductivity type; and a photodetector circuit located on the substrate semiconductor layer and including a photodetector and a sensing circuit. The photodetector includes: a pinned photodiode layer of a second conductivity type, which forms a pn junction with the substrate semiconductor layer; at least one floating diffusion region, the floating diffusion region being laterally spaced from a periphery of the pinned photodiode layer of the second conductivity type; and at least one transfer gate. The photodetector circuit is configured to perform at least two different operations by applying at least two different pulse patterns to the at least one transfer gate. The at least two different pulse patterns differ from each other in at least one of the following: pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and a pulse activation at a corresponding one of the at least one transfer gate.

[0225] In some embodiments, the at least one transfer gate is composed of a single transfer gate. At least two different pulse patterns are sequentially applied to the single transfer gate.

[0226] In some embodiments, the at least one transfer gate comprises a plurality of transfer gates. At least two different pulse patterns are applied to at least two different transfer gates among the plurality of transfer gates.

[0227] In some embodiments, the at least one floating diffusion region includes a plurality of floating diffusion regions that are electrically isolated from one another.

[0228] In some embodiments, the floating diffusion regions include a first floating diffusion region and a second floating diffusion region. The transfer gates include a first transfer gate covering a first channel region between the second conductivity type pinned photodiode layer and the first floating diffusion region, and a second transfer gate covering a second channel region between the second conductivity type pinned photodiode layer and the second floating diffusion region.

[0229] In some embodiments, the sensing circuit includes: a first source follower transistor for generating a first output voltage proportional to the charge accumulated in the first floating diffusion region; and a second source follower transistor for generating a second output voltage proportional to the charge accumulated in the second floating diffusion region.

[0230] In some embodiments of the present disclosure, a complementary metal oxide semiconductor image sensor includes an array of multiple pixels located on a substrate semiconductor layer having a first conductivity type doping. Each of the pixels includes at least one sub-pixel, and each sub-pixel includes a photodetector circuit, the photodetector circuit including a photodetector and a sensing circuit. The photodetector includes: a pinned photodiode layer of a second conductivity type, which forms a pn junction with the substrate semiconductor layer; a plurality of floating diffusion regions, the floating diffusion regions are electrically isolated from each other or from each other and are laterally spaced from the periphery of the pinned photodiode layer of the second conductivity type; and a plurality of transfer gates. The photodetector circuit is used to perform at least two different operations by applying at least two different pulse patterns to the transfer gates. The at least two different pulse patterns differ from each other or from each other in one of the following: pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and a pulse start at a corresponding one of the transfer gates.

[0231] In some embodiments, the floating diffusion regions include a first floating diffusion region and a second floating diffusion region. The transfer gates include a first transfer gate, the first transfer gate covers a first channel region between a pinned photodiode layer of a second conductivity type and the first floating diffusion region, and include a second transfer gate, the second transfer gate covers a second channel region between a pinned photodiode layer of a second conductivity type and the second floating diffusion region. The sensing circuit includes a first source follower transistor and a second source follower transistor, the first source follower transistor is used to generate a first output voltage proportional to the charge accumulated in the first floating diffusion region, and the second source follower transistor is used to generate a second output voltage proportional to the charge accumulated in the second floating diffusion region.

[0232] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be implemented herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of operating a device, characterized in that Include: The device is provided including a photodetector circuit, wherein the photodetector circuit includes a photodetector and a sensing circuit, the photodetector and the sensing circuit being located above a substrate semiconductor layer having a doping of a first conductivity type, wherein the photodetector comprises: a pinned photodiode layer of a second conductivity type forming a pn junction with the substrate semiconductor layer; at least one floating diffusion region, the floating diffusion region being laterally spaced apart from a periphery of the pinned photodiode layer of the second conductivity type; and at least one transfer gate; as well as performing at least two different operations in the photodetector circuit by applying at least two different pulse patterns to the at least one transfer gate, wherein the at least two different pulse patterns differ from each other in at least one of pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and a pulse initiation at a corresponding one of the at least one transfer gate, The at least two different operations include: an image capture operation and at least one additional operation, and the at least one additional operation includes a single operation or multiple operations selected from the following: a phase detection autofocus operation, a single photon avalanche diode operation, and a near infrared operation.

2. The method according to claim 1, characterized in that The image capture operation generates an electrical output from the sensing circuit, the electrical output having a magnitude proportional to an amount of charge accumulated in the pinned photodiode layer of the second conductivity type; as well as The at least one additional operation enhances the quality of a two-dimensional image of detected photon intensities.

3. The method according to claim 2, characterized in that in: The photodetector includes a pinned layer of the first conductivity type, which forms another pn junction with the pinned photodiode layer of the second conductivity type; as well as The at least one additional operation includes a pinning operation that accumulates charge carriers of the first conductivity type in a pinned layer of the first conductivity type.

4. The method according to claim 2, characterized in that: The at least one additional operation includes an overflow discharge operation, wherein the charges in the second conductivity type pinned photodiode layer are discharged before performing the image capture operation.

5. The method according to claim 1, characterized in that in: The at least one transfer gate consists of a single transfer gate; and The at least two different pulse patterns are sequentially applied to the single transfer gate.

6. The method according to claim 1, characterized in that in: The at least one transfer gate comprises a plurality of transfer gates; as well as The at least two different pulse patterns are applied to at least two different transfer gates within the plurality of transfer gates.

7. The method according to claim 1, characterized in that The at least one floating diffusion region includes a plurality of floating diffusion regions electrically isolated from each other.

8. The method according to claim 7, characterized in that in: The plurality of floating diffusion regions include a first floating diffusion region and a second floating diffusion region; and The at least one transfer gate includes a first transfer gate covering a first channel region between the pinned photodiode layer of the second conductivity type and the first floating diffusion region, and includes a second transfer gate covering a second channel region between the pinned photodiode layer of the second conductivity type and the second floating diffusion region.

9. The method according to claim 8, characterized in that The sensing circuit comprises: a first source follower transistor for generating a first output voltage proportional to the charge accumulated in the first floating diffusion region; and A second source follower transistor is used to generate a second output voltage proportional to the charges accumulated in the second floating diffusion region.

10. The method according to claim 9, characterized in that The sensing circuit includes two output nodes, and the two output nodes are used to separately output a first output voltage from the first source-follower transistor and a second output voltage from the second source-follower transistor.

11. The method according to claim 1, characterized in that: in: The device comprises a CMOS image sensor including an array of a plurality of pixels; and Each of the plurality of pixels includes at least one sub-pixel.

12. A semiconductor structure, characterized in that: Include: A substrate semiconductor layer having a doping of a first conductivity type; and a photodetector circuit, located on the semiconductor layer of the substrate and comprising a photodetector and a sensing circuit, in: The photodetector includes: a pinned photodiode layer of a second conductivity type forming a pn junction with the substrate semiconductor layer; at least one floating diffusion region laterally spaced from a periphery of the pinned photodiode layer of the second conductivity type; and at least one transfer gate; The photodetector circuit is configured to perform at least two different operations by applying at least two different pulse patterns to the at least one transfer gate; and The at least two different pulse patterns differ from each other in at least one of: pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and the initiation of a pulse at a corresponding one of the at least one transfer gate, The at least two different operations include: an image capture operation and at least one additional operation, and the at least one additional operation includes a single operation or multiple operations selected from the following: a phase detection autofocus operation, a single photon avalanche diode operation, and a near infrared operation.

13. The semiconductor structure according to claim 12, characterized in that: in: The at least one transfer gate consists of a single transfer gate; and The at least two different pulse patterns are sequentially applied to the single transfer gate.

14. The semiconductor structure according to claim 12, characterized in that: in: The at least one transfer gate comprises a plurality of transfer gates; as well as The at least two different pulse patterns are applied to at least two different transfer gates within the plurality of transfer gates.

15. The semiconductor structure according to claim 12, characterized in that: The at least one floating diffusion region includes a plurality of floating diffusion regions that are electrically isolated from each other.

16. The semiconductor structure according to claim 15, characterized in that in: The plurality of floating diffusion regions include a first floating diffusion region and a second floating diffusion region; and The at least one transfer gate includes a first transfer gate covering a first channel region between the pinned photodiode layer of the second conductivity type and the first floating diffusion region, and includes a second transfer gate covering a second channel region between the pinned photodiode layer of the second conductivity type and the second floating diffusion region.

17. The semiconductor structure according to claim 16, characterized in that: The sensing circuit comprises: a first source follower transistor for generating a first output voltage proportional to the charge accumulated in the first floating diffusion region; and A second source follower transistor is used to generate a second output voltage proportional to the charges accumulated in the second floating diffusion region.

18. A complementary metal oxide semiconductor image sensor, characterized in that: An array of a plurality of pixels is provided on a substrate semiconductor layer doped with a first conductivity type, in: Each of the plurality of pixels includes at least one sub-pixel, and each sub-pixel includes a photodetector circuit including a photodetector and a sensing circuit; The photodetector comprises: a pinned photodiode layer of a second conductivity type forming a pn junction with the substrate semiconductor layer; a plurality of floating diffusion regions electrically isolated from each other and laterally spaced apart from a periphery of the pinned photodiode layer of the second conductivity type; and a plurality of transfer gates; The photodetector circuit is configured to perform at least two different operations by applying at least two different pulse patterns to the plurality of transfer gates; and The at least two different pulse patterns differ from each other in one of: pulse duration, pulse amplitude, and a delay time between a control signal applied to the sensing circuit and the initiation of a pulse at a corresponding one of the plurality of transfer gates, The at least two different operations include: an image capture operation and at least one additional operation, and the at least one additional operation includes a single operation or multiple operations selected from the following: a phase detection autofocus operation, a single photon avalanche diode operation, and a near infrared operation.

19. The complementary metal oxide semiconductor image sensor according to claim 18, wherein: in: The plurality of floating diffusion regions include a first floating diffusion region and a second floating diffusion region; The plurality of transfer gates include a first transfer gate covering a first channel region between the second conductivity type pinned photodiode layer and the first floating diffusion region, and a second transfer gate covering a second channel region between the second conductivity type pinned photodiode layer and the second floating diffusion region; as well as The sensing circuit includes a first source follower transistor and a second source follower transistor. The first source follower transistor is used to generate a first output voltage proportional to the charge accumulated in the first floating diffusion region, and the second source follower transistor is used to generate a second output voltage proportional to the charge accumulated in the second floating diffusion region.

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