Memory device, magnetic tunnel junction memory device, and method of forming the same

Abstract

A memory device, a magnetic tunnel junction memory device, and a method of forming the same. A top electrode and a pillar of a hard mask portion are stacked above a layer stack including a continuous reference magnetization layer, a continuous non-magnetic tunnel barrier layer, and a continuous free magnetization layer. A continuous dielectric liner may be deposited and anisotropically etched to form an inner dielectric spacer. The continuous free magnetization layer, the continuous non-magnetic tunnel barrier layer, and the continuous reference magnetization layer may be anisotropically etched to form a vertical stack of a corresponding reference magnetization layer, a corresponding non-magnetic tunnel barrier layer, and a corresponding free magnetization layer as a magnetic tunnel junction. The inner dielectric spacer prevents re-deposition of the metal material of the hard mask portion on the sidewalls of the magnetic tunnel junction. The hard mask portion may be removed, and a metal cell contact structure may be formed on top of each top electrode.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory device, a magnetic tunnel junction memory device, and a method of forming the same. Background Art

[0002] Semiconductor memory devices are widely used in modern electronic devices. Some semiconductor memory devices use corresponding vertically stacked memory cells that include a bottom electrode, a memory element, and a top electrode. For example, a magnetic tunnel junction memory device may use such a vertical stack, where the memory element includes a magnetic tunnel junction. The magnetic tunnel junction needs to be patterned without metal contamination to avoid internal electrical short circuits. Summary of the Invention

[0003] The present disclosure provides a magnetic tunnel junction memory device including: a vertical stack including a reference magnetization structure, a non-magnetic tunnel barrier, and a free magnetization structure and positioned above a semiconductor substrate; a top electrode overlying a central portion of the free magnetization structure; and an inner dielectric spacer overlying a peripheral portion of the free magnetization structure and laterally surrounding the top electrode and including a tapered outer sidewall having a cone angle in a range of 2 degrees to 10 degrees with respect to a vertical direction.

[0004] The present disclosure provides a memory device including: a field effect transistor positioned on a semiconductor substrate; a metal interconnect structure formed in a dielectric material layer overlying the field effect transistor; and

[0005] an array of magnetic tunnel junction (MTJ) memory cells formed in a dielectric matrix layer overlying the dielectric material layer, wherein each magnetic tunnel junction memory cell within the array includes: a vertical stack including a reference magnetization structure, a non-magnetic tunnel barrier, and a free magnetization structure and positioned above a semiconductor substrate; a top electrode overlying a central portion of the free magnetization structure; an inner dielectric spacer overlying a peripheral portion of the free magnetization structure and laterally surrounding the top electrode and including a tapered outer sidewall; and an outer dielectric spacer laterally surrounding the inner dielectric spacer and the vertical stack and laterally surrounded by the dielectric matrix layer.

[0006] The present disclosure provides a method for forming a magnetic tunnel junction memory device on a semiconductor substrate, including: forming a pillar stack including a top electrode and a hard mask portion, the top electrode and the hard mask portion being laterally spaced apart from each other above a vertical stack including a continuous reference magnetization layer, a continuous non-magnetic tunnel barrier layer, and a continuous free magnetization layer; forming an inner dielectric spacer by depositing a continuous dielectric liner above the pillar stack and anisotropically etching the continuous dielectric liner; and anisotropically etching the continuous free magnetization layer, the continuous non-magnetic tunnel barrier layer, and the continuous reference magnetization layer using the inner dielectric spacer and the hard mask portion as etching masks. Wherein: forming a vertical stack including corresponding reference magnetization structures, corresponding non-magnetic tunnels barriers, and corresponding free magnetization structures; and each of the vertical stacks has a top perimeter that coincides with an outer bottom perimeter of a corresponding one of the inner dielectric spacers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figure 1 is a vertical cross-sectional view of an exemplary structure after forming a complementary metal-oxide-semiconductor (CMOS) transistor and a metal interconnect structure formed in a dielectric material layer according to an embodiment of the present disclosure.

[0009] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a dielectric capping layer, a via-level dielectric layer, and a lower electrode contact via cavity according to an embodiment of the present disclosure.

[0010] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming a continuous metal barrier layer and a metal via fill material portion according to an embodiment of the present disclosure.

[0011] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming a continuous bottom electrode material layer, a continuous non-magnetic metal buffer layer, a continuous synthetic antiferromagnetic layer, a continuous non-magnetic tunnel barrier layer, a continuous free magnetization layer, at least one continuous capping layer, a continuous top electrode material layer, a continuous dielectric liner layer, and a hard mask material layer according to an embodiment of the present disclosure.

[0012] Figure 5A vertical cross-sectional view of an exemplary structure after patterning a hard mask material layer into a hard mask portion according to an embodiment of the present disclosure.

[0013] Figure 6 A vertical cross-sectional view of an exemplary structure after stacking columns including a top electrode, a dielectric liner, and a hard mask portion according to an embodiment of the present disclosure.

[0014] Figure 7 A vertical cross-sectional view of an exemplary structure after conformal deposition of a continuous dielectric liner according to an embodiment of the present disclosure.

[0015] Figure 8 A vertical cross-sectional view of an exemplary structure after forming inner dielectric spacers according to an embodiment of the present disclosure.

[0016] Figure 9 A vertical cross-sectional view of an exemplary structure after forming an array of discrete vertical stacks including a synthetic antiferromagnetic structure, a non-magnetic tunnel barrier layer, a free magnetization layer, and at least one capping layer according to an embodiment of the present disclosure.

[0017] Figure 10 A vertical cross-sectional view of an exemplary structure after forming an array of outer dielectric spacers around a vertical stack according to an embodiment of the present disclosure.

[0018] Figure 11 A vertical cross-sectional view of an exemplary structure after forming a non-magnetic metal barrier layer, a bottom electrode, and a bottom electrode connection via structure according to an embodiment of the present disclosure.

[0019] Figure 12 A vertical cross-sectional view of an exemplary structure after forming an etch stop dielectric layer, a silicon oxide liner layer, and a first dielectric matrix layer according to an embodiment of the present disclosure.

[0020] Figure 13 A vertical cross-sectional view of an exemplary structure after a chemical mechanical planarization process for planarizing the first dielectric matrix layer according to an embodiment of the present disclosure.

[0021] Figure 14 A vertical cross-sectional view of an exemplary structure after forming a second dielectric matrix layer and via cavities in a logic region according to an embodiment of the present disclosure.

[0022] Figure 15 A vertical cross-sectional view of an exemplary structure after forming integrated lines and via cavities in a logic region and cell contact cavities in a memory array region according to an embodiment of the present disclosure.

[0023] Figure 16A vertical cross-sectional view of an exemplary structure after forming an integrated line and via structure in a logic region and a metal cell contact structure in a memory array region according to an embodiment of the present disclosure.

[0024] Figure 17 A vertical cross-sectional view of an exemplary structure after forming an additional metal interconnect structure formed in an additional dielectric material layer according to an embodiment of the present disclosure.

[0025] Figure 18 A flowchart showing the general processing steps of the method of the present disclosure.

[0026] Explanation of reference numerals in the drawings

[0027] 9: Semiconductor substrate;

[0028] 100: Memory array region;

[0029] 101: Memory cell;

[0030] 108: Dielectric capping layer;

[0031] 110: Via-level dielectric layer;

[0032] 121: Lower electrode contact via cavity;

[0033] 122: Metal barrier;

[0034] 122L: Continuous metal barrier layer;

[0035] 124: Metal via fill material portion;

[0036] 126: Bottom electrode;

[0037] 126L: Continuous bottom electrode material layer;

[0038] 128: Non-magnetic metal buffer layer;

[0039] 128L: Continuous non-magnetic metal buffer layer;

[0040] 140: Synthetic antiferromagnetic structure;

[0041] 140L: Continuous synthetic antiferromagnetic layer;

[0042] 141: Ferromagnetic hard mask;

[0043] 141L: Continuous ferromagnetic hard layer;

[0044] 142: Antiferromagnetic coupling structure;

[0045] 142L: Continuous antiferromagnetic coupling layer;

[0046] 143: Reference magnetization structure;

[0047] 143L: Continuous reference magnetization layer;

[0048] 146: Non-magnetic tunnel barrier;

[0049] 146L: Continuous non-magnetic tunnel barrier layer;

[0050] 148: Free magnetization structure;

[0051] 148L: Continuous free magnetization layer;

[0052] 158: Top cap structure;

[0053] 158L: Continuous top cap layer;

[0054] 160: Top electrode;

[0055] 160L: Continuous top electrode material layer;

[0056] 161: Inner dielectric spacer;

[0057] 161L: Continuous dielectric lining;

[0058] 162: First dielectric spacer;

[0059] 164: Second dielectric spacer;

[0060] 166: Dielectric pad;

[0061] 166L: Continuous dielectric pad layer;

[0062] 168: Hard mask portion;

[0063] 168L: Hard mask material layer;

[0064] 170: Etch stop dielectric layer;

[0065] 172: Silicon oxide lining layer;

[0066] 176: First dielectric matrix layer;

[0067] 178: Second dielectric matrix layer;

[0068] 181: Via cavity;

[0069] 183: Integrated line and via cavity;

[0070] 184: Integrated line and via structure;

[0071] 187: Cell contact cavity;

[0072] 188: Metal cell contact structure;

[0073] 200: Logic region;

[0074] 601: Contact level dielectric material layer;

[0075] 610: First metal wire level dielectric material layer;

[0076] 612: Device contact via structure;

[0077] 618: First metal wire structure;

[0078] 620: Second wire and via level dielectric material layer;

[0079] 622: First metal via structure;

[0080] 628: Second metal wire structure;

[0081] 630: Third wire and via level dielectric material layer;

[0082] 632: Second metal via structure;

[0083] 638: Third metal wire structure;

[0084] 640: Fourth wire and via level dielectric material layer;

[0085] 642: Third metal via structure;

[0086] 648: Fourth metal wire structure;

[0087] 660: Sixth wire and via level dielectric material layer;

[0088] 662: Fifth metal via structure;

[0089] 668: Sixth metal wire structure;

[0090] 700: Complementary metal oxide semiconductor circuit;

[0091] 720: Shallow trench isolation structure;

[0092] 732: Source region;

[0093] 735: Semiconductor channel;

[0094] 738: Drain region;

[0095] 742: Source side metal semiconductor alloy region;

[0096] 748: Drain side metal semiconductor alloy region;

[0097] 750: Gate structure;

[0098] 752: Gate dielectric;

[0099] 754: Gate electrode;

[0100] 756: Dielectric gate spacer;

[0101] 758: Gate cap dielectric;

[0102] 1810, 1820, 1830: Steps;

[0103] TP: Common tapered plane. Detailed Description

[0104] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0105] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless otherwise explicitly stated, it is assumed that elements with the same reference numeral have the same material composition and the same thickness range.

[0106] The present disclosure relates to semiconductor devices, and more particularly, to a semiconductor memory device and a method of forming the same that use self-aligned dielectric spacers to pattern magnetic tunnel junctions. Generally, the structures and methods of the present disclosure can be used as memory devices that include magnetic tunnel junctions that are free of metal residues on their sidewalls. A hard mask portion that includes a metal material can be used to pattern a top electrode and the magnetic tunnel junction thereunder. The hard mask portion can be used in two separate anisotropic etching processes to pattern the top electrode and the magnetic tunnel junction thereunder. After patterning the top electrode using a first anisotropic etching process, an inner dielectric spacer having a tapered outer sidewall can be formed around the top electrode. A second anisotropic etching process can use a combination of the hard mask portion and the inner dielectric spacer to pattern the magnetic tunnel junction. Metal residues that may be generated during the second anisotropic etching process can be spaced apart from the top electrode by the inner dielectric spacer. Accordingly, such metal residues can be prevented from causing an electrical short circuit (i.e., an electrical connection) between the top electrode and the magnetic tunnel junction.

[0107] It should be understood that a memory device in accordance with an embodiment of the present disclosure can include a single discrete memory cell, a one-dimensional array of memory cells, or a two-dimensional array of memory cells. It should also be understood that the one-dimensional array of memory cells of the present disclosure can be implemented as a periodic one-dimensional array of memory cells, and the two-dimensional array of memory cells of the present disclosure can be implemented as a periodic two-dimensional array of memory cells. Additionally, although the present disclosure is described using an embodiment in which a two-dimensional array of memory cells is formed within a fifth metal interconnect level (which is generally referred to as a fifth line-and-via (M5+V4) level), embodiments in which a two-dimensional array of memory cells can be formed within different metal interconnect levels are expressly contemplated herein.

[0108] Reference Figure 1, showing an exemplary structure according to an embodiment of the present disclosure. The exemplary structure may include a semiconductor substrate 9 which may be a commercially available silicon semiconductor substrate. A shallow trench isolation structure 720 including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor substrate 9. Appropriate doped semiconductor wells (e.g., p-type wells and n-type wells) may be formed in each region laterally enclosed by a continuous portion of the shallow trench isolation structure 720. Field effect transistors may be formed above the top surface of the semiconductor substrate 9. For example, each field effect transistor may include a source region 732, a drain region 738, a semiconductor channel 735 including a surface portion of the semiconductor substrate 9 extending between the source region 732 and the drain region 738, and a gate structure 750. Each gate structure 750 may include a gate dielectric 752, a gate electrode 754, a gate capping dielectric 758, and dielectric gate spacers 756. A source-side metal semiconductor alloy region 742 may be formed on each source region 732, and a drain-side metal semiconductor alloy region 748 may be formed on each drain region 738.

[0109] The exemplary structure may include a storage array region 100 in which an array of memory elements may be subsequently formed, and a logic region 200 in which logic devices that support the operation of the array of memory elements may be formed. In one embodiment, the devices (e.g., field effect transistors) in the storage array region 100 may include bottom electrode access transistors that provide access to the bottom electrodes of the memory cells to be subsequently formed. At this processing step, top electrode access transistors may be formed in the logic region 200 that provide access to the top electrodes of the memory cells to be subsequently formed. The devices (e.g., field effect transistors) in the logic region 200 may provide functions that may be required to operate the array of memory cells to be subsequently formed. Specifically, the devices in the logic region may be configured to control the programming operation, the erase operation, and the sense (read) operation of the array of memory cells. For example, the devices in the logic region may include sense circuits and / or top electrode bias circuits. The devices formed on the top surface of the semiconductor substrate 9 may include complementary metal oxide semiconductor (CMOS) transistors and optionally additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.), and are collectively referred to as the CMOS circuit 700.

[0110] Different metal interconnect structures formed in the dielectric material layer can subsequently be formed over the semiconductor substrate 9 and devices (such as field effect transistors). The dielectric material layer can include, for example, a contact-level dielectric material layer 601, a first metal wire-level dielectric material layer 610, a second wire and via-level dielectric material layer 620, a third wire and via-level dielectric material layer 630, and a fourth wire and via-level dielectric material layer 640. The metal interconnect structures can include: a device contact via structure 612 formed in the contact-level dielectric material layer 601 and contacting corresponding components of the CMOS circuit 700; a first metal wire structure 618 formed in the first metal wire-level dielectric material layer 610; a first metal via structure 622 formed in the lower portion of the second wire and via-level dielectric material layer 620; a second metal wire structure 628 formed in the upper portion of the second wire and via-level dielectric material layer 620; a second metal via structure 632 formed in the lower portion of the third wire and via-level dielectric material layer 630; a third metal wire structure 638 formed in the upper portion of the third wire and via-level dielectric material layer 630; a third metal via structure 642 formed in the lower portion of the fourth wire and via-level dielectric material layer 640; and a fourth metal wire structure 648 formed in the upper portion of the fourth wire and via-level dielectric material layer 640. In one embodiment, the second metal wire structure 628 can include a source line connected to the source-side power supply of the array of storage elements. The voltage provided by the source line can be applied to the bottom electrode through access transistors provided in the storage array region 100.

[0111] Each of the dielectric material layers (dielectric material layer 601, dielectric material layer 610, dielectric material layer 620, dielectric material layer 630, dielectric material layer 640) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous carbon fluoride, a porous variant thereof, or a combination thereof. Each of the metal interconnect structures (metal interconnect structure 612, metal interconnect structure 618, metal interconnect structure 622, metal interconnect structure 628, metal interconnect structure 632, metal interconnect structure 638, metal interconnect structure 642, metal interconnect structure 648) may include at least one conductive material, which may be a combination of a metal liner layer (such as a metal nitride or a metal carbide) and a metal fill material. Each metal liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metal fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the disclosed scope may also be used. In one embodiment, the first metal via structure 622 and the second metal line structure 628 may be formed as an integrated line and via structure by a dual damascene process, the second metal via structure 632 and the third metal line structure 638 may be formed as an integrated line and via structure by a dual damascene process, and / or the third metal via structure 642 and the fourth metal line structure 648 may be formed as an integrated line and via structure by a dual damascene process. Although embodiments in which an array of memory cells is formed above the fourth line and via level dielectric material layer 640 are used to describe the present disclosure, embodiments in which an array of memory cells may be formed at different metal interconnect layer levels are explicitly contemplated herein.

[0112] Reference Figure 2 , the dielectric capping layer 108 and the via level dielectric layer 110 may be formed in sequence above the metal interconnect structure and the dielectric material layer. For example, the dielectric capping layer 108 may be formed on the top surface of the fourth metal line structure 648 and on the top surface of the fourth line and via level dielectric material layer 640. The dielectric capping layer 108 may include a dielectric capping material, which may protect the metal interconnect structure thereunder, such as the fourth metal line structure 648. In one embodiment, the dielectric capping layer 108 may include a material that provides high etch resistance, i.e., a dielectric material that may also act as an etch stop material during subsequent anisotropic etch processes for etching the via level dielectric layer 110. For example, the dielectric capping layer 108 may include silicon carbide or silicon nitride and may have a thickness in the range of 5 nanometers to 30 nanometers, although smaller and larger thicknesses may also be used.

[0113] The via-level dielectric layer 110 may include any material that can be used for dielectric material layers (dielectric material layer 601, dielectric material layer 610, dielectric material layer 620, dielectric material layer 630, dielectric material layer 640). For example, the via-level dielectric layer 110 may include undoped silicate glass or doped silicate glass deposited by decomposition of tetraethylorthosilicate (TEOS). The thickness of the via-level dielectric layer 110 may range from 50 nanometers to 200 nanometers, although smaller and larger thicknesses may also be used. The dielectric capping layer 108 and the via-level dielectric layer 110 may be formed as planar blanket (unpatterned) layers having corresponding planar top surfaces and corresponding planar bottom surfaces that extend through the memory array region 100 and the logic region 200.

[0114] Via cavities may be formed through the via-level dielectric layer 110 and the dielectric capping layer 108. For example, a photoresist layer (not shown) may be applied over the via-level dielectric layer 110 and patterned to form an opening in the region of the memory array region 100 corresponding to a respective one of the overlying fourth metal line structures 648. An anisotropic etch may be performed to transfer the pattern in the photoresist layer through the via-level dielectric layer 110 and the dielectric capping layer 108. The via cavities formed by the anisotropic etch process are referred to herein as lower electrode contact via cavities 121 because bottom electrode connection via structures are subsequently formed in the lower electrode contact via cavities 121. The lower electrode contact via cavities 121 may have tapered sidewalls having a taper angle (relative to the vertical direction) in the range of 1 degree to 10 degrees. The top surface of the fourth metal line structure 648 may be physically exposed at the bottom of each lower electrode contact via cavity 121. The photoresist layer may subsequently be removed, for example, by ashing.

[0115] Reference Figure 3 Subsequently, a continuous metal barrier layer 122L may be formed as a continuous material layer. The continuous metal barrier layer 122L may cover the physically exposed top surface of the fourth metal line structure 648, the tapered sidewalls of the lower electrode contact via cavities 121, and the top surface of the via-level dielectric layer 110 without any holes therethrough. The continuous metal barrier layer 122L may include a conductive metal nitride such as TiN, TaN, and / or WN. Other suitable materials within the disclosed scope may also be used. The thickness of the continuous metal barrier layer 122L may range from 3 nanometers to 20 nanometers, although smaller and larger thicknesses may also be used.

[0116] For example, a metal fill material such as tungsten or copper may be deposited in the remaining volume of the lower electrode contact via cavity 121. A portion of the metal fill material that overlies a horizontal plane of the topmost surface of the continuous metal barrier layer 122L may be removed by a planarization process such as chemical mechanical planarization to form a metal via fill material portion 124. Each metal via fill material portion 124 may have a top surface that is coplanar with the topmost surface of the continuous metal barrier layer 122L.

[0117] Reference Figure 4 , a layer stack including a continuous bottom electrode material layer 126L, a continuous non-magnetic metal buffer layer 128L, a continuous synthetic antiferromagnetic layer 140L, a continuous non-magnetic tunneling barrier layer 146L, a continuous free magnetization layer 148L, at least one continuous capping layer 158L, and a continuous top electrode material layer 160L may be formed over the continuous metal barrier layer 122L and the metal via fill material portion 124. The layers within the layer stack may be deposited by respective chemical vapor deposition processes or respective physical vapor deposition processes. Each layer within the layer stack may be deposited as a planar blanket material layer that always has a respective uniform thickness.

[0118] The continuous bottom electrode material layer 126L includes at least one metal material such as TiN, TaN, WN, W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, alloys thereof, and / or combinations thereof. Other suitable materials within the disclosed covered ranges may also be used. For example, the continuous bottom electrode material layer 126L may include tungsten (W) and / or may consist primarily of tungsten (W). The thickness of the continuous bottom electrode material layer 126L may be in the range of 10 nanometers to 100 nanometers, although smaller and larger thicknesses may also be used.

[0119] The continuous non-magnetic metal buffer layer 128L includes a non-magnetic material that may act as a seed layer. Specifically, the continuous non-magnetic metal buffer layer 128L may provide a template crystal structure that aligns the polycrystalline grains of the material of the continuous synthetic antiferromagnetic layer 140L along a direction that maximizes the magnetization of the reference layers within the continuous synthetic antiferromagnetic layer 140L. The continuous non-magnetic metal buffer layer 128L may include Ti, a CoFeB alloy, a NiFe alloy, ruthenium, or combinations thereof. The thickness of the continuous non-magnetic metal buffer layer 128L may be in the range of 3 nanometers to 30 nanometers, although smaller and larger thicknesses may also be used.

[0120] The continuous synthetic antiferromagnet (SAF) layer 140L may include a layer stack of a continuous ferromagnetic hard layer 141L, a continuous antiferromagnetic coupling layer 142L, and a continuous reference magnetization layer 143L. Each of the continuous ferromagnetic hard layer 141L and the continuous reference magnetization layer 143L may have a corresponding fixed magnetization direction. The continuous antiferromagnetic coupling layer 142L provides antiferromagnetic coupling between the magnetization of the continuous ferromagnetic hard layer 141L and the magnetization of the continuous reference magnetization layer 143L such that the magnetization directions of the continuous ferromagnetic hard layer 141L and the continuous reference magnetization layer 143L remain fixed during the operation of the memory cells to be formed subsequently. The continuous ferromagnetic hard layer 141L may include a hard ferromagnetic material such as PtMn, IrMn, RhMn, FeMn, OsMn, etc. The continuous reference magnetization layer 143L may include a hard ferromagnetic material such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the disclosed covered ranges may also be used. The continuous antiferromagnetic coupling layer 142L may include ruthenium or iridium. The thickness of the continuous antiferromagnetic coupling layer 142L may be selected such that the exchange interaction caused by the continuous antiferromagnetic coupling layer 142L stabilizes the relative magnetization directions of the continuous ferromagnetic hard layer 141L and the continuous reference magnetization layer 143L in opposite directions, i.e., in an antiparallel alignment. In one embodiment, the net magnetization of the continuous SAF layer 140L may be minimized by matching the magnitude of the magnetization of the continuous ferromagnetic hard layer 141L with the magnitude of the magnetization of the continuous reference magnetization layer 143L. The thickness of the continuous SAF layer 140L may range from 5 nanometers to 30 nanometers, but smaller and larger thicknesses may also be used. Each of the continuous reference magnetization layer 143L, the continuous antiferromagnetic coupling layer 142L, the continuous ferromagnetic hard layer 141L, the continuous bottom electrode material layer 126L, the metal via filling material portion 124, and the continuous metal barrier layer 122L may always have a corresponding uniform thickness.

[0121] The continuous non-magnetic tunnel barrier layer 146L may include a tunneling barrier material, which may be an electrically insulating material having a thickness that allows electron tunneling. For example, the continuous non-magnetic tunnel barrier layer 146L may include magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2), or zirconium oxide (ZrO2). Other suitable materials within the disclosed covered ranges may also be used. The thickness of the continuous non-magnetic tunnel barrier layer 146L may be from 0.7 nanometers to 1.3 nanometers, but smaller and larger thicknesses may also be used.

[0122] The continuous free magnetization layer 148L comprises a ferromagnetic material having two stable magnetization directions, the two stable magnetization directions being parallel or antiparallel to the magnetization direction of the continuous reference magnetization layer 143L. The continuous free magnetization layer 148L comprises a hard ferromagnetic material such as Co, CoFe, CoFeB, CoFeTa, NiFe, CoPt, CoFeNi, etc. Other suitable materials within the disclosed scope may also be used. The thickness of the continuous free magnetization layer 148L may range from 1 nanometer to 6 nanometers, but smaller and larger thicknesses may also be used.

[0123] At least one continuous capping layer 158L comprises at least one capping material. Exemplary capping materials that can be used for at least one continuous capping layer 158L include (but are not limited to) metallic materials such as Be, Mg, Al, Ti, Ta, W, Ge, Pt, Ru, Cu, their alloys, and their layer stacks. Other suitable materials within the disclosed scope may also be used. Additionally or alternatively, at least one continuous capping layer 158L may comprise a conductive metal nitride. The total thickness of at least one continuous capping layer 158L may range from 0.5 nanometer to 5 nanometers, but smaller and larger thicknesses may also be used.

[0124] The continuous top electrode material layer 160L comprises at least one metallic material such as W, Cu, Al, Ti, Ta, Ru, Co, Mo, Pt, their alloys, and / or their combinations. Other suitable materials within the disclosed scope may also be used. In one embodiment, the continuous top electrode material layer 160L comprises elemental metal. For example, the continuous top electrode material layer 160L may comprise tungsten (W) and / or may consist mainly of tungsten (W). The thickness of the continuous top electrode material layer 160L may range from 30 nanometers to 120 nanometers, but smaller and larger thicknesses may also be used.

[0125] The continuous dielectric cushion layer 166L comprises a dielectric cushion material such as silicon oxide, silicon nitride, or a dielectric metal oxide. For example, the continuous dielectric cushion layer 166L may comprise silicon oxide and / or may consist mainly of silicon oxide. The thickness of the continuous dielectric cushion layer 166L may range from 5 nanometers to 20 nanometers, but smaller and larger thicknesses may also be used.

[0126] The hard mask material layer 168L can be deposited over the continuous dielectric liner layer 166L. The hard mask material layer 168L includes a hard mask material that can be a metal material or a dielectric material. In one embodiment, the hard mask material layer 168L includes at least one metal nitride material such as, for example, TiN, TaN, and / or WN and / or consists essentially of the at least one metal nitride material. In one embodiment, the hard mask material layer 168L consists essentially of a single metal nitride material selected from TiN, TaN, and WN. The thickness of the hard mask material layer 168L can range from 40 nanometers to 160 nanometers, such as from 60 nanometers to 120 nanometers, although smaller and larger thicknesses can also be used.

[0127] Reference Figure 5 , a photoresist layer (not shown) can be applied over the hard mask material layer 168L and can be patterned lithographically to form discrete patterned photoresist material portions that are laterally spaced apart from each other. An anisotropic etching process can be performed to etch the unmasked portions of the hard mask material layer 168L using the discrete patterned photoresist material portions as an etch mask. The continuous dielectric liner layer 166L can be used as an etch stop layer for the anisotropic etching process. Each patterned portion of the hard mask material layer 168L includes a hard mask portion 168.

[0128] The hard mask portion 168 can be formed over a respective one of the metal via fill material portions 124. In one embodiment, each of the hard mask portions 168 can have an area that overlaps with a respective one of the metal via fill material portions 124. In one embodiment, the hard mask portions 168 and the metal via fill material portions 124 can be formed as a two-dimensional periodic array having the same two-dimensional periodicity. Each hard mask portion 168 can have a horizontal cross-sectional shape that is circular, oval, ovoid, a rounded polygon (i.e., a shape obtained from a polygon by rounding the corners), a polygon, or a two-dimensional shape having a closed perimeter. The maximum lateral dimension (e.g., the diameter of the bottom surface) of each hard mask portion 168 can range from 20 nanometers to 120 nanometers, such as from 30 nanometers to 90 nanometers, although smaller and larger maximum lateral dimensions can also be used. The sidewalls of the hard mask portion 168 can taper at a taper angle in the range of 1 degree to 5 degrees (such as in the range of 2 degrees to 4 degrees) relative to the vertical direction. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0129] Reference Figure 6, an anisotropic etching process can be performed to transfer the pattern in the hard mask portion 168 through the continuous dielectric liner layer 166L and the continuous top electrode material layer 160L. The unmasked portions of the continuous dielectric liner layer 166L and the top electrode material layer 160L are etched by the anisotropic etching process. At least one continuous capping layer 158L can be used as an etch stop layer. Each patterned portion of the continuous dielectric liner layer 166L includes a dielectric liner 166. Each patterned portion of the continuous top electrode material layer 160L includes a top electrode 160. Each top electrode 160 can have a horizontal cross-sectional shape that is substantially the same as or laterally extends from the shape of the bottom surface of the overlying hard mask portion 168. The maximum lateral dimension of the top electrode 160 (e.g., the diameter of the bottom surface) can be in the range of 20 nanometers to 125 nanometers, such as in the range of 30 nanometers to 95 nanometers, but smaller and larger maximum lateral dimensions can also be used. The sidewalls of the top electrode 160 can taper at a taper angle in the range of 1 degree to 5 degrees (e.g., in the range of 2 degrees to 4 degrees) relative to the vertical direction.

[0130] A pillar stack (pillar stack 160, pillar stack 166, pillar stack 168) including the top electrode 160, the dielectric liner 166, and the hard mask portion 168 can be formed over at least one continuous capping layer 158L. The pillar stack (pillar stack 160, pillar stack 166, pillar stack 168) can be formed as a two-dimensional array that can be a two-dimensional periodic array. The pillar stacks (pillar stack 160, pillar stack 166, pillar stack 168) can be laterally spaced apart from each other and can be formed over a layer stack including a continuous reference magnetization layer 143L, a continuous non-magnetic tunnel barrier layer 146L, and a continuous free magnetization layer 148L. In one embodiment, the anisotropic etching process can redeposit the metal material etched away from the hard mask portion 168 onto the sidewalls of the top electrode 160. Because at least one continuous capping layer 158L overlies the continuous non-magnetic tunnel barrier layer 146L, this redeposited metal material on the sidewalls of the top electrode 160 does not cause any harmful effects.

[0131] Reference Figure 7, a continuous dielectric liner 161L can be formed over the pillar stacks (pillar stack 160, pillar stack 166, pillar stack 168) and at least one continuous capping layer 158L. The continuous dielectric liner 161L comprises a dielectric material such as silicon oxide, silicon nitride, silicon carbonitride (SiCN), or a dielectric metal oxide (e.g., aluminum oxide of hafnium oxide). The continuous dielectric liner 161L can be deposited by a conformal deposition process such as atomic layer deposition (ALD) or chemical vapor deposition (e.g., low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition with high conformal coverage). The thickness of the continuous dielectric layer 161L as measured on the sidewalls of the pillar stacks (pillar stack 160, pillar stack 166, pillar stack 168) can be in the range of 2 nanometers to 20 nanometers, e.g., in the range of 3 nanometers to 10 nanometers, but smaller and larger thicknesses can also be used.

[0132] Reference Figure 8 , an anisotropic etching process can be performed to etch the horizontal portions of the continuous dielectric liner 161L. The anisotropic etching process can be or can not be selective to the material of at least one continuous capping layer 158L. Each remaining vertical extending portion of the continuous dielectric liner 161L constitutes a dielectric spacer called an inner dielectric spacer 161 herein. Each inner dielectric spacer 161 laterally surrounds and contacts a corresponding top electrode 160, and overlies a layer stack containing a continuous reference magnetization layer 143L, a continuous non-magnetic tunnel barrier layer 146L, and a continuous free magnetization layer 148L. In one embodiment, each inner dielectric spacer 161 can have a variable width that severely decreases with the vertical distance from the horizontal plane of the bottom surface containing the top electrode 160. In one embodiment, the outer sidewall of the inner dielectric spacer 161 can have a taper angle greater than the taper angle of the inner sidewall of the inner dielectric spacer 161 with respect to the vertical direction. For example, the outer sidewall of the inner dielectric spacer 161 can have a taper angle in the range of 2 degrees to 10 degrees (e.g., in the range of 3 degrees to 6 degrees), and the inner sidewall of the inner dielectric spacer 161 can have a taper angle in the range of 1 degree to 5 degrees (e.g., in the range of 2 degrees to 4 degrees). In one embodiment, the distance between the inner perimeter and the outer perimeter of the bottom surface of each inner dielectric spacer 161 can be uniform. The thickness of the bottommost portion of each inner dielectric spacer 161 can be in the range of 2 nanometers to 20 nanometers, e.g., in the range of 3 nanometers to 10 nanometers, but smaller and larger thicknesses can also be used.

[0133] Reference Figure 9, another anisotropic etching process may be performed to etch the unmasked portions of at least one continuous top cap layer 158L, continuous free magnetization layer 148L, continuous non-magnetic tunnel barrier layer 146L, and continuous synthetic antiferromagnetic layer 140L. As discussed above, the continuous synthetic antiferromagnetic layer 140L may include a layer stack of a continuous ferromagnetic hard layer 141L, a continuous antiferromagnetic coupling layer 142L, and a continuous reference magnetization layer 143L. The hard mask portion 168 and the inner dielectric spacer 161 may be used together as an etch mask layer for the anisotropic etching process. The continuous non-magnetic metal buffer layer 128L may be used as an etch stop layer.

[0134] An array of discrete vertical stacks of synthetic antiferromagnetic structures 140, non-magnetic tunnel barriers 146, free magnetization structures 148, and at least one top cap structure 158 may be formed over the continuous non-magnetic metal buffer layer 128L. Each synthetic antiferromagnetic structure 140 may be a patterned portion of the continuous synthetic antiferromagnetic layer 140L. Each non-magnetic tunnel barrier 146 may be a patterned portion of the continuous non-magnetic tunnel barrier layer 146L. Each free magnetization structure 148 may be a patterned portion of the continuous free magnetization layer 148L. Each at least one top cap structure 158 may be a patterned portion of at least one continuous top cap layer 158L. Each synthetic antiferromagnetic structure 140 may include a layer stack of a ferromagnetic hard mask 141, an antiferromagnetic coupling structure 142, and a reference magnetization structure 143. A vertical stack including a corresponding ferromagnetic hard mask 141, a corresponding antiferromagnetic coupling structure 142, a corresponding reference magnetization structure 143, a corresponding non-magnetic tunnel barrier 146, a corresponding free magnetization structure 148, and a corresponding at least one top cap structure 158 may be formed. Each vertical stack (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158) may include a corresponding magnetic tunnel junction.

[0135] Each of the vertical stacks (vertical stacks 141, 142, 143, 146, 148, 158) may have a top perimeter that coincides with the outer bottom perimeter of a corresponding one of the inner dielectric spacers 161. At least one top cap structure 158 within the vertical stacks (vertical stacks 141, 142, 143, 146, 148, 158) may include a non-magnetic conductive material and may contact the bottom surface of the overlying top electrode 160. The central portion of the free magnetization structure 148 within the vertical stacks (vertical stacks 141, 142, 143, 146, 148, 158) that are underlain by the top electrode 160. The peripheral portion of the free magnetization structure 148 within the vertical stacks (vertical stacks 141, 142, 143, 146, 148, 158) that are underlain by each inner dielectric spacer 161 and laterally surrounds the corresponding top electrode 160. Each inner dielectric spacer 161 may include a tapered outer sidewall having a cone angle in the range of 2 degrees to 10 degrees with respect to the vertical direction.

[0136] In one embodiment, the bottom perimeter of the tapered outer sidewall of each inner dielectric spacer 161 may vertically coincide with the outer sidewall of the corresponding underlying vertical stack (vertical stacks 141, 142, 143, 146, 148, 158). In other words, the bottom perimeter of the tapered outer sidewall of each inner dielectric spacer 161 and the outer sidewall of the corresponding underlying vertical stack (vertical stacks 141, 142, 143, 146, 148, 158) may be positioned in the same plane having a cone angle of less than 10 degrees. In one embodiment, the bottom perimeter of the tapered outer sidewall of each inner dielectric spacer 161 may vertically coincide with the top perimeter of at least one top cap structure 158 within the corresponding underlying vertical stack (vertical stacks 141, 142, 143, 146, 148, 158).

[0137] In one embodiment, the reference magnetization structure 143, the non-magnetic tunnel barrier 146, and the free magnetization structure 148 may include sidewalls that are fully located within a common tapered plane TP, which has a straight profile in a vertical cross-sectional view and a closed two-dimensional shape in a horizontal cross-sectional view. The common tapered plane TP may be a conical plane, an ellipsoidal conical plane, or a generally continuous plane with curvature and a cone angle such that the surfaces of the sidewalls of each layer within the vertical stack (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158) are fully contained within the common tapered plane TP. The horizontal cross-sectional shape of the common tapered plane TP coincides with the horizontal cross-sectional shapes of the various layers within the vertical stack (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158).

[0138] Reference Figure 10 , at least one dielectric spacer material layer may be conformally deposited over an array of discrete vertical stacks (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158), over the top electrode 160, over the hard mask portion 168, and over the physically exposed portions of the top surface of the continuous non-magnetic metal buffer layer 128L. For example, a first dielectric spacer material layer comprising a first dielectric spacer material and a second dielectric spacer material layer comprising a second dielectric spacer material may be sequentially deposited using a respective conformal deposition process (e.g., a chemical vapor deposition process). For example, the first dielectric spacer material may include silicon nitride or a dielectric metal oxide (e.g., aluminum oxide), and the second dielectric spacer material may include silicon oxide (e.g., TEOS oxide). The thickness of the first dielectric spacer material layer may be in the range of 3 nanometers to 20 nanometers, and the thickness of the second dielectric spacer material layer may be in the range of 20 nanometers to 100 nanometers, although each of the first dielectric spacer material layer and the second dielectric spacer material layer may use smaller and larger thicknesses.

[0139] An anisotropic etching process may be performed to remove horizontal portions of at least one dielectric spacer material layer. The anisotropic etching process for etching the first dielectric spacer material and the second dielectric spacer material may be selective to the material of the continuous non-magnetic metal buffer layer 128L. Each remaining portion of the first dielectric spacer material layer constitutes a first dielectric spacer 162, and each remaining portion of the second dielectric spacer material layer constitutes a second dielectric spacer 164. Each set of the first dielectric spacer 162 and the second dielectric spacer 164 constitutes an outer dielectric spacer (outer dielectric spacers 162, outer dielectric spacers 164). Generally, an array of outer dielectric spacers (outer dielectric spacers 162, outer dielectric spacers 164) may be formed around and on an array of discrete vertical stacks (vertical stacks 141, vertical stacks 142, vertical stacks 143, vertical stacks 146, vertical stacks 148, vertical stacks 158) and an array of inner dielectric spacers 161. In one embodiment, each discrete vertical stack (vertical stacks 141, vertical stacks 142, vertical stacks 143, vertical stacks 146, vertical stacks 148, vertical stacks 158) may be laterally surrounded by the first dielectric spacer 162 and the second dielectric spacer 164. In another embodiment, the first dielectric spacer 162 may be omitted. In such an embodiment, each discrete vertical stack (vertical stacks 141, vertical stacks 142, vertical stacks 143, vertical stacks 146, vertical stacks 148, vertical stacks 158) may be laterally surrounded by a single dielectric spacer (i.e., the second dielectric spacer 164 that constitutes the entire outer dielectric spacer). In one embodiment, the distance between the inner perimeter and the outer perimeter of the bottom surface of each outer dielectric spacer (outer dielectric spacers 162, outer dielectric spacers 164) may always be uniform.

[0140] Reference Figure 11, an etching process can be performed to pattern the continuous non-magnetic metal buffer layer 128L, the continuous bottom electrode material layer 126L, and the continuous metal barrier layer 122L by performing an anisotropic etching process. External dielectric spacers (external dielectric spacers 162, external dielectric spacers 164) and the hard mask portion 168 can be used as etching masks to anisotropically etch the continuous non-magnetic metal buffer layer 128L, the continuous bottom electrode material layer 126L, and the continuous metal barrier layer 122L. The portions of the continuous metal barrier layer 122L, the continuous bottom electrode material layer 126L, and the continuous non-magnetic metal buffer layer 128L that are not shielded by the external dielectric spacers (external dielectric spacers 162, external dielectric spacers 164) and the top electrode 160 can be removed by the etching process. The etching process can be selective to the material of the via-level dielectric layer 110. The etching process can include an anisotropic etching process (e.g., a reactive ion etching process) and / or an isotropic etching process (e.g., a wet etching process). If the top electrode 160 includes a material different from the materials of the continuous metal barrier layer 122L, the continuous bottom electrode material layer 126L, and the continuous non-magnetic metal buffer layer 128L, then the etching process can be selective to the material of the top electrode 160 (i.e., the material of the top electrode 160 is not significantly etched).

[0141] Each patterned portion of the continuous non-magnetic metal buffer layer 128L constitutes the non-magnetic metal buffer layer 128. Each patterned portion of the continuous bottom electrode material layer 126L constitutes the bottom electrode 126. Each patterned portion of the continuous metal barrier layer 122L constitutes the metal barrier 122. Each vertical stack of the non-magnetic metal buffer layer 128, the bottom electrode 126, and the metal barrier 122 can have vertically coincident sidewalls, and the sidewalls can be positioned in the same vertical plane. Each continuous combination of the top electrode 160, the discrete vertical stacks (vertical stacks 141, vertical stacks 142, vertical stacks 143, vertical stacks 146, vertical stacks 148, vertical stacks 158), the non-magnetic metal buffer layer 128 (which is an optional component), and the bottom electrode 126 constitutes the memory cell 101, and the memory cell 101 is a magnetoresistive memory cell. Each combination of the metal barrier 122 and the metal via fill material portion 124 constitutes a bottom electrode connection via structure (bottom electrode connection via structures 122, bottom electrode connection via structures 124), and the bottom electrode connection via structure (bottom electrode connection via structures 122, bottom electrode connection via structures 124) provides an electrical connection between the corresponding bottom electrode 126 and the corresponding fourth metal wire structure 648.

[0142] Typically, an array of bottom electrode connection via structures (bottom electrode connection via structures 122, 124) may be formed on a corresponding one of the underlying metal interconnect structures. An array of memory cells 101 may be formed on the array of bottom electrode connection via structures (bottom electrode connection via structures 122, 124). The array of memory cells 101 may be formed over a semiconductor substrate 9 in a memory array region 100. Each of the memory cells 101 may include a vertical stack including a bottom electrode 126, a memory element (such as a magnetic tunnel junction (magnetic tunnel junctions 143, 146, 148)), and a top electrode 160. Each magnetic tunnel junction (magnetic tunnel junctions 143, 146, 148) may include a vertical stack of a reference magnetization structure 143, a non-magnetic tunnel barrier 146, and a free magnetization structure 148.

[0143] In an alternative embodiment, patterning of a continuous non-magnetic metal buffer layer 128L, a continuous bottom electrode material layer 126L, and a continuous metal barrier layer 122L may be performed after forming an array of discrete vertical stacks (vertical stacks 141, 142, 143, 146, 148, 158) and before forming an array of outer dielectric spacers (outer dielectric spacers 162, 164). In this case, the outer dielectric spacers (outer dielectric spacers 162, 164) may be formed on sidewalls of the non-magnetic metal buffer layer 128, the bottom electrode 126, and the metal barrier 122.

[0144] In one embodiment, the non-magnetic metal buffer layer 128 may be positioned between an underlying bottom electrode 126 and an overlying vertical stack (vertical stacks 141, 142, 143, 146, 148, 158). The outer bottom perimeter of the outer dielectric spacers (outer dielectric spacers 162, 164) may coincide with the perimeter of the top surface of the non-magnetic metal buffer layer 128. Each of the reference magnetization structures 143 may be electrically connected through a subset of metal interconnect structures (metal interconnect structures 612, 618, 622, 628, 632, 638, 642, 648) to a corresponding one of the nodes of a field effect transistor positioned on the semiconductor substrate 9.

[0145] Reference Figure 12, an etch stop dielectric layer 170 and an optional silicon oxide liner layer 172 may be sequentially formed by corresponding deposition processes. The etch stop dielectric layer 170 may comprise a dielectric material, which may be used as a planarization stop material during a chemical mechanical planarization process. The etch stop dielectric layer 170 may then be used as an etch stop material during an anisotropic etching process. The etch stop dielectric layer 170 may comprise a non-reactive dielectric hard mask material. For example, the etch stop dielectric layer 170 may comprise and / or may consist primarily of aluminum oxide (Al2O3), aluminum nitride (AlN), hafnium oxide (HfO2), zirconium oxide (ZrO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), or a nitrogen-free antireflection layer (NFARL) comprising a nitrogen-free inorganic polymer material. Other suitable materials within the disclosed scope may also be used. The etch stop dielectric layer 170 may be deposited by plasma-enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), or atmospheric pressure chemical vapor deposition (APCVD). The etch stop dielectric layer 170 may be deposited conformally or non-conformally.

[0146] The etch stop dielectric layer 170 may be formed over and on an array of outer dielectric spacers (outer dielectric spacer 162, outer dielectric spacer 164), and over an array of memory cells 101. The etch stop dielectric layer 170 may include: a horizontally extending portion that continuously extends through the memory array region 100 and into the logic region 200; and an array of vertically protruding portions that laterally surround each memory cell 101 in the array of memory cells 101. The thickness of the horizontally extending portion of the etch stop dielectric layer 170 in the logic region 200 or above the top surface of the top electrode 160 may be in the range of 5 nanometers to 50 nanometers, although smaller and larger thicknesses may also be used.

[0147] Optional silicon oxide liner layer 172 (if present) may include SiC, SiO2, SiN, or SiON. In one embodiment, the silicon oxide liner layer 172 includes a non-porous silicon oxide material, such as TEOS oxide material formed by plasma enhanced chemical vapor deposition (PECVD). The silicon oxide liner layer 172 may include undoped silicate glass or doped silicate glass. The silicon oxide liner layer 172 may be formed by a conformal or non-conformal deposition process. The thickness of the horizontal portion of the silicon oxide liner layer 172 positioned in the logic region 200 or above the top surface of the top electrode 160 may range from 5 nanometers to 50 nanometers, although smaller and larger thicknesses may also be used.

[0148] The first dielectric matrix layer 176 may be formed over the silicon oxide liner layer 172 and the etch stop dielectric layer 170. The first dielectric matrix layer 176 may be formed by a chemical vapor deposition process. In one embodiment, the first dielectric matrix layer 176 includes a low dielectric constant (low-k) dielectric material having a dielectric constant less than that of thermally grown silicon oxide (i.e., 3.9). In one embodiment, the first dielectric matrix layer 176 includes an extremely-low-k (ELK) dielectric material having a dielectric constant less than 2.5. In one embodiment, the first dielectric matrix layer 176 includes a porous silicon oxide-like dielectric material having a dielectric constant less than 2.5. In this case, the porous silicon oxide-like dielectric material may include a SiCO-like material doped with a pore-forming agent having a porous structure. The porous structure may be formed by incorporating a pore-generating material (pore-forming agent) into a carbon-doped oxide using a chemical vapor deposition process. The chemical vapor deposition process may include a plasma enhanced chemical vapor deposition process (PECVD) or a thermal chemical vapor deposition process. At a wavelength of 632.8 nanometers (which is the wavelength of a commercially available HeNe laser measuring instrument), the refractive index of the ELK dielectric material in the first dielectric matrix layer 176 may range from 1.0 to 1.4.

[0149] Compared with a second portion of the top surface of the first dielectric matrix layer 176 formed in the logic region 200, a first portion of the top surface of the first dielectric matrix layer 176 positioned in the memory array region 100 may have a greater vertical separation distance from the semiconductor substrate 9. In other words, the top surface of the first dielectric matrix layer 176 may be higher in the memory array region 100 than in the logic region 200. The first portion of the top surface of the first dielectric matrix layer 176 may include the topmost portion of the top surface of the first dielectric matrix layer 176. The height difference between the first portion of the top surface of the first dielectric matrix layer 176 positioned in the memory array region 100 and the second portion of the top surface of the first dielectric matrix layer 176 formed in the logic region 200 is attributed to the presence of an array of memory cells 101 and an array of outer dielectric spacers (outer dielectric spacers 162, outer dielectric spacers 164) in the memory array region 100.

[0150] During the deposition of the first dielectric matrix layer 176, the profile of the top surface of the first dielectric matrix layer 176 initially follows the profile of the physically exposed surfaces of the array of memory cells 101 and the array of outer dielectric spacers (outer dielectric spacers 162, outer dielectric spacers 164) in the memory array region 100. When the material portions of the first dielectric matrix layer 176 merge at the intermediate positions between each pair of adjacent outer dielectric spacers (outer dielectric spacers 162, outer dielectric spacers 164), the profile of the top surface of the first dielectric matrix layer 176 gradually flattens and rises as the dielectric material continues to accumulate until the deposition process of the first dielectric matrix layer 176 terminates. In one embodiment, the duration of the deposition process of the first dielectric matrix layer 176 may be selected such that the top surface of the portion of the first dielectric matrix layer 176 in the logic region 200 is in the same horizontal plane as the top surface of the top electrode 160. In other words, the duration of the deposition process of the first dielectric matrix layer 176 may be selected such that the thickness of the first dielectric matrix layer 176 in the logic region 200 is the same as the distance obtained by adding the height of the memory cell 101 and the thickness of the metal barrier 122, then subtracting the thickness of the silicon oxide liner layer 172 in the logic region 200, and then subtracting the thickness of the etch stop dielectric layer 170 in the logic region 200.

[0151] The height difference between the first portion of the top surface of the first dielectric matrix layer 176 located in the memory array region 100 and the second portion of the top surface of the first dielectric matrix layer 176 formed in the logic region 200 can be in the range of 40% to 100%, for example, in the range of 70% to 90%, of the vertical distance between the horizontal plane including the top surface of the via-level dielectric layer 110 and the horizontal plane including the top surface of the top electrode 160. In one embodiment, the first dielectric matrix layer 176 can have a vertical undulation in height in the memory array region 100. In one embodiment, the height difference between the first portion of the top surface of the first dielectric matrix layer 176 located in the memory array region 100 and the second portion of the top surface of the first dielectric matrix layer 176 formed in the logic region 200 can be in the range of 40 nanometers to 400 nanometers, for example, in the range of 80 nanometers to 200 nanometers, although smaller and larger height differences can also be used.

[0152] Reference Figure 13 , the material portion covering the horizontal plane including the top surface of the top electrode 160 can be removed by a planarization process. The planarization process can use a chemical mechanical planarization process. Specifically, portions of the first dielectric matrix layer 176, the optional silicon oxide liner layer 172, the etch stop dielectric layer 170, the hard mask portion 168, and the dielectric liner 166 can be removed during the chemical mechanical planarization process. In one embodiment, the dielectric liner 166 can be used as a termination structure during the planarization process. Optionally, a wet etching process can be used during the planarization process, which etches the material of the hard mask portion 168 without etching the material of the dielectric liner 166. Generally, the entire hard mask portion 168 can be removed above the top electrode 160. The top surface of the top electrode 160 can be physically exposed after the planarization process. The planarized top surface of the first dielectric matrix layer 176 can be coplanar with the top surface of the top electrode 160.

[0153] In one embodiment, each of the inner dielectric spacers 161 can have a physically exposed annular horizontal top surface. Each of the outer dielectric spacers (outer dielectric spacer 162, outer dielectric spacer 164) can have a physically exposed annular horizontal top surface. In one embodiment, the annular top surface of the silicon oxide liner layer 172 and the annular top surface of the etch stop dielectric layer 170 can be physically exposed within the horizontal plane including the top surface of the first dielectric matrix layer 176.

[0154] An array of magnetic tunnel junction (MTJ) memory cells 101 may be formed in a first dielectric matrix layer 176, and dielectric material layers (dielectric material layer 601, dielectric material layer 610, dielectric material layer 620, dielectric material layer 630, dielectric material layer 640) are overlaid on the first dielectric matrix layer 176. Each MTJ memory cell 101 within the array includes: a vertical stack (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158) that includes a reference magnetization structure 143, a non-magnetic tunnel barrier 146, and a free magnetization structure 148, and is positioned above a semiconductor substrate 9; a top electrode 160 that overlies a central portion of the free magnetization structure 148; an inner dielectric spacer 161 that overlies a peripheral portion of the free magnetization structure 148 and laterally surrounds the top electrode 160, and includes a tapered outer sidewall; and outer dielectric spacers (outer dielectric spacer 162, outer dielectric spacer 164) that laterally surround the inner dielectric spacer 161 and the vertical stack (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158), and are laterally surrounded by a dielectric matrix layer such as the first dielectric matrix layer 176.

[0155] In one embodiment, each MTJ memory cell 101 includes a bottom electrode 126 that contacts the bottom surface of the vertical stack (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158) and the annular bottom surface of the outer dielectric spacers (outer dielectric spacer 162, outer dielectric spacer 164). In one embodiment, the inner dielectric spacer 161 of each MTJ memory cell 101 may include a tapered outer sidewall having a cone angle in the range of 2 degrees to 10 degrees relative to the vertical direction. In one embodiment, the bottom perimeter of the tapered outer sidewall of the inner dielectric spacer 161 may be vertically coincident with the outer sidewall of the vertical stack (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158) within each MTJ memory cell 101.

[0156] Reference Figure 14, a second dielectric matrix layer 178 may be deposited over and directly on the physically exposed horizontal surfaces of the remaining portions of the first dielectric matrix layer 176. The second dielectric matrix layer 178 may have the same material composition as the material composition of the first dielectric matrix layer 176, or may have a material composition different from the material composition of the first dielectric matrix layer 176. In one embodiment, the second dielectric matrix layer 178 may comprise, for example, a low dielectric constant (low-k) dielectric material such as an ELK dielectric material having a dielectric constant of less than 2.5. In one embodiment, the second dielectric matrix layer 178 comprises a porous silica-based dielectric material having a dielectric constant of less than 2.5. The thickness of the second dielectric matrix layer 178 may be the same as the target height of the metal cell contact structure to be formed on the top surface of the top electrode 160. For example, the second dielectric matrix layer 178 may have a thickness in the range of 20 nanometers to 160 nanometers (e.g., in the range of 40 nanometers to 80 nanometers), but smaller and larger thicknesses may also be used. In one embodiment, the entire top surface of the second dielectric matrix layer 178 may be positioned in a first horizontal plane, and the entire bottom surface of the second dielectric matrix layer 178 may be positioned in a second horizontal plane. Thus, the entire second dielectric matrix layer 178 may always have a uniform thickness.

[0157] A first photoresist layer (not shown) may be applied over the second dielectric matrix layer 178 and may be patterned lithographically to form an array of openings in the logic region 200. The pattern of the openings in the photoresist layer may be transferred through the second dielectric matrix layer 178, the first dielectric matrix layer 176, the silica liner layer 172, and the etch stop dielectric layer 170. In one embodiment, the etch stop dielectric layer 170 may be used as an etch stop layer for a first etch step of the material for etching the second dielectric matrix layer 178, the first dielectric matrix layer 176, and the silica liner layer 172, and an etch chemistry of the material of the etch stop dielectric layer 170 may be used during a second etch step of an anisotropic etching process. A via cavity 181 is formed under each opening in the photoresist layer. The top surface of the via-level dielectric layer 110 may be physically exposed at the bottom of each via cavity 181. Subsequently, the first photoresist layer may be removed, for example, by ashing.

[0158] Reference Figure 15, A second photoresist layer may be applied over the second dielectric matrix layer 178 and may be patterned lithographically to form line patterns. The regions of the line patterns in the photoresist layer may encompass all regions of the via cavities 181. Thus, when the second photoresist layer is developed, the second photoresist layer may be removed from inside the via cavities 181. An anisotropic etching process may be performed to transfer the line patterns in the second photoresist layer into the underlying material portions. Each via cavity 181 may vertically extend through the via-level dielectric layer 110 and the dielectric capping layer 108 such that the top surface of the corresponding fourth metal line structure 648 may be physically exposed below each via cavity 181. Additionally, portions of the second dielectric matrix layer 178 not masked by the patterned second photoresist layer may be etched through to form line cavities. Integrated line and via cavities 183 may be formed in the logic region 200. Each integrated line and via cavity 183 may include a corresponding line cavity and at least one via cavity adjacent to the bottom surface of the corresponding line cavity. A unit contact cavity 187 corresponding to a respective one of the overlying top electrodes 160 may be formed in the memory array region 100.

[0159] The anisotropic etching processes for forming the unit contact cavities 187 and the integrated line and via cavities 183 may be selective to the material of the etch stop dielectric layer 170. The unit contact cavities 187 may be formed by performing an anisotropic etching process through the second dielectric matrix layer 178 that etches the material of the second dielectric matrix layer 178 without etching the material of the etch stop dielectric layer 170. In one embodiment, the lateral extent of a unit contact cavity 187 (referred to herein as a first unit contact cavity) selected from an array of unit contact cavities 187 may be greater than the lateral extent of the corresponding underlying top electrode 160, i.e., greater than the lateral extent of the top electrode underlying the first unit contact cavity. In one embodiment, multiple unit contact cavities 187 may have respective lateral extents greater than the lateral extent of the corresponding underlying top electrodes 160. In one embodiment, each of the unit contact cavities 187 may have a respective lateral extent greater than the lateral extent of the corresponding underlying top electrode 160.

[0160] In one embodiment, the bottom surface of the line trench within the integrated line and via cavity 183 may be formed below the horizontal interface between the first dielectric matrix layer 176 and the second dielectric matrix layer 178. The vertical protruding portions of the etch stop dielectric layer 170 that laterally surround the memory cells 101 act as etch stop material portions, while the bottom surface of the line trench vertically depresses below the horizontal interface between the first dielectric matrix layer 176 and the second dielectric matrix layer 178.

[0161] Reference Figure 16, at least one conductive material may be deposited in the line and via cavity 183 and in the cell contact cavity 187. The at least one conductive material may include, for example, a metal liner material such as TiN, TaN, or WN and a metal fill material such as W, Cu, Co, Ru, Mo, Al, alloys thereof, and / or layer stacks thereof. Other suitable materials within the disclosed scope may also be used. The excess of the at least one conductive material covering the horizontal plane of the top surface of the second dielectric matrix layer 178 may be removed by a planarization process such as a chemical mechanical polishing process. Each remaining portion of the at least one conductive material filling the integrated line and via cavity 183 constitutes an integrated line and via structure 184. Each remaining portion of the at least one conductive material filling the cell contact cavity 187 constitutes a metal cell contact structure 188. The integrated line and via structure 184, the metal cell contact structure 188, and the bottom electrode connection via structures (bottom electrode connection via structures 122, bottom electrode connection via structures 124) together constitute the memory cell level metal interconnect structure (metal interconnect structures 122, metal interconnect structures 124, metal interconnect structures 184, metal interconnect structures 188), that is, the metal interconnect structure positioned in the memory cell level, and the memory cell level occupies the volume between the horizontal plane including the top surface of the fourth metal line structure 648 and the horizontal plane including the top surfaces of the integrated line and via structure 184 and the metal cell contact structure 188.

[0162] Reference Figure 17 , and then additional dielectric material layers and additional metal interconnect structures may be formed as needed. The combination of the dielectric capping layer 108, the via level dielectric layer 110, the etch stop dielectric layer 170, the silicon oxide liner layer 172, the first dielectric matrix layer 176, and the second dielectric matrix layer 178 together serve as the fifth line and via level dielectric material layer. A sixth line and via level dielectric material layer 660 may be formed above the second dielectric matrix layer 178. A fifth metal via structure 662 may be formed in the lower portion of the sixth line and via level dielectric material layer 660, and a sixth metal line structure 668 is formed in the upper portion of the sixth line and via level dielectric material layer 640. Bonding pads (not shown) may be formed above the additional metal interconnect structures.

[0163] Reference Figure 18, A general method of forming a memory device is provided according to an embodiment of the present disclosure. Referring to step 1810, a pillar stack (pillar stack 160, pillar stack 166, pillar stack 168) including a top electrode 160 and a hard mask portion 168 that are laterally spaced apart from each other may be formed above a layer stack including a continuous reference magnetization layer 143L, a continuous non-magnetic tunnel barrier layer 146L, and a continuous free magnetization layer 148L. Referring to step 1820, an inner dielectric spacer 161 may be formed by depositing a continuous dielectric liner 161L above the pillar stack (pillar stack 160, pillar stack 166, pillar stack 168) and anisotropically etching the continuous dielectric liner 161L. Referring to step 1830, the continuous free magnetization layer 148L, the continuous non-magnetic tunnel barrier layer 146L, and the continuous reference magnetization layer 143L may be anisotropically etched using the inner dielectric spacer 161 and the hard mask portion as an etch mask. A vertical stack (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158) including corresponding reference magnetization structures 143, corresponding non-magnetic tunnel barriers 146, and corresponding free magnetization structures 148 may be formed. Each of the vertical stacks (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158) has a top perimeter that coincides with the outer bottom perimeter of a corresponding one of the inner dielectric spacers 161.

[0164] In one embodiment, it further includes forming an outer dielectric spacer around each combination of the vertical stack and the inner dielectric spacer by depositing and anisotropically etching at least one dielectric material layer.

[0165] In one embodiment, it further includes: forming a continuous bottom electrode material layer above the semiconductor substrate, wherein the continuous reference magnetization layer is formed above the continuous bottom electrode material layer; and forming a bottom electrode by anisotropically etching the continuous bottom electrode material layer using the outer dielectric spacer as an etch mask, wherein the bottom electrode has an upper perimeter that coincides with the outer bottom perimeter of a corresponding one of the outer dielectric spacers.

[0166] In one embodiment, it further includes: depositing a first dielectric matrix layer above the vertical stack and the outer dielectric spacer; planarizing the first dielectric matrix layer, wherein the hard mask portion is removed during the planarization of the first dielectric matrix layer; and forming a second dielectric matrix layer above the planarized top surface of the first dielectric matrix layer.

[0167] In one embodiment, it further includes forming a metal unit contact structure passing through the second dielectric matrix layer on a corresponding one of the top electrodes.

[0168] In one embodiment, it further includes: forming a field effect transistor above the semiconductor substrate; and forming a metal interconnect structure above the field effect transistor, the metal interconnect structure being formed in a dielectric material layer. Wherein: the layer stack is formed above the metal interconnect structure; and each of the reference magnetization layers is electrically connected to a corresponding node of the field effect transistors.

[0169] Referring to all the figures and according to various embodiments of the present disclosure, a magnetic tunnel junction memory device is provided. The magnetic tunnel junction memory device includes: vertical stacks (vertical stacks 141, 142, 143, 146, 148, 158), including a reference magnetization structure 143, a non-magnetic tunnel barrier 146, and a free magnetization structure 148, and positioned above a semiconductor substrate 9; a top electrode 160, covering a central portion of the free magnetization structure 148; and an inner dielectric spacer 161, covering a peripheral portion of the free magnetization structure 148 and laterally surrounding the top electrode 160, and including a tapered outer sidewall having a cone angle in the range of 2 degrees to 10 degrees with respect to the vertical direction.

[0170] In one embodiment, a bottom perimeter of the tapered outer sidewall of the inner dielectric spacer is vertically coincident with an outer sidewall of the vertical stack.

[0171] In one embodiment, it further includes an outer dielectric spacer that laterally surrounds the inner dielectric spacer and the vertical stack.

[0172] In one embodiment, it further includes a bottom electrode below the vertical stack and the outer dielectric spacer.

[0173] In one embodiment, it further includes a non-magnetic metal buffer layer positioned between the bottom electrode and the vertical stack, wherein a bottom perimeter of the outer dielectric spacer coincides with a perimeter of a top surface of the non-magnetic metal buffer layer.

[0174] In one embodiment, it further includes a metal via fill material portion that contacts a bottom surface of the bottom electrode and has a smaller lateral extent than the bottom electrode.

[0175] In one embodiment, the inner dielectric spacer has a variable width that severely decreases with a vertical distance from a horizontal plane including a bottom surface of the top electrode.

[0176] In one embodiment, the vertical stack includes a top cap layer that includes a non-magnetic conductive material and contacts a bottom surface of the top electrode.

[0177] In one embodiment, the reference magnetization structure, the non-magnetic tunnel barrier, and the free magnetization structure include sidewalls that are fully located within a common conical plane that has a straight profile in a vertical cross-sectional view and a closed two-dimensional shape in a horizontal cross-sectional view.

[0178] In one embodiment, further comprising: a field effect transistor positioned on the semiconductor substrate; and a metal interconnect structure formed in a dielectric material layer that overlies the field effect transistor and is beneath the vertical stack, wherein the reference magnetization structure is connected to a node of the field effect transistor by a subset of the metal interconnect structure.

[0179] In one embodiment, further comprising: at least one dielectric matrix layer that laterally surrounds the vertical stack, the top electrode, and the inner dielectric spacer; and a metal cell contact structure formed in an upper portion of the at least one dielectric matrix layer and contacting a top surface of the top electrode.

[0180] According to another embodiment of the present disclosure, a memory device is provided, the memory device including: a field effect transistor positioned on a semiconductor substrate 9; metal interconnect structures (metal interconnect structure 612, metal interconnect structure 618, metal interconnect structure 622, metal interconnect structure 628, metal interconnect structure 632, metal interconnect structure 638, metal interconnect structure 642, metal interconnect structure 648) formed in a dielectric material layer (dielectric material layer 601, dielectric material layer 610, dielectric material layer 620, dielectric material layer 630, dielectric material layer 640) overlying the field effect transistor; and an array of magnetic tunnel junction (MTJ) memory cells 101 formed in a dielectric matrix layer (such as a first dielectric matrix layer 176) overlying the dielectric material layer (dielectric material layer 601, dielectric material layer 610, dielectric material layer 620, dielectric material layer 630, dielectric material layer 640), wherein each MTJ memory cell 101 within the array includes: a vertical stack (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158) including a reference magnetization structure 143, a non-magnetic tunnel barrier 146, and a free magnetization structure 148, and positioned above the semiconductor substrate 9; a top electrode 160 overlying a central portion of the free magnetization structure 148; an inner dielectric spacer 161 overlying a peripheral portion of the free magnetization structure 148 and laterally surrounding the top electrode 160, and including a tapered outer sidewall; and outer dielectric spacers (outer dielectric spacer 162, outer dielectric spacer 164) laterally surrounding the inner dielectric spacer 161 and the vertical stack (vertical stack 141, vertical stack 142, vertical stack 143, vertical stack 146, vertical stack 148, vertical stack 158), and laterally surrounded by the dielectric matrix layer (such as a first dielectric matrix layer 176).

[0181] In one embodiment, each magnetic tunnel junction memory cell includes a bottom electrode contacting a bottom surface of the vertical stack and a circular bottom surface of the outer dielectric spacer.

[0182] In one embodiment, the inner dielectric spacer of each magnetic tunnel junction memory cell includes a tapered outer sidewall having a cone angle in a range of 2 degrees to 10 degrees with respect to the vertical direction; and a bottom perimeter of the tapered outer sidewall of the inner dielectric spacer is vertically coincident with an outer sidewall of the vertical stack within each magnetic tunnel junction memory cell.

[0183] Various embodiments of the present disclosure can be used to provide magnetic tunnel junctions (magnetic tunnel junction 140, magnetic tunnel junction 146, magnetic tunnel junction 148) that can resist electrical short - circuits of the top electrode 160. The inner dielectric spacer 161 prevents the deposition of metal materials that may cause an electrical short - circuit between the magnetic tunnel junctions (magnetic tunnel junction 140, magnetic tunnel junction 146, magnetic tunnel junction 148) and the top electrode 160 by covering the sidewalls of the top electrode 160 during the entire anisotropic etching process for patterning the magnetic tunnel junctions (magnetic tunnel junction 140, magnetic tunnel junction 146, magnetic tunnel junction 148). The magnetic tunnel junctions (magnetic tunnel junction 140, magnetic tunnel junction 146, magnetic tunnel junction 148) can have a higher manufacturing yield and enhanced reliability during use by protecting the top electrode 160 from electrical short - circuits with the inner dielectric spacer 161 during the manufacturing process.

[0184] The foregoing outlines the features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A magnetic tunnel junction memory device, characterized in that Comprising: A vertical stack including a reference magnetization structure, a non-magnetic tunnel barrier, and a free magnetization structure, and positioned above a semiconductor substrate; A top electrode covering a central portion of the free magnetization structure; An inner dielectric spacer covering a peripheral portion of the free magnetization structure and laterally surrounding the top electrode, and including a tapered outer sidewall having a cone angle in the range of 2 degrees to 10 degrees with respect to the vertical direction; An outer dielectric spacer laterally surrounding the inner dielectric spacer and the vertical stack; And A metal unit contact structure contacting a top surface of the top electrode in a horizontal plane including a top surface of a dielectric matrix layer, wherein the metal unit contact structure contacts a top surface of the inner dielectric spacer and a top surface of the outer dielectric spacer, and the top surface of the top electrode, the top surface of the inner dielectric spacer, and the top surface of the outer dielectric spacer are substantially flush.

2. The magnetic tunnel junction memory device according to claim 1, wherein the bottom perimeter of the tapered outer sidewall of the inner dielectric spacer is vertically coincident with the outer sidewall of the vertical stack.

3. The magnetic tunnel junction memory device according to claim 1, further comprising a bottom electrode under the vertical stack and the outer dielectric spacer.

4. The magnetic tunnel junction memory device according to claim 3, further comprising a non-magnetic metal buffer layer positioned between the bottom electrode and the vertical stack, wherein the bottom perimeter of the outer dielectric spacer coincides with the perimeter of the top surface of the non-magnetic metal buffer layer.

5. The magnetic tunnel junction memory device according to claim 3, further comprising a metal via filling material portion that contacts the bottom surface of the bottom electrode and has a smaller lateral extent than the bottom electrode.

6. The magnetic tunnel junction memory device according to claim 1, wherein the inner dielectric spacer has a variable width that severely decreases as the vertical distance from a horizontal plane containing the bottom surface of the top electrode increases.

7. The magnetic tunnel junction memory device according to claim 1, wherein the vertical stack includes a top cap layer that includes a non-magnetic conductive material and contacts the bottom surface of the top electrode.

8. The magnetic tunnel junction memory device according to claim 1, wherein the reference magnetization structure, the non-magnetic tunnel barrier, and the free magnetization structure include sidewalls that are fully positioned within a common tapered plane that has a straight profile in a vertical cross-sectional view and a closed two-dimensional shape in a horizontal cross-sectional view.

9. The magnetic tunnel junction memory device according to claim 1, further comprising: A field effect transistor positioned on the semiconductor substrate; And A metal interconnect structure formed in a dielectric material layer covering the field effect transistor and under the vertical stack, wherein the reference magnetization structure is connected to a node of the field effect transistor through a subset of the metal interconnect structure.

10. The magnetic tunnel junction memory device according to claim 1, wherein the dielectric matrix layer laterally surrounds the vertical stack, the top electrode, and the inner dielectric spacer; and wherein the magnetic tunnel junction memory device further comprises: A metal unit contact structure formed in an upper portion of the dielectric matrix layer and contacting a top surface of the top electrode.

11. A memory device, characterized in that Comprising: A field effect transistor positioned on a semiconductor substrate; A metal interconnect structure formed in a dielectric material layer covering the field effect transistor; And An array of magnetic tunnel junction (MTJ) memory cells formed in a dielectric matrix layer covering the dielectric material layer, wherein each magnetic tunnel junction memory cell in the array comprises: A vertical stack including a reference magnetization structure, a non-magnetic tunnel barrier, and a free magnetization structure, and positioned above a semiconductor substrate; A top electrode covering a central portion of the free magnetization structure; An inner dielectric spacer covering a peripheral portion of the free magnetization structure and laterally surrounding the top electrode, and including a tapered outer sidewall; and An outer dielectric spacer laterally surrounding the inner dielectric spacer and the vertical stack, and laterally surrounded by the dielectric matrix layer, wherein the outer dielectric spacer includes: A first dielectric spacer including an annular horizontally extending portion and a vertically extending portion, the vertically extending portion being adjacent to an inner periphery of the annular horizontally extending portion and contacting a sidewall of the vertical stack and a sidewall of the inner dielectric spacer; and A second dielectric spacer covering an annular top surface of the annular horizontally extending portion of the first dielectric spacer and laterally surrounding the first dielectric spacer, wherein materials of the first dielectric spacer and the second dielectric spacer are different.

12. The memory device according to claim 11, wherein each magnetic tunnel junction memory cell comprises a bottom electrode that contacts the bottom surface of the vertical stack and the annular bottom surface of the outer dielectric spacer.

13. The memory device according to claim 12, wherein: The inner dielectric spacer of each magnetic tunnel junction memory cell includes a tapered outer sidewall having a cone angle in the range of 2 degrees to 10 degrees with respect to the vertical direction; and A bottom periphery of the tapered outer sidewall of the inner dielectric spacer is vertically coincident with an outer sidewall of the vertical stack within each magnetic tunnel junction memory cell.

14. A method of forming a magnetic tunnel junction memory device on a semiconductor substrate, characterized in that Comprising: Form a pillar stack including a top electrode and a hard mask portion, the top electrode being spaced apart from the hard mask portion above a vertical stack containing a continuous reference magnetization layer, a continuous non-magnetic tunnel barrier layer, and a continuous free magnetization layer; Form an inner dielectric spacer by depositing a continuous dielectric liner above the pillar stack and anisotropically etching the continuous dielectric liner; And Use the inner dielectric spacer and the hard mask portion as an etch mask to anisotropically etch the continuous free magnetization layer, the continuous non-magnetic tunnel barrier layer, and the continuous reference magnetization layer, Wherein: Form a vertical stack containing a corresponding reference magnetization structure, a corresponding non-magnetic tunnel barrier, and a corresponding free magnetization structure; and Each of the vertical stacks has a top perimeter that coincides with the outer bottom perimeter of a corresponding one of the inner dielectric spacers, Wherein the method further includes: Forming an outer dielectric spacer that laterally surrounds the inner dielectric spacer and the vertical stack and is laterally surrounded by a dielectric matrix layer; and Forming a metal cell contact structure that contacts the top surface of the top electrode, the top surface of the inner dielectric spacer, and the top surface of the outer dielectric spacer, and the top surfaces of the top electrode, the inner dielectric spacer, and the outer dielectric spacer are substantially flush.

15. The method of forming a magnetic tunnel junction memory device on a semiconductor substrate according to claim 14, further comprising: Form a continuous bottom electrode material layer above the semiconductor substrate, wherein the continuous reference magnetization layer is formed above the continuous bottom electrode material layer; And forming a bottom electrode by anisotropically etching the continuous bottom electrode material layer using the outer dielectric spacer as an etch mask, wherein the bottom electrode has an upper perimeter that coincides with the outer bottom perimeter of a corresponding one of the outer dielectric spacers.

16. The method of forming a magnetic tunnel junction memory device on a semiconductor substrate according to claim 14, further comprising: Form a field effect transistor above the semiconductor substrate; And Form a metal interconnect structure above the field effect transistor, the metal interconnect structure being formed in a dielectric material layer, Wherein: A layer stack is formed above the metal interconnect structure; and Each of the reference magnetization layers is electrically connected to a node of a corresponding one of the field effect transistors.

17. A memory device, comprising: A magnetic tunnel junction memory cell is located in a dielectric matrix layer, the magnetic tunnel junction memory cell including: A vertical stack including a reference magnetization structure, a non-magnetic tunnel barrier, and a free magnetization structure; A top electrode covering a central portion of the free magnetization structure; An inner dielectric spacer covering a peripheral portion of the free magnetization structure and laterally surrounding the top electrode, and including a tapered outer sidewall, the bottom perimeter of the tapered outer sidewall coinciding with the perimeter of the top surface of the free magnetization structure; An outer dielectric spacer laterally surrounding the inner dielectric spacer and the vertical stack and being laterally surrounded by the dielectric matrix layer; And A metal cell contact structure that contacts the top surface of the top electrode, the top surface of the inner dielectric spacer, and the top surface of the outer dielectric spacer, and the top surfaces of the top electrode, the inner dielectric spacer, and the outer dielectric spacer are substantially flush.

18. The memory device according to claim 17, wherein the outer dielectric spacer comprises: A first dielectric spacer including an annular horizontally extending portion and a vertically extending portion, the vertically extending portion being adjacent to the inner circumference of the annular horizontally extending portion and contacting the sidewalls of the vertical stack and the sidewalls of the inner dielectric spacer; and A second dielectric spacer covering the annular top surface of the annular horizontally extending portion of the first dielectric spacer and laterally surrounding the first dielectric spacer.

19. The memory device according to claim 17, wherein: The magnetic tunnel junction memory cell includes a non-magnetic metal buffer contacting the bottom surface of the vertical stack; and The periphery of the top surface of the non-magnetic metal buffer coincides with the periphery of the bottom surface of the outer dielectric spacer.

20. The memory device according to claim 17, further comprising an etch stop dielectric spacer, comprising: A horizontally extending portion located below the dielectric matrix layer; And A vertically extending portion that laterally surrounds the magnetic tunnel junction memory cell, contacts the entire outer sidewall of the outer dielectric spacer, and has an opening above the inner dielectric spacer and the top electrode, wherein the uppermost surface of the vertically extending portion is located in the same horizontal plane as the top surface of the dielectric matrix layer.

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