Clock signal selection circuit, delay chain circuit, and delay locked loop

Abstract

The present invention discloses a clock signal selection circuit, which includes a delay chain circuit and a delay locked loop for the clock selection signal. The above clock signal selection circuit includes a negative edge D flip-flop, a first low-level latch, and a selection unit. The selection unit is used to receive a first clock signal and a second clock signal, and the second clock signal is a delayed signal of the first clock signal. The negative edge D flip-flop has its signal input terminal connected to an external control circuit, its clock control terminal is used to receive an externally input trigger signal, and its signal output terminal is connected to the signal input terminal of the first low-level latch. The clock control terminal of the first low-level latch is used to receive the second clock signal, and its signal output terminal is connected to the selection unit to control the selection unit to output the first clock signal or the second clock signal. The control signal is processed by the negative edge D flip-flop and the first low-level latch to control the operation of the selection unit, avoiding the selection unit from outputting the second clock signal when the second clock signal is at a high level, so as to avoid the generation of glitches.

Description

Technical Field

[0001] The present invention relates to the field of phase-locked loops, and more particularly to a DLL delay-locked loop. Background Art

[0002] In the USB2.0 data recovery design, a DLL delay-locked loop is used to generate five or eight clocks for oversampling data. Taking the DLL delay-locked loop with five clocks as an example, its principle is as follows:

[0003] A five-stage delay chain circuit is used to control the delay of each clock, and a phase detector circuit is used to lock the phase relationship between the last-stage clock (the clock signal output by the tail delay chain circuit) and the input clock (the initial clock signal). The output signal of the phase detector is input to the control circuit to control the delay parameter of each clock.

[0004] However, in the prior art, there are glitches in the clock signals output by each delay chain circuit, which will cause data recovery errors. Summary of the Invention

[0005] In view of the drawback that there are glitches in the clock signals output by the delay chain circuit in the prior art, the present invention provides a clock signal selection circuit (hereinafter simply referred to as the selection circuit), and also proposes a delay chain circuit and a delay-locked loop using the selection circuit.

[0006] To solve the above technical problems, the present invention is solved by the following technical solutions:

[0007] A clock signal selection circuit includes a negative-edge D flip-flop, a first low-level latch, and a selection unit. The selection unit is used to receive a first clock signal and a second clock signal, and the second clock signal is a delayed signal of the first clock signal;

[0008] For the negative-edge D flip-flop, its signal input terminal is connected to an external control circuit, its clock control terminal is used to receive an externally input trigger signal, and its signal output terminal is connected to the signal input terminal of the first low-level latch;

[0009] The clock control terminal of the first low-level latch is used to receive the second clock signal, and its signal output terminal is connected to the selection unit to control the selection unit to output the first clock signal or the second clock signal.

[0010] As an implementable manner, the selection unit includes:

[0011] An inverter, a second low-level latch, and a logic branch;

[0012] The signal output terminal of the first low-level latch is connected to the input terminal of the logic branch;

[0013] The input end of the inverter is connected to the signal output end of the negative-edge D flip-flop, and the output end is connected to the signal input end of the second low-level latch;

[0014] The clock control end of the second low-level latch is used to receive the first clock signal, and the signal output end is connected to the input end of the logic branch;

[0015] The input end of the logic branch is also used to receive the first clock signal and the second clock signal, and its output end is used to output the first clock signal or the second clock signal.

[0016] As an implementable manner, the logic branch includes:

[0017] A first AND gate, whose first input end is connected to the signal output end of the first low-level latch, and the second input end is used to receive the second clock signal;

[0018] A second AND gate, whose first input end is connected to the signal output end of the second low-level latch, and the second input end is used to receive the first clock signal;

[0019] An OR gate, whose first input end is connected to the output end of the first AND gate, the second input end is connected to the output end of the second AND gate, and the output end is used to output the first clock signal or the second clock signal.

[0020] The present invention also provides a delay chain circuit, which includes a plurality of selection circuits connected in series, and also includes delay chains corresponding to the selection circuits one by one;

[0021] The selection circuit is the clock signal selection circuit described in any one of the above;

[0022] For the delay chain, both its input end and output end are connected to the corresponding selection circuit, its input end is used to receive the first clock signal, and the output end is used to output the second clock signal.

[0023] As an implementable manner:

[0024] The number of the delay chains is n;

[0025] The delay chain corresponding to the k-th selection circuit includes 2 n-k delay units, k ≤ n, and k is a positive integer.

[0026] As an implementable manner:

[0027] The delay chain corresponding to the first selection circuit is used as the first delay chain; the input of the first delay chain is the input clock signal of the corresponding delay chain circuit, and the output is the delayed signal output after the input clock signal passes through 2 n-1 delay units.

[0028] The output end of the first delay chain is respectively connected to the clock control ends of the negative-edge D flip-flops in each selection circuit, that is, the delay signal output by the first delay chain is used as the trigger signal for each negative-edge D flip-flop.

[0029] As an implementable embodiment:

[0030] The number of the delay chains is 6.

[0031] A delay-locked loop of the present invention includes a control circuit, a delay circuit, and a phase discrimination circuit. The control circuit is respectively connected to the delay circuit and the phase discrimination circuit, and the delay circuit is connected to the phase discrimination circuit;

[0032] The delay circuit includes a plurality of delay chain circuits connected in series in sequence;

[0033] The delay chain circuit is the delay chain circuit described in any one of the above.

[0034] As an implementable embodiment:

[0035] The delay chain circuit includes a first delay chain circuit, a last delay chain circuit, and a plurality of intermediate delay chain circuits;

[0036] The input of the first delay chain circuit is the input of the delay circuit where it is located, that is, an initial clock signal is input, and the output of the last delay chain circuit is the output of the delay circuit where it is located.

[0037] The last delay chain circuit and any one of the intermediate delay chain circuits are connected to the phase discrimination circuit.

[0038] As an implementable embodiment, the phase discrimination circuit includes:

[0039] A first signal input end, which is used to receive an initial clock signal;

[0040] A second signal input end, which is connected to the output end of the last delay chain circuit;

[0041] A third signal input end, which is connected to the output end of an intermediate delay chain circuit;

[0042] A first phase discrimination unit, which is respectively connected to the first signal input end, the second signal input end, and the control circuit, and is used to output a locking signal to the control circuit;

[0043] A second phase discrimination unit, which is respectively connected to the first signal input end, the second signal input end, and the control circuit, and is used to output a corresponding first feedback signal to the control circuit;

[0044] A third phase discrimination unit, which is respectively connected to the first signal input end, the third signal input end, and the control circuit, and is used to output a corresponding second feedback signal to the control circuit.

[0045] Due to the adoption of the above technical solutions, the present invention has remarkable technical effects:

[0046] In the present invention, through the design of the negative-edge D flip-flop and the first low-level latch, after processing the control signal input by the control circuit, a selection signal with a fixed phase relationship with the corresponding second clock signal is output. That is, the edge change of the selection signal must occur during the period when the second clock signal is at a low level; the selection unit is made to perform clock switching based on the selection signal, so as to avoid the selection unit outputting the second clock signal when the second clock signal is at a high level, thereby avoiding the generation of glitches and effectively reducing the problem of duty cycle distortion.

[0047] The design of the number of delay units in each delay chain of the present invention makes its minimum adjustment unit one delay unit, which is convenient for adjustment;

[0048] The design of the phase discriminator circuit of the present invention enables it to not only identify the phase relationship between the initial clock signal and the clock signal output by the tail delay chain circuit to determine whether the phase-locked loop is locked, but also determine whether it is harmonic locking (which is an error state) by identifying the phase relationship between the initial clock signal and the clock signal output by a pre-specified intermediate delay chain circuit, ensuring that the locked state achieved by the phase-locked loop is a normal locked state. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0050] Figure 1 is a schematic diagram of the module connection of a clock signal selection circuit of the present invention;

[0051] Figure 2 is Figure 1 a schematic diagram of the module connection of the selection unit 130 in

[0052] Figure 3 is a schematic diagram of the module connection of a delay chain circuit 1 of the present invention;

[0053] Figure 4 is a schematic diagram of the circuit connection of a delay chain circuit 1 of the present invention;

[0054] Figure 5 is a schematic diagram of the principle of glitch generation in the output signal of the prior art;

[0055] Figure 6 is Figure 4 a schematic diagram of the principle for the delay chain circuit 1 to resist glitches;

[0056] Figure 7 is a schematic circuit diagram of a delay-locked loop according to the present invention;

[0057] Figure 8 is Figure 7 a schematic circuit diagram of the phase discrimination circuit 3 in

[0058] Figure 9 is Figure 7 a state transition diagram of the control circuit 2 in

[0059] Figure 10 is Figure 7 a schematic diagram of the working process of the control circuit 2 in Specific embodiments

[0060] The present invention will be further described in detail below in conjunction with embodiments. The following embodiments are explanations of the present invention and the present invention is not limited to the following embodiments.

[0061] Embodiment 1: A clock signal selection circuit, as Figure 1 shown, includes a negative-edge D flip-flop 110, a first low-level latch 120, and a selection unit 130. The selection unit 130 is configured to receive a first clock signal and a second clock signal, and the second clock signal is a delayed signal of the first clock signal;

[0062] The negative-edge D flip-flop 110 (also known as a falling-edge D flip-flop), its signal input terminal is connected to the external control circuit 2 to receive the control signal sent by the external control circuit 2, the clock control terminal is configured to receive an externally input trigger signal, and the signal output terminal is connected to the signal input terminal of the first low-level latch 120;

[0063] Referring to Figure 4 , Figure 4 in which DFFNRQ represents the negative-edge D flip-flop 110, the D terminal is the signal input terminal of the negative-edge D flip-flop 110, the clk terminal is the clock control terminal of the negative-edge D flip-flop 110, and the Q terminal is the signal output terminal of the negative-edge D flip-flop 110.

[0064] The clock control terminal of the first low-level latch 120 is configured to receive the second clock signal, and the signal output terminal is connected to the selection unit 130 to control the selection unit 130 to output the first clock signal or the second clock signal.

[0065] Referring to Figure 4 , Figure 4In the figure, LANRQ represents a low-level latch, the D terminal is the signal input terminal of the low-level latch, the clk terminal is the clock control terminal of the low-level latch, and the Q terminal is the signal output terminal of the low-level latch. Figure 4 Among them, the low-level latch connected to the signal output terminal of the negative-edge D flip-flop 110 is the first low-level latch 120.

[0066] Note that in this technical field, high level and low level have specific meanings. In digital logic circuits, low level represents 0 and high level represents 1.

[0067] In the prior art, a clock selection circuit often consists of a flip-flop and a switching switch. Two different clock signals (an initial clock signal and a delayed signal, or two delayed signals with different delays) are input to the switching switch. When the flip-flop detects the rising edge of the initial clock signal, it samples the control signal and controls the switching switch according to the sampling result, so that the switching switch outputs one of the clock signals. However, when the switching switch switches the clock signal, the output signal often has glitches.

[0068] In this embodiment, when the negative-edge D flip-flop 110 detects the falling edge of the trigger signal, it samples the control signal. When the sampling result is high level (i.e., "1"), it outputs a pulse signal and uses this pulse signal as the processing signal. The first low-level latch 120 processes this pulse signal according to the phase of the second clock signal and outputs a selection signal. The edge change of this selection signal must occur during the period when the second clock signal is low level, so as to prevent the selection unit 130 from outputting this clock signal when the second clock signal is high level, thereby avoiding the generation of glitches and reducing the problem of duty cycle distortion at the same time.

[0069] The above selection unit 130 can use a switching switch to output the first clock signal or the second clock signal based on the selection signal output by the first low-level latch 120. For example, when the level of the collected selection signal changes, the switching switch is made to act to switch the output clock signal.

[0070] The above selection unit 130 can also be implemented by a logic circuit. Refer to Figure 2 , in this embodiment, the selection unit 130 includes:

[0071] An inverter 131, a second low-level latch 132, and a logic branch 133;

[0072] The signal output terminal of the first low-level latch 120 is connected to the input terminal of the logic branch 133;

[0073] The input terminal of the inverter 131 is connected to the signal output terminal of the negative-edge D flip-flop 110, and the output terminal is connected to the signal input terminal of the second low-level latch 132;

[0074] The clock control terminal of the second low-level latch 132 is used to receive the first clock signal, and the signal output terminal is connected to the input terminal of the logic branch 133;

[0075] Figure 4 The low-level latch connected to the signal output terminal of the inverter 131 is the second low-level latch 132.

[0076] The input terminal of the logic branch 133 is further used to receive the first clock signal and the second clock signal, and its output terminal is used to output the first clock signal or the second clock signal.

[0077] The logic branch 133 includes:

[0078] A first AND gate, whose first input terminal is connected to the signal output terminal of the first low-level latch 120, and the second input terminal is used to receive the second clock signal;

[0079] A second AND gate, whose first input terminal is connected to the signal output terminal of the second low-level latch 132, and the second input terminal is used to receive the first clock signal;

[0080] An OR gate, whose first input terminal is connected to the output terminal of the first AND gate, the second input terminal is connected to the output terminal of the second AND gate, and the output terminal is used to output the first clock signal or the second clock signal.

[0081] Embodiment 2. A delay chain circuit 1, as Figure 3 shown, includes a plurality of selection circuits 10 connected in series, and further includes delay chains 11 corresponding to the selection circuits 10 one by one;

[0082] The selection circuit 10 is the clock signal selection circuit described in any one of Embodiment 1;

[0083] For the delay chain 11, its input terminal and output terminal are both connected to the corresponding selection circuit 10, its input terminal is used to receive the first clock signal, and the output terminal is used to output the second clock signal.

[0084] Each selection circuit 10 selects whether the corresponding delay chain 11 is connected to the delay chain circuit 1 according to an externally input control signal, so as to control the delay value of the delay chain circuit 1 where it is located;

[0085] Furthermore:

[0086] The number of the delay chains 11 is n;

[0087] The delay chain 11 corresponding to the kth selection circuit 10 contains 2 n-k delay units, k ≤ n, and k is a positive integer.

[0088] Those skilled in the art can select existing and publicly disclosed delay units to form the delay chain 11 according to actual needs. In this embodiment, the design is based on the 22nm process, where n is 6. At this time, there are 6 delay chains 11 in the delay chain circuit 1, and the number of delay units in each delay chain 11 is a power of 2, with a total of 63 delay units. This design can achieve a minimum adjustment unit of 1 for the delay units, that is, the delay value of the delay chain circuit 1 can be adjusted based on the delay value of a single delay unit.

[0089] Furthermore:

[0090] The delay chain 11 corresponding to the first selection circuit 10 is used as the first delay chain 11;

[0091] The output end of the first delay chain 11 is respectively connected to the clock control ends of the negative-edge D flip-flops 110 in each selection circuit 10.

[0092] As can be seen from the above, the clock control end of the negative-edge D flip-flop 110 is used to receive the trigger signal. In the prior art, the trigger signal often uses the input clock signal of the delay chain circuit 1 where it is located. In actual use, those skilled in the art can specify a clock signal as the trigger signal according to actual needs;

[0093] In this embodiment, through the design of the delay chain 11, in the delay chain circuit 1, the delay values of each delay chain 11 are arranged in descending order. The input of the first delay chain 11 is the input clock signal of the delay chain circuit 1 where it is located, and it has the most delay units. Therefore, the phase of the delay signal passing through this delay chain circuit 1 is the latest. Using it as the trigger signal can further reduce the generation of glitches.

[0094] The following will Figure 4 introduce in detail the working principle of the delay chain circuit 1 for anti-glitch and reducing duty cycle distortion;

[0095] The delay chain circuit 1 includes 6 delay chain 11 modules, and each delay chain 11 module includes a connected delay chain 11 and a selection circuit 10;

[0096] Figure 4 In the first delay chain 11 module, the first clock signal is the input clock signal i_clkin, and the second clock signal is clkout31, that is, the delay signal obtained by the input clock signal i_clkin passing through the delay chain 11 with 32 delay units. The clock signal output by this first delay chain 11 module is mx clkout31;

[0097] Figure 4The first clock signal corresponding to the second delay chain 11 module is mx_clkout31, and the second clock signal is clkout47, that is, the input clock signal mx_clkout31 outputs a delayed signal through the delay chain 11 with 16 delay units, and the clock signal output by the second delay chain 11 module is mx_clkout47;

[0098] In the prior art, the input clock signal i_clkin of the delay chain circuit 1 is used as a trigger signal. When the rising edge of the input clock signal i_clkin is detected, the received control signal i_delay_ctrl[0:5] is sampled, and signal switching is performed according to the sampling result;

[0099] From Figure 5 it can be seen that the first delay chain 11 module outputs mx_clkout31 after signal selection based on the control signal i_delay_ctrl[5]. In the next delay stage, a glitch appears in mx_clkout47 output after signal selection by the second delay chain 11 module based on the control signal i_delay_ctrl[4].

[0100] In this embodiment, clkout31 is used as a trigger signal. The negative-edge D flip-flop 110 (DFFNRQ) samples the control signal i_delay_ctrl[0:5], and the processed signal ndff_sel_f_d is output according to the sampling result. The processed signal ndff_sel_f_d and the corresponding second clock signal are input to the low-level latch LANRQ, and the signal output by the low-level latch LANRQ is used as the final selection signal;

[0101] From Figure 6 it can be seen that in this embodiment, the control signal i_delay_ctrl[0:5] is sampled based on the falling edge of clkout31;

[0102] The control signal corresponding to the first delay chain 11 module is i_delay_ctrl[5], the processed signal is ndff_sel5_f_d, and the selection signal is clk2_sel5_f_d. The waveforms of the processed signal and the selection signal are the same. The first clock signal is i_clkin, the second clock signal is clkout31, and the finally output clock signal is mx_clkout31. As Figure 6 shown, the clock signal is switched when the level of clk2_sel5_f_d changes. The second period T2 of mx_clkout31 is lengthened, and the second period T3 is shortened;

[0103] The control signal corresponding to the second delay chain 11 module is i_delay_ctrl[4], the processing signal is ndff_sel4_f_d, the selection signal is clk2_sel4_f_d, the first clock signal is mx_clkout31, the second clock signal is clkout47, and the finally output clock signal is mx_clkout47. As Figure 6 shown, when the level of ndff_sel4_f_d changes to switch the clock signal, it cannot compensate for the second period T3 and is still prone to glitches. However, when clock selection is based on clk2_sel4_f_d, since the edge change of clk2_sel4_f_d occurs during the period when clkout47 is at a low level, it can avoid the generation of glitches and can also elongate the third period T3 to reduce the problem of duty cycle distortion.

[0104] After the remaining 4 delay chain 11 modules perform delay and clock selection in sequence, the third period T3 will continue to be elongated to ensure that the problem of the T3 period being shortened to zero will not occur.

[0105] Embodiment 3: A delay-locked loop, as Figure 7 shown, includes a control circuit 2, a delay circuit, and a phase discrimination circuit 3. The control circuit 2 is respectively connected to the delay circuit and the phase discrimination circuit 3, and the delay circuit is connected to the phase discrimination circuit 3;

[0106] The delay circuit includes a plurality of delay chain circuits 1 connected in series in sequence;

[0107] The delay chain circuit 1 is the delay chain circuit 1 described in any one of Embodiment 2.

[0108] The selection of the number of delay chain circuits 1 is related to the required clock output, the required delay value of a single delay chain circuit 1, and the number of selection circuits 10 in the delay chain circuit 1. When m delay chain circuits 1 are serially cascaded, m clock outputs will be provided, and each delay chain circuit 1 realizes a delay of T / m. The larger the required delay value of each delay chain circuit 1, the more selection circuits 10 are required, and the smaller the required delay value, the fewer selection circuits 10 are required. Therefore, those skilled in the art can set the number of delay chain circuits 1 and the number of selection circuits 10 in each delay chain circuit 1 according to actual needs, and this embodiment does not limit it.

[0109] In this embodiment, the number of delay chain circuits 1 is 5.

[0110] Furthermore:

[0111] When the number of delay chain circuits 1 is greater than or equal to 3, the delay chain circuit 1 includes a first delay chain circuit 1, a last delay chain circuit 1, and a plurality of intermediate delay chain circuits 1;

[0112] The tail delay chain circuit 1 and any one of the intermediate delay chain circuits 1 are connected to the phase discrimination circuit 3.

[0113] In the prior art, the phase discrimination circuit 3 only performs phase comparison based on the initial clock signal and the clock signal output by the tail delay chain circuit 1, and sends the comparison result to the control circuit 2. The control circuit 2 controls the delay values of the respective delay chain circuits 1 according to the comparison result until locking occurs;

[0114] In this embodiment, the clock signal output by a certain intermediate delay chain circuit 1 is additionally sent to the phase discrimination circuit 3, so that the phase discrimination circuit 3 can perform phase comparison between the clock signal output by this intermediate delay chain circuit 1 and the clock signal output by the tail delay chain circuit 1, facilitating the control circuit 2 to identify whether harmonic locking occurs, and continuing to adjust the delay values of the respective delay chain circuits 1 when harmonic locking occurs to achieve true locking.

[0115] Furthermore, the phase discrimination circuit 3 includes:

[0116] A first signal input terminal for receiving the initial clock signal;

[0117] A second signal input terminal connected to the output terminal of the tail delay chain circuit 1;

[0118] A third signal input terminal connected to the output terminal of an intermediate delay chain circuit 1;

[0119] A first phase discrimination unit 31, which is respectively connected to the first signal input terminal, the second signal input terminal and the control circuit 2, and is used for outputting a locking signal to the control circuit 2;

[0120] A second phase discrimination unit 32, which is respectively connected to the first signal input terminal, the second signal input terminal and the control circuit 2, and is used for outputting a corresponding first feedback signal to the control circuit 2;

[0121] A third phase discrimination unit 33, which is respectively connected to the first signal input terminal, the third signal input terminal and the control circuit 2, and is used for outputting a corresponding second feedback signal to the control circuit 2;

[0122] The control circuit 2 is used for receiving the locking signal, the first feedback signal and the second feedback signal, and is also used for outputting corresponding control signals to the respective delay chain circuits 1.

[0123] In view of the situation that the current delay-locked loop cannot identify harmonic locking, and it is difficult to achieve locking in the case of clock jitter resulting in unlocking or repeated locking and unlocking, this embodiment designs the phase discrimination circuit 3;

[0124] In this embodiment, the circuit schematic diagram of the phase discrimination circuit 3 is as Figure 8As shown, it includes a first phase discriminator unit 31, a second phase discriminator unit 32, and a third phase discriminator unit 33. The first phase discriminator unit 31 is an existing phase detector, which is used to perform a locking judgment based on the initial clock signal and the clock signal output by the tail delay chain circuit 1.

[0125] Both the second phase discriminator unit 32 and the third phase discriminator unit 33 adopt positive-edge D flip-flops. The clock control terminals of the second phase discriminator unit 32 and the third phase discriminator unit 33 both receive the initial clock signal. The signal input terminal of the second phase discriminator unit 32 receives the clock signal output by the tail delay chain circuit 1, and the signal input terminal of the third phase discriminator unit 33 receives the clock signal output by a pre-specified intermediate delay chain circuit 1 (in this embodiment, the third delay chain circuit 1 is specified).

[0126] The second phase discriminator unit 32 is used to identify the situation where locking cannot be achieved due to clock jitter. For example, if the output of the first phase discriminator unit 31 remains 0, while the output of the second phase discriminator unit 32 alternates between 0 and 1, it indicates that the DLL is approaching the locked state. Therefore, at this time, it can be directly determined that the DLL is in the locked state, that is, the state machine of the control circuit 2 reaches the locked state.

[0127] The third phase discriminator unit 33 is used to identify whether harmonics occur. When the result output by the first phase discriminator unit 31 is locked, the control circuit 2 determines whether harmonic locking occurs according to the output of the third phase discriminator unit 33, and after harmonic locking occurs, reconfigures the adjustment starting point according to the preset rules, and re-locks the delay values of each delay chain circuit 1 until the PLL where it is located is stably locked.

[0128] Refer to Figure 9 , after the control circuit 2 is started, it enters the initial state CNT_IDLE. After its reset is released, it enters the adjustment state CNT_UPDATE and starts automatic adjustment based on the phase discrimination result; if it is locked, it enters the locked state LOCKED, otherwise it continues to automatically adjust the delay of each delay chain circuit 1; after entering the locked state LOCKED, if it remains stably locked, it will always be in this state. Once unlocked, it enters the waiting for lock state WAIT_LOCKED;

[0129] When the control circuit 2 is in the waiting for lock state, if it is unlocked for a few short cycles due to clock jitter and then re-locked, it enters the locked state LOCKED again. As Figure 7 shown by the signal i_locked_stable_reg in, those skilled in the art can set how many clock cycles to wait according to the actual situation. When entering the waiting for lock state WAIT_LOCKED, after waiting for the preset number of clock cycles, it judges whether it is unlocked. If it is still in the unlocked state, it enters the adjustment state CNT_UPDATE to continue adjusting, otherwise it resumes the locked state LOCKED.

[0130] When the jitter exists all the time, the value of o_clk_locked output by the first phase discriminator unit 31 is always 0, while the value of o_clk_fs output by the second phase discriminator unit 32 alternates between 0 and 1. This phenomenon indicates that the DLL is actually at the locking edge. Therefore, in this embodiment, the control circuit 2 is made to automatically recognize the locking based on the outputs of o_clk_locked and o_clk_fs and stop the adjustment.

[0131] For example, when o_clk_locked is 0, it means that the phase relationship between i_clkin5 and i_clkin0 is outside the range of 6 delay units and is considered unlocked. According to their phase relationship, the adjustment continues. Each time an adjustment is made, the delay value of 5 delay units is increased or decreased (because there is a 5-stage delay chain circuit 1). In theory, it can be locked with one adjustment. However, if there is clock jitter at this time, the phase difference between i_clkin0 and i_clkin5 will be widened (greater than the delay value of 6 delay units). The first phase discriminator unit 31 still considers it unlocked, but in fact, it has reached the locked state at this time. Since the first phase discriminator unit 31 considers it unlocked and continues to adjust, but if the clock is normal in the next cycle, continuing the adjustment will widen the phase relationship between the two again (such as increasing the delay). Continuing the adjustment will require reducing the delay in the next cycle, making the value of o_clk_fs alternate between 0 and 1, and o_clk_locked always being 0, indicating that the current DLL is in a situation of repeatedly increasing and then decreasing the delay but unable to lock. For this situation, the control circuit 2 automatically recognizes the locking and stops the adjustment.

[0132] Refer to Figure 10 , the following details the working process of the delay-locked loop provided in this embodiment:

[0133] STEP1: After power-on, start the automatic adjustment function of the DLL. After starting, enter STEP2;

[0134] The starting method is to configure i_dll_int_start_en as high level.

[0135] Control each delay chain circuit 1 to sequentially increase or decrease the connected delay units one by one;

[0136] That is, if an increase is required, the five-stage delay chain circuit 1 increases by 1 in sequence, that is, every time a clock cycle passes, a certain delay chain circuit 1 increases by 1; if a decrease in delay is required, the five-stage delay chain circuit 1 decreases by 1 in sequence after five clock cycles, so as to ensure that within one clock cycle, only one delay chain circuit 1 adjusts the delay, avoiding the generation of clock glitches.

[0137] STEP2: Determine whether it is locked;

[0138] Determine whether to lock according to o_clk_locked output by the first phase discriminator unit 31, o_clk_fs output by the second phase discriminator unit 32, and o_clk2_fs output by the third phase discriminator unit 33;

[0139] In this case, when o_clk_locked = 1, it represents locking, enter STEP5, otherwise enter STEP3.

[0140] STEP3: Determine whether to unlock;

[0141] That is, determine whether it is unlocked after DLL locking;

[0142] When o_clk_locked output by the first phase discriminator unit 31 = 0 and the state of the control circuit 2 is the locked state, it is determined to be unlocked, and the state of the control circuit 2 is changed to the waiting-to-lock state. At this time, enter STEP4;

[0143] When o_clk_locked output by the first phase discriminator unit 31 = 0 and the state of the control circuit 2 is the adjusting state, it means that the DLL has never been locked. At this time, determine whether it cannot be locked due to clock jitter according to o_clk_fs. If o_clk_fs alternates between 0 and 1, it is determined to be locked, and the state of the control circuit 2 is changed to the locked state, enter STEP8, otherwise continue to enter STEP2 after increasing / decreasing the delay unit.

[0144] STEP4: Wait based on the pre-configured waiting period;

[0145] The pre-configured waiting period i_locked_stable_reg = aT (n = 0 to 255), where T is the period, indicating that after unlocking, wait for a clock cycles and then determine whether to unlock. According to the judgment result, determine whether to adjust the delay value of the delay chain circuit 1 to achieve locking, that is, enter STEP2 after waiting for a clock cycles.

[0146] STEP5: Determine whether it is harmonic locking;

[0147] When o_clk_locked = 1, that is, after determining locking, enter this step. If o_clk2_fs is 1 at this time, it is harmonic locking, enter STEP6, otherwise enter STEP8.

[0148] STEP6: Re-configure the automatic adjustment starting point;

[0149] Under the harmonic locking state, it is necessary to configure the starting point of automatic adjustment, reduce the number of delay units connected in each delay chain circuit 1, and the reconfigured value is 1 / 2 of the initial value, that is, the value of i_delay_ctrl_reg. At the same time, configure i_delay_ctrl_up_en to 1 so that the value of i_delay_ctrl_reg can be updated to the internal control circuit 2, and then enter STEP7.

[0150] STEP7: Start automatic adjustment again;

[0151] Disable i_delay_ctrl_up_en (i_delay_ctrl_up_en = 0), and then enter STEP2 to continue to judge and wait for locking.

[0152] STEP8: The DLL is in a stable locked state.

[0153] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0154] It should be noted that:

[0155] The phrase "an embodiment" or "embodiment" mentioned in the specification means that the specific features, structures or characteristics described in connection with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "an embodiment" or "embodiment" that appear throughout the specification do not necessarily refer to the same embodiment.

[0156] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted to include the preferred embodiments as well as all changes and modifications that fall within the scope of the present invention.

[0157] In addition, it should be noted that for the specific embodiments described in this specification, the shapes, names of the components, etc. can be different. Any equivalent or simple changes made according to the structure, features and principles described in the inventive concept of the present invention are included in the protection scope of the present invention. Those skilled in the art of the present invention can make various modifications or supplements or use similar methods to replace the specific embodiments described, as long as they do not deviate from the structure of the present invention or exceed the scope defined by this claim book, they should fall within the protection scope of the present invention.

Claims

1. A clock signal selection circuit, characterized in that, It includes a negative-edge D flip-flop, a first low-level latch, and a selection unit. The selection unit is used to receive a first clock signal, a second clock signal, and the output signal of the negative-edge D flip-flop. The second clock signal is a delayed signal of the first clock signal; The negative-edge D flip-flop has its signal input terminal connected to an external control circuit. Its clock control terminal is used to receive an externally input trigger signal. Its signal output terminal is connected to the signal input terminal of the first low-level latch, and the signal output terminal is also connected to the selection unit; The clock control terminal of the first low-level latch is used to receive the second clock signal, and its signal output terminal is connected to the selection unit to control the selection unit to output the first clock signal or the second clock signal; Among them, the selection unit includes: An inverter, a second low-level latch, and a logic branch; The signal output terminal of the first low-level latch is connected to the input terminal of the logic branch; The input terminal of the inverter is connected to the signal output terminal of the negative-edge D flip-flop, and the output terminal is connected to the signal input terminal of the second low-level latch; The clock control terminal of the second low-level latch is used to receive the first clock signal, and its signal output terminal is connected to the input terminal of the logic branch; The input terminal of the logic branch is also used to receive the first clock signal and the second clock signal, and its output terminal is used to output the first clock signal or the second clock signal; The logic branch includes: A first AND gate, whose first input terminal is connected to the signal output terminal of the first low-level latch, and the second input terminal is used to receive the second clock signal; A second AND gate, whose first input terminal is connected to the signal output terminal of the second low-level latch, and the second input terminal is used to receive the first clock signal; An OR gate, whose first input terminal is connected to the output terminal of the first AND gate, the second input terminal is connected to the output terminal of the second AND gate, and the output terminal is used to output the first clock signal or the second clock signal.

2. A delay chain circuit, characterized in that, It includes a plurality of selection circuits connected in series, and also includes a delay chain corresponding to each selection circuit; The selection circuit is the clock signal selection circuit described in claim 1; The delay chain, its input terminal and output terminal are both connected to the corresponding selection circuit. Its input terminal is used to receive the first clock signal, and the output terminal is used to output the second clock signal.

3. According to the delay chain circuit described in claim 2, it is characterized in that: The number of the delay chains is n; The delay chain corresponding to the k-th selection circuit includes 2 n-k delay units, where k ≤ n and k is a positive integer.

4. According to the delay chain circuit described in claim 3, it is characterized in that: The delay chain corresponding to the first selection circuit is used as the first delay chain; The output terminal of the first delay chain is respectively connected to the clock control terminals of the negative-edge D flip-flops in each selection circuit.

5. According to the delay chain circuit described in claim 3 or 4, it is characterized in that: The number of the delay chains is 6.

6. A delay-locked loop includes a control circuit, a delay circuit, and a phase detection circuit. The control circuit is respectively connected to the delay circuit and the phase detection circuit, and the delay circuit and the phase detection circuit are connected; It is characterized in that: The delay circuit includes a plurality of delay chain circuits connected in series in sequence; The delay chain circuit is the delay chain circuit described in any one of claims 2 to 5.

7. The delay locked loop according to claim 6, wherein: The delay chain circuit includes a head delay chain circuit, a tail delay chain circuit, and a plurality of intermediate delay chain circuits; The tail delay chain circuit and any one of the intermediate delay chain circuits are connected to the phase discrimination circuit.

8. The delay-locked loop according to claim 7, wherein, The phase discrimination circuit includes: A first signal input terminal for receiving an initial clock signal; A second signal input terminal connected to the output terminal of the tail delay chain circuit; A third signal input terminal connected to the output terminal of an intermediate delay chain circuit, wherein the tail delay chain circuit and the intermediate delay chain circuit refer to when the number of delay chain circuits is greater than or equal to 3, the delay chain circuit includes a head delay chain circuit, a tail delay chain circuit, and a plurality of intermediate delay chain circuits; A first phase discrimination unit respectively connected to the first signal input terminal, the second signal input terminal, and the control circuit, and configured to output a locking signal to the control circuit; A second phase discrimination unit respectively connected to the first signal input terminal, the second signal input terminal, and the control circuit, and configured to output a corresponding first feedback signal to the control circuit; A third phase discrimination unit respectively connected to the first signal input terminal, the third signal input terminal, and the control circuit, and configured to output a corresponding second feedback signal to the control circuit.

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