Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device is provided. The method includes: forming a lower mold having a lower layer stacked on a substrate and a lower channel structure passing through the lower layer; forming an upper mold having an upper layer stacked on the lower mold and an upper channel structure passing through the upper layer; removing the upper mold to expose the upper surface of the lower mold; separating an upper original image showing a trace of the upper channel structure from a lower original image showing the lower channel structure from an original image capturing the upper surface of the lower mold; inputting the upper original image into a learning neural network to obtain an upper restored image showing a cross section of the upper channel structure; and comparing the upper restored image with the lower original image to verify the alignment of the upper and lower molds.

Description

[0001] Priority is claimed on Korean Patent Application No. 10-2020-0007921 filed on January 21, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a method of manufacturing a semiconductor device. Background Art

[0003] Semiconductor devices may include various components formed on a substrate. Recently, to increase the integration density of semiconductor devices, various structures extending in a direction perpendicular to the upper surface of the substrate have been used to implement the components included in the semiconductor devices. As the height of the structures extending in a direction perpendicular to the upper surface of the substrate increases, at least one of the structures may be divided into multiple structures formed through multiple operations. If the multiple structures are not properly aligned, the reliability of the semiconductor device may deteriorate. Summary of the Invention

[0004] Embodiments of the inventive concept provide a method of manufacturing a semiconductor device capable of improving reliability and electrical characteristics of the semiconductor device by accurately predicting an alignment state of structures to be connected to each other in one direction.

[0005] An embodiment of the inventive concept provides a method for manufacturing a semiconductor device, the method comprising: forming a lower mold having a lower layer stacked on a substrate and a lower channel structure passing through the lower layer; forming an upper mold including an upper layer stacked on the lower mold and an upper channel structure passing through the upper layer; removing the upper mold to expose an upper surface of the lower mold; separating an upper original image in which traces of the upper channel structure are displayed and a lower original image in which the lower channel structure is displayed from an original image capturing the upper surface of the lower mold; inputting the upper original image into a neural network to obtain an upper restored image in which a cross-section of the upper channel structure is displayed; and comparing the upper restored image with the lower original image to verify an alignment state of the upper and lower molds.

[0006] An embodiment of the inventive concept also provides a method for manufacturing a semiconductor device, the method comprising: forming a first structure; forming a second structure connected to the first structure in one direction; removing the second structure to expose the first structure; separating a first original image in which the cross-section of the first structure is displayed and a second original image in which the trace of the second structure is displayed from an original image capturing a cross-section of the first structure and a trace of the second structure in the one direction; inputting the second original image into a neural network to obtain a second restored image in which the cross-section of the second structure is displayed; and comparing the first original image with the second restored image to verify an alignment state of the first structure and the second structure.

[0007] An embodiment of the inventive concept also provides a method for manufacturing a semiconductor device, the method including: forming a sample, the sample including a lower mold and an upper mold, the lower mold having a lower layer stacked in a first direction perpendicular to an upper surface of a substrate, the upper mold having an upper layer stacked on the lower mold in the first direction and an upper channel structure passing through the upper layer; removing the upper mold from the sample to expose the upper surface of the lower mold; capturing the upper surface of the lower mold to obtain a sample image; damaging at least a portion of a remaining area corresponding to the upper channel structure in each sample image to generate an input image; inputting the input image into a neural network to obtain an output image having a restored area, in which the remaining area corresponding to the upper channel structure is restored; and teaching the neural network until a discriminator that compares the output image with the sample image determines that the output image is identical to the sample image. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 A block diagram of a semiconductor device according to an embodiment of the inventive concept is shown.

[0010] Figure 2 A structure of a semiconductor device according to an embodiment of the inventive concept is shown.

[0011] Figure 3 A flowchart describing a method of fabricating a semiconductor device according to an embodiment of the inventive concept is shown.

[0012] Figure 4A A verification apparatus used in a method of manufacturing a semiconductor device according to an embodiment of the inventive concept is illustrated.

[0013] Figure 4B A method for manufacturing a semiconductor device according to an embodiment of the inventive concept is shown. Figure 4A The neural network of the Neural Processing Unit (NPU) in the .

[0014] Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 and Figure 12 A view illustrating a method of fabricating a semiconductor device according to an embodiment of the inventive concept is shown.

[0015] Figure 13 、 Figure 14 、 Figure 15 and Figure 16Views illustrating a method of fabricating a semiconductor device according to an embodiment of the inventive concept.

[0016] Figure 17A 、 Figure 17B and Figure 17C A view is shown describing a method of determining an alignment state of a semiconductor device according to an embodiment of the inventive concept.

[0017] Figure 18A 、 Figure 18B and Figure 18C A view is shown describing a method of determining an alignment state of a semiconductor device according to an embodiment of the inventive concept.

[0018] Figure 19 、 Figure 20 and Figure 21 A view illustrating a sample manufacturing method of teaching a neural network in a method of manufacturing a semiconductor device according to an embodiment of the inventive concept is shown.

[0019] Figure 22A 、 Figure 22B and Figure 22C A view illustrating a method of teaching a neural network in a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0020] Figure 23A 、 Figure 23B and Figure 23C A view illustrating a method of teaching a neural network in a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0021] Figure 24A 、 Figure 24B and Figure 24C A view illustrating a method of teaching a neural network in a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0022] Figure 25A 、 Figure 25B and Figure 25C A view illustrating a method of teaching a neural network in a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0023] Figure 26 A flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept is shown.

[0024] Figure 27 An example of a semiconductor device to which the method of manufacturing the semiconductor device according to an embodiment of the inventive concept is applied is shown.

[0025] Figure 28 An example of a semiconductor device to which the method of manufacturing the semiconductor device according to an embodiment of the inventive concept is applied is shown. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0027] As the tradition in the field of inventive concept, embodiment can be described and illustrated according to the block of one or more functions described for execution.These blocks that can be referred to as unit or module etc. here are physically realized by analog and / or digital circuit (such as logic gate, integrated circuit, microprocessor, microcontroller, memory circuit, passive electronic component, active electronic component, optical component, hard wiring circuit etc.), and can be selectively driven by firmware and / or software.Circuit can be for example embodied as one or more semiconductor chips, or be implemented on the substrate support such as printed circuit board etc.The circuit constituting block can be realized by dedicated hardware, or by processor (for example, one or more programmed microprocessors and associated circuit), or by the combination of dedicated hardware of some functions of execution block and the processor of other functions of execution block to realize.Without departing from the scope of inventive concept, each block of embodiment can be physically separated into two or more interactive and discrete blocks.Similarly, without departing from the scope of inventive concept, the block of embodiment can be physically combined into more complicated block.

[0028] Figure 1 A block diagram of a semiconductor device according to an embodiment of the inventive concept is shown.

[0029] First refer to Figure 1 , the memory device 10 may include a memory cell array 20 and a peripheral circuit 30. The peripheral circuit 30 may include a row decoder 31, a voltage generator 32, a page buffer 33, an input / output circuit 34, and control logic (eg, circuit) 35, among other circuits.

[0030] The memory cell array 20 may include a plurality of memory cells and may be divided into a plurality of blocks BLK1, BLK2 to BLKn. The plurality of memory cells may be connected to a row decoder 31 via a string select line SSL, a word line WL, and a ground select line GSL, and may be connected to a page buffer 33 via a bit line BL. In an example, in each of the blocks BLK1 to BLKn, a plurality of memory cells arranged at the same height from the substrate may be connected to the same word line WL, and a plurality of memory cells arranged at the same position in a plane parallel to the upper surface of the substrate may constitute a memory cell string sharing a single channel region. In addition, a portion of the memory cell string included in each of the blocks BLK1 to BLKn may be connected to a single bit line BL.

[0031] The row decoder 31 may decode address data ADDR received from the control logic 35 or the like, and may input a voltage for driving the word line WL to the word line WL. The row decoder 31 may input a word line voltage generated by the voltage generator 32 to the word line WL under the control of the control logic 35. For example, the row decoder 31 may be connected to the word line WL through a pass transistor, and may input the word line voltage to the word line WL when the pass transistor is turned on.

[0032] The page buffer 33 may be connected to the memory cell array 20 via the bit lines BL and may read information stored in the memory cells or write data in the memory cells. The page buffer 33 may include a column decoder and a sense amplifier. The column decoder may select at least a portion of the bit lines BL of the memory cell array 20, and the sense amplifier may read data of the memory cells connected to the bit lines BL selected by the column decoder during a read operation.

[0033] The input / output circuit 34 may receive data DATA during a program operation and transfer the data DATA to the page buffer 33, and may output data DATA read from the memory cell array 20 by the page buffer 33 to the outside or to the control logic 35 during a read operation. The input / output circuit 34 may transfer an address or command received from an external memory controller to the control logic 35.

[0034] The control logic 35 may control the operations of the row decoder 31, the voltage generator 32, the page buffer 33, and various other circuits of the memory device 10. The voltage generator 32 may generate control voltages required for the operation of the memory device 10, such as a program voltage, a read voltage, an erase voltage, a pass voltage, etc., by using an externally input power voltage. The voltage generated by the voltage generator 32 may be supplied to the peripheral circuit 30 and the memory cell array 20.

[0035] Figure 2 A structure of a semiconductor device according to an embodiment of the inventive concept is shown.

[0036] exist Figure 2 In the embodiment shown in FIG, the semiconductor device may be a memory device 100. Referring to FIG. Figure 2 The memory device 100 according to an embodiment of the inventive concept may include a cell region C and a peripheral circuit region P arranged in a vertical direction (z-axis direction). The peripheral circuit region P may be disposed below the cell region C. The peripheral circuit region P may include a first substrate 101, and the cell region C may include a second substrate 102 different from the first substrate 101.

[0037] For example, the peripheral circuit region P may include a plurality of peripheral circuit elements 103 disposed on the first substrate 101, a plurality of wirings 105 connected to the peripheral circuit elements 103, a first interlayer insulating layer 107 covering the peripheral circuit elements 103 and the wirings 105, etc. The peripheral circuit elements 103 included in the peripheral circuit region P may constitute circuits necessary for driving the memory device 100, such as a page buffer, a row decoder circuit, etc., for example.

[0038] The second substrate 102 included in the cell region C may be provided on the first interlayer insulating layer 107. The cell region C may include a gate electrode layer and an insulating layer IL alternately stacked on the second substrate 102, and the gate electrode layer may include a ground selection line GSL, a word line WL, at least one dummy word line DWL, and string selection lines SSL1 and SSL2. The insulating layer IL may be alternately stacked with the ground selection line GSL, the word line WL, the dummy word line, and the string selection lines SSL1 and SSL2. The number of the ground selection lines GSL and the string selection lines SSL1 and SSL2 is not limited to Figure 2 As shown in FIG, various modifications may be made. An interlayer insulating layer 150 may be provided over the gate electrode layer and the insulating layer IL. In addition, the insulating layer IL and the gate electrode layer may be divided into a plurality of blocks by a word line cutting layer 140, and the string selection lines SSL1 and SSL2 may be divided into a plurality of lines by a string selection line cutting layer 160.

[0039] The cell region C may include a channel structure CH extending in a first direction (z-axis direction) perpendicular to the upper surface of the second substrate 102, and the channel structure CH may be connected to the second substrate 102 through the ground selection line GSL, the word line WL, and the string selection lines SSL1 and SSL2. The channel structure CH may include a channel layer 110, an embedded insulating layer 120 filling the inner space of the channel layer 110, a bit line connection layer 130, etc. Each channel structure CH may be connected to at least one bit line through the bit line connection layer 130. In contrast, the dummy channel structure DCH penetrating the string selection line cutting layer 160 may not be connected to a bit line.

[0040] At least one gate insulating layer (not shown) may be provided outside the channel layer 110. In an embodiment, the gate insulating layer may include a tunneling layer, a charge storage layer, a blocking layer, etc. sequentially arranged from the channel layer 110. In an embodiment, at least one of the tunneling layer, the charge storage layer, and the blocking layer may be formed to have a shape surrounding the ground selection line GSL, the word line WL, and the string selection lines SSL1 and SSL2.

[0041] exist Figure 2In the embodiment shown in , in order to overcome the process difficulties caused by the increase in integration, a portion of the gate electrode layer including a portion of the ground selection line GSL and the word line WL can be stacked, and a lower channel structure can be formed to first prepare or provide a lower mold LM. In addition, on the lower mold LM, the remaining gate electrode layer including the remaining word lines WL and the string selection lines SSL1 and SSL2 can be stacked, and an upper channel structure can be formed to prepare or provide an upper mold UM. Therefore, as shown in FIG. Figure 2 As shown in , each channel structure CH may include an upper channel structure and a lower channel structure.

[0042] Since the lower mold LM and the upper mold UM are formed separately, the alignment state of the upper channel structure and the lower channel structure in each of the channel structures CH may affect the reliability and performance of the memory device 100. For example, when the formed upper channel structure and the lower channel structure deviate from each other in at least one of the second direction (x-axis direction) and the third direction (y-axis direction) parallel to the upper surfaces of the substrates 101 and 102, the memory device 100 may include malfunctioning or bad memory cells.

[0043] The embodiment of the inventive concept provides a method for accurately verifying the alignment state between structures connected to each other in one direction. For example, the method according to the embodiment of the inventive concept can be used to accurately verify the alignment state between the structures connected to each other in one direction. Figure 2 Therefore, various semiconductor devices (such as Figure 2 reliability and performance of the memory device 100).

[0044] Figure 3 A flowchart describing a method of fabricating a semiconductor device according to an embodiment of the inventive concept is shown.

[0045] For example, application reference Figure 3 The semiconductor device of the fabrication method described may be a vertical memory device (such as that described with reference to Figure 2 Memory device 100 described above). However, Figure 3 The manufacturing method can be applied to other semiconductor devices.

[0046] Reference Figure 3 The method for manufacturing a semiconductor device according to an embodiment of the inventive concept begins with forming a lower mold (S10). The lower mold may include a lower layer and a lower channel structure stacked on a substrate. For example, the lower layer may include a lower sacrificial layer for forming a portion of a ground select line and a word line, and an insulating layer alternately stacked with the lower sacrificial layer. The lower channel structure may extend in a direction perpendicular to the upper surface of the substrate and may pass through the lower layer.

[0047] An upper molding may be formed on the lower molding (S11). The upper molding may include an upper layer stacked on the lower molding and an upper channel structure passing through the upper layer. In an example, the upper layer may include an upper sacrificial layer for forming a portion of a word line and a string selection line and an insulating layer alternately stacked with the upper sacrificial layer.

[0048] The upper channel structure may be formed at the same position as the lower channel structure on a plane parallel to the upper surface of the substrate. However, due to process errors, etc., in an actual structure, the upper channel structure may not be formed at the same position as the lower channel structure. In addition, the upper channel structure may be formed so as to be dug into (e.g., protrude into) at least a portion of the lower channel structure from the upper surface of the lower channel structure. For example, the lower surface of the upper channel structure may be located at a height lower than the upper surface of the lower channel structure.

[0049] Next, the upper mold may be removed by an etching process (S12). In an embodiment, the etching process may be a wet etching process. The upper mold may be removed to expose the upper surface of the lower mold to the outside. A cross-section of the lower channel structure and traces of the upper channel structure dug into the lower channel structure may be present on the upper surface of the lower mold exposed to the outside.

[0050] In the manufacturing method according to an embodiment of the inventive concept, a predetermined verification device may be employed. For example, the verification device may be a computer device in which a predetermined neural network, a predetermined image processing function, etc. are implemented. The verification device may capture the upper surface of the lower molded part to obtain an original image (S13).

[0051] The verification device may separate the original image into an upper original image and a lower original image (S14). The upper original image may be an image in which the trace of the upper channel structure is displayed, and the lower original image may be an image in which a cross-section of the lower channel structure is displayed. The upper original image may be input into a learning neural network, and the neural network may reconstruct the trace of the upper channel structure from the upper original image to output an upper restored image in which the cross-section of the upper channel structure is displayed (S15). In an example, the neural network may be a generative adversarial network (GAN).

[0052] The verification device may compare the upper restored image with the lower original image to verify the alignment of the upper and lower molded parts (S16). Since the cross section of the upper channel structure (e.g., the lower surface of the upper channel structure) can be fully displayed in the upper reconstructed image, the alignment of the upper and lower molded parts can be accurately verified by comparing the cross section of the upper channel structure with the cross section of the lower channel structure.

[0053] Figure 4A and Figure 4BA verification apparatus used in a method of manufacturing a semiconductor device according to an embodiment of the inventive concept is illustrated.

[0054] First, see Figure 4A , the verification device 200 may include a processor 210 and a memory 220. According to an embodiment, in addition to the processor 210 and the memory 220, the verification device 200 may further include other components, such as an input / output device, a communication module (e.g., a circuit), a camera module (e.g., a device), etc. The processor 210 may include a neural processing unit (NPU) 211 and an image signal processor (ISP) 212. The neural processing unit (NPU) 211 may be a block (e.g., a circuit) for performing artificial intelligence (AI) calculations and inferences, and the image signal processor (ISP) 212 is used to perform image processing. The memory 220 may store images necessary for verifying the alignment state of the upper and lower molded parts, etc.

[0055] The NPU 211 may perform operations using a predetermined neural network. Figure 4B , a neural network according to an embodiment of the inventive concept may include a generator 230 and a discriminator 240. The generator 230 receives an input image 232 to generate an output image 233, and may include an encoder and a decoder. For example, the input image 232 received by the generator 230 may be a version of an actual image 231 with at least a portion intentionally damaged. The generator 230 may reconstruct the input image 232 to generate an output image 233.

[0056] The discriminator 240 may compare the output image 233 with the actual image 231. For example, the verification device 200 may use the sample images to teach the generator 230 until the discriminator 240 cannot distinguish the output image 233 from the actual image 231 (e.g., the output image 233 is identical to the actual image 231). The neural network including the generator 230 and the discriminator 240 as taught by the verification device 200 can be characterized as a learning neural network.

[0057] In an embodiment of the inventive concept, a neural network can verify the alignment of the lower and upper structures. In one example, the neural network can be used to reconstruct a cross-section of the upper channel structure from an upper original image showing the traces of the upper channel structure to obtain an upper restored image. The neural network can be used to accurately reconstruct a cross-section of the upper channel structure having an irregular shape, rather than a regular cross-section such as an ellipse or a circle. Thus, the alignment of the upper and lower channel structures can be accurately verified.

[0058] Figures 5 to 12 Views are shown describing a method of fabricating a semiconductor device according to an embodiment of the inventive concept.

[0059] Reference Figures 5 to 12 The semiconductor device described may be a memory device. First, referring to Figure 5 , a plurality of lower layers 310 are stacked on the upper surface of the substrate 301. The lower layer 310 may include a lower insulating layer 311 and a lower sacrificial layer 313. The lower insulating layer 311 and the lower sacrificial layer 313 may be formed of an insulating material. For example, the lower insulating layer 311 and the lower sacrificial layer 313 may be formed of different materials each having a predetermined etching selectivity. For example, the lower insulating layer 311 may be formed of silicon oxide, and the lower sacrificial layer 313 may be formed of silicon nitride.

[0060] Reference Figure 6 , forming a lower channel structure LCH that passes through the lower layer 310 and extends to the substrate 301. The lower channel structure LCH may include a gate insulating layer 303, a lower channel layer 304, an embedded insulating layer 305, and other layers. In various embodiments, the number and structure of the layers included in the lower channel structure LCH may vary.

[0061] The gate insulating layer 303 may include a blocking layer, a charge storage layer, a tunneling layer, and other layers. The lower channel layer 304 may be formed of a semiconductor material such as polysilicon and may or may not be doped with impurities depending on the embodiment. The lower channel layer 304 may have a hollow cylindrical shape, and the void space in the lower channel layer 304 may be filled with an embedded insulating layer 305. The lower channel structure LCH and the lower layer 310 may be provided to form a lower mold LM.

[0062] Next, refer to Figure 7 An upper mold UM is formed on the lower mold LM. The upper mold UM may include an upper layer 320 stacked on the lower mold LM and an upper channel structure UCH extending through the upper layer 320 to the lower channel structure LCH. The upper layer 320 may include an upper insulating layer 321 and an upper sacrificial layer 323. The upper layer 320 may be covered with an interlayer insulating layer 330.

[0063] The upper channel structure UCH may have the same structure as that of the lower channel structure LCH. Figure 7 , the upper channel structure UCH may include a gate insulating layer 306, an upper channel layer 307, an embedded insulating layer 308, etc. The upper channel structure UCH may be formed to be dug into (e.g., protruded into) the lower channel structure LCH and the uppermost lower layer 310 to a predetermined depth. Therefore, the lower surface of the upper channel structure UCH may be located at a lower level than the upper surface of the lower channel structure LCH. In addition, the lower surface of the upper channel structure UCH may be located at a lower level than the upper surface of the lower mold LM.

[0064] The upper channel structure UCH may be connected to the lower channel structure LCH, and specifically, the upper channel layer 307 may be connected to the lower channel layer 304. However, due to errors occurring during processing or manufacturing, the upper channel structure UCH and the lower channel structure LCH may not be aligned correctly. Therefore, it may happen that the upper channel layer 307 and the lower channel layer 304 may not be connected to each other. Hereinafter, reference will be made to Figure 8 and Figure 9 Describe in more detail Figure 7 Part A and Part B.

[0065] Reference Figure 8 and Figure 9 , the upper channel structure UCH and the lower channel structure LCH are shown to be connected. Figure 8 In the portion A shown in FIG, the upper channel structure UCH and the lower channel structure LCH are relatively well aligned. However, in FIG. Figure 9 In the portion B shown in FIG, the upper channel structure UCH and the lower channel structure LCH are formed to be offset from each other. For example, the upper channel structure UCH may be misaligned with respect to the lower channel structure LCH. Figure 8 Compared to portion A in FIG, the upper channel layer 307 and the lower channel layer 304 in portion B are not properly connected, and reliability and / or operational characteristics of the semiconductor device may be deteriorated.

[0066] Figure 10 3 shows a plan view of the semiconductor device when viewed from a plane parallel to the upper surface of the substrate 301. Figure 10 The alignment error between the upper channel structure UCH and the lower channel structure LCH may occur in various forms. Specifically, when the alignment error between the upper channel structure UCH and the lower channel structure LCH exceeds a certain range, problems may occur in the connection between the upper channel layer 307 and the lower channel layer 304.

[0067] The embodiment of the inventive concept provides a method for accurately verifying the alignment state of the upper channel structure UCH and the lower channel structure LCH. In order to verify the alignment state of the upper channel structure UCH and the lower channel structure LCH, as shown in FIG. Figure 11 , the upper mold UM is removed. When the upper mold UM is removed, a trace 340 caused by the upper channel structure UCH may exist in the cross section of the lower channel structure LCH exposed to the outside. Referring to FIG. Figure 12 , the trace 340 of the upper channel structure UCH may exist together with the cross section 350 of the lower channel structure LCH.

[0068] In an embodiment of the inventive concept, it is possible to capture Figure 12The upper surface of the lower mold LM shown in the figure is obtained by taking an original image, and the trace 340 of the upper channel structure UCH and the cross section of the lower channel structure LCH can be separated from the original image. The image in which the trace 340 of the upper channel structure UCH is displayed can be defined as an upper original image, and the image in which the cross section 350 of the lower channel structure LCH is displayed can be defined as a lower original image. In the method according to an embodiment of the inventive concept, the upper original image can be input to a verification device including a learning neural network and an image processing function. The neural network can reconstruct the cross section of the upper channel structure UCH from the upper original image to output an upper restored image. The verification device can compare the upper restored image and the lower original image to verify the alignment state of the upper mold UM and the lower mold LM. Hereinafter, reference will be made to Figures 13 to 16 Embodiments of the inventive concept are described in more detail.

[0069] Figures 13 to 16 Views are shown describing a method of fabricating a semiconductor device according to an embodiment of the inventive concept.

[0070] Figure 13 An upper original image UOI is shown in which a trace 340 of an upper channel structure UCH is displayed. Figure 14 The lower original image LOI is shown in which a cross section 350 of the lower channel structure LCH is shown. The cross section 350 of the lower channel structure LCH shown in the lower original image LOI is almost complete, while the trace 340 shown in the upper original image UOI shows only a portion of the cross section of the upper channel structure UCH.

[0071] In the verification device employed in the manufacturing method according to the embodiment of the inventive concept, the upper original image UOI can be restored by using a generative adversarial network (GAN). When the upper original image UOI is input to the generative adversarial network (GAN), a trace 340 corresponding to a portion of the cross section of the upper channel structure UCH can be restored to obtain Figure 15 The verification device may regard the restoration trace of the upper channel structure UCH displayed in the upper restoration image URI as a cross section 360 of the upper channel structure UCH.

[0072] The verification device may overlap the upper restored image URI and the lower original image LOI to verify the alignment state of the upper molding UM and the lower molding LM. The verification device may determine the alignment state of the upper channel structure UCH and the lower channel structure LCH to verify the alignment state of the upper molding UM and the lower molding LM. Figure 16 A resultant image generated by overlapping an upper restored image URI and a lower original image LOI by the verification device according to an embodiment is shown.

[0073] Reference Figure 16In the resulting image shown in , the cross-section 360 of the upper channel structure UCH and the cross-section 350 of the lower channel structure LCH can be displayed as overlapping each other. The verification device can compare the center position of the cross-section 360 of each upper channel structure UCH with the center position of the cross-section 350 of each lower channel structure LCH to verify the alignment state of the upper channel structure UCH and the lower channel structure LCH. For example, the verification device compares the center position of the cross-section 360 of the first upper channel structure UCH with the center position of the cross-section 350 of the corresponding first lower channel structure LCH, compares the center position of the cross-section 360 of the second upper channel structure UCH with the center position of the cross-section 350 of the corresponding second lower channel structure LCH, and so on. In addition, the verification device can divide the cross section 360 of each upper channel structure UCH into a first region inside the cross section 350 of each lower channel structure LCH and a second region outside the cross section 350 of each lower channel structure LCH, and the area of the first region and the area of the second region can be used to verify the alignment state of the upper channel structure UCH and the lower channel structure LCH. For example, the verification device can divide the cross section 360 of the first upper channel structure UCH into a first region inside the cross section 350 of the corresponding first lower channel structure LCH and a second region outside the cross section 350 of the corresponding first lower channel structure LCH, can divide the cross section 360 of the second upper channel structure UCH into a first region inside the cross section 350 of the corresponding second lower channel structure LCH and a second region outside the cross section 350 of the corresponding second lower channel structure LCH, and so on. Hereinafter, reference will be made to 17A to 17C and 18A to 18C Embodiments of the inventive concept are described in more detail.

[0074] 17A to 17C and 18A to 18C A view is shown describing a method of determining an alignment state of a semiconductor device according to an embodiment of the inventive concept.

[0075] In reference 17A to 17C In the described embodiment, the center position of the cross section 360 of each upper channel structure UCH and the center position of the cross section 350 of each lower channel structure LCH can be used to verify the alignment state of the upper mold UM and the lower mold LM and / or the alignment state of the upper channel structure UCH and the lower channel structure LCH. 17A to 17C In the depicted embodiment, the center position of the cross section 360 of each upper channel structure UCH and the center position of the cross section 350 of each lower channel structure LCH may be the center of gravity of a figure defined as the outline of each of the cross section 360 and the cross section 350 .

[0076] Reference Figure 17A, there may be a first distance D1 between a first center C1 of a cross section 350 of the lower channel structure LCH and a second center C2 of a cross section 360 of the upper channel structure UCH. The cross section 350 of the lower channel structure LCH may have a first radius R1. The verification device may compare the first distance D1 and the first radius R1. For example, when the ratio of the first distance D1 and the first radius R1 is less than a predetermined reference value, the verification device may determine that the alignment state of the upper channel structure UCH and the lower channel structure LCH is good. When the ratio of the first distance D1 and the first radius R1 is equal to or greater than the predetermined reference value, the verification device may determine that the alignment state of the upper channel structure UCH and the lower channel structure LCH is poor.

[0077] Reference Figure 17B A second distance D2 may exist between a first center C1 of a cross section 350 of the lower channel structure LCH and a second center C2 of a cross section 360 of the upper channel structure UCH. The cross section 350 of the lower channel structure LCH may have a second radius R2. As described above, the verification device may compare the second distance D2 and the second radius R2 to determine the alignment status of the upper channel structure UCH and the lower channel structure LCH.

[0078] exist Figure 17C In the embodiment shown in , the verification device can compare the third distance D3 and the third radius R3 to determine the alignment state of the upper channel structure UCH and the lower channel structure LCH. 17A to 17C In the embodiment shown in Figure 17A and Figure 17B In the embodiment shown in FIG, it can be determined that the alignment state of the upper channel structure UCH and the lower channel structure LCH is good by comparing the first distance D1 with the first radius R1 and by comparing the second distance D2 with the second radius R2. Figure 17C In the embodiment shown in , the verification apparatus may determine the alignment difference between the upper channel structure UCH and the lower channel structure LCH by comparing the third distance D3 and the third radius R3.

[0079] In reference 18A to 18C In the depicted embodiment, the cross-section 360 of each upper trench structure UCH can be divided into first regions A1, A3, and A5 and second regions A2, A4, and A6, respectively. The areas of the first regions A1, A3, and A5 and the areas of the second regions A2, A4, and A6 can be used to verify the alignment of the upper mold UM and the lower mold LM and / or the alignment of the upper trench structure UCH and the lower trench structure LCH. For example, the first regions A1, A3, and A5 can be regions within the cross-section 350 of the corresponding lower trench structure LCH, and the second regions A2, A4, and A6 can be regions outside the cross-section 350 of the corresponding lower trench structure LCH.

[0080] For example, when the first areas A1, A3 and A5 are larger than the second areas A2, A4 and A6, the alignment state may be determined to be good. Alternatively, the alignment state may be verified by comparing the ratio of the first areas A1, A3 and A5 to the second areas A2, A4 and A6 with a predetermined reference value.

[0081] Reference Figure 18A , compared with the second area A2, the first area A1 may have a relatively large area. Figure 18B In the embodiment, the first region A3 may have an area larger than that of the second region A4. Figure 18A and Figure 18B In the embodiment shown in , the alignment state of the lower channel structure LCH and the upper channel structure UCH can be determined to be good. Figure 18C In the embodiment shown in , the second region A6 may have an area larger than that of the first region A5. Figure 18C In the embodiment shown in , the alignment states of the lower channel structure LCH and the upper channel structure UCH may be determined to be poor.

[0082] Figures 19 to 21 A view is shown describing a manufacturing method of a sample for teaching a neural network in a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0083] In a method of manufacturing a semiconductor device according to an embodiment of the inventive concept, an AI operation using a neural network can be performed by a verification device. A plurality of samples can be provided to the neural network for learning in the verification device. The samples can be formed by a process similar to that of the semiconductor device to be manufactured. For example, referring to Figures 19 to 21 The fabrication method of the described samples can be similar to that of reference Figures 5 to 12 A method of manufacturing a semiconductor device is described.

[0084] First, refer to Figure 19 , a lower layer 410 may be stacked on the substrate 401. The lower layer 410 may include a lower insulating layer 411 and a lower sacrificial layer 413, and a lower mold LM may be provided by the lower layer 410.

[0085] Next, refer to Figure 20, an upper mold UM may be formed on the lower mold LM. The upper mold UM may include an upper layer 420, an upper channel structure UCH, etc. The upper layer 420 may include upper insulating layers 421 and upper sacrificial layers 423 stacked alternately. Each upper channel structure UCH may include a gate insulating layer 406, an upper channel layer 407, an embedded insulating layer 408, etc. Each upper channel structure UCH may be formed to be dug into (e.g., protruding into) at least a portion of the uppermost lower layer 410. For example, the lower surface of each upper channel structure UCH may be located at a level lower than the upper surface of the uppermost layer in the lower mold LM.

[0086] Reference Figure 21 , the upper mold UM may be removed. When the upper mold UM is removed, a remaining area 430 corresponding to the lower surface of the upper channel structure UCH may appear in the lower mold LM. In an embodiment, the manufacturing method of the sample may be terminated by removing the upper mold UM. Figure 21 As shown in , a sample of the lower mold LM in which the remaining region 430 of the upper channel structure UCH exists may be manufactured as a plurality of samples.

[0087] In an embodiment of the inventive concept, a sample image capturing the upper surface of the lower mold LM from each sample can be input into a verification device. Since the lower mold LM does not include a channel structure in each sample, the remaining area 430 of the upper channel structure UCH included in the sample image can have a shape corresponding to the entire lower surface of the upper channel structure UCH.

[0088] The verification device may intentionally damage the region corresponding to the remaining region 430 of the upper channel structure UCH in each sample image to generate an input image. The verification device may input the input image into a neural network, and the discriminator may compare the output image restored by the neural network with the sample image. The verification device may teach the neural network until the discriminator cannot distinguish the output image from the sample image. The neural network taught by the verification device may be characterized as a learning neural network.

[0089] Figures 22A to 22C 、 Figures 23A to 23C 、 Figures 24A to 24C and Figures 25A to 25C A view describing a method of teaching a neural network in a method of manufacturing a semiconductor device according to an embodiment of the inventive concept is shown.

[0090] First, refer to Figures 22A to 22C, three sample images 500, 510, and 520 may be prepared for neural network learning. Each of the three sample images 500, 510, and 520 may be an image obtained by capturing the upper surface of the lower molding of each different sample. Referring to the first sample image 500, it may include a lower layer 413A disposed on the uppermost end of the lower molding and a remaining area 430A corresponding to a cross-section of the upper channel structure removed during the sample manufacturing process. Figure 22A As shown in , each remaining region 430A may have various shapes according to the shape of the cross section of each upper channel structure.

[0091] like Figure 22B and Figure 22C The second sample image 510 and the third sample image 520 shown in FIG. 3 may have similar configurations to the first sample image 500. The second sample image 510 may include a lower layer 413B disposed on the uppermost end of the lower molded member and a remaining region 430B corresponding to the cross-section of the removed upper channel structure. The third sample image 520 may also include a lower layer 413C disposed on the uppermost end of the lower molded member and a remaining region 430C corresponding to the cross-section of the removed upper channel structure.

[0092] Reference Figures 23A to 23C , the verification device may intentionally damage the remaining regions 430A, 430B, and 430C corresponding to the cross-section of the upper channel structure in each of the sample images 500, 510, and 520. For example, the verification device may intentionally remove portions of the respective remaining regions 430A, 430B, and 430C, thereby changing the shapes of the remaining regions 430A, 430B, and 430C. Figures 23A to 23C As shown in FIG, input images 501, 511, and 521 may be generated, in which only portions of the damaged remaining regions 440A, 440B, and 440C are displayed. The verification device may input the input images 501, 511, and 521 into a neural network. The neural network may be, for example, a generative adversarial network (GAN) including a discriminator, which reconstructs the input images 501, 511, and 521 to generate images as shown in FIG. Figures 24A to 24C The output images 503, 513 and 523 shown in FIG are then compared with the sample images 500, 510 and 520. Figures 24A to 24C , in the output images 503 , 513 , and 523 , restored regions 450A, 450B, and 450C in which the damaged remaining regions 440A, 440B, and 440C are restored by the neural network may be displayed.

[0093] The neural network’s discriminator can distinguish Figures 24A to 24CThe output images 503, 513 and 523 shown in FIG are respectively Figures 22A to 22C For comparison, refer to the sample images 500, 510, and 520 shown in FIG. Figures 25A to 25C In an embodiment, the discriminator may overlap the output images 503, 513, and 523 with the sample images 500, 510, and 520, respectively, and may compare the restored regions 450A, 450B, and 450C with the remaining regions 430A, 430B, and 430C. Based on the differences between the restored regions 450A, 450B, and 450C and the remaining regions 430A, 430B, and 430C, the discriminator may determine each of the output images 503, 513, and 523 as a false image (i.e., an image that has not been correctly restored) or a true image. The verification device may teach the generator of the neural network until the discriminator determines each of the output images 503, 513, and 523 as a true image, for example, the discriminator fails to distinguish the output images 503, 513, and 523 from the sample images 500, 510, and 520.

[0094] When the learning of the generator is completed, or in other words, when the teaching of the generator is completed by the verification device, the verification device can be used in a method for manufacturing a semiconductor device. The verification device can separate an upper original image in which the trace of the upper channel structure is displayed and a lower original image in which the cross section of the lower channel structure is displayed from an original image captured after removing the upper molding of the semiconductor device. The verification device can reconstruct the trace of the upper channel structure displayed on the upper original image by using the neural network for which learning is completed to obtain an upper restored image in which the cross section of the upper channel structure is displayed. The verification device can compare the upper restored image with the lower original image to determine the alignment state of the upper channel structure and the lower channel structure.

[0095] In addition to memory devices having an upper channel structure and a lower channel structure, the method of manufacturing a semiconductor device according to an embodiment of the inventive concept can be applied to various semiconductor devices. For example, the method of manufacturing a semiconductor device according to an embodiment of the inventive concept can be applied to verifying the alignment state of structures connected to each other in one direction. Hereinafter, reference will be made to Figure 26 Embodiments of the inventive concept are described in more detail.

[0096] Figure 26 A flowchart describing a method of fabricating a semiconductor device according to an embodiment of the inventive concept is shown.

[0097] Reference Figure 26, the method for manufacturing a semiconductor device according to an embodiment of the inventive concept begins with forming a first structure (S20). The first structure can be defined in various ways. For example, the first structure can be a via structure connected to the gate and / or active region of the semiconductor device, or can be a via structure connected to a wiring pattern in the upper portion of the semiconductor device. As another example, the first structure can be a through-silicon via (TSV, also known as "through-silicon via") passing through the substrate.

[0098] After forming the first structure, a second structure is formed (S21). The second structure may be connected to the first structure in one direction. The second structure may be of the same type as the first structure, or may be of a different type than the first structure. After forming the second structure, the second structure is removed by an etching process, etc., to expose a cross-section of the first structure (S22).

[0099] When the cross section of the first structure is exposed, the exposed surface is captured (e.g., the exposed surface is imaged) to obtain an original image (S23). The cross section of the first structure, the trace of the second structure, etc. may be displayed in the original image. Then, the verification device used in the method of manufacturing a semiconductor device separates the first original image and the second original image from the original image (S24). The first original image may be an image in which the cross section of the first structure is displayed, and the second original image may be an image in which the trace of the second structure is removed.

[0100] Then, the verification device, such as that described previously, inputs the second original image into the neural network that has completed learning in advance to obtain a second restored image (S25). The second restored image can be an image obtained by reconstructing the trace of the second structure displayed on the second original image into a cross-section of the second structure. Then, the verification device compares the first original image with the second restored image to verify the alignment state between the first structure and the second structure (S26). In operation S26, the above reference can be used. Figure 8 and Figure 9 One of the methods described.

[0101] For example, the method of manufacturing a semiconductor device according to an embodiment of the inventive concept may be used to verify the alignment state of structures to be aligned with each other in a specific direction. Figure 26 Specific examples of the described methods may be understood with reference to the embodiments described with reference to the semiconductor device including the upper molding and the lower molding.

[0102] Figure 27 and Figure 28 A view illustrating a semiconductor device to which a method of manufacturing the semiconductor device according to an embodiment of the inventive concept is applicable is shown.

[0103] exist Figure 27In the embodiment shown in , the semiconductor device to which the manufacturing method according to the embodiment of the inventive concept is applied may be a dynamic random access memory (DRAM) device. Figure 27 A semiconductor device 600 according to an embodiment of the inventive concept may include a substrate 601, and a device isolation layer 602, an active region 603, a gate structure 610, a bit line structure 620 connected to at least a portion of the active region 603, a capacitor structure 640, etc. may be formed on the substrate 601. The gate structure 610 may intersect the active region 603 and the bit line structure 620 and may be embedded in the substrate 601. The gate structure 610 may be a word line.

[0104] The gate structure 610 may include a gate electrode layer 611, a cap layer 612, and the like. The gate electrode layer 611 may be formed of a conductive material (such as a metal or a metal compound), and the cap layer 612 may be formed of an insulating material (such as silicon nitride). A gate insulating layer 605 may be disposed between the gate electrode layer 611 and the substrate 601, and the gate insulating layer 605 may be formed of silicon oxide, for example.

[0105] The active region 603 may be doped with impurities and may provide a source region and a drain region of a switching element included in the memory cell. The active region 603 located between the gate structure 610 and the device isolation layer 602 may be connected to the capacitor structure 640 via a contact 650. The active region 603 disposed between a pair of adjacent gate structures 610 may be connected to the bit line structure 620 via a contact 652.

[0106] The bit line structure 620 and the contact 650 may be embedded in the intermediate insulating layer 630. The intermediate insulating layer 630 may include a first intermediate insulating layer 631 and a second intermediate insulating layer 632. The contact 652 connected to the bit line structure 620 may be embedded in the first intermediate insulating layer 631, and the contact 650 connected to the capacitor structure 640 may be embedded in the first intermediate insulating layer 631 and the second intermediate insulating layer 632. The bit line structure 620 may include a bit line conductive layer 621, a bit line capping layer 622, a spacer layer 623, and the like.

[0107] The capacitor structure 640 may be connected to the active region 603 through a contact 650 and may include lower electrode layers 641 and 642, a dielectric layer 643, an upper electrode layer 644, etc. The capacitor structure 640 may extend in a direction perpendicular to the upper surface of the substrate 601. The lower electrode layers 641 and 642 may have a Figure 27 The cylindrical shape shown in , or may have a hollow cylindrical shape.

[0108] In order to increase the capacitance provided by the capacitor structure 640, the height of the lower electrode layers 641 and 642 may be increased. For example, the lower electrode layers 641 and 642 may be formed by forming a mask layer on the intermediate insulating layer 630, removing regions corresponding to the lower electrode layers 641 and 642 from the mask layer by an etching process or the like to form trenches, and then filling the trenches with a conductive material. When it is desired to increase the height of the lower electrode layers 641 and 642, it may be difficult to form the lower electrode layers 641 and 642 in a single etching process. In this case, as Figure 27 As shown in FIG, the lower electrode layers 641 and 642 may be formed to distinguish a first lower electrode layer 641 and a second lower electrode layer 642. The first lower electrode layer 641 and the second lower electrode layer 642 may be connected in a direction perpendicular to the upper surface of the substrate 601.

[0109] In order to precisely align the first lower electrode layer 641 and the second lower electrode layer 642, a manufacturing method according to an embodiment of the inventive concept can be applied. For example, after forming the first lower electrode layer 641 and the second lower electrode layer 642, the second lower electrode layer 642 can be removed and an original image can be captured. In the original image, the trace of the second lower electrode layer 642 and the cross-section of the first lower electrode layer 641 can overlap each other. According to an embodiment of the inventive concept, the verification device can obtain a first original image in which only the cross-section of the first lower electrode layer 641 is displayed and a second original image in which only the trace of the second lower electrode layer 642 is displayed from the original image.

[0110] The verification device may reconstruct the trace of the second lower electrode layer 642 displayed on the second original image by using a learning neural network to obtain a second restored image. The verification device may compare the first original image with the second restored image to determine the alignment state of the first lower electrode layer 641 and the second lower electrode layer 642. When the alignment state of the first lower electrode layer 641 and the second lower electrode layer 642 is determined to be poor, the operation of forming the second lower electrode layer 642 may be modified to accurately align the first lower electrode layer 641 and the second lower electrode layer 642.

[0111] The method of manufacturing a semiconductor device according to an embodiment of the inventive concept may also be used to verify the alignment of structures other than the first lower electrode layer 641 and the second lower electrode layer 642. For example, the method of manufacturing a semiconductor device according to an embodiment of the inventive concept may be applied to verify the alignment of the first lower electrode layer 641 and the contact 650.

[0112] exist Figure 28 In the embodiment shown in , the semiconductor device to which the manufacturing method according to the embodiment of the inventive concept is applied may be a phase change random access memory (PRAM) device. Figure 28The semiconductor device 700 may include a peripheral circuit region P having a plurality of circuit elements 711 formed on a semiconductor substrate 710 and a cell region C having a plurality of memory cells 730 and 750. The cell region C may include a bit line 740 and word lines 720 and 760 extending in a direction parallel to the upper surface of the substrate 710 and intersecting each other. The bit line 740 may be provided in an interlayer insulating layer 745.

[0113] For example, the cell region C may include a lower word line 720 disposed below the bit line 740 and an upper word line 760 disposed on the bit line 740. The lower memory cell 730 may be disposed between the bit line 740 and the lower word line 720, and the upper memory cell 750 may be disposed between the bit line 740 and the upper word line 760. The lower memory cell 730 and the upper memory cell 750 may have the same structure.

[0114] The circuit element 711 may be adjacent to the element isolation layer 712 and may be connected to the element contact 771. The circuit element 711 may be covered by the interlayer insulating layer 715. Figure 28 In the embodiment shown in , the circuit element 711 is shown as being connected to the upper word line 760 , but the circuit element 711 may be connected to the bit line 740 or the lower word line 720 .

[0115] The lower word line 720 may be connected to the heating electrode layer 721. Figure 28 In the embodiment shown in FIG, the heating electrode layer 721 is shown as being connected to a pair of lower memory cells 730 adjacent in the second direction, but is not necessarily limited thereto. For example, each lower memory cell 730 may be connected to a corresponding single heating electrode layer 721 among the heating electrode layers 721.

[0116] The heating electrode layers 721 may be separated from each other by a lower insulating layer 722. Insulating spacers 723 and inner insulating layers 724 and 725 may be provided in the heating electrode layers 721. The lower insulating layer 722, the insulating spacers 723, and the inner insulating layers 724 and 725 may be formed of, for example, silicon oxide, silicon nitride, or the like.

[0117] Each lower memory cell 730 may include a variable resistance layer 731 contacting the heating electrode layer 721, and a first electrode layer 732, a selection element layer 734, and a second electrode layer 736 sequentially stacked on the variable resistance layer 731. According to an embodiment, a first interface layer 733 and a second interface layer 735 may be provided between the selection element layer 734 and the first electrode layer 732 and between the selection element layer 734 and the second electrode layer 736, respectively.

[0118] The variable resistance layer 731 may be formed of a material capable of inducing phase change by heat transferred from the heating electrode layer 721. The selection element layer 734 may include a material whose resistance changes according to the magnitude of a voltage applied thereto.

[0119] The upper memory cell 750, the heating electrode layer 761, and the upper word line 760 may be disposed on the bit line 740. Figure 28 , the heating electrode layer 761 may be connected to the upper word line 760, and the heating electrode layers 761 may be separated from each other by the upper insulating layer 762. Insulating spacers 763 and inner insulating layers 764 and 765 may be disposed in the heating electrode layer 761. The upper memory cell 750 may have the same structure as that of the lower memory cell 730.

[0120] Reference Figure 28 , the element contact 771 may be connected to at least one of the upper word lines 760 through the word line contact WC. Considering the distance difference between the element contact 771 and the upper word line 760, the word line contact WC may include cell contacts 772 connected to each other in one direction perpendicular to the upper surface of the substrate.

[0121] The manufacturing method according to an embodiment of the inventive concept can be applied to verify the alignment state of the cell contact 772 and / or the alignment state of the word line contact WC and the element contact 771. For example, after forming the semiconductor device 700, a plurality of original images can be acquired by removing the cell contacts 772 one by one and capturing images. Each original image can be separated into a first original image showing a cross section of the relative lower structure and a second original image showing a trace of the relative upper structure. The trace of the second original image can be restored to the shape of the corresponding cross section of the relative upper structure by learning a neural network to obtain a second restored image. The verification device according to an embodiment of the inventive concept can compare the first original image with the second restored image to verify the alignment state of the structure at the boundary between the various layers.

[0122] exist Figure 28 In the embodiment shown in , the alignment states of various structures to be connected at the boundaries between various layers can be verified simultaneously. For example, the alignment states of the memory cells 730 and 750 with the bit line 740 and the alignment states of the cell contacts 772 constituting the word line contacts WC can be verified. In addition, the alignment states between the memory cells 730 and 750 and the heater electrode layers 721 and 761 can be verified. If, as a result of the verification, there is a boundary where the alignment state is determined to be poor, the operation for forming the upper structure based on the boundary can be modified to improve the yield of the manufacturing process of the semiconductor device 700.

[0123] According to embodiments of the inventive concept, in a semiconductor device where the alignment of a lower structure and an upper structure is required, a plane from which the upper structure has been removed can be captured to obtain an upper original image showing the trace of the upper structure. The upper original image can be input into a learning neural network, and the neural network can reconstruct the trace of the upper structure to generate an upper restored image. The upper restored image can be compared with the lower original image showing the lower structure, and based on the comparison result, the alignment of the upper and lower structures can be verified.

[0124] Various advantages and effects of the inventive concept are not limited to the above description, and should be easily understood and apparent in view of the specific embodiments of the inventive concept as described.

[0125] While embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a lower molding having a lower layer stacked on a substrate and a lower channel structure passing through the lower layer; forming an upper molding, the upper molding comprising an upper layer stacked on the lower molding and an upper channel structure passing through the upper layer; removing the upper molded part to expose the upper surface of the lower molded part; separating an upper original image showing the trace of the upper channel structure and a lower original image showing the lower channel structure from an original image capturing the upper surface of the lower molding; inputting the upper original image into a neural network to obtain an upper restored image showing a cross section of the upper channel structure; as well as The upper restored image is compared with the lower original image to verify an alignment state of the upper and lower moldings.

2. The method according to claim 1, wherein The neural network includes a generative adversarial network.

3. The method according to claim 1, wherein The step of removing the upper molding includes using a wet etching process.

4. The method according to claim 1, wherein The comparing step for verifying the alignment state includes comparing the cross-section of the upper channel structure displayed in the upper restored image with a cross-section of a corresponding lower channel structure among the lower channel structures displayed in the lower original image to verify the alignment state of the upper and lower moldings.

5. The method according to claim 4, wherein The comparing step for verifying the alignment state includes comparing a center position of the cross section of the upper channel structure displayed in the upper restored image with a center position of the cross section of the corresponding lower channel structure in the lower channel structure displayed in the lower original image to verify the alignment state of the upper and lower molds.

6. The method according to claim 5, wherein: The comparing step for verifying the alignment state includes calculating a distance between the center position of the cross-section of the upper channel structure and the center position of the cross-section of the corresponding lower channel structure among the lower channel structures, and comparing a radius of the cross-section of the corresponding lower channel structure among the lower channel structures and a ratio of a corresponding distance among the distances with predetermined reference values, respectively, to verify the alignment state of the upper molding and the lower molding.

7. The method according to claim 5, wherein: The comparison step for verifying the alignment state includes calculating the center of gravity of the profile of the cross section to obtain a center position.

8. The method according to claim 4, wherein The comparing step for verifying the alignment state comprises: overlapping the upper restored image and the lower original image to generate a resultant image; dividing the cross section of the upper channel structure into a first region inside the cross section of the corresponding lower channel structure in the lower channel structure and a second region outside the cross section of the corresponding lower channel structure in the lower channel structure in the obtained image; and The alignment state of the upper molding and the lower molding is verified using the area of the first region and the area of the second region.

9. The method according to claim 4, wherein: The cross section of the upper channel structure displayed in the upper restored image is a lower surface of the upper channel structure, and The cross-section of the corresponding lower channel structure among the lower channel structures displayed in the lower original image is an upper surface of the corresponding lower channel structure among the lower channel structures.

10. The method according to claim 1, wherein The cross-section of the upper channel structure displayed in the upper restored image has an area smaller than an area of a cross-section of a corresponding lower channel structure in the lower channel structure displayed in the lower original image.

11. The method according to claim 1, wherein The cross-section of the upper channel structure displayed in the upper restored image has a shape different from a shape of a cross-section of a corresponding lower channel structure in the lower channel structure displayed in the lower original image.

12. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a first structure; forming a second structure connected to the first structure in one direction; removing the second structure to expose the first structure; Separating a first original image showing the cross section of the first structure and a second original image showing the trace of the second structure from an original image capturing a cross section of the first structure and a trace of the second structure in the one direction; inputting the second original image into a neural network to obtain a second restored image showing a cross-section of the second structure; as well as The first original image is compared with the second restored image to verify the alignment status of the first structure and the second structure.

13. The method according to claim 12, wherein: The comparing step for verifying the alignment status includes overlapping the first original image and the second restored image to generate a resultant image.

14. The method according to claim 13, wherein The comparing step for verifying the alignment state includes comparing a center position of the cross section of the first structure with a center position of the cross section of the second structure to verify the alignment state of the first structure and the second structure.

15. The method according to claim 13, wherein: The comparing step for verifying the alignment state comprises: dividing the cross section of the second structure into a first region inside the cross section of the first structure and a second region outside the cross section of the first structure in the obtained image; and The alignment state of the first structure and the second structure is verified using the area of the first region and the area of the second region.

16. A method for manufacturing a semiconductor device, the method comprising: forming samples, each comprising: a lower molding having a lower layer stacked in a first direction perpendicular to an upper surface of a substrate; and an upper molding having an upper layer stacked on the lower molding in the first direction and an upper channel structure passing through the upper layer; removing the upper molded part from the specimen to expose an upper surface of the lower molded part; capturing the upper surface of the lower molded part to obtain a sample image; damaging at least a portion of a remaining area corresponding to the upper channel structure in each of the sample images to generate an input image; inputting the input image into a neural network to obtain an output image having a restored region in which the remaining region corresponding to the upper channel structure is restored; and The neural network is trained until a discriminator comparing the output image to the sample image determines that the output image is identical to the sample image.

17. The method according to claim 16, wherein The neural network is a generative adversarial network.

18. The method according to claim 16, wherein The upper surface of the lower molding exposed by removing the upper molding includes a trace of the upper channel structure.

19. The method according to claim 16, wherein In the sample, the upper channel structures respectively protrude into at least a portion of an uppermost layer among the lower layers in the first direction.

20. The method according to claim 19, wherein The remaining area corresponds to a lower surface of the upper channel structure.

Images