Memory Array Decoding and Interconnects

Abstract

This application relates to memory array decoding and interconnects. Thin film transistors can access two or more memory cell levels arranged in a cross-point architecture. The manufacturing technology can use one or more via patterns formed at the top layer of a composite stack, which can facilitate the construction of the thin film transistors within the composite stack while using a reduced number of processing steps. By leveraging different groups of the vias, different configurations of the thin film transistors can be constructed using the manufacturing technology. Additionally, the thin film transistors and via-based related manufacturing techniques described herein can be used to construct circuits and components of a memory device (such as decoder circuitry, interconnects between aspects of one or more memory arrays).

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT Application No. PCT / US2019 / 064600, filed Dec. 5, 2019, by Castro et al., entitled “MEMORY ARRAY DECODING AND INTERCONNECTS,” which claims priority to U.S. Patent Application No. 16 / 223,632, filed Dec. 18, 2018, by Castro et al., entitled “MEMORY ARRAY DECODING AND INTERCONNECTS,” each of which is assigned to the assignee of this patent application and each of which is hereby incorporated by reference in its entirety. BACKGROUND OF THE DISCLOSURE

[0003] The following generally relates to decoding a memory array, and more particularly, to memory array decoding and interconnects.

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, a binary device has two states typically represented by a logic “1” or a logic “0”. In other systems, more than two states may be stored. To access the stored information, a component of the electronic device may read or sense the stored state in the memory device. To store information, a component of the electronic device may write or program the state in the memory device.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash, phase change memory (PCM), and others. Memory devices may include volatile memory cells or non-volatile memory cells. Non-volatile memory cells can retain their stored logical state for long periods of time even without an external power source. Volatile memory cells lose their stored state over time unless they are periodically refreshed by an external power source.

[0006] Improvements to memory devices generally can include increasing memory cell density, increasing read / write speed, increasing reliability, enhancing data retention capabilities, reducing power consumption, or reducing manufacturing costs, among other metrics. It can be desirable to build more memory cells per unit area to increase memory cell density and reduce cost per bit without increasing the size of the memory device. Improved techniques (e.g., faster, lower cost) for manufacturing memory devices, including those with increased memory cell density or other beneficial features, also can be desirable. SUMMARY OF THE INVENTION

[0007] A device is described. The device can include: a conductive plug extending through a plurality of memory cell levels; a plurality of transistors, each of which at least partially surrounds the conductive plug; and a driver coupled to the conductive plug and configured to selectively couple an electrode in a level included in the plurality of levels to the conductive plug via the transistors of the plurality of transistors.

[0008] Another device is described. The device can include: a conductive plug extending through a plurality of memory cell levels; a plurality of transistors, each of which has a source or drain in contact with the conductive plug; and a driver coupled to the conductive plug and configured to selectively couple an electrode in a level included in the plurality of levels to the conductive plug via the transistors of the plurality of transistors.

[0009] A method is described. The method can include: receiving an indication of an access operation to a memory cell; identifying a memory cell level that includes the memory cell, the level being included in a plurality of levels; at least partially based on the identification and using a first transistor included in the level, coupling an electrode included in the level to a conductive plug extending through the plurality of levels; and driving the electrode to a voltage associated with the access operation at least partially based on coupling the electrode to the conductive plug.

[0010] A device is described. The device can include: a memory array including a plurality of electrodes at a first layer and a plurality of memory cells at a second layer; a plurality of transistors configured to select an electrode from the plurality of electrodes, each of the plurality of transistors including: a gate electrode at the second layer; and a semiconductor material at the first layer.

[0011] Describe another device. The device may include: a plurality of memory cell levels, each including a first layer, a second layer, a third layer, and a plurality of memory arrays; a plurality of first electrodes extending in a first direction; and a plurality of second electrodes extending in a second direction intersecting the first direction, wherein in the region between the memory arrays of the plurality of memory arrays: each first electrode of the plurality of first electrodes includes a first portion at the second layer, a second portion at the first layer, and a third portion at the second layer; and each second electrode of the plurality of second electrodes includes a first portion at the second layer, a second portion at the third layer, and a third portion at the second layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Illustrate an example memory device including a three-dimensional memory cell array that supports memory array decoding and interconnects in accordance with an embodiment of the present disclosure.

[0013] Figure 2 Illustrate an example of a three-dimensional memory array that supports memory array decoding and interconnects in accordance with an embodiment of the present disclosure.

[0014] Figures 3A to 3L Illustrate an exemplary manufacturing technique that supports memory array decoding and interconnects in accordance with an embodiment of the present disclosure.

[0015] Figures 4A to 4AA Illustrate an exemplary manufacturing technique that supports memory array decoding and interconnects in accordance with an embodiment of the present disclosure.

[0016] Figures 5A to 5N Illustrate an exemplary manufacturing technique that supports memory array decoding and interconnects in accordance with an embodiment of the present disclosure.

[0017] Figures 6A to 6R Illustrate an exemplary manufacturing technique that supports memory array decoding and interconnects in accordance with an embodiment of the present disclosure.

[0018] Figures 7A to 7D Illustrate a diagram of an exemplary memory array that includes an active array region and a socket region that support memory array decoding and interconnects in accordance with an embodiment of the present disclosure.

[0019] Figures 8A to 8C Illustrate a diagram of an exemplary socket region and decoding scheme that support memory array decoding and interconnects in accordance with an embodiment of the present disclosure.

[0020] Figure 9 Illustrate a diagram of an exemplary decoding scheme that supports memory array decoding and interconnects in accordance with an embodiment of the present disclosure.

[0021] Figure 10A AND 10BA diagram illustrating an exemplary crossover region supporting memory array decoding and interconnects according to an embodiment of the present disclosure.

[0022] Figure 11 A diagram illustrating an exemplary memory device supporting memory array decoding and interconnects according to an embodiment of the present disclosure.

[0023] Figures 12 to 14 A method of thin film transistors and related fabrication techniques supporting memory array decoding and interconnects according to an embodiment of the present disclosure.

[0024] Figure 15 And 16 A method supporting memory array decoding and interconnects according to an embodiment of the present disclosure. Detailed Description

[0025] Building more memory cells per unit area can increase the areal density of the memory cells within a memory device. The increased areal density of the memory cells can facilitate a lower cost per bit and / or a larger memory capacity at a fixed cost for the memory device. The three-dimensional (3D) integration of two or more two-dimensional (2D) memory cell arrays can increase the areal density while also alleviating the difficulties associated with scaling the various feature sizes of the memory cells. In some cases, a 2D memory cell array can be referred to as a memory cell tier. In some cases, a memory device that includes multiple memory cell tiers can be referred to as a 3D memory device. Each memory cell tier of the 3D memory device can be selected (e.g., activated) or inhibited (e.g., deactivated, deselected) by circuitry that can be configured to determine which tier to select and perform an access operation on one or more memory cells of the selected tier. In some cases, the circuitry can include complementary metal oxide semiconductor (CMOS) transistors formed in or on a substrate, and the 3D integration tier of the memory cells can be located above the CMOS circuitry (e.g., fabricated on top of the CMOS circuitry). In some cases, the memory cell tier and associated components located above the substrate can be included in a set of layers (which can be collectively referred to as bit array layers).

[0026] A CMOS circuit system can determine a particular tier of a 3D memory device based on an access command from a host device, e.g., by decoding an address of a memory cell associated with and included in a particular tier in the access command. In some embodiments, as the number of tiers in a 3D memory device increases (e.g., 4 tiers, 8 tiers, 16 tiers, 32 tiers) to increase the areal density, the CMOS circuit system can increase in size to support decoding (e.g., determining which tier is selected from the increased tiers) and driving the additional tiers (e.g., providing sufficient current to access the memory cells of the selected tier). This increase in the size of the CMOS circuit system (e.g., increasing the substrate area occupied by the CMOS circuit system) can offset the benefits originally associated with the 3D integration of two or more 2D memory cell arrays.

[0027] The fabrication techniques, methods, and related devices described herein can facilitate the construction of thin-film transistors (TFTs) that can be positioned within a tier of a 3D memory device (e.g., within an array layer that collectively includes two or more memory cell tiers). In some cases, multiple sets of TFTs can be fabricated simultaneously within an array layer (e.g., two or more array layers each including a set of TFTs). The TFTs positioned within the array layer can be configured to select (e.g., activate) or inhibit (e.g., deactivate) a corresponding memory cell tier. In some cases, the TFTs can be part of a memory tier decoder (which can also be referred to as a memory tier selector) that can be coupled to a CMOS circuit system in a substrate. Thus, the TFTs can be coupled to the CMOS circuit system to facilitate the CMOS circuit system in performing its functions (e.g., determining a particular tier among multiple tiers of a 3D integration to be selected and driving current to access the memory cells of the particular tier). In this manner, the TFTs positioned within the array layer can facilitate accommodating additional memory cell tiers of a 3D memory device while alleviating the impact associated with the substrate area occupied by the CMOS circuit system. For example, in some cases, the CMOS circuit system can incorporate the TFTs while occupying substantially the same area to support one or more additional memory cell tiers. In some cases, the TFTs positioned within the array layer can alleviate the effects of various array parasitic components, such as leakage current, parasitic capacitance.

[0028] In some cases, the TFTs can be configured to perform additional functions (e.g., functions other than selecting or inhibiting memory cell levels, such as full decoding functions), such that the area of the CMOS circuitry below the array layer can be reduced, e.g., by delegating at least some aspects of its decoding function to the TFTs located in the array layer. Additionally, because the TFTs can provide individual levels isolated from the remaining levels (e.g., the TFTs can select individual levels while inhibiting the remaining levels) to thereby relax the current requirements (e.g., drive current requirements) during access operations. Relaxing the current requirements can have several benefits associated with the CMOS circuitry compared to alternative methods, where the CMOS circuitry can be configured to provide current to multiple levels during access operations. For example, relaxing the current requirements can facilitate the CMOS circuitry occupying a smaller area, using a (having) simpler circuit configuration, or providing one or more additional functions without increasing the occupied area.

[0029] The fabrication techniques, methods, and related apparatus described herein can be based on techniques, methods, and related apparatus that facilitate the simultaneous construction of multiple memory cell levels and associated array electrodes (e.g., a set of array layers and associated array electrodes each including a memory cell level), as described elsewhere. That is, aspects of constructing multiple memory cell levels and associated array electrodes are described in the following: U.S. Patent Application No. 15 / 961,540 to Castro et al. titled "Cross-Point Memory Array and Related Fabrication Techniques", U.S. Patent Application No. 15 / 961,547 to Castro et al. titled "Cross-Point Memory Array and Related Fabrication Techniques", and U.S. Patent Application No. 15 / 961,550 to Castro et al. titled "Buried Lines and Related Fabrication Techniques", the entire text of each of which is hereby expressly incorporated by reference. The vias can be formed at the top layer of a composite stack that can be used to construct multiple memory cell levels and array electrodes in a region and TFTs in different regions. As used herein, a via can refer to an opening or an opening that can be used to form associated via holes and other structures below a material (layer, surface) containing the opening, which includes an opening that is later filled with a material (which can include a non-conductive material).

[0030] Accordingly, the manufacturing techniques, methods, and related apparatus described herein can facilitate a flexible sequence of fabricating TFTs relative to fabricating multiple memory cell levels and array electrodes. This flexibility can provide optimized process steps to mitigate various unwanted factors associated with various processing conditions, such as thermal effects on the memory cells, the risk of cross-contamination with materials used for the memory cells (e.g., chalcogenide materials), and the like. As an example, the TFTs can be formed prior to fabricating the memory cells to reduce the thermal budget (e.g., the sum of the durations of the processing steps at various temperatures) for maintaining the memory cells. In some cases, the manufacturing techniques, methods, and related apparatus described herein can provide a reduction in the cost of manufacturing 3D memory devices because the same composite stack of materials can be used to fabricate the TFTs and to fabricate multiple memory cell levels and array electrodes.

[0031] The manufacturing techniques, methods, and related apparatus described herein can support the selection (or inhibition) of memory cell levels disposed in a cross-point architecture. For example, each memory cell level in a cross-point architecture can include a set of first access lines (e.g., word lines, first array electrodes) in a first plane and a set of second access lines (e.g., bit lines, second array electrodes) in a second plane, where the first access lines and the second access lines extend in different directions. For instance, the first access lines can be substantially perpendicular to the second access lines. Each topological intersection of the first access lines and the second access lines can correspond to a memory cell. Thus, a memory cell level in a cross-point architecture can include a memory array having a set of memory cells placed at the topological intersections of the access lines (e.g., a 3D grid structure of the access lines). As described herein, TFTs (e.g., memory level selectors / inhibitors) can be fabricated in an array layer that includes multiple memory cell levels and array electrodes. Accordingly, the TFTs can be coupled to the access lines (e.g., word lines, bit lines, first array electrodes, second array electrodes) and thus support the selection (and access) of multiple memory cell levels disposed in a cross-point architecture.

[0032] In addition, the TFT can support various cross-point architectures, such as a tiled architecture or derivatives thereof. The tiled architecture in the context of a memory device may refer to an array of memory cells comprising a set of memory tiles, each of the set of memory tiles comprising a similar configuration of components (e.g., word line decoders, bit line decoders, sensing components, a subgroup of the memory cell array) similar to the arrangement of the patches in a mosaic tile. The memory tiles can be considered as the building blocks (e.g., modular building blocks) of the memory cell array of a memory device adopting a tiled architecture. In this way, the memory cell array of the memory device can be expanded or shrunk by increasing or decreasing the number of memory tiles. In other words, a cross-point architecture may refer to a memory array comprising a topological cross-point of a first access line and a second access line, where each topological cross-point corresponds to a memory cell, and a tiled architecture may refer to constructing an array by arranging a set of memory tiles each forming a subgroup of the memory cell array.

[0033] The configuration of the TFT can be varied (e.g., the associated geometry and structure can be varied) to meet various constraints or requirements. In some cases, the relevant constraints and requirements of the TFT may be based on the select function and suppression (e.g., deselection) functions provided by one or more TFTs. For example, the TFT can be configured to provide a specific current driving capability (e.g., select function) when activated. Additionally or alternatively, the TFT can be configured to maintain an acceptably low leakage current (e.g., suppression function) when deactivated. In some cases, multiple (e.g., two) sets of TFTs can be constructed for each array electrode within a memory cell level. For example, one set of TFTs can be configured to actively drive the array electrode of the memory cell level when selecting the memory cell level (e.g., provide the desired or required drive current). Additionally or alternatively, another set of TFTs can be configured to drive a suppression level (e.g., maintain a low leakage current) when suppressing (e.g., not accessing, deselecting) the memory cell level. In some cases, multiple sets of TFTs present in a single device can be processed in different ways with respect to each other to optimize for the current driving capabilities and voltage ranges that the multiple sets of TFTs can jointly support (e.g., one set of TFTs can be optimized for drive current capability while another set of TFTs can be optimized for low leakage current capability).

[0034] In some cases, a control gate of a TFT (e.g., a gate electrode) may be formed within the same layer in which a memory element (e.g., an element configurable to store information, such as a chalcogenide element) is formed. The control gate of the TFT may determine a path for current to flow between a first electrode (e.g., a drain) of the TFT and a second electrode (e.g., a source) of the TFT. In some cases, based on how the channel of the TFT is formed relative to the gate electrode, first electrode, and second electrode of the TFT, the path of current flow may be vertical, horizontal, or a combination of both. In some cases, the channel of the TFT may be coupled to a bulk connection of a node of the underlying CMOS circuitry to control the electrical characteristics of the channel that may vary based on various functions (e.g., a select function, an inhibit function, or other functions) that the TFT may perform.

[0035] In addition, the manufacturing techniques, methods, and related devices described herein may facilitate constructing one or more composite circuits, such as circuits that include various combinations of TFTs (e.g., TFT-based decoder units) within a plane of an array layer. For example, a TFT-based decoder unit may perform cluster-level decoding to activate (or deactivate) a particular tile within a tile cluster. Additionally or alternatively, another TFT-based decoder unit may perform tile-level decoding to activate a particular access line from a set of access lines included within a tile. The manufacturing techniques and methods described herein may also be used to construct crossover regions where a first set of electrodes of a first group of TFTs may span a second set of electrodes of a second group of TFTs without causing a short circuit between the first set and second set of electrodes.

[0036] The features of the present disclosure introduced above are further described herein in the context of various TFT structures and TFT-based circuits in a composite stack of construction materials (which may also be used to construct a memory array in a cross-point architecture). Specific examples of structures and techniques for manufacturing the TFT structures and TFT-based circuits are then described. These and other features of the present disclosure are further illustrated and described with reference to device diagrams, formation method diagrams, and flowcharts related to the TFTs and associated manufacturing techniques.

[0037] Figure 1 An example memory device 100 including a three-dimensional memory cell array that supports memory array decoding and interconnects is illustrated in accordance with an embodiment of the present disclosure. Memory device 100 may also be referred to as an electronic memory device. Figure 1 is an illustrative diagram of the various components and features of memory device 100. Thus, it should be understood that the components and features of memory device 100 are shown to illustrate functional interrelationships, rather than their actual physical locations within memory device 100.

[0038] In Figure 1In an illustrative example, memory device 100 includes a three-dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 that are programmable to store different states. In some embodiments, each memory cell 105 is programmable to store two states represented as logic 0 and logic 1. In some embodiments, the memory cells 105 may be configured to store more than two logic states (e.g., multi-level cells). In some embodiments, the memory cells 105 may include self-selecting memory cells. It should be understood that the memory cells 105 may also include another type of memory cell, such as 3D XPoint TM memory cells, PCM cells including a storage component and a selection component, electro-bridge RAM (CBRAM) cells, or FeRAM cells. Although Figure 1 some of the elements included in are marked with numerical indicators, other corresponding elements are not marked, but they are the same or should be understood as similar in an attempt to enhance the visibility and clarity of the depicted features.

[0039] The 3D memory array 102 may include more than two two-dimensional (2D) memory arrays (e.g., array layers including more than two memory cell levels and array electrodes) stacked on top of each other. This can increase the number of memory cells that can be placed or fabricated on a single die or substrate compared to a single 2D array, which in turn can reduce production costs or improve the performance of the memory device or both. In Figure 1 the depicted example, the memory array 102 includes two levels of memory cells 105 (e.g., memory cells 105-a and memory cells 105-b) and can thus be considered a 3D memory array; however, the number of levels is not limited to 2, and other examples may include additional levels (e.g., 4 levels, 8 levels, 16 levels, 32 levels). Each level may be aligned or positioned such that the memory cells 105 can be (fully, overlapping, or substantially) aligned with each other across each level to thus form a memory cell stack 145. In some cases, a memory cell level may be referred to as a memory cell plane.

[0040] In some embodiments, each row of memory cells 105 is connected to a word line 110, and each column of memory cells 105 is connected to a bit line 115. Both the word line 110 and the bit line 115 may also be collectively referred to as access lines. Additionally, an access line may serve as the word line 110 for one or more memory cells 105 (e.g., memory cells 105 below the access line) at a level of the memory device 100 and as the bit line 115 for one or more memory cells 105 (e.g., memory cells 105 above the access line) at another level of the memory device. Thus, without loss of understanding or operation, references to word lines and bit lines or their equivalents may be interchangeable. The word line 110 and the bit line 115 may be substantially perpendicular to each other and may support the memory cell array.

[0041] Memory cell 105 can generally be located at the intersection of two access lines, such as word line 110 and bit line 115. This intersection can be referred to as the address of memory cell 105. The target memory cell 105 can be the memory cell 105 located at the intersection of the energized (e.g., activated) word line 110 and the energized (e.g., activated) bit line 115; that is, both the word line 110 and the bit line 115 can be energized to read or write the memory cell 105 at their intersection. Other memory cells 105 that are in electronic communication (e.g., connected to the same word line 110 or bit line 115) with the same word line 110 or bit line 115 can be referred to as non-target memory cells 105.

[0042] As Figure 1 shown, two memory cells 105 in memory cell stack 145 can share a common conductive line, such as bit line 115. That is, bit line 115 can be coupled to upper memory cell 105-b and lower memory cell 105-a. Other configurations may be possible; for example, a third layer (not shown) can share word line 110 with upper memory cell 105-b.

[0043] In some cases, an electrode can couple memory cell 105 to word line 110 or bit line 115. The term electrode can refer to an electrical conductor and can include traces, wires, conductive lines, conductive layers, or the like that provide an electrical conduction path between elements or components of memory device 100. Thus, the term electrode can refer to an access line (such as word line 110 or bit line 115) in some cases and can refer to an additional conductive element that serves as an electrical contact between the access line and memory cell 105 in some cases. In some embodiments, memory cell 105 can include a chalcogenide material located between a first electrode and a second electrode. The first electrode can couple the chalcogenide material to word line 110, and the second electrode couples the chalcogenide material to bit line 115. The first electrode and the second electrode can be the same material (such as carbon) or different materials. In other embodiments, memory cell 105 can be directly coupled to one or more access lines, and electrodes other than the access lines can be omitted.

[0044] Operations such as reading and writing can be performed on memory cell 105 by activating or selecting word line 110 and digit line 115. Activating or selecting word line 110 or digit line 115 can include applying a voltage to the corresponding line. Word line 110 and digit line 115 can be made of a conductive material, such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, a conductive doped semiconductor, or other conductive materials, alloys, compounds, or the like.

[0045] In some architectures, the logic storage devices of the cells (e.g., the resistive component in a CBRAM cell, the capacitive component in a FeRAM cell) can be electrically isolated from the digital lines by a selection component. The word line 110 can be connected to the selection component and can control the selection component. For example, the selection component can be a transistor and the word line 110 can be connected to the gate of the transistor. Alternatively, the selection component can be a variable resistive component, which can include a chalcogenide material. Activating the word line 110 results in an electrical connection or a closed circuit between the logic storage device of the memory cell 105 and its corresponding digital line 115. Subsequently, the digital line can be accessed to read from or write to the memory cell 105. After selecting the memory cell 105, the resulting signal can be used to determine the stored logic state. In some cases, the first logic state can correspond to no current or a weak current passing through the memory cell 105, while the second logic state can correspond to a finite current.

[0046] In some cases, the memory cell 105 can include a self - selecting memory cell having two terminals, and the separate selection component can be omitted. Thus, the terminals of the self - selecting memory cell can be electrically connected to the word line 110 and the other terminal of the self - selecting memory cell can be electrically connected to the digital line 115.

[0047] Access to the memory cell 105 can be controlled by a row decoder 120 and a column decoder 130. For example, the row decoder 120 can receive a row address from the memory controller 140 and activate an appropriate word line 110 based on the received row address. In some cases, the row decoder 120 can include multiple sets of TFTs for selecting a particular tier of the 3D memory array 102. For example, the row decoder 120 can include a first set of TFTs associated with the lower tier (e.g., the memory tier containing the memory cell 105 - a) to select the lower tier and a second set of TFTs associated with the upper tier (e.g., the memory tier containing the memory cell 105 - b) to inhibit (e.g., deselect) the upper tier. In some cases, the TFTs can be co - located in the array layer containing the 3D memory array 102. In some cases, the TFTs located in the array layer can be coupled to the row decoder 120, and the row decoder 120 can be located in the substrate above which the 3D memory array 102 is located. Similarly, the column decoder 130 can receive a column address from the memory controller 140 and activate an appropriate digital line 115. In some cases, similar to the row decoder 120, the column decoder 130 can include additional multiple sets of TFTs for selecting a particular tier of the 3D memory array 102. For example, the memory array 102 can include multiple word lines 110 labeled WL_1 to WL_M and multiple digital lines 115 labeled DL_1 to DL_N, where M and N depend on the array size. Thus, the memory cell 105 at the intersection can be accessed by activating the word line 110 and the digital line 115 (e.g., WL_2 and DL_3).

[0048] After access, the memory cell 105 can be read or sensed by the sensing component 125 to determine the storage state of the memory cell 105. For example, a voltage can be applied to the memory cell 105 (using the corresponding word line 110 and bit line 115), and the presence of a resulting current passing through the memory cell 105 can depend on the applied voltage and the threshold voltage of the memory cell 105. In some cases, more than one voltage can be applied. Additionally, if the applied voltage does not result in current flow, other voltages can be applied until a current is detected by the sensing component 125. The storage logic state of the memory cell 105 can be determined by evaluating the voltage that causes current flow. In some cases, the voltage can be ramped up in magnitude until current flow is detected. In other cases, a predetermined voltage can be applied sequentially until a current is detected. Similarly, a current can be applied to the memory cell 105 and the magnitude of the voltage that produces the current can depend on the resistance or threshold voltage of the memory cell 105.

[0049] In some cases, the memory cell 105 (e.g., a self - select memory cell) can include a chalcogenide material. The chalcogenide material of the self - select memory cell can remain in an amorphous state during the operation of the self - select memory cell. In some cases, operating the self - select memory cell can include applying programming pulses of various shapes to the self - select memory cell to determine a specific threshold voltage of the self - select memory cell, i.e., the threshold voltage of the self - select memory cell can be modified by changing the shape of the programming pulse, which can alter the local composition of the chalcogenide in the amorphous state. The specific threshold voltage of the self - select memory cell can be determined by applying reading pulses of various shapes to the self - select memory cell. For example, when the applied voltage of the reading pulse exceeds the specific threshold voltage of the self - select memory cell, a limited amount of current can flow through the self - select memory cell. Similarly, when the applied voltage of the reading pulse is less than the specific threshold voltage of the self - select memory cell, no appreciable amount of current can flow through the self - select memory cell.

[0050] In some embodiments, the sensing component 125 can read the information stored in the memory cell 105 by detecting current or no current flow through the selected memory cell 105. In this way, the memory cell 105 (e.g., a self - select memory cell) can store one bit of data based on the threshold voltage level (e.g., two threshold voltage levels) associated with the chalcogenide material, where the threshold voltage level when current flows through the memory cell 105 indicates the logic state stored by the memory cell 105. In some cases, the memory cell 105 can exhibit a specific number of different threshold voltage levels (e.g., three or more threshold voltage levels) to thereby store more than one bit of data.

[0051] The sense component 125 may include various transistors or amplifiers to detect and amplify a signal difference associated with the sensed memory cell 105, which may be referred to as latching. Subsequently, the detected logic state of the memory cell 105 may be output as output 135 by the column decoder 130. In some cases, the sense component 125 may be part of the column decoder 130 or the row decoder 120. Alternatively, the sense component 125 may be connected to or in electronic communication with the column decoder 130 or the row decoder 120. Figure 1 An alternative option of arranging the sense component 125-a (shown as a dashed box) is also shown. One of ordinary skill in the art will appreciate that the sense component 125 may be associated with the column decoder or the row decoder without losing its functional use.

[0052] The memory cell 105 may be set or written by similarly activating the associated word line 110 and digit line 115, and at least one logic value may be stored in the memory cell 105. The column decoder 130 or the row decoder 120 may receive data written to the memory cell 105, such as input / output 135.

[0053] In some memory architectures, accessing the memory cell 105 may degrade or corrupt the stored logic state, and a rewrite or refresh operation may be performed to restore the memory cell 105 to its original logic state. For example, in DRAM, the capacitor may be partially or fully discharged during a sense operation to destroy the stored logic state, and thus the logic state may be rewritten after the sense operation. Additionally, in some memory architectures, activating a single word line 110 may cause all memory cells in a row (e.g., coupled to the word line 110) to discharge; thus, it may be necessary to rewrite some or all of the memory cells 105 in the row. However, in non-volatile memories (such as self-selecting memories, PCM, CBRAM, FeRAM, or NAND memories), accessing the memory cell 105 does not corrupt the logic state, and thus the memory cell 105 may not need to be rewritten after access.

[0054] The memory controller 140 may control the operations (e.g., read, write, rewrite, refresh, discharge) of the memory cells 105 through various components such as a row decoder 120, a column decoder 130, and a sense component 125. In some cases, one or more of the row decoder 120, the column decoder 130, and the sense component 125 may be co-located with the memory controller 140. The memory controller 140 may generate row and column address signals to activate the desired word lines 110 and digit lines 115. The memory controller 140 may also generate and control various voltages or currents used during operation of the memory device 100. Generally, the amplitude, shape, polarity, and / or duration of the applied voltage or current discussed herein may be adjusted or varied and may differ for the various operations discussed in operating the memory device 100. Additionally, one, multiple, or all of the memory cells 105 within the memory array 102 may be accessed simultaneously; for example, multiple or all of the cells of the memory array 102 may be accessed simultaneously during a reset operation in which all of the memory cells 105 or a group of the memory cells 105 are set to a single logical state.

[0055] In some cases, the lower word line 110 ( Figure 1 labeled as WL_B1 in Figure 1 ), the upper word line 110 ( Figure 1 labeled as WL_T1 in Figure 1 ), and lines at any number of additional levels (not shown) may be formed simultaneously. Additionally, both the lower word line 110 and the upper word line 110 may be disposed (formed) in a layer initially including the same dielectric material, and a single via pattern may be used for one or more processing steps to simultaneously form the lower-level word line 110 and the upper-level word line 110 at their respective layers, such as removing portions of the dielectric material and replacing them with conductive material. Similarly, the lower memory cells 105 (e.g., Figure 1 the memory cell 105-a illustrated as a solid black circle in Figure 1 ), the upper memory cells 105 (e.g., Figure 1 the memory cell 105-b illustrated as a white circle in Figure 1 ), and memory cells 105 at any number of additional levels of the memory cells (not shown) may be formed simultaneously. In some cases, the 3D memory array 102 may be located above a substrate including various circuitry such as the row decoder 120, the sense component 125, the column decoder 130, or the like.

[0056] [[ID=e25]]Figure 2 An example of a 3D memory array 202 that supports memory array decoding and interconnects in accordance with an embodiment of the present disclosure is illustrated. The 3D memory array 202 may be a reference Figure 1An example of the described memory array 102 or a portion of a 3D memory device including more than two memory cell levels. The 3D memory array 202 can include a first array or level 205-a of memory cells positioned above a substrate 204 and a second array or level 205-b of memory cells on top of the first array or level 205-a. The 3D memory array 202 can also include word lines 110-a and 110-b and bit lines 115-a, which can be reference Figure 1 Examples of the described lines 110 and bit lines 115. As Figure 2 In the illustrative example depicted in, the memory cells of the first level 205-a and the second level 205-b can each include self-selecting memory cells. In some examples, the memory cells of the first level 205-a and the second level 205-b can each include another type of memory cell suitable for a cross-point architecture, such as a CBRAM cell or a FeRAM cell. Although Figure 2 Some of the elements included in are labeled with numerical designators, and other corresponding elements are not labeled, but they are the same or should be understood as similar in an attempt to enhance the visibility and clarity of the depicted features.

[0057] In some cases, the memory cells of the first level 205-a can each include a first electrode 215-a, a chalcogenide material 220-a, and a second electrode 225-a. Additionally, the memory cells of the second level 205-b can each include a first electrode 215-b, a chalcogenide material 220-b, and a second electrode 225-b. In some embodiments, access lines (such as word lines 110, bit lines 115) can include an electrode layer (such as a conformal layer) instead of electrodes 215 or 225 and can thus include multi-layer access lines. In such embodiments, the electrode layer of the access line can be in contact with the memory material (such as chalcogenide material 220). In some embodiments, access lines (such as word lines 110, bit lines 115) can be in direct contact with the memory material (such as chalcogenide material 220), with no electrode layer or electrode therebetween.

[0058] In some embodiments, the memory cells of the first level 205-a and the second level 205-b can have a common conductive line such that corresponding (e.g., vertically aligned along the y-direction) memory cells of each level 205-a and 205-b can share a bit line 115 or a word line 110, as referenced Figure 1 described. For example, both the first electrode 215-b of the second level 205-b and the second electrode 225-a of the first level 205-a can be coupled to the bit line 115-a such that the bit line 115-a is shared by (vertically aligned and adjacent) memory cells (along the y-direction).

[0059] In some embodiments, the 3D memory array 202 may include additional bit lines (not shown) such that the first electrode 215-b of the second tier 205-b may be coupled to the additional bit lines and the second electrode 225-a of the first tier 205-a may be coupled to the bit line 115-a. The additional bit lines may be electrically isolated from the bit line 115-a (e.g., an insulating material may be inserted between the additional bit lines and the bit line 115-a). Thus, the first tier 205-a and the second tier 205-b may be separated and may operate independently of each other. In some cases, an access line (e.g., a word line 110 or a bit line 115) may include a selection component (e.g., a two-terminal selector device, which may be configured as one or more thin film materials integrated with the access line) for a respective memory cell at each intersection. Thus, the access line and the selection component may together form a composite material layer that serves as both the access line and the selection component.

[0060] In some cases, the architecture of the 3D memory array 202 may be referred to as an example of a cross-point architecture because memory cells may be formed at the topological intersections between the word lines 110 and the bit lines 115, as Figure 2 illustrated. This cross-point architecture may provide relatively high density data storage at a lower production cost than some other memory architectures. For example, a memory array with a cross-point architecture may have memory cells with a reduced area and may thus support a higher memory cell density than some other architectures. For example, compared to other architectures (e.g., an architecture with a three-terminal selection component) having a 6F 2 memory cell area, the cross-point architecture may have a 4F 2 memory cell area, where F is the minimum feature size (e.g., the minimum feature size). For example, a DRAM memory array may use transistors (e.g., thin film transistors), which are three-terminal devices, as the selection component for each memory cell. Thus, a DRAM memory array including a given number of memory cells may have a larger memory cell area than a memory array with a cross-point architecture including the same number of memory cells.

[0061] Although Figure 2Examples show two memory levels, but other configurations may include any number of levels (e.g., 4 levels, 8 levels, 16 levels, 32 levels). In some embodiments, one or more memory levels may include select memory cells that include a chalcogenide material 220. In other embodiments, one or more memory levels may include FeRAM cells that include a ferroelectric material. In other embodiments, one or more memory levels may include CBRAM cells that include a metal oxide or chalcogenide material. For example, the chalcogenide material 220 may include a chalcogenide glass, such as an alloy of (e.g.) selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some embodiments, a chalcogenide material that primarily has selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy.

[0062] In some cases, the lines 110-a, word lines 110-b, and bit lines 115-a of the 3D memory array 202 may be referred to as array electrodes. As described herein, a set of TFTs may be constructed in the array layer such that a subgroup of the set of TFTs may be coupled to array electrodes (e.g., word lines 110, bit lines 115) of a level of the memory array (e.g., the first level of memory cell 205-a, the second level of memory cell 205-b). In some cases, the set of TFTs may be coupled to circuitry (e.g., CMOS circuitry below the array layer) in the substrate 204 to facilitate various functions of the circuitry. For example, the set of TFTs may select a particular level of the memory array (e.g., select function) based on an input from the circuitry (e.g., a decoded result associated with an access command) and at the same time deselect more than two levels of the memory array (e.g., inhibit function). In some cases, the set of TFTs may perform a more advanced function (e.g., full decoding function) to share one or more functions that may otherwise be implemented by the circuitry.

[0063] FIGS. 3-6 illustrate various aspects of the manufacturing techniques of the present disclosure. For example, various cross-sectional views may illustrate the parallel nature of generating specific structures (e.g., source, drain, gate, and channel of a TFT) at one or more buried target layers of a composite stack, each target layer including a target material. As described herein, in some cases, vias (e.g., access vias) may be used to generate structures in the target material at the target buried layer. Various top views may illustrate how a particular set of vias may be used to generate various structures of a TFT. The manufacturing techniques described herein may facilitate the simultaneous formation of the same structures at different lower layers, such as a set of gate electrodes of a TFT or a set of channel material elements of a TFT. Thus, the manufacturing techniques described herein may facilitate the simultaneous formation of a set of TFTs in an array layer that includes more than two memory cell levels, each level including access lines (e.g., word lines, bit lines, array electrodes) and a 3D cross-point structure of memory cells.

[0064] Figures 3A to 3L Describe exemplary manufacturing techniques according to the present disclosure. Figures 3A to 3L Describe aspects of several process steps for simultaneously fabricating more than two TFTs (e.g., TFTs that can be referred to as vertical TFTs in which current flows in a direction perpendicular to a horizontal substrate when the TFT is activated). In some cases, such TFTs can be fabricated in the socket region of an array layer. In some cases, the TFT can be referred to as an array electrode driver. The socket region can refer to an area of the array layer where various interconnects can be formed (e.g., interconnects between the TFT and underlying circuitry (such as the logic circuitry in substrate 204, row decoder 120 described with reference to Figure 2 the interconnects between the TFT and the ends of array electrodes (such as lines 110 and / or bit lines 115 described with reference to Figure 2 ). Figures 3A to 3L A top view (e.g., layout of the socket region) including a portion of the socket region is provided to illustrate various structures in which different via groups can be used to simultaneously fabricate TFTs. Figures 3A to 3L A cross-sectional side view including a portion of the socket region is also provided to illustrate aspects of process features during several process steps for simultaneously fabricating TFTs.

[0065] Figure 3A A cross-sectional side view of a stack 305 including several different layers that can include various materials is provided. In some cases, the stack can be referred to as a composite stack. In some cases, stack 305 can be located above a substrate (such as substrate 204 described with reference to Figure 2 ). The specific materials of stack 305 can be selected based on a number of factors (such as the desired type of memory technology (e.g., self-selective memory, FeRAM, CBRAM), the desired number of memory cell levels (e.g., more than two memory cell levels)). As depicted in the illustrative example of Figure 3A stack 305 can include an initial layer stack suitable for fabricating two memory cell levels (e.g., a first level 205-a of memory cells located above substrate 204 and a second array or level 205-b of memory cells on top of the first array or level 205-a, as described with reference to Figure 2 ).

[0066] Stack 305 can include a layer 310, which can be the top layer of stack 305. In some embodiments, layer 310 includes a dielectric material. In some embodiments, layer 310 includes a hard mask material such that layer 310 can be referred to as a hard mask (HM) layer. Via patterns can be formed in layer 310 due to (e.g.,) a lithography step. In some cases, this lithography step can form a first set of vias (e.g., Figure 3BThe third group of vias 340-c) and the second group of vias (such as Figure 3B the vias 340-b) of the second group shown in

[0067] The stack 305 may also include a layer 315. In the Figure 3A illustrative example, the stack 305 includes two layers 315 (i.e., layer 315-a and layer 315-b), but any number of layers is feasible. In some embodiments, each layer 315 may include a first dielectric material (which may also be referred to as D1). As described herein, each layer 315 may be modified to include a set of first array electrodes (such as electrode pads or electrode segments, conductive lines, access lines, word lines). In some cases, each layer 315 may be referred to as a first layer, a first electrode layer, or a D1 layer.

[0068] The stack 305 may also include a layer 320. In the Figure 3A illustrative example, the stack 305 includes two layers 320 (i.e., layer 320-a and layer 320-b), but any number of layers 320 is feasible. In some embodiments, each layer 320 may include a placeholder material, which may later be partially removed and replaced with a desired material (such as a memory material, a gate electrode material, a semiconductor material). In some embodiments, each layer 320 may initially include a memory material, which may be processed to form one or more memory elements. In some cases, the layer 320 may be referred to as a second layer, a memory layer, or a DM layer.

[0069] The stack 305 may also include a layer 325. In the Figure 3A illustrative example, the stack 305 includes a single layer 325, but any number of layers 325 is feasible. In some embodiments, each layer 325 may include a second dielectric material (which may be referred to as D2). As described herein, the layer 325 may be modified to include a set of second array electrodes (such as electrode pads, conductive lines, access lines, bit lines). In some cases, each layer 325 may be referred to as a third layer, a second electrode layer, or a D2 layer.

[0070] The stack 305 may include a layer 330. In some cases, the layer 330 may include an etch stop material to withstand the various etching processes described herein. In some cases, the layer 330 may include the same hard mask material as the layer 310, or may include a different material. In some cases, the layer 330 may provide a buffer layer with respect to the circuits or other structures formed in a substrate (such as the substrate 204 described with reference to Figure 2 or other layers (not shown) that may be located below the layer 330. In some cases, the layer 330 may provide a buffer layer with respect to one or more memory cell levels fabricated in earlier processing steps.

[0071] Figure 3BA top view of a stack 305 that can construct a socket area including more than two TFTs (e.g., vertical TFTs) as described herein. Figure 3B A set of vias 340 (depicted as white, gray, or hatched squares) in an array pattern is illustrated. Figure 3B Also illustrated are various structures that can be formed simultaneously within the stack 305 using different via groups (e.g., vias 340-a of the first group, vias 340-b of the second group, vias 340-c of the third group). For example, Figure 3B A set of array electrodes 350, a set of electrode pads 355 (depicted as dark shaded rectangles), and a set of gate electrodes 360 (one of which is depicted in the top view) are illustrated, each of which can be formed at different junctions of a process sequence to construct a TFT.

[0072] As described elsewhere, a first via subgroup (e.g., vias 340-a of the first group) can be used to construct a set of array electrodes 350 (e.g., array electrodes 350-c and 350-d). Additionally, a second via subgroup (e.g., vias 340-b of the second group depicted as gray squares) can be used to construct a set of electrode pads (e.g., electrode pad 355-b). In some cases, electrode pad 355-b can be the second electrode (e.g., drain) of a TFT at the first layer 315-a. In some cases, a channel (e.g., a series of merged cavities in a row) can be formed at the first layer (e.g., D1 layer 315-a, D1 layer 315-b) by using vias 340-b of the second group to construct an electrode pad, e.g., the channel is aligned with vias 340-b of the second group. The channel at the first layer can be filled with an electrode material (e.g., a conductive material). Subsequently, a set of dielectric plugs corresponding to vias 340-b of the second group can be formed to separate the electrode pad in D1 layer 315-a from another electrode pad in D1 layer 315-b. The dielectric plugs can extend through the electrode material filling the channel at the first layer.

[0073] In addition, a third via subgroup (e.g., vias 340-c of the third group) can be used to construct a set of gate electrodes 360 as described herein with reference to Figures 3C to 3F Furthermore, one or more vias (e.g., vias depicted as hatched squares that include vias 340-d, vias 340-e) can be used to split an array electrode (e.g., array electrode 350-f) into more than two segments. Thus, in some cases, an electrode pad (e.g., electrode pad 355-b) can be coupled to a single array electrode (e.g., array electrode 350-e). In some cases, an electrode pad (and thus one or more TFTs constructed therein) can be positioned between the two ends of a single array electrode. For example, an electrode pad (e.g., electrode pad 355-b) can be positioned substantially in the middle region of a single array electrode (e.g., array electrode 350-e).

[0074] In some cases, the array electrodes 350 can be access lines (e.g., word lines, bit lines, conductive lines) coupled to a set of memory cells in the active array region of the array layer or can be part of an access line. The active region can refer to the region of the array layer where the access lines and the set of memory cells form a memory cell array. In some cases, the memory cell array (e.g., the access lines and the set of memory cells) can be constructed according to a cross-point architecture in the active array region. In this manner, a set of TFTs formed in the socket region of the array layer can be coupled to the array electrodes 350 (and thus to the set of memory cells associated with the array electrodes 350) in the active array region of the array layer.

[0075] Figures 3C to 3F Illustrate a manufacturing technique for forming a set of gate electrodes 360 of the TFTs within the stack 305 using the vias 340-c of the third group. In some cases, before forming a set of gate electrodes 360 at layer 320, a set of array electrodes 350 and a set of electrode pads 355 may have been formed within the stack 305.

[0076] Figure 3C Illustrate a cross-sectional side view of the stack 305 after forming vias and traversing the dashed line AA shown Figure 3B The cross-sectional side view can correspond to a part of an electrode pad (e.g., Figure 3B the electrode pad 355-a shown) that includes the via 340-f. Figure 3C The electrode pads depicted (e.g., Figure 3C the electrode pads 355-c and 355-d shown) may have been previously formed in the D1 layer. The electrode pads 355-c and 355-d are depicted using a shaded pattern different from Figure 3A the original D1 layer (e.g., layer 315-a, layer 315-b) to indicate that Figure 3C the part of the D1 layer shown has been replaced by the electrode material forming the set of electrode pads 355. Figure 3C Figure 3C Also illustrate an opening 341 that can correspond to a cross-sectional side view of a via hole (e.g., a via hole corresponding to the via 340-f included in the vias 340-c of the third group).

[0077] ​In some cases, a lithography step may transfer the shape of via 340 onto stack 305. In some cases, the lithography step may include forming a photoresist layer (not shown) having the shape of via 340 (e.g., defined by the absence of photoresist material within via 340) on top of layer 310. In some instances, an etching process step may be performed after the lithography step to transfer the shape of via 340 onto layer 310 such that the shape of via 340 established within layer 310 may be reused as an access via during subsequent processing steps, i.e., layer 310 including the shape of via 340 may act as a hard mask layer providing an access via in the shape of via 340 for subsequent processing steps.

[0078] In some cases, an anisotropic etching process step may form an opening 341 through stack 305 and the width of opening 341 may be substantially the same as the width of a via (e.g., via 340-f). The anisotropic etching step may remove target material in one direction (e.g., an orthogonal direction relative to the substrate) by applying an etchant (e.g., a mixture of one or more chemical elements) to the target material. Additionally, the etchant may exhibit selectivity (e.g., chemical selectivity) for removing only the target material (e.g., the hard mask material at layer 310) while leaving other materials (e.g., photoresist) exposed to the etchant. When removing one or more layers of material (e.g., the first dielectric material at D1 layer 315, the placeholder material at DM layer 320, the second dielectric material at D2 layer 325), the anisotropic etching step may use one or more etchants during a single anisotropic etching step. In some cases, the anisotropic etching step may use an etchant that exhibits selectivity for removing a desired group of materials (e.g., oxides and nitrides) while leaving other groups of materials (e.g., metals) exposed to the etchant.

[0079] Figure 3D Illustrates a cross-sectional side view of stack 305 taken across dashed line AA after performing at least one etching process step and one deposition process step using a via hole (e.g., opening 341) formed within stack 305 as described with reference to Figure 3C as described.

[0080] In some cases, an etching process step may include an isotropic etching step that removes target material in all directions. In some cases, the isotropic etching step may apply an etchant that exhibits selectivity (e.g., chemical selectivity) for removing only the target material (e.g., the placeholder material in DM layer 320) while preserving other materials (e.g., the electrode material of electrode pads 355-c or 355-d, the second dielectric material of D2 layer, the hard mask material of HM layer) exposed to the etchant (e.g., a mixture of one or more chemical elements). When removing one or more layers of material, the isotropic etching step may employ different etchants during a single isotropic etching step. In some cases, the isotropic etchant (e.g., the etchant used in the isotropic etching step) may be chemically selected between the first dielectric material and at least one other material in the stack. In this manner, the etching process step may form a series of cavities within each DM layer, such as a series of cavities 342 corresponding to vias 340-c of the third group. When the overlapping cavities (e.g., adjacent cavities, such as cavity 342-a and the next cavity (not shown) within DM layer 320-a) are completely overlapped, the overlapping cavities may merge to form a channel at the DM layer. In this manner, a channel may be formed at a second layer (e.g., layer 320-a, layer 320-b) that can be aligned with a first set of vias (e.g., vias 340-c of the third group shown in Figure 3B .

[0081] Still referring to Figure 3D , a deposition process step may be performed after the etching process step to form a layer of insulating material (e.g., insulating layer 365) on the surfaces of cavities 342 (and thus the channels) and via holes (e.g., opening 341). In some cases, insulating layer 365 may be conformal (e.g., maintain a substantially uniform thickness) with the non-uniform surface across at least two layers (e.g., across electrode pad 355-c and recessed DM layer 320-a and then D2 layer 325). In some cases, insulating layer 365 may facilitate the formation of crossover regions as described herein. In some cases, the deposition process step may form an insulating layer 365 that is conformal with the channels.

[0082] Figure 3E FIG. shows a cross-sectional side view of stack 305 along dashed line AA after completing at least one deposition process step. The deposition process step may be based on the use of via holes (e.g., already shown by reference Figure 3DThe described insulating layer 365 partially fills the opening 341) to form the insulating layer 365 to fill the channels formed in the DM layer (e.g., DM layers 320-a and 320-b). In some cases, the deposition process step may deposit the electrode material 361. The electrode material 361 may form a set of gate electrodes 360. In some cases, the electrode material 361 may include polysilicon, refractory metal elements (such as tungsten, titanium, tantalum), or their nitrides, or a combination thereof. In some cases, the extra electrode material 361 that may be present above the HM layer 310 may be removed by using a chemical mechanical polishing (CMP) process step or an etch-back process step.

[0083] Figure 3F A cross-sectional side view of the stack 305 across the dashed line AA after at least one etching process step of using the vias 340-c of the third group to remove the electrode material 361 from the via holes is illustrated. Figure 3F The opening 341-a corresponding to the cross-sectional side view of the via hole (e.g., the via hole corresponding to the via 340-f included in the vias 340-c of the third group) is also illustrated. In some cases, the anisotropic etching process step may form the opening 341-a and the width of the opening 341-a may be substantially the same as the width of the via (e.g., via 340-f). Since the anisotropic etching process step removes the electrode material 361 from the via hole, the electrode material (e.g., electrode material 361-a in the DM layer 320-a) in one DM layer may be separated from the electrode material (e.g., electrode material 361-b in the DM layer 320-b) in another DM layer. In this way, more than two gate electrodes (e.g., a set of gate electrodes 360) may be formed in the stack 305 simultaneously.

[0084] Figure 3G A cross-sectional side view of the stack 305 across the dashed line AA after at least one etching process step and deposition process step (as described with reference to Figure 3F is illustrated) using the via holes (e.g., opening 341-a) formed in the stack 305.

[0085] In some cases, the etching process step may include a selective isotropic etching step, which may selectively remove the electrode material 361 while retaining the rest of the stack 305 exposed to the isotropic etching process. Due to the isotropic etching step, the electrode material 361 (e.g., electrode materials 361-a and 361-b) in the DM layer may be recessed, as Figure 3GAs shown. In some cases, isotropic etching can remove a portion of the gate electrode (e.g., gate electrode 360 including electrode material 361) to form a cavity at the second layer (e.g., layer 320). In some cases, the etching process steps may also include an anisotropic etching step that selectively removes a portion of layer 330 (e.g., the hard mask material at layer 330) to create a hole (e.g., opening 341-b at layer 330) through layer 330. In some cases, the width of opening 341-b may be substantially the same as the width of opening 341-a. Opening 341-b may be coupled to a conductive element 385 that may be part of a logic circuit system layer. For example, conductive element 385 may represent a node of a circuit system in the substrate (e.g., row decoder 120 constructed in substrate 204). In another example, conductive element 385 may be coupled to a node of row decoder 120 (e.g., a node where a select signal exists) to activate one or more levels of the array layer.

[0086] Still referring to Figure 3G , the deposition step can use a via (e.g., via hole 341-a) to form an oxide material 370 above the exposed surface of the electrode material 361. In this way, the oxide material 370 can be formed in the cavity at the second layer (e.g., layer 320), where the oxide material 370 can contact the gate electrode 360 including the electrode material 361. In some cases, the oxide material 370 may be referred to as a gate oxide that may be present between the gate electrode and the active channel region of a TFT. The deposition step can be a selective oxidation step or a selective deposition step that can be configured to form the oxide material 370 only above the exposed surface of the electrode material 361.

[0087] Figure 3H Illustrates a cross-sectional side view of stack 305 taken across dashed line AA after performing at least a first etching process step, a deposition process step, and a second etching process step using a via hole (e.g., opening 341-a) formed within stack 305 as described with reference to Figure 3G . The first etching process step can include an isotropic etching step that removes a portion of the electrode sheet 355 (e.g., the second electrode of a TFT), e.g., selectively removes the exposed electrode material of the electrode sheet 355 within the via hole 341-a. The isotropic etching step can form one or more cavities at the first layer (e.g., layer 315).

[0088] Subsequently, an ohmic material 375 can be formed to fill the vias 341-a and the spaces (such as cavities) associated with the vias 341-a, such as the cavities at the D1 layer (such as layer 315) generated by removing part of the electrode sheet 355, and the spaces at the DM layer (such as layer 320) generated by removing the electrode material 361. Thus, the ohmic material 375 can contact the second electrode (such as the electrode sheet 355). In some cases, the ohmic material 375 can provide an ohmic contact between the electrode material (such as the electrode sheet 355-c or 355-d) and the semiconductor material (such as the semiconductor material 380) to be formed later (for example, as referred to in Figure 3I the semiconductor material 380 described).

[0089] The ohmic material can be a material configured to provide a current path between a conductive material (such as the electrode sheet 355-c or 355-d) and a semiconductor material (such as the semiconductor material 380) that has a bidirectionally uniform or at least substantially uniform resistance. That is, the current path from the conductive material through the ohmic material to the semiconductor material can exhibit the same or substantially the same resistance as the current path from the semiconductor material through the transition material to the ohmic material. Thus, the ohmic material can avoid a rectifying junction or other non-ohmic or directional contact or current path between the conductive material (such as the electrode sheet 355-c or 355-d) and the semiconductor material (such as the semiconductor material 380). In some cases, the ohmic material 375 can be referred to as a transition material. The ohmic material 375 can include various compounds that contain transition metal elements (such as titanium, cobalt, nickel, copper, tungsten, tantalum). The second etching process step can include an anisotropic etching step that uses the openings 341-a to remove the ohmic material 375 in the vertical direction within the vias. In this way, the ohmic material outside the vias (such as the ohmic material 375-a, the ohmic material 375-b) can remain intact.

[0090] Figure 3I Illustrate the use of vias (such as the open vias 341-a) formed in the stack 305 to perform at least one first etching process step, a first deposition process step, a second etching process step, and a second deposition step (as referred to in Figure 3HA cross-sectional side view of the stack 305 across the dashed line AA after (as described). The first etching process step may include an isotropic etching step that selectively removes portions of the ohmic material 375 exposed within the opening 341-a (e.g., the ohmic material 375-a at the D1 layer, a portion of the ohmic material 375-b at the DM layer). In this way, the isotropic etching step may form a cavity spanning the first layer (e.g., layer 315) and the second layer (e.g., layer 320). The first etching process step may also include an etching step that selectively removes the insulating layer 365 exposed due to the removal of portions of the ohmic material 375. The first deposition process step may use the semiconductor material 380 to fill the vias (e.g., opening 341-a) and the space created by the first etching process step (e.g., the cavity spanning the first and second layers). The second etching process step may use the opening 341-a to remove the semiconductor material 380 in the vertical direction within the via. The second deposition step may selectively form an insulating material 390 above the exposed surface of the semiconductor material 380 within the via such that the insulating material 390 can contact the semiconductor material 380. In some cases, the thickness of the insulating material 390 may be determined based on the second gate effect (e.g., to avoid the second gate effect).

[0091] Figure 3J Illustrates a cross-sectional side view of the stack 305 across the dashed line AA after performing at least one first etching process step, deposition process step, and second etching process step (as described with reference to the via (e.g., opening 341-a) formed within the stack 305). The first etching process step may include an anisotropic etching step that selectively removes a portion of the third layer (e.g., layer 325, D2 layer) to create a cavity therein. Subsequently, the deposition process step may use the ohmic material 375 (e.g., ohmic material 375-e) to fill the via and the cavity. The second etching process step may remove the ohmic material 375 in the vertical direction from the via such that the ohmic material (e.g., ohmic material 375-e) remains in the cavity at the third layer. The remaining ohmic material (e.g., ohmic material 375-e) at the third layer may contact the third electrode (e.g., the conductive plug 396 as described with reference to Figure 3I and Figure 3K and 3L ).

[0092] Figure 3K Illustrates performing at least one deposition process step (as described with reference to the via (e.g., opening 341-a) formed within the stack 305). Figure 3JCross-sectional side view of stack 305 across dashed line AA after (as described). The deposition process step may use electrode material 395 to fill the vias. In some cases, electrode material 395 may be the same as the electrode material of electrode sheet 355 or array electrodes 350. Due to using electrode material 395 to fill the vias (e.g., forming conductive plug 396), conductive element 385 (e.g., a node associated with a logic circuit system layer) may be coupled to ohmic material 375-e, and ohmic material 375-e contacts semiconductor material 380-a. Semiconductor material 380-a further coupled to the electrode material 361-a of gate electrode 360 (e.g., gate electrode 360 in contact with oxide material 370-a) through oxide material 370-a may form an active channel for current to flow based on the voltage applied to gate electrode 360. Additionally, semiconductor material 380-a contacts ohmic material 375-a, and ohmic material 375-a contacts electrode sheet 355-c.

[0093] Thus, Figure 3K A cross-sectional side view of TFTs (e.g., two vertical TFTs 335-a and 335-b) constructed in a socket area including array layer including stack 305 can be illustrated. Conductive plug 396 (e.g., a via filled with electrode material 395) may act as a common source electrode of the TFT, such as a third electrode extending through the third layer (e.g., layer 325). Conductive plug 396 may further be coupled to conductive element 385 (e.g., a node associated with a logic circuit system). Semiconductor material 380-a surrounding conductive plug 396 may act as the active channel of upper TFT 335-a. Similarly, semiconductor material 380-b surrounding conductive plug 396 may act as the active channel of lower TFT 335-b. Electrode sheet 355-c coupled to semiconductor material 380-a (e.g., through ohmic material 375-a) may act as the drain of upper TFT 335-a. Similarly, electrode sheet 355-d coupled to semiconductor material 380-b (e.g., through ohmic material 375-d) may act as the drain of lower TFT 335-b.

[0094] In some cases, Figure 3K (In view of Figure 3L ) depicts ohmic material 375-a at the first layer (e.g., D1 layer 315), where ohmic material 375-a surrounds semiconductor material 380-a at the first layer and contacts semiconductor material 380-a at the first layer. Figure 3K Also depicted is insulating material 390-a inserted between conductive plug 396 and semiconductor material 380-a. Additionally, Figure 3KDepict a portion of an ohmic material (e.g., ohmic material 375-e) at a third layer (e.g., D2 layer 325), where the ohmic material 375-e contacts a semiconductor material 380-a such that a conductive plug 396 can be coupled to the semiconductor material 380-a. In some cases, the ohmic material 375-e can surround the conductive plug 396.

[0095] Figure 3K Depict a current path 345 to illustrate some operational aspects of the TFT. For example, a first signal (e.g., a select signal from a logic circuit system) at a conductive element 385 can provide a first voltage (e.g., 0V) to a conductive plug (e.g., the common source of both the upper TFT 335-a and the lower TFT 335-b). Additionally, a second voltage (e.g., 1V) applied to a gate electrode (e.g., the upper gate electrode 360 including electrode material 361-a) can be greater than the threshold voltage of the TFT (e.g., 0.2V) to form a conductive path (e.g., an active channel region) within the semiconductor material 380-a. Further, a third voltage (e.g., 0.5V) can be applied to an electrode pad 355-c (e.g., the drain of the upper TFT 335-a) such that current can flow from the source of the TFT (e.g., the conductive plug 396 coupled to a node of the logic circuit system) to the drain of the TFT (e.g., the electrode pad 355-c coupled to an array electrode (i.e., a word line)), which is indicated as the upper current path 345-a. Similarly, a lower current path 345-b can be established when a second voltage is applied to the lower gate electrode including electrode material 361-b and a third voltage is applied to an electrode pad 355-d (e.g., the drain of the lower TFT 335-b). In some cases, the voltages associated with the TFT (e.g., the first voltage, the second voltage, the third voltage) can be non-independent of each other, such as during a decoding function or a selection function performed by the TFT. In some cases, if there is a separate circuit (e.g., a circuit driving a voltage to the TFT, an active memory cell conducting current), then the voltages associated with the TFT can be independent of each other.

[0096] Figure 3K The TFT illustrated in can depict a word line socket region because the electrode pads 355 in the D1 layer can be coupled to an array electrode (e.g., a word line) constructed in the D1 layer. Additionally, Figure 3K The TFT illustrated in can be operable to activate or deactivate one of two memory cell levels in an active unit region of an array layer that makes up the stack 305. In some cases, the drain of the TFT (e.g., the drain of the upper TFT 335-a connected to the electrode pad 355-c) can be driven to a voltage related to the voltage present at the conductive element 385 through a conductive path (e.g., an active channel region), as described herein.

[0097] Figure 3LShows a top view of a stack 305 including more than two TFTs (e.g., vertical TFTs) which include all gate, source, and drain electrodes. Figure 3L Also shows various structures of a socket region (e.g., word line socket region) for forming an array layer. For example, Figure 3L Describes a set of array electrodes 350, a set of electrode pads 355 (depicted as dark shaded rectangles), and a set of gate electrodes 360 as described herein.

[0098] For example, Figure 3L Shows a top view of a conductive plug 396 (e.g., via hole 341-a filled with electrode material 395) extending through stack 305, where stack 305 includes a first layer (e.g., D1 layer 315), a second layer (e.g., DM layer 320), and a third layer (e.g., D2 layer 325). A via (e.g., via 340-f shared between a second group of vias 340-b and a third group of vias 340-c as described with reference to Figure 3B can be used to form conductive plug 396. Figure 3L Further shows semiconductor material 380-a at the first layer (e.g., D1 layer 315) and the second layer (e.g., DM layer 320), where semiconductor material 380-a surrounds conductive plug 396. Figure 3L Also shows oxide material 370-a located at the second layer (e.g., DM layer 320) and in contact with semiconductor material 380-a. Additionally, Figure 3L shows gate electrode 360-a at the second layer (e.g., DM layer 320). Gate electrode 360-a including electrode material 361-a is in contact with oxide material 370-a, also as depicted in Figure 3K . In some cases, the combination of semiconductor material 380-a, oxide material 370-a, and electrode material 361-a can form an active channel within semiconductor material 380-a of a TFT (e.g., vertical TFT), where current can flow through the active channel based on a voltage applied to gate electrode 360-a.

[0099] In some cases, Figure 3L shows a portion of an ohmic material (e.g., ohmic material 375-a) at the first layer (e.g., D1 layer 315), where ohmic material 375-a is in contact with semiconductor material 380-a and surrounds conductive plug 396, also as shown in Figure 3K . Figure 3L Also shows insulating material 390-a inserted between conductive plug 396 and semiconductor material 380-a.

[0100] Figures 4A to 4AA Describes exemplary manufacturing techniques according to the present disclosure. Figures 4A to 4AADescribes aspects of several process steps for simultaneously constructing more than two TFTs (e.g., TFTs that can be referred to as planar TFTs where current flows in a horizontal (parallel) direction relative to a horizontal substrate when the TFT is activated). In some cases, such TFTs can be fabricated in the socket region of an array layer, as described herein. In some cases, the TFTs can be referred to as array electrode drivers. Figures 4A to 4AA A top view (e.g., layout of the socket region) of a portion of the socket region is included to illustrate various structures where different via groups can be used to simultaneously construct TFTs. Figures 4A to 4AA A cross-sectional side view of a portion of the socket region is also included to illustrate aspects of process features during several process steps for simultaneously constructing TFTs.

[0101] Figures 4A to 4AA Illustrates an exemplary manufacturing technique for constructing planar TFTs in a composite stack (e.g., stack 305 for constructing vertical TFTs as described in Figures 3A to 3L ). Thus, the composite stack can be used to construct vertical TFTs or planar TFTs or both in the socket region of the array layer. As described herein, the composite stack can also be used to construct 3D cross-point arrays of memory cells and associated electrodes in the active array region of the array layer. In this way, the composite stack can provide an array layer each containing a memory cell level and an electrode, where the electrode (and thus the memory cell) can be further coupled to a TFT (e.g., a vertical TFT, a horizontal TFT, a combination of vertical and horizontal TFTs).

[0102] Figure 4A A top view of stack 405 is included where a socket region can be constructed that contains more than two TFTs (e.g., horizontal TFTs), as described herein. Stack 405 can be an example of stack 305 described in Figures 3A to 3L . Figure 4A Illustrates a set of vias 440 in an array pattern (depicted as white, gray, or cross-hatched squares). The set of vias 440 can be formed to pass through the top layer (e.g., layer 310 of stack 305) of stack 405 that includes a first layer (e.g., layer 315 of stack 305) and a second layer (e.g., layer 320 of stack 305). The set of vias 440 can be an example of the set of vias 340 described in Figures 3A to 3L . Figure 4A Also illustrates various structures that can be formed simultaneously within stack 405 using different via groups (e.g., the first group of vias 440-a, the second group of vias 440-b). For example, Figure 4A illustrates a set of array electrodes 450 (which can be an example of the array electrodes 350 described in Figures 3A to 3L ) and a set of gate electrodes 460 (which can be an example of the gate electrodes 350 described in Figures 3A to 3LExamples of the described gate electrodes 360), each of which may be formed at different junctions of a process sequence to construct a TFT.

[0103] As described elsewhere, a first subgroup of vias (e.g., vias 440-a of the first group) may be used to construct a set of array electrodes 450 (e.g., array electrodes 450-a and 450-b). In some cases, the array electrodes may act as the third electrode of the TFT. Additionally, a second subgroup of vias (e.g., vias 440-b of the second group) may be used to construct a set of gate electrodes 460 (e.g., gate electrode 460-a), as referenced herein Figures 3C to 3F as described.

[0104] In some cases, vias (e.g., the vias depicted as gray squares, which include via 440-z) that can form cavities (e.g., cavity 442-z corresponding to via 440-z) may be used to split a subgroup of array electrodes 450 (e.g., array electrodes 450-b, array electrodes 450-c) into segments. Subsequently, an etching process step may remove portions of the array electrodes 450 exposed within the cavity to split the subgroup of array electrodes 450 into more than two segments. As referenced herein Figure 4Y splitting a subgroup of array electrodes can facilitate a subgroup of TFTs formed in a socket region to drive a single array electrode (e.g., array electrodes 450-a, array electrodes 450-d). In some cases, the subgroup of TFTs may be located between the two ends of a single array electrode. For example, the subgroup of TFTs may be generally located in the middle region of a single array electrode.

[0105] Figure 4B Illustrates a cross-sectional side view of stack 405 across Figure 4A the dashed line AA shown in Figure 4A after using a third via group (e.g., the vias depicted as hatched squares in Figures 3A to 3L which include vias 440-c and 440-d) to form via holes (e.g., opening 441-d corresponding to via 440-d). The cross-sectional side view may correspond to a portion of the socket region that includes gate electrodes 460-a and 460-b. Electrode material 461 (which may be an example of electrode material 361 referenced in Figure 4B The electrode material 461 depicted in Figure 4A corresponds to the gate electrodes 460 depicted in Figure 4B Illustrates an insulating layer 465 (which may be referenced in Figures 3A to 3LThe described example of the insulating layer 365 partially surrounds the electrode material 461. In some cases, an etching process (e.g., an anisotropic etching process) may remove a portion of the insulating layer 465 that is exposed to the etching process for forming the vias.

[0106] Figure 4C Illustrates the use of a third via group (e.g., Figure 4A the vias depicted as hatched squares in, which include via 440-c and via 440-d) to form a via hole (e.g., opening 441-d) and then cross Figure 4A A cross-sectional side view of stack 405 along the dashed line BB shown in. Figure 4C Depicts the same as Figure 4B A different cross-sectional side view of stack 405 in the process steps depicted in to highlight various aspects of the manufacturing technology for forming the TFT. Figure 4C The cross-sectional side view also corresponds to a portion of the socket area including gate electrodes 460-a and 460-b. Figure 4C Illustrates an insulating layer (e.g., insulating layer 465-a) surrounding the electrode material 461-c (which may form gate electrode 460-b) because Figure 4C the insulating layer 465 taken in the cross-sectional side view remains intact when forming the via hole. For example, the anisotropic etching process may not reach the insulating layer 465-a. Additionally, Figure 4C Illustrates that the array electrodes 450 may have been formed in the D1 layer of stack 405, such as array electrode 450-d1, array electrode 450-d2.

[0107] Figure 4D Illustrates the use of the via holes (e.g., opening 441-d) formed within stack 405 to perform at least one etching process step and a deposition process step (as described with reference to Figure 4A and 4B ) and then a top view of stack 405. Additionally, Figure 4D Depicts that specific vias (e.g., via 440-z and corresponding cavity 442-z described with reference to Figure 4A ) have been used to remove portions of the array electrodes (e.g., array electrode 450-b, array electrode 450-c). Thus, some of the array electrodes (e.g., array electrode 450-b, array electrode 450-c) may be unconnected to the array electrodes in the active array region of the array layer.

[0108] Figure 4E Illustrates a cross-sectional side view of stack 405 along the dashed line AA shown in after the etching process step and the deposition process step. Similarly, Figure 4D Illustrates a cross-sectional side view of stack 405 along the dashed line AA shown in after the etching process step and the deposition process step. Figure 4F Illustrates a cross-sectional side view of stack 405 along the dashed line AA shown in after the etching process step and the deposition process step. Figure 4DCross-sectional side view of stack 405 of dashed line BB shown therein. In this manner, Figures 4D to 4F Describe various aspects of the structural features formed within stack 405 due to the etching process steps and the deposition process steps.

[0109] In some cases, the etching process step may include a first isotropic etching process that uses a via hole (e.g., opening 441-d) to reach a layer below the top layer (e.g., hard mask layer) of stack 405. The first isotropic etching process may selectively remove the first dielectric material of the D1 layer within stack 405. The first isotropic etching process may leave other materials (e.g., materials other than the first dielectric material of the D1 layer) exposed to the via hole substantially unchanged, such as the insulating layer 465, the electrode material 461, the second dielectric material in the D2 layer. Due to the first isotropic etching process, via cavity 442 (e.g., Figure 4D The via cavity 442-b corresponding to via 440-d depicted therein, Figure 4E And 4F The via cavity 442-c and via cavity 442-d corresponding to via 440-d depicted therein) may be formed at the D1 layer. Figure 4D It is illustrated that via cavities (e.g., via cavity 442-a and via cavity 442-b depicted as light gray squares in the top view) may reach the array electrodes 450 (e.g., array electrodes 450-c, array electrodes 450-d) to expose the array electrodes 450 at the D1 layer.

[0110] In some cases, the etching process may further include a second isotropic etching process that may selectively remove portions of the array electrodes 450 at the D1 layer, such as portions of the array electrodes 450 that are exposed to the second isotropic etching process due to the first isotropic etching process. The second isotropic etching process may leave other materials (e.g., materials other than the array electrodes 450 at the D1 layer) exposed to the via holes and via cavities substantially unchanged, such as the insulating layer 465, the electrode material 461, the first dielectric material at the D1 layer, the second dielectric material at the D2 layer. Due to the second isotropic etching process, Figure 4F It is illustrated that a portion of the array electrodes 450 (e.g., array electrodes 450-d1, array electrodes 450-d2) has been removed to form (e.g., expand) via cavities (e.g., via cavity 442-c, via cavity 442-d). Additionally, Figure 4D It is illustrated that the second isotropic etching process may remove portions of the array electrodes, such as the overlapping regions between the via cavities (e.g., via cavity 442-a) and the array electrodes (e.g., array electrodes 450-c, array electrodes 450-d).

[0111] In some cases, the etching process may further include a third isotropic etching process that selectively removes the insulating layer 465 at the DM layer exposed in the via holes and via cavities. The third isotropic etching process may leave other materials exposed in the via holes and via cavities (such as materials other than the insulating layer 465) substantially unchanged, such as the electrode material 461, the first dielectric material in the D1 layer, the second dielectric material in the D2 layer, and the array electrodes 450 at the D1 layer. Due to the third isotropic etching process, portions of the electrode material 461 may become exposed to the deposition process.

[0112] In some cases, the deposition process step may selectively form an oxide material 470 (which may be an example of the oxide material 370 described in reference Figures 3A to 3L above) over the exposed surface of the electrode material 461. In some cases, the oxide material 470 may act as the gate oxide of the TFT.

[0113] In some cases, using a via (such as via 440-d) of a second group of vias 440-b that has been used to form the gate electrode (such as gate electrode 460-b) of the TFT, a second isotropic etching process may form cavities (such as cavities 442-c, cavities 442-d) at the first layer to expose a portion of the gate electrode (such as electrode material 461-b1, electrode material 461-b2). Using the via (such as via 440-d), the deposition process step may form an oxide material (such as oxide material 470-e, oxide material 470-f) in contact with the gate electrode (such as electrode material 461-b1, electrode material 461-b2).

[0114] Figure 4G Illustrates a top view of the stack 405 after performing at least one deposition process step (as described in reference Figure 4E using the via holes (such as the opening 441-d shown in Figure 4E and 4F and the via cavities (such as the via cavity 442 shown in Figures 4D to 4F formed within the stack 405). Figure 4H Illustrates a cross-sectional side view of the stack 405 taken along the dashed line AA shown in Figure 4G after the deposition process step. Similarly, Figure 4I Illustrates a cross-sectional side view of the stack 405 taken along the dashed line BB shown in Figure 4G after the deposition process step.

[0115] In some cases, the deposition process step may use a semiconductor material 480 (which may be an example of the semiconductor material 380 described in reference Figures 3A to 3L above) to fill the via holes and via cavities. Figure 4GA top view of a via cavity (eg, via cavity 442 - a depicted as a dark grey square) filled with semiconductor material 480 is depicted. Figure 4H It is depicted that semiconductor material 480 may be in contact with oxide material 470 (eg, gate oxide). Figure 4I It is depicted that semiconductor material 480 may fill the cavity and may be in contact with oxide material 470 (eg, gate oxide).

[0116] In some cases, the deposition step may be performed in a chamber (e.g., vias 440-d) using vias of the second group of vias 440-b that have been used to form gate electrodes of TFTs (e.g., gate electrodes 460-b). Figure 4E and 4F A semiconductor material (eg, semiconductor material 480) is formed in cavity 442-c, cavity 442-d) shown in FIG, and the semiconductor material may be in contact with an oxide material (eg, oxide material 470-e).

[0117] Figure 4J The third via group (eg, Figure 4J The passages depicted as cross-hatched squares in FIG. 4 , including passages 440 - c and 440 - d , perform at least one etching process step and a deposition process step (as shown in FIG. Figures 4G to 4I A top view of the stack 405 after (as described). Figure 4K Illustrating the traversal after the etching process step and the deposition process step Figure 4J 4. Similarly, Figure 4L Describes the traversal following the deposition process step Figure 4J A cross-sectional side view of the stack 405 is shown along the dashed line BB.

[0118] In some cases, the etching process may include a first anisotropic etching process that selectively removes semiconductor material 480 within via holes (e.g., via holes corresponding to the third via group) along a vertical direction (e.g., a vertical direction relative to a horizontal substrate). In some cases, the etching process may include a second anisotropic etching process that selectively removes oxide material 470 in the via holes. Due to the etching process that removes semiconductor material 480 in the via holes, semiconductor material at the upper D1 layer (e.g., semiconductor material 480-a) may be separated from semiconductor material at the lower D1 layer (e.g., semiconductor material 480-b), as shown in FIG. Figure 4K As shown in .

[0119] In some cases, the deposition process step may include filling the via hole with a dielectric material (eg, an insulating material).In some cases, a CMP process or an etch-back process may be used to remove additional dielectric material on top of the stack 405. Figure 4KDepict a viaduct filled with a dielectric material (such as dielectric plugs 444-a, dielectric plugs 444-b) that separates the semiconductor material 480-a at the upper D1 layer from the semiconductor material 480-b at the lower D1 layer. The semiconductor material (such as semiconductor material 480-a) at the first layer (such as the D1 layer of stack 405) can surround the dielectric plug (such as dielectric plug 444-b). In addition, the gate electrodes (such as electrode materials 461-b1, electrode materials 461-b2) at the second layer (such as the DM layer of stack 405) can surround the dielectric plug (such as dielectric plug 444-b). Additionally, an oxide material (such as oxide material 470-e) can be located between the semiconductor material (such as semiconductor material 480-a) and the gate electrode (such as electrode material 461-b1). Figure 4L The structural features depicted in Figure 4I remain the same as the structural features depicted in Figure 4L because the structural features depicted in Figure 4L are positioned away from the viaduct hole. For example, the etching process steps and deposition process steps do not affect the structural features depicted in

[0120] Figure 4M Illustrate a top view of stack 405 after performing at least one etching process step on the fourth viaduct group (such as the viaducts depicted as dot-filled squares in Figure 4M , which includes viaducts 440-e to viaducts 440-i). Some viaducts in the fourth group (such as viaduct 440-e and viaduct 440-f) are adjacent to a viaduct cavity filled with semiconductor material (such as viaduct cavity 442-a that has been filled with semiconductor material 480), as described with reference to Figures 4J to 4L . Figure 4N Illustrate a cross-sectional side view of stack 405 across the dashed line AA shown in Figure 4M after the etching process step. Similarly, Figure 4O Illustrate a cross-sectional side view of stack 405 across the dashed line BB shown in Figure 4M after the etching process step.

[0121] In some cases, the etching process step can include an anisotropic etching process that can remove various materials in a vertical direction (such as in a vertical direction relative to the horizontal substrate) to form viaduct holes corresponding to the fourth viaduct group, such as viaduct holes 441-e to 441-i corresponding to viaducts 440-e to 440-i respectively. In some cases, the various materials that can be removed by the anisotropic etching process include the HM layer (top layer) and D1 layer of stack 405, insulating layer 465, electrode material 461, and D2 layer of stack 405. In some cases, the anisotropic etching process can stop at the bottom layer of stack 405, as shown in Figure 4N . Figure 4OThe structural features depicted in are the same as Figure 4L the structural features depicted in, because Figure 4O the structural features depicted in are positioned away from the third via hole group (such as via holes 441-e to 441-i). For example, the anisotropic etching process does not affect Figure 4O the structural features depicted in.

[0122] Figure 4P Illustrates the use of via holes (such as via holes 441-e to 441-i) corresponding to the fourth via group (such as Figure 4P the vias depicted as dot-filled squares in, which include via holes 440-e to via holes 440-i) to perform at least one etching process step on the stack 405 (as described with reference to Figure 4M and 4N ), a top view of the stack 405 after the etching process step. Figure 4Q Illustrates a cross-sectional side view of the stack 405 across the Figure 4P dotted line AA shown in after the etching process step. Similarly, Figure 4R illustrates a cross-sectional side view of the stack 405 across the Figure 4P dotted line BB shown in after the etching process step.

[0123] In some cases, the etching process step may include a first isotropic etching process. The first isotropic etching process may selectively remove a portion of the first dielectric material at the D1 layer to create cavities (such as cavities 442-e, cavities 442-f), such that the cavities may expose the array electrodes 450 at the D1 layer, as Figure 4P and 4R shown. Additionally, Figures 4P to 4R depicts that more than two cavities may be adjacent to form a channel (such as channel 443-a). In some cases, the etching process may include a second isotropic etching process. The second isotropic etching process may selectively remove the exposed array electrodes 450 at the D1 layer (such as array electrodes 450-d1, array electrodes 450-d2), as Figure 4P and 4R depicted.

[0124] In some cases, the etching process step may remove any exposed oxide material 470 (such as gate oxide), while removing a portion of the dielectric material at the D1 layer or the exposed array electrodes 450 at the D2 layer. The etching process may leave the semiconductor material (such as semiconductor material 480) substantially intact. Additionally, the etching process may leave the second dielectric material of the D2 layer of the stack 405 substantially intact. Figure 4RDepict the steps of the etching process to extend the cavity to reach the array electrodes 450 at the D1 layer and remove a part of the array electrodes (such as array electrode 450-d1, array electrode 450-d2), while the semiconductor material remains substantially intact.

[0125] In some cases, using at least via 440-g (which can be used to form the second electrode of a transistor, as Figures 4Y to 4AA will be described), the etching process steps (such as the first isotropic etching process) can form a second cavity (such as channel 443-a1) at the first layer (such as the D1 layer), so that a part of the third electrode (such as electrode 450-d) and the semiconductor material (such as semiconductor material 480-a, semiconductor material 480-c) can be exposed. Additionally, using at least a third via (such as via 440-i), the etching process steps (such as the first isotropic etching process) can form a third cavity (such as cavity 442-e1) at the first layer, so that the semiconductor material (such as semiconductor material 480-c) can be exposed.

[0126] Figure 4S Illustrate a top view of stack 405 after performing at least a first deposition process step and a second deposition process step using via holes (such as via holes 441-e to 441-i) corresponding to a fourth via group (such as Figure 4S the vias depicted as dot-filled squares in, which include vias 440-e to 440-i) as described with reference to Figures 4P to 4R . Figure 4T Illustrate a cross-sectional side view of stack 405 across the dashed line AA shown in Figure 4S after the first deposition process step and the second deposition process step. Similarly, Figure 4U Illustrate a cross-sectional side view of stack 405 across the dashed line BB shown in Figure 4S after the first deposition process step and the second deposition process step.

[0127] In some cases, the first deposition process step can include selectively forming an insulating layer 466 above the exposed surface of the electrode material 461, as Figure 4N and 4Q shown. In some cases, the insulating layer 466 can be an instance of the insulating layer 365 described with reference to Figures 3A to 3L . The insulating layer 466 can provide electrical isolation between the electrode material 461 (such as the upper surface gate electrode 460 including electrode material 461-a1, the lower surface gate electrode 460 including electrode material 461-a2) and the ohmic material deposited during the second deposition process step.

[0128] In some cases, the second deposition process step can include using an ohmic material 475 (which can be Figures 3A to 3Lthe cavities and channels formed in stack 405 are filled with an example of the described ohmic material 375 (e.g., refer to Figures 4P to 4R the described cavities 442 and channels 443). Figure 4S Top view showing cavities and channels filled with an ohmic material 475 (e.g., ohmic material 475-a, ohmic material 475-b, ohmic material 475-c). Figure 4T and 4U Cross-sectional side view showing cavities and channels filled with an ohmic material 475 (e.g., ohmic material 475-a, ohmic material 475-b, ohmic material 475-c). Additionally, Figure 4U shows a semiconductor material (e.g., semiconductor material 480-a1) in contact with an ohmic material (e.g., ohmic material 475-a1), and the ohmic material in contact with an array electrode (e.g., array electrode 450-d1). As will be referenced herein Figure 4Y and 4Z described, when the TFT is fully constructed, the combination of the semiconductor material, the ohmic material, and the array electrode can form the current path of the TFT, and the current path is in the horizontal direction (e.g., a direction parallel to the horizontal substrate).

[0129] In some cases, the second deposition process step may use an ohmic material (e.g., ohmic material 475-b1, ohmic material 475-c1) to fill the second cavity (e.g., refer to Figure 4Q and 4R the described channel 443-a1) and the third cavity (e.g., refer to Figure 4Q and 4R the described cavity 442-e1) at the first layer (e.g., D1 layer).

[0130] Figure 4V Shows a top view of stack 405 after performing at least one etching process step and deposition process step (as described in reference Figure 4V on the fourth via group that has been filled with an ohmic material (e.g., the vias depicted as dot-filled squares in Figures 4S to 4U which include via 440-e to via 440-i). Figure 4W Shows a cross-sectional side view of stack 405 across the dashed line AA shown in Figure 4V after the etching process step and deposition process step. Similarly, Figure 4X Shows a cross-sectional side view of stack 405 across the dashed line BB shown in Figure 4V after the etching process step and deposition process step.

[0131] In some cases, the etching process may include an anisotropic etching process that removes the ohmic material in a vertical direction (e.g., a vertical direction relative to a horizontal substrate). Due to the etching process for removing the ohmic material, via holes (e.g., via holes 441-e to 441-i corresponding to vias 440-e to 440-i respectively) may be formed to separate the ohmic material (e.g., ohmic material 475-a1, ohmic material 475-c1) at the upper D1 layer from the ohmic material (e.g., ohmic material 475-a2, ohmic material 475-c2) at the lower D1 layer. Subsequently, a deposition process may use a dielectric material to fill the via holes. Figure 4W Illustrate via holes (e.g., via holes 441-e to 441-i) filled with a dielectric material. The extra dielectric material above the HM layer of the stack 405 may be removed by a CMP process or an etch-back process. Figure 4X The structural features depicted in Figure 4U remain the same as the structural features depicted in Figure 4X since the structural features depicted in Figure 4X are positioned away from the third via hole group (e.g., via holes 441-e to 441-i). For example, the anisotropic etching process and the subsequent deposition process do not affect

[0132] Figure 4Y Illustrate a top view of the stack 405 after performing at least one etching process step and one deposition process step (as described with reference to Figures 4V to 4X ) on the fifth via group (e.g., the vias depicted as dark gray squares, which include via 440-g) that has been filled with a dielectric material. Figure 4Z Illustrate a cross-sectional side view of the stack 405 across the dashed line AA shown in Figure 4Y after the etching process step and the deposition process step. Similarly, Figure 4AA Illustrate a cross-sectional side view of the stack 405 across the dashed line BB shown in Figure 4Y after the etching process step and the deposition process step.

[0133] In some cases, an etching process step may include an anisotropic etching process. The anisotropic etching process may remove dielectric material from a via hole (e.g., via hole 441-g corresponding to via 440-g). Additionally, the anisotropic etching process may selectively remove a portion of the underlying layer (e.g., etch stop layer, HM layer) of stack 405 to form a hole (e.g., opening 441-j) through the underlying layer of stack 405. In some cases, the width of opening 441-j may be substantially the same as the width of opening 441-g. Opening 441-j may be coupled to a conductive element 485 that may be part of a logic circuit system layer. For example, conductive element 485 may represent a node of a circuit system in a substrate (e.g., row decoder 120 constructed in substrate 204). In another example, conductive element 485 may be coupled to a node of row decoder 120 (e.g., a node where a select signal exists) to activate one or more levels of an array layer. In some cases, an etching process step may include an isotropic etching process that may follow the anisotropic etching. The isotropic etching process may selectively remove ohmic material exposed within the via hole, such as ohmic material at the recessed etch D1 layer (e.g., ohmic material 475-b1, ohmic material 475-b2).

[0134] In some cases, a deposition process may use electrode material 495 (which may be an example of the electrode material 395 described in reference Figures 3A to 3L to fill a via hole (e.g., via hole 441-g). The additional electrode material 495 above the top layer (e.g., HM layer) of stack 405 may be removed by a CMP process or an etch-back process. Due to using electrode material 495 to fill the via hole (e.g., forming conductive plug 496), conductive element 485 (e.g., a node associated with a logic circuit system layer) may be coupled to an ohmic material (e.g., ohmic material 475-b1), as shown in Figure 4Z . In some cases, conductive plug 496 (e.g., via hole 441-g corresponding to via 440-g, which has been filled with electrode material 495) may act as a second electrode of a TFT. Figure 4AA The structural features depicted in Figure 4X remain the same as the structural features depicted in Figure 4AA because the structural features depicted in Figure 4AA are positioned away from the fifth via group. For example, the etching process and subsequent deposition process do not affect the structural features depicted in

[0135] As referred to herein in reference Figures 4Y to 4AAAs described, the conductive element 485 can be coupled to ohmic materials (such as ohmic materials 475-b1, ohmic materials 475-b2), and the ohmic materials are in contact with semiconductor materials (such as semiconductor materials 480-a1, semiconductor materials 480-a2). The semiconductor materials (such as semiconductor materials 480-a1, semiconductor materials 480-a2) are in contact with ohmic materials (such as ohmic materials 475-a1, ohmic materials 475-b2), and the ohmic materials are in contact with the array electrodes (such as array electrodes 450-d1, array electrodes 450-d2), as Figure 4AA shown. In this way, a current path can be established between the conductive element 485 and the array electrodes (such as array electrodes 450-d1, array electrodes 450-d2) based on the voltage applied to the gate electrodes (such as the upper layer gate electrode 460 including the electrode material 461-a1, the lower layer gate electrode 460 including the electrode material 461-a2) to form an active channel in the semiconductor materials (such as semiconductor materials 480-a1, semiconductor materials 480-a2) through which current flows (as Figure 4Y and 4Z indicated by the dashed arrows).

[0136] Figures 4Y to 4AA Describe various features of the planar TFT. For example, Figure 4Z the planar TFT depicted in can include dielectric plugs (such as dielectric plugs 444-a, dielectric plugs 444-b) extending through a stack including a first layer and a second layer (such as stack 405 including layer D1 and layer DM). The planar TFT can also include semiconductor material (such as semiconductor material 480-a1) at the first layer surrounding the dielectric plug (such as dielectric plug 444-a). In addition, the planar TFT can include a gate electrode (such as the electrode material 461-a1 forming the gate electrode 460-a) at the second layer surrounding the dielectric plug (such as dielectric plug 444-a). Additionally, the planar TFT can include an oxide material (such as oxide material 470-a) between the semiconductor material 480-a1 and the gate electrode (such as the electrode material 461-a1 forming the gate electrode 460-a).

[0137] Figure 4Z the planar TFT depicted in can include a conductive plug (such as conductive plug 496) extending through the stack and ohmic materials (such as ohmic materials 475-b1, ohmic materials 475-b2) at the first layer surrounding the conductive plug. The ohmic material (such as ohmic material 475-b1) surrounding the conductive plug is in contact with the semiconductor material (such as semiconductor material 480-a1) surrounding the dielectric plug (such as dielectric plug 444-a), as Figures 4Y to 4AAdepicted in. The planar TFT may also include a second dielectric plug (e.g., dielectric plug 444-b) extending through the stack, and the semiconductor material (e.g., semiconductor material 480-a1) at the first layer surrounding the dielectric plug (e.g., dielectric plug 444-a) includes a first segment of semiconductor material, and the ohmic material (e.g., ohmic material 475-b1) surrounding the conductive plug (e.g., conductive plug 496) contacts a second segment of the semiconductor material (e.g., semiconductor material 480-b1) surrounding the second dielectric plug (e.g., dielectric plug 444-b), as Figures 4Y to 4AA depicted in.

[0138] Figures 5A to 5N Illustrate exemplary fabrication techniques in accordance with the present disclosure. Figures 5A to 5N Describe aspects of several process steps for simultaneously fabricating more than two TFTs (e.g., TFTs that may be referred to as wrap-around TFTs and in which current flows in a direction along the outer surface of the gate electrode when the TFT is activated). In some cases, such TFTs may be fabricated in the socket region of the array layer, as described herein. Figures 5A to 5N A top view (e.g., layout of the socket region) including a portion of the socket region to illustrate various structures in which different via groups may be used to simultaneously fabricate TFTs. Figures 5A to 5N Also include a cross-sectional side view of a portion of the socket region to illustrate aspects of process features during several process steps for simultaneously fabricating TFTs.

[0139] Figures 5A to 5N Illustrate for constructing a composite stack (e.g., stack 305 for constructing a vertical TFT as described with reference to Figures 3A to 3L stack 405 for constructing a planar TFT as described with reference to Figures 4A to 4AA exemplary fabrication techniques for wrap-around TFTs within. Thus, the composite stack may be used to construct vertical TFTs, planar TFTs, wrap-around TFTs, or any combination thereof in the socket region of the array layer. As described herein, the composite stack may also be used to construct 3D cross-point arrays of memory cells and associated electrodes in the active array region of the array layer. In this way, the composite stack may provide an array layer that constructs each including a memory cell plane and an electrode, where the electrode (and thus the memory cell) may further be coupled to a TFT (e.g., a vertical TFT, a horizontal TFT, a wrap-around TFT, or any combination thereof).

[0140] Figure 5A Illustrate a top view of stack 505 of a socket region in which more than two TFTs (e.g., wrap-around TFTs) may be constructed, as described herein. As an example, Figure 5ADescribe two sets of TFTs each including two TFT subgroups. Each set of TFTs can drive a single set of array electrodes. Additionally, each set of TFTs can include a first TFT subgroup coupled to a first node associated with the logic circuit system layer and a second TFT subgroup coupled to a second node associated with the logic circuit system layer. In some cases, the first node can correspond to a node configured to supply current to a first circuit for activating a memory cell level. Thus, the first node can be referred to as a select node and the first circuit can be referred to as a select driver. In some cases, the second node can correspond to a node of a second circuit configured to keep leakage current associated with one or more deactivated memory cell levels below a threshold. Thus, the second node can be referred to as a suppression node and the second circuit can be referred to as a suppression driver. Figure 5N Describe additional aspects of the TFT operation.

[0141] Stack 505 can be a reference Figures 3A to 3L An example of the described stack 305. Figure 5A Illustrate a set of vias 540 in an array pattern (depicted as white squares, squares with an 'x', squares with an 'o'). A set of vias 540 can be formed to pass through the top layer (e.g., layer 310, HM layer of stack 305) of a stack 505 including a first layer (e.g., layer 315, D1 layer of stack 305), a second layer (e.g., layer 320, DM layer of stack 305), and a third layer (e.g., layer 325, D2 layer of stack 305). A set of vias 540 can be a reference Figures 3A to 3L An example of the described set of vias 340. Figure 5A Also illustrate various structures that can be formed simultaneously within stack 505 using different via groups. For example, Figure 5 Illustrate a set of gate electrodes 560 of the TFT (which can be a reference ​ An example of the described gate electrodes 360), a set of array electrodes 550 (which can be a reference ​ An example of the described array electrodes 350), where each can be formed at different junctions of a process sequence for constructing the TFT.

[0142] A first subgroup of vias (e.g., the first group of vias 540 - a) can be used to construct a set of gate electrodes 560 (e.g., gate electrodes 560 - a to gate electrodes 560 - d), as referenced herein ​ as described. Additionally, as described elsewhere, a set of array electrodes 550 (e.g., array electrodes 550 - a to array electrodes 550 - j) can be constructed using the vias depicted as squares with an 'x'. Additionally, a set of electrode pads (e.g., electrode pads 555 - a, electrode pads 555 - b) can be constructed using the vias depicted as squares with an 'o'. In some cases, the second set of vias can include vias depicted as squares with an 'x' and vias depicted as squares with an 'o'. As ​As depicted, each electrode sheet (e.g., electrode sheet 555-a) can be connected to two array electrodes (e.g., electrode 550-a and electrode 550-c). Thus, the array electrode group can include an electrode sheet group. In some cases, the array electrode can serve as the second electrode of the TFT. Additionally, a third via (e.g., via 540-b1, via 540-b2) can be used to construct a conductive plug, as described herein with reference to ​ and 5M In some cases, the conductive plug can serve as the third electrode of the TFT and the conductive plug (e.g., the third electrode) can extend at least through the third layer (e.g., layer 325 of stack 305, D2 layer). ​ Also illustrated is a third via group (e.g., via 540-c1, via 540-c2, via 540-c3) formed to pass through the top layer of stack 505.

[0143] ​ The cross-sectional side view of ​ can correspond to where the dashed line AA in ​ extends through the socket area of fourteen (14) vias. For example, ​ illustrates fourteen vias (e.g., vias depicted as white or gray squares, vias depicted as squares with an ×, vias depicted as squares with an ○) above the cross-sectional side view of stack 505 to use one or more specific vias to match various structural features (e.g., via holes, via cavities, channels (i.e., adjacent to via cavities), dielectric plugs, conductive plugs) formed within stack 505 to form such structural features in stack 505. Additionally, arrows are added to indicate one or more specific vias at different junctions of the process sequence for constructing the TFT.

[0144] ​ Illustrates a cross-sectional side view of stack 505 after using the third via group (e.g., via 540-c1, via 540-c2, via 540-c3) to form via holes (e.g., via holes corresponding to the vias indicated by the arrows). In some cases, an anisotropic etching process can form the via holes, as described herein. Figure 5B Also illustrated is that electrode material 561 (which can be an example of electrode material 361 described in reference to Figures 3A to 3L ) can have been previously formed in the second layer (e.g., DM layer) of stack 505, as described herein with reference to Figures 3C to 3F . Figure 5B The electrode material 561 depicted in Figure 5A corresponds to the gate electrode 560 depicted in Figure 5B Illustrates an insulating layer 565 (which can be a reference to Figures 3A to 3LThe example of the described insulating layer 365 partially surrounds the electrode material 561. Figure 5B It is also described that electrode pads (such as electrode pads 555-a, electrode pads 555-b) can be previously formed in the first layer (such as D1 layer) of the stack 505.

[0145] Figure 5C It is described that at least one etching process step is performed using via holes (such as via holes corresponding to the vias indicated by the arrows) formed using a third via group (such as vias 540-c1, vias 540-c2, vias 540-c3), as shown in the cross-sectional side view of the stack 505 after (as described in the reference Figure 5B ). In some cases, the etching process step may include an isotropic etching process that selectively removes the first dielectric material at the D1 layer and the second dielectric material at the D2 layer. The isotropic etching can keep other materials (such as materials other than the first dielectric material at the D1 layer and the second dielectric material at the D2 layer) exposed to the via holes substantially unchanged, such as the insulating layer 565 and the electrode material 561. Due to the isotropic etching process, via cavities (such as via cavities 542-a1, via cavities 542-a2, via cavities 542-a3) can be formed. The via cavity 542 can span the first layer (such as the D1 layer where the array electrodes 550 are present), the second layer (such as the DM layer where the gate electrodes 560 are present), and the third layer (such as the D2 layer). In addition, via cavities (such as via cavities 542-b1, via cavities 542-b2) can expose the array electrodes (such as array electrodes 550-k1, array electrodes 550-k2). Additionally, the via cavity 542 can expose the insulating layer 565 conformal to the gate electrode 560.

[0146] Figure 5D It is described that at least one etching process step is performed using the formed third via group (such as vias 540-c1, vias 540-c2, vias 540-c3) and the corresponding via holes and via cavities, as shown in the cross-sectional side view of the stack 505 after (as described in the reference Figure 5C ). In some cases, the etching process step may include an isotropic etching process that selectively removes the array electrodes at the D1 layer exposed to the isotropic etching process (such as the array electrodes 550-k1, array electrodes 550-k2 described in the reference Figure 5C ). The isotropic etching can keep other materials (such as materials other than the array electrodes at the D1 layer) exposed to the via holes and via cavities substantially unchanged, such as the insulating layer 565, the electrode material 561, the first dielectric material at the first layer, the placeholder material at the second layer, and the second dielectric material at the third layer.

[0147] Figure 5EIllustration of a cross-sectional side view of stack 505 after performing at least one etching process step and one deposition process step using a formed third via group (e.g., vias 540-c1, 540-c2, 540-c3) and corresponding via holes and via cavities (using reference Figure 5D as described). In some cases, the etching process step may include an isotropic etching process that selectively removes a portion of the insulating layer 565 in contact with the gate electrode. The isotropic etching may leave other materials exposed to the via holes and via cavities (e.g., materials other than the insulating material at the DM layer) substantially unchanged, such as the electrode material 561 forming the gate electrode 560, the first dielectric material at the first layer, the placeholder material at the second layer, and the second dielectric material at the third layer. In some cases, the deposition process step may form an oxide material 570 in contact with the gate electrode (which may be an example of the oxide material 370 described in reference Figures 3A to 3L ). In some cases, the oxide material may be referred to as the gate oxide of the TFT.

[0148] Figure 5F Illustration of a cross-sectional side view of stack 505 after performing at least one deposition process step using a formed third via group (e.g., vias 540-c1, 540-c2, 540-c3) and corresponding via holes and via cavities (using reference Figure 5D as described). In some cases, the deposition process step may fill the via holes and via cavities with a semiconductor material 580 (which may be an example of the semiconductor material 380 described in reference Figures 3A to 3L ), and the semiconductor material 580 may be in contact with the oxide material 570, which is in contact with the gate electrode, as described in reference Figure 5E .

[0149] Figure 5G Illustration of a cross-sectional side view of stack 505 after performing at least one etching process step and one deposition process step using a fourth via group (e.g., a fourth set of vias indicated by arrows). Referring to Figure 5A , the fourth via group may include vias common to the first via group (e.g., vias 540-a1, 540-a2, 540-a3, 540-a4) and the third via group (e.g., vias 540-c1, 540-c2, 540-c3). In some cases, the etching process step may include an anisotropic etching process that removes the semiconductor material 580 that has filled the via holes and via cavities, as described in reference Figure 5FAs described. The anisotropic etching process can remove the semiconductor material 580 in a vertical direction (e.g., a vertical direction with respect to a horizontal substrate) to form via holes corresponding to the fourth via group (e.g., via holes to be filled with dielectric material later). Removing the semiconductor material 580 within the via holes corresponding to the fourth via group can remove parasitic current paths having shorter channel lengths of the TFTs, such that the main current paths of the TFTs can have longer channel lengths, as referenced Figure 5M As described. In some cases, a deposition process step can use a dielectric material to fill the via holes. In some cases, the via holes filled with dielectric material can be referred to as dielectric plugs (e.g., dielectric plugs 544-a, dielectric plugs 544-b), which extend through the gate electrodes (e.g., gate electrode 560-a including electrode material 561-a).

[0150] Figure 5H A cross-sectional side view of the stack 505 after performing at least one etching process step using a fifth via group (e.g., a fifth via group including the vias indicated by arrows) is illustrated. Referenced Figure 5A , the fifth via group can include vias 540-e (e.g., via 540-e1 including via 540-b1, via 540-e2 including via 540-b2, via 540-e3, via 540-e4). In some cases, the etching process can include an anisotropic etching process that removes the first dielectric material of the first layer (e.g., D1 layer), the dummy material of the second layer (e.g., DM layer), and the second dielectric material of the third layer (e.g., D2 layer) (e.g., to form a via hole corresponding to via 540-b1). The anisotropic etching process can also remove the dielectric material of the via holes that have been filled to form the array electrodes (e.g., the via holes corresponding to the vias depicted as squares with an × (which include via 540-b2)). The anisotropic etching process can leave other materials exposed to the via holes substantially unchanged, such as the insulating layer 565.

[0151] In some cases, the etching process step can further include an isotropic etching process that selectively removes the first dielectric material of the first layer (e.g., D1 layer). The isotropic etching process can leave other materials exposed to the via holes substantially unchanged, such as the dummy material of the second layer (e.g., DM layer), the second dielectric material of the third layer (e.g., D2 layer), the insulating layer 565. The isotropic etching process using the fifth via group (e.g., the fifth via group including via 540-b1, via 540-b2) can form via cavities (e.g., via cavities 542-c1, via cavities 542-c2) to expose the semiconductor material (e.g., semiconductor material 580-a) of the TFTs and the second electrodes (e.g., electrode pads 555-a1, electrode pads 555-a2) at the first layer (e.g., D1 layer).

[0152] Figure 5I Cross-sectional side view of stack 505 after performing at least one deposition process step using via holes formed based on a fifth set of vias (e.g., the fifth set of vias including the vias indicated by the arrows). In some cases, the deposition process step may use an ohmic material 575 (which may be an example of the ohmic material 375 described in reference Figures 3A to 3L to fill the via cavities (e.g., via cavity 542-c1, via cavity 542-c2) described in reference Figure 5H such that the ohmic material (e.g., ohmic material 575-a) can contact the semiconductor material (e.g., semiconductor material 580-a) and the second electrode (e.g., array electrode 555-a1). An additional ohmic material on top of stack 505 may be removed using a CMP process or an etch-back process.

[0153] Figure 5J Cross-sectional side view of stack 505 after performing at least one etching process step and one deposition process step using a fifth set of vias (e.g., the fifth set of vias including the vias indicated by the arrows). In some cases, the etching process step may include an anisotropic etching process that can remove a portion of the ohmic material in a vertical direction (e.g., a vertical direction relative to the horizontal substrate) to form via holes (e.g., via holes corresponding to the fifth set of vias). The anisotropic etching process may leave other materials exposed in the via holes substantially unchanged, such as the placeholder material of the second layer (e.g., the DM layer), the second dielectric material of the third layer (e.g., the D2 layer), and the insulating layer 565. In some cases, after the anisotropic etching process, the deposition process step using the via holes (e.g., via holes corresponding to the fifth set of vias) may form an insulating material 566 that contacts the ohmic material (e.g., ohmic material 575-a1, ohmic material 575-a2) held within the via cavity (e.g., the via cavity 542-c1 filled with the ohmic material as described in reference Figure 5I . In some cases, the insulating material 566 may be an example of the material that can form the insulating layer 365 described in reference Figures 3A to 3L . In some cases, the deposition process step may include a selective deposition process that can deposit the insulating material 566 only on the exposed surface of the ohmic material 575.

[0154] Figure 5K Cross-sectional side view of stack 505 after performing at least one etching process step (as described in reference Figure 5JCross-sectional side view of stack 505 after the (as described). In some cases, the etching process step may include an isotropic etching process that selectively removes the second dielectric material at the third layer (e.g., D2 layer). The isotropic etching process may leave other materials exposed in the vias (e.g., materials other than the second dielectric material of the D2 layer) substantially unchanged, such as the insulating material 566, the insulating layer 565, the semiconductor material 580, and the dummy material at the second layer (e.g., DM layer). Due to the isotropic etching process, a via cavity (e.g., via cavity 542-d) may be formed such that the semiconductor material 580-a is exposed to subsequent process steps.

[0155] Figure 5L Cross-sectional side view of stack 505 after performing at least one deposition process step and an etching process step using a fifth set of vias (e.g., the fifth set of vias including the vias indicated by the arrows). In some cases, the deposition process step may use an ohmic material to fill the via holes (e.g., the via holes corresponding to the fifth set of vias). The ohmic material may also fill the via cavities (e.g., the via cavity 542-d as referenced Figure 5K as described) formed at the third layer (e.g., D2 layer), such that the ohmic material (e.g., ohmic material 575-b) may contact the semiconductor material 580-a. In some cases, the etching process step may include an anisotropic etching process that removes a portion of the ohmic material from the via holes in a vertical direction (e.g., a vertical direction relative to the horizontal substrate). In some cases, the anisotropic etching process may create holes (e.g., opening 541-a) at the bottom layer (e.g., layer 330) of the stack 505. The holes may be coupled to conductive elements (e.g., conductive elements 585-a to conductive elements 585-d) that may be part of a logic circuit system layer. In some cases, the conductive element 585-a may be coupled to the inhibit node of an inhibit driver. In some cases, the conductive element 585-b may be coupled to the select node of a select driver.

[0156] Figure 5M Cross-sectional side view of stack 505 after performing at least one deposition process step using a fifth set of vias (e.g., the fifth set of vias including the vias indicated by the arrows). In some cases, the deposition step may use the electrode material 595 to fill the via holes (e.g., the via holes corresponding to the fifth set of vias) and the holes (e.g., the opening 541-a as referenced Figure 5L as described) at the bottom layer. An additional electrode material 595 on top of the stack may be removed using a CMP process or an etch-back process. The via holes filled with the electrode material 595 may be referred to as conductive plugs (e.g., conductive plug 596). The conductive plugs may couple the conductive elements 585 to the semiconductor material (e.g., semiconductor material 580-a) of the TFT through an ohmic material (e.g., ohmic material 575-b) and may complete the construction of the TFT.

[0157] In some cases, Figure 5M the TFTs described in Figure 5M may include conductive plugs extending through a stack including a first layer, a second layer, and a third layer, a gate electrode at the second layer, a second electrode at the first layer, and semiconductor material at the first and second layers, the semiconductor material being coupled to the second electrode via a first segment of ohmic material at the first layer and to the conductive plug via a second segment of ohmic material at the third layer. In some cases, the semiconductor material at the first and second layers extends into the third layer. In some cases, the TFTs may include dielectric plugs extending through the gate electrode.

[0158] Figure 5M Two sets of TFTs are described (e.g., a first set of TFTs 535-a, a second set of TFTs 535-b). Each set of TFTs may include a first subgroup of TFTs (e.g., a subgroup of TFTs including an upper TFT and a lower TFT) coupled to a first node associated with a logic circuit system layer (e.g., via a conductive element 585-a coupled to an inhibit node of an inhibit driver) and a second subgroup of TFTs (e.g., a subgroup of TFTs including an upper TFT and a lower TFT) coupled to a second node associated with the logic circuit system layer (e.g., via a conductive element 585-b coupled to a select node of a select driver). As described with reference to Figure 5N each set of TFTs may drive (e.g., activate, inhibit) a single set of array electrodes (e.g., array electrodes 550-a1 connected to array electrode 550-d1 in the upper layer, array electrodes 550-a2 connected to array electrode 550-d2 in the lower layer). In some cases, the two sets of TFTs may be processed in different ways to correspondingly adjust their operating characteristics. For example, the first subgroup of TFTs may be processed to provide a low leakage current characteristic within a specific operating voltage range and the second subgroup of TFTs may be processed to provide a high drive current characteristic.

[0159] Figure 5M Current paths (e.g., current paths 545-a, 545-b) of the TFTs (e.g., the upper TFT of the first set of TFTs 535-a) are also described. The current paths illustrate how a particular TFT may couple a node of the logic circuit system layer to an array electrode when the TFT is activated to access a memory cell in the active array region of the array layer. For example, the conductive element 585-b may be coupled to a select node of a select driver. The conductive element 585-b is coupled to a conductive plug 596 that may serve as a common source for TFTs (e.g., the upper TFT and the lower TFT of the second subgroup of the first set of TFTs 535-a). The conductive plug 596 contacts the semiconductor material 580-b via an ohmic material 575-c. The semiconductor material 580-b may form an active channel that allows current to flow based on a voltage applied to the gate electrode 560 (e.g., the gate electrode 560-b1 including electrode material 561-b1).

[0160] In addition, the semiconductor material 580-b is connected to the array electrode 555-a1 through the ohmic material 575-b1. The array electrode 555-a1 can serve as the common drain of the upper TFTs of the first group of TFTs 535-a. In this way, when an active channel is formed within the semiconductor material (such as the semiconductor material 580-b) (when the voltage applied to the gate electrode (such as the gate electrode 560-b1 including the electrode material 561-b1) is greater than the threshold voltage of the upper TFT and when there is a voltage difference between the source (which is coupled to the node of the logic circuit system layer) and the drain (which is coupled to the array electrode) of the upper TFT), current can flow (such as the current path 545-b) between the source and the drain of the upper TFT (such as the upper TFT of the second TFT subgroup of the first group of TFTs 535-a).

[0161] Similarly, when another current path (such as the current path 545-a) is activated (such as when the upper TFT of the first TFT subgroup of the first group of TFTs 535-a is activated), the array electrode 555-a1 can be coupled to the conductive element 585-a, and the conductive element 585-a can be coupled to different nodes (such as the suppression node) of the logic circuit system layer. In this way, the array electrode (such as the array electrode 555-a1 in the upper layer) can be coupled to more than two nodes (such as the suppression node, the selection node) of the logic circuit system layer using the upper TFTs of the first group of TFTs 535-a. More generally, one of the four TFTs of the first group of TFTs 535-a can be activated to couple a node (such as the selection node or the suppression node connected to the source of the TFT) of the logic circuit system layer to the array electrode (such as the array electrode connected to the drain of the TFT).

[0162] The current flowing within the TFT flows in a way that surrounds the gate electrode and the TFT can be referred to as a wrap-around TFT. As Figure 5M illustrated, the channel length of the wrap-around TFT (such as the distance between the source and the drain of a TFT) can be greater than that of a vertical TFT (as described with reference to Figure 3K or a horizontal TFT (as described with reference to Figure 4Z ). This increased channel length can be beneficial for some aspects of TFT operation, such as being less prone to experiencing leakage current problems related to the channel length.

[0163] Figure 5N A top view illustrating a stack 505 in which the socket region includes two groups of TFTs (such as wrap-around TFTs) is described herein. Figure 5M The cross-sectional side view of Figure 5N can correspond to the socket region where the dashed line AA extends (as shown in Figure 5NDescribe aspects of the structural features constructed using the fabrication techniques described herein. For example, Figure 5N Depict the bulk region 581 of the TFT (e.g., the bulk region 581-a that includes the semiconductor material 580-a). The bulk region 581 may correspond to the third via group described in reference Figure 5A and 5F (e.g., the bulk region 581-a corresponds to the via 540-c1 of the third group).

[0164] Figure 5N Also depict the fifth via group as a square with horizontal lines (e.g., the via including the via 540-b1) or a square with vertical lines (e.g., the via including the via 540-b2). The via depicted as a square with horizontal lines may correspond to the via coupled to the conductive element 585-a or the conductive element 585-d. The via depicted as a square with vertical lines may correspond to the via coupled to the conductive element 585-b or the conductive element 585-c. In some cases, the conductive element 585-a (or the conductive element 585-d) may be coupled to the inhibition node of the inhibition driver and the conductive element 585-b (or the conductive element 585-c) may be coupled to the selection node of the selection driver. Each via of the fifth via group may include a conductive plug (e.g., the conductive plug 596 described in reference Figure 5J ) surrounded by an insulating material 576 (e.g., an insulating material deposited on the surface of the ohmic material 575 at the D1 layer, as described in reference Figure 5M ). However, the conductive plug may be coupled to the corresponding bulk region 581 at the second layer of the stack through the ohmic material, as described in reference Figure 5M

[0165] Figure 5N Also depict an ohmic material (e.g., the ohmic material 575-a) positioned between the bulk region (e.g., the bulk region 581-a) and the electrode tab (e.g., the electrode tab 555-a connected to the array electrodes 550-a and 550-d). The ohmic material provides a low-resistance path for current to flow between the bulk region (e.g., where a channel for current flow may be formed) and the electrode tab (e.g., the electrode tab 555-a) or the conductive plug (e.g., the conductive plug 596).

[0166] Figure 5N Also depict current paths (e.g., the current paths 545-e, 545-f). The current path 545-e may correspond to the reference Figure 5MThe described current path 545-a or current path 545-b. In other words, the current flow following the current path 545-a (or current path 545-b) can reach the electrode pad 555-b and continue to flow using the array electrode 550-a and the array electrode 550-c. Similarly, the current path 545-f can correspond to the reference Figure 5M The described current path 545-c or current path 545-d.

[0167] Figure 5N It is also illustrated that more than one TFT (such as a wrap-around TFT) can be connected in series to provide a greater amount of current than a single TFT can provide. For example, Figure 5N It depicts that the array electrodes can be joined when the array electrode (such as the array electrode 550-a) is connected to the electrode pad (such as the electrode pad 555-a) which is further connected to another array electrode (such as the array electrode 550-c). As an example, Figure 5N It depicts five (5) individual TFTs connected in series to form one TFT (such as indicated by five conductive plugs arranged in a single column connected to a single electrode pad 555-a), which can supply four times more current than a single TFT. Any number of TFTs can be connected in series to provide any amount of current that may be needed or desired, as described herein.

[0168] Figure 5N The TFT configuration illustrated in can facilitate providing an electrical connection dedicated to the bulk region 581. This electrical connection dedicated to the bulk region can be beneficial for aspects of TFT operation, such as avoiding problems related to the floating body of the TFT. For example, the bulk region 581-b can be extended to include additional via rows (such as including three via rows between the gate electrode 560-b and the gate electrode 560-c instead of one via row), such that one or more vias of the additional vias (such as one or more vias of the middle row of the three via rows) can be coupled to the nodes of the logic circuit system layer using the manufacturing techniques described herein. In some cases, one or more holes (such as via holes corresponding to one or more vias) can be formed through the bulk region (such as the bulk region 581-b containing the semiconductor material 580) to the logic circuit system layer and one or more holes can be filled with an electrode material (such as the electrode material 595 referenced Figure 5M described) to form the fourth electrode of the transistor (such as the base of the TFT). Additionally or alternatively, the bulk region 581-a can be extended to include additional vias (such as vias positioned at the left boundary of the bulk region 581-a) and the additional vias can be coupled to the logic circuit system layer. In this way, the logic circuit system can provide a specific voltage to the bulk region based on the various operating modes of the TFT (such as operating in an inhibition mode or a selection mode).

[0169] Figures 6A to 6RDescribe exemplary fabrication techniques in accordance with the present disclosure. Figures 6A to 6R Describe aspects of several process steps for simultaneously fabricating more than two TFTs, such as hybrid TFTs in which current flows in a combined vertical and horizontal direction when the TFTs are activated. In some cases, such TFTs can be fabricated in the socket region of the array layer, as described herein. Figures 6A to 6R Include a top view (e.g., layout of the socket region) of a portion of the socket region to illustrate various structures in which different via groups can be used to simultaneously fabricate TFTs. Figures 6A to 6R Also include a cross-sectional side view of a portion of the socket region to illustrate aspects of process features during several process steps for simultaneously fabricating TFTs.

[0170] Figures 6A to 6R Describe for fabricating a composite stack (e.g., stack 305 for fabricating vertical TFTs as described in Figures 3A to 3L stack 405 for fabricating planar TFTs as described in Figures 4A to 4AA stack 505 for fabricating wrap-around TFTs as described in Figures 5A to 5N exemplary fabrication techniques for hybrid TFTs within the composite stack. Thus, the composite stack can be used to fabricate vertical TFTs, planar TFTs, wrap-around TFTs, hybrid TFTs, or any combination thereof in the socket region of the array layer. As described herein, the composite stack can also be used to fabricate a 3D cross-point array of memory cells and associated electrodes in the active array region of the array layer. In this way, the composite stack can provide an array layer that constructs each including a memory cell plane and an electrode, where the electrode (and thus the memory cell) can be further coupled to a TFT (e.g., vertical TFT, horizontal TFT, wrap-around TFT, hybrid TFT, or any combination thereof).

[0171] Figure 6A Describe a top view of stack 605 in which a socket region including more than two TFTs (e.g., hybrid TFTs) can be fabricated, as described herein. As an example, Figure 6ADescribe four groups of TFTs. Each group of TFTs can drive a single group of array electrodes from one end or the other end of the array electrodes. In some cases, two groups of TFTs can drive a single group of array electrodes, such as a first group of TFTs from one end and a second group of TFTs from the other end. Additionally, the first group of TFTs can couple the array electrodes to a first node associated with the logic circuit system layer and the second subgroup of TFTs can couple the array electrodes to a second node associated with the logic circuit system layer. In some cases, the first node can correspond to a selection node and the first circuit can be referred to as a selection driver. In some cases, the second node can correspond to an inhibition node and the second circuit can be referred to as an inhibition driver. In some cases, the two groups of TFTs can be processed in different ways to correspondingly adjust their operating characteristics. For example, the first group of TFTs can be processed to provide high drive current characteristics and the second subgroup of TFTs can be processed to provide low leakage current characteristics within a specific operating voltage range.

[0172] Stack 605 can be a reference Figures 3A to 3L An example of the described stack 305. Figure 6A Describe a group of vias 640 in an array pattern (depicted as white squares, squares with an ×, squares with an ○). A group of vias 640 can be formed to pass through the top layer (e.g., layer 310, HM layer of stack 305) of stack 605 that includes a first layer (e.g., layer 315, D1 layer of stack 305), a second layer (e.g., layer 320, DM layer of stack 305), and a third layer (e.g., layer 325, D2 layer of stack 305). A group of vias 640 can be a reference Figures 3A to 3L An example of the described group of vias 340. Figure 6A Also describe various structures that can be formed simultaneously within stack 605 using different via groups. For example, Figure 6A Describe a group of gate electrodes 660 of the TFT (which can be a reference Figures 3A to 3L An example of the described gate electrodes 360), a group of array electrodes 650 (which can be a reference Figures 3A to 3L An example of the described array electrodes 350), where each can be formed at different junctions of the process sequence for constructing the TFT.

[0173] A first subgroup of vias (e.g., the first group of vias 640-a) can be used to construct a group of gate electrodes 660 (e.g., gate electrodes 660-a, gate electrodes 660-b), as referenced herein Figures 3C to 3F as described. Additionally, as described elsewhere, a group of array electrodes 650 (e.g., array electrodes 650-a to array electrodes 650-d) can be constructed using vias depicted as squares with an × (e.g., the second via group). Additionally, a subgroup of the second via group (e.g., vias 640-b1, vias 640-b2) can be used to construct a group of electrode pads (e.g., electrode pads 655-a, electrode pads 655-b). AsFigure 6A As depicted, each electrode sheet (e.g., electrode sheet 655-b) can be connected to an array electrode (e.g., array electrode 650-a). Thus, the array electrode group can include a set of electrode sheets.

[0174] In some cases, according to the manufacturing techniques described herein, a subgroup of array electrodes (e.g., array electrodes 650-b, array electrode 650-c) can be severed (e.g., separated, disconnected) from the rest of the array electrodes by using a subgroup of vias (e.g., via 640-x). In some cases, the array electrode can act as the second electrode of a TFT. Additionally, a third via (e.g., via 640-c1, via 640-c2) can be used to construct a conductive plug, as referenced herein Figure 6P and 6Q described. In some cases, the conductive plug can act as the third electrode of a TFT and the conductive plug (e.g., the third electrode) can extend at least through a third layer (e.g., layer 325 of stack 305, D2 layer). Figure 6A Also illustrated is a third via group formed to pass through the top layer of stack 605 (e.g., the via depicted as a square with a ○).

[0175] Figures 6B to 6Q The cross-sectional side view of Figure 6A can correspond to where the dashed line AA in Figure 6B extends through the socket area of the via. For example,

[0176] Figure 6B Illustrated is a cross-sectional side view of stack 605, as referenced Figure 6A described. Figure 6B Illustrated is that electrode material 661 (which can be an example of electrode material 361 as referenced Figures 3A to 3L described) can have been previously formed in the second layer (e.g., DM layer) of stack 605, as referenced herein Figures 3C to 3F described. Figure 6B The electrode material 661 depicted in Figure 6A corresponds to the gate electrode 660 depicted in Figure 6B Illustrated is an insulating layer 665 (which can be as referenced Figures 3A to 3LThe described example of the insulating layer 365 partially surrounds the electrode material 661. Figure 6B It is also described that electrode sheets (such as electrode sheet 655-b1, electrode sheet 655-b2) may have been previously formed in the first layer (such as D1 layer) of the stack 605. In addition, Figure 6B It describes via holes filled with dielectric material, which may be referred to as dielectric plugs (such as dielectric plug 644-a1, dielectric plug 644-a2) extending through the gate electrode (such as gate electrode 660-a including electrode material 661-a).

[0177] Figure 6C It shows a cross-sectional side view of the stack 605 after performing at least one etching process step using a third via group (such as the vias indicated by the arrows). In some cases, the etching process step may include an anisotropic etching process, which may form via holes (such as via holes 641-c1 to via holes 641-c5) corresponding to the third via group (as described herein), for example, vertically removing various materials through the stack 605 and stopping on the bottom layer of the stack 605.

[0178] Figure 6D It shows a cross-sectional side view of the stack 605 after performing at least one etching process step using a third via group to form a via cavity 642. The via cavity 642 may be concentric with the via holes formed within the stack 605, as referenced Figure 6C as described. In some cases, the etching scheme may include an isotropic etching process, which selectively removes the first dielectric material of the first layer (such as D1 layer) and the second dielectric material of the third layer (such as D2 layer). The isotropic etching process may leave other materials exposed in the via holes, such as dummy materials of the second layer (such as DM layer), insulating layer 665, array electrode sheets 655. In some cases, the via cavities corresponding to more than two via holes (such as via holes 641-c2 to via holes 641-c4) may be combined to form a via cavity (such as via cavity 643). Due to the isotropic etching process, the array electrodes (such as electrode sheets 655) are exposed to subsequent process steps. In some cases, the via cavities (such as via cavity 642-c1a, via cavity 642-c1b, via cavity 642-c1c) may span the first layer (such as D1 layer), the second layer (such as DM layer), and the third layer (such as D2 layer).

[0179] Figure 6E It shows a cross-sectional side view of the stack 605 after performing at least one deposition process step using a third via group (such as the vias indicated by the arrows). In some cases, the deposition process step may use an ohmic material 675, which may be a reference Figures 3A to 3LExamples of the described ohmic material 375) are used to fill the vias (such as via 641-c1 to via 641-c5) and associated via cavities and channels (such as the described via cavity 642 and channel 643). Due to the deposition process steps, the ohmic material 675 can contact the array electrodes 655. Figure 6D The described via cavity 642 and channel 643).

[0180] Figure 6F A cross-sectional side view of the stack 605 after performing at least one etching process step and deposition process step using a third via group (such as the vias indicated by the arrows) is illustrated. In some cases, the etching process step may include an anisotropic etching process that can vertically remove the ohmic material 675 in the vias (such as the vias corresponding to the third via group) thereby leaving the ohmic material 675 in the via cavity (such as ohmic material 675-a1, ohmic material 675-a2, ohmic material 675-a3). The etching process step may leave other materials exposed in the vias, such as placeholder material of the DM layer, insulating layer 665. In some cases, the deposition process step may use an insulating material to fill the vias formed by the etching process step (such as the anisotropic etching process that has removed the ohmic material in the vias). In some cases, a CMP process or etch-back process may be used to remove the additional insulating material on top of the stack 605.

[0181] Figure 6G A cross-sectional side view of the stack 605 after performing at least one etching process step using a fourth via group (such as the vias indicated by the arrows) is illustrated. Referring to Figure 6A , the fourth via group may include via 640-d1 or via 640-d2. In some cases, the fourth via group (such as via 640-d1) may include a subgroup of the third via group (such as the vias depicted as squares with ○) and the via that can form the third electrode of the TFT (such as via 640-c1), as described in reference to Figure 6P and 6Q . In some cases, the etching process step may include an anisotropic etching process that can vertically remove the dielectric material (or insulating material) that may be present in the vias corresponding to the fourth via group. The anisotropic etching process can leave other materials exposed in the vias substantially unchanged, such as the ohmic material 675, the electrode material 661 forming the gate electrode 660, the insulating layer 665, the first dielectric material of the first layer (such as D1 layer), the placeholder material of the second layer (such as DM layer), the second dielectric material of the third layer (such as D2 layer). Due to the anisotropic etching process, the ohmic material 675 (such as the ohmic material 675-b that has filled the channel 643 described in reference to Figure 6D ) can be exposed to subsequent process steps.

[0182] Figure 6H A cross-sectional side view of stack 605 after performing at least one etch process step using a fourth via group (e.g., the vias indicated by the arrows) is illustrated. In some cases, the etch process step may include an isotropic etch process that selectively removes the ohmic material 675 of the filled channels (e.g., channel 643 as referenced Figure 6D as described). The isotropic etch process may leave other materials exposed to the via holes and channels substantially unchanged, such as the electrode material 661 forming the gate electrode 660, the insulating layer 665, the first dielectric material at the first layer (e.g., D1 layer), the dummy material at the second layer (e.g., DM layer), and the second dielectric material at the third layer (e.g., D2 layer). Due to the isotropic etch process, the first dielectric material at the first layer (e.g., D1 layer) and the dummy material at the second layer (e.g., DM layer) may be exposed to subsequent process steps.

[0183] Figure 6I A cross-sectional side view of stack 605 after performing at least one etch process step using a fourth via group (e.g., the vias indicated by the arrows) is illustrated. In some cases, the etch process step may include an isotropic etch process that selectively removes the first dielectric material at the first layer (e.g., D1 layer) and the dummy material at the second layer (e.g., DM layer). The isotropic etch process may leave other materials exposed to the via holes and channels substantially unchanged, such as the electrode material 661 forming the gate electrode 660, the insulating layer 665, the second dielectric material at the third layer (e.g., D2 layer), and the ohmic material 675. Due to the isotropic etch process, some portions of the insulating layer 665 may be exposed to subsequent process steps. In some cases, using the fourth via group, the isotropic etch process may form via cavities (e.g., via cavity 642-d1, via cavity 642-d2) and channels (e.g., channel 643-a that includes more than two adjacent via cavities). Such via cavities or channels may span the first layer (e.g., D1 layer), the second layer (e.g., DM layer), and the third layer (e.g., D2 layer).

[0184] Figure 6J A cross-sectional side view of stack 605 after performing at least one etch process step and a deposition process step using a fourth via group (e.g., the vias indicated by the arrows) is illustrated. In some cases, the etch process step may include an isotropic etch process that selectively removes the exposed portions of the insulating layer 665. The isotropic etch process may leave other materials exposed to the via holes and channels substantially unchanged, such as the electrode material 661 forming the gate electrode 660, the second dielectric material at the third layer (e.g., D2 layer), and the ohmic material 675. In some cases, the deposition step may form an oxide material 670 that contacts the electrode material 661 forming the gate electrode 660 (which may be referenced Figures 3A to 3LExamples of the described oxide material 370). In other words, due to the etching process steps and the deposition process steps, the exposed portions of the insulating layer 665 can be replaced by the oxide material 670. In some cases, the oxide material 670 can be referred to as the gate oxide of the TFT.

[0185] Figure 6K A cross-sectional side view of the stack 605 after performing at least one deposition process step using a fourth via group (e.g., the vias indicated by the arrows) is illustrated. In some cases, the deposition process step can use the semiconductor material 680 to fill the reference Figure 6I Via cavities or channels described (e.g., via cavity 642, channel 643). A CMP process or an etch-back process can be used to remove the excess semiconductor material on top of the stack 605. Due to using the semiconductor material 680 to fill the via cavity or channel, the semiconductor material 680 can contact the ohmic material 675 that is further connected to the array electrode (e.g., electrode pad 655, the second electrode of the TFT). In addition, the semiconductor material 680 can contact the oxide material 670 that is further connected to the gate electrode 660 (e.g., the gate electrode 660 including the electrode material 661).

[0186] Figure 6L A cross-sectional side view of the stack 605 after performing at least one etching process step and one deposition process step using a fourth via group (e.g., the vias indicated by the arrows) is illustrated. In some cases, the etching process step can remove the semiconductor material 680 that has filled the reference Figure 6K Via cavities or channels described to form via holes (e.g., via holes corresponding to the fourth via group). In some cases, the deposition process step can use an insulating material (or a dielectric material) to fill the via holes. In some cases, removing the semiconductor material 680 within the via holes corresponding to the fourth via group can remove the parasitic current paths with a shorter channel length of the TFT, such that the main current path of the TFT can have a longer channel length, as described in the reference Figure 6Q Described. In some cases, the deposition process step can use a dielectric material to fill the via holes. In some cases, the via holes filled with the dielectric material can be referred to as dielectric plugs (e.g., dielectric plugs 644-a, dielectric plugs 644-b) extending through the gate electrode (e.g., the gate electrode 660-a including the electrode material 661-a). A CMP process or an etch-back process can be used to remove the excess insulating material on top of the stack 605.

[0187] Figure 6M A cross-sectional side view of the stack 605 after performing at least one etching process step and one deposition process step using a fifth via group (e.g., the vias indicated by the arrows) is illustrated. Reference Figure 6A, the fifth via group may include via 640-c1 or via 640-c2. In some cases, the etching process step may include an anisotropic etching process that can vertically remove the insulating material filling the via hole (as described in reference Figure 6L ) to thereby form a via hole (e.g., via hole 641-c2 corresponding to via 640-c2) passing through the first layer (e.g., D1 layer), the second layer (e.g., DM layer), and the third layer (e.g., D2 layer). The anisotropic etching process using the fifth via group can expose the semiconductor material 680 in the via hole (e.g., via hole 641-c2 corresponding to via 640-c2) to subsequent process steps. In some cases, the deposition step may selectively grow an insulating material 690 in contact with the semiconductor material 680 at the first layer (e.g., D1 layer) and the second layer (e.g., DM layer).

[0188] Figure 6N A cross-sectional side view of the stack 605 after performing at least one etching process step using the fifth via group (e.g., the via indicated by the arrow) is illustrated. In some cases, the etching process step using the fifth via group (e.g., via 640-c2) may laterally remove the semiconductor material 680 at the third layer (e.g., D2 layer) to form a cavity (e.g., cavity 642-e) at the third layer. The insulating material 690 on the surface of the semiconductor material 680 can keep the semiconductor material 680 at the first layer (e.g., D1 layer) and the second layer (e.g., DM layer). The etching process step may expose a portion of the semiconductor material 680 to subsequent process steps.

[0189] Figure 6O A cross-sectional side view of the stack 605 after performing at least one deposition process step using the fifth via group (e.g., the via indicated by the arrow) is illustrated. In some cases, the deposition process step may fill the via hole (e.g., via hole 641-c2 as described in reference Figure 6M ) and the associated via cavity (e.g., via cavity 642-e as described in reference Figure 6N ) with an ohmic material 675-e.

[0190] Figure 6PCross-sectional side view of stack 605 after performing at least one etching process step using a fifth via group (e.g., the vias indicated by the arrows). In some cases, the etching process may include an anisotropic etching process that may remove ohmic material 675-e in a via hole (e.g., the via hole corresponding to via 640-c2). In some cases, the anisotropic etching process may create a hole (e.g., hole 641) at the bottom layer (e.g., layer 330) of stack 605. The hole may be coupled to a conductive element (e.g., conductive element 685) that may be part of a logic circuit system layer. In some cases, conductive element 685 may be coupled to an inhibit node of an inhibit driver. In some cases, conductive element 685 may be coupled to a select node of a select driver.

[0191] Figure 6Q Cross-sectional side view of stack 605 after performing at least one deposition process step using a fifth group of vias (e.g., the vias indicated by the arrows). In some cases, the deposition step may use electrode material 695 to fill the via holes (e.g., the via hole corresponding to via 640-c2) and holes (e.g., hole 641 as described in reference Figure 6P The via holes filled with electrode material 695 may be referred to as conductive plugs (e.g., conductive plug 696). Conductive plug 696 may couple conductive element 685 to the semiconductor material (e.g., semiconductor material 680-a) of the TFT through an ohmic material (e.g., ohmic material 675-e) and may complete the construction of the TFT.

[0192] In some cases, Figure 6Q The TFTs illustrated in

[0193] Figure 6Q The current paths (e.g., current paths 645-a, current paths 645-b) of the TFTs (e.g., upper TFTs) are also illustrated. The current paths illustrate how a particular TFT may couple a node of the logic circuit system layer to an array electrode when the TFT is activated to access a memory cell in the active array region of the array layer. For example, conductive element 685 may be coupled to a select node of a select driver. Conductive element 685 and may act as Figure 6QThe common source conductive plugs 696 of the TFTs (e.g., both the upper TFT and the lower TFT) depicted therein are coupled. The conductive plugs 696 are in contact with the semiconductor material 680-a through the ohmic material 675-e. The semiconductor material 680-a can form an active channel for current to flow based on the voltage applied to the gate electrode 660 (e.g., the gate electrode 660-a including the electrode material 661-a).

[0194] In addition, the semiconductor material 680-a is connected to the electrode pad 655-a1 through the ohmic material 675-a1. The electrode pad 655-a1 (and thus Figure 6R the array electrode 650-e depicted therein) can act as the drain of the TFT (e.g., the left TFT of the upper TFT). In this way, when an active channel is formed within the semiconductor material (e.g., the semiconductor material 680-a) (when the voltage applied to the gate electrode (e.g., the gate electrode 660-a including the electrode material 661-a) is greater than the threshold voltage of the TFT and when there is a voltage difference between the source of the TFT (which is coupled to the node of the logic circuit system layer) and the drain (which is coupled to the array electrode)), current can flow (e.g., the current path 645-a) between the source and the drain of the TFT.

[0195] The current flowing within the TFT flows in both the vertical and horizontal directions (e.g., relative to the horizontal substrate) and the TFT can be referred to as a hybrid TFT (e.g., a hybrid of the vertical TFT described in Figure 3K and the horizontal TFT described in Figure 4Z ). As Figure 6Q illustrated, the channel length of the hybrid TFT (e.g., the distance between the source and the drain of the TFT) can be greater than the channel length of the vertical TFT or the horizontal TFT. This increased channel length can be beneficial for some aspects of TFT operation, such as being less likely to experience leakage current problems related to the channel length.

[0196] Figure 6R A top view illustrating a stack 605 in which the socket area includes four TFTs (e.g., hybrid TFTs) is shown. Figure 6Q The cross-sectional side view of Figure 6R can correspond to the socket area where the dashed line AA extends, as Figure 6R shown. Figure 6R Aspects of the structural features constructed using the manufacturing techniques described herein are illustrated. For example, Figure 6R the array electrode 650 that can act as the second electrode (e.g., the drain) of the TFT, the gate electrode 660 of the TFT, and the conductive plug 696 are depicted. Figure 6Q A top view of the current paths (e.g., the current paths 645-c, the current path 645-d) described in

[0197] Figures 7A to 7D A diagram illustrating an exemplary memory array including an active array region and a socket region that supports memory array decoding and interconnects, in accordance with embodiments of the present disclosure. Figures 7A to 7D Describes aspects where a set of TFTs can be simultaneously constructed within the composite stack 705 described in reference Figure 7C such as one or more vertically integrated composite stacks 305 described in reference Figures 3A to 3L within the socket region. Figures 7A to 7D A top view (e.g., layout of the socket region) including a portion of the socket region to illustrate that a subgroup of the set of TFTs can be configured to couple nodes of a circuit system layer (e.g., row decoder 120 constructed in substrate 204) to a subgroup of array electrodes (e.g., access lines, word lines, bit lines) of the active array region where memory cells are located. Additionally, Figures 7A to 7D A cross-sectional side view including a different portion of the socket region to illustrate that the set of TFTs can couple the array electrodes to the nodes of the circuit system layer. In some cases, the circuit system layer can be a portion of the substrate above which the array layer is located.

[0198] Figures 7A to 7D Also includes a circuit representation of the set of TFTs to illustrate that the set of TFTs can facilitate access operations in conjunction with the circuit system layer. Figures 7A to 7D Depicts the socket region including a set of vertical TFTs as an illustrative example, but the present disclosure is not limited thereto. For example, the socket region can include other types of TFTs described herein or any combination thereof. Additionally, Figures 3A to 3L describes aspects of the manufacturing techniques and operations of the vertical TFTs.

[0199] Figure 7A A top view 700 of an array layer including an active array region and two socket regions, each including a set of TFTs. In some cases, the active array region can include a set of memory cell levels constructed within the composite stack 705. As described herein, the set of TFTs can also be constructed in the socket regions of the composite stack 705. In some cases, the set of TFTs can include vertical TFTs described in reference Figures 3A to 3L Thus, each TFT of the set of TFTs can include a conductive plug 796 (e.g., reference Figure 3LThe described conductive plug 396). The TFT group may further include a first TFT subgroup (e.g., TFTs 735-a, 735-c) and a second TFT subgroup (e.g., TFTs 735-b, 735-d). In some cases, the first TFT subgroup (e.g., TFT 735-a) may be configured to couple a first node (e.g., a select node) of a circuit system layer (e.g., a row decoder 120 constructed in substrate 204) to one or more array electrodes 750 (which may also be referred to as electrodes, access lines, word lines, or bit lines). Additionally or alternatively, the second TFT subgroup (e.g., TFT 735-b) may be configured to couple a second node (e.g., a suppression node) of the circuit system layer to one or more array electrodes 750.

[0200] Furthermore, in some cases, the first TFT subgroup and the second TFT subgroup may be constructed in different ways based on their operating characteristics. For example, the first TFT subgroup (e.g., the TFT for selection) may be constructed to provide an appropriate drive current amount, and the second TFT subgroup (e.g., the TFT for suppression) may be constructed to provide an acceptable leakage current (e.g., limit the leakage current to an acceptable amount). In some cases, the second TFT subgroup may be constructed using relatively simpler processing steps (e.g., associated with a smaller number of processing steps than the first TFT subgroup) or may be constructed to facilitate lower voltage operation (e.g., configured to support a lower supply voltage than the first TFT subgroup). In some cases, the first TFT subgroup and the second TFT subgroup may be different types of TFTs (e.g., n-type TFTs, p-type TFTs). In some cases, a base terminal (e.g., a fourth terminal referring to the base of the described TFT) may be incorporated into the composite stack 705 such that the base terminal may facilitate controlling the threshold voltage of the TFT. Figure 5N In some cases, the base terminal of the described TFT may be incorporated into the composite stack 705 such that the base terminal may facilitate controlling the threshold voltage of the TFT.

[0201] In some cases, the two socket regions shown in the top view 700 may illustrate socket regions associated with word lines (which may also be referred to as a first type of access line). The array electrodes 750 may correspond to electrodes (e.g., word lines) at the first layer of the composite stack (e.g., the D1 layer of stack 305). In other cases, the two socket regions shown in the top view 700 may illustrate socket regions associated with bit lines (which may also be referred to as a second type of access line). Thus, the array electrodes 750 may instead correspond to electrodes (e.g., bit lines) at the third layer (e.g., the D2 layer of stack 305). Memory cells associated with the array electrodes (e.g., word lines, first type of access lines, bit lines, second type of access lines) may be constructed at the second layer (e.g., the DM layer of stack 305).

[0202] The top view 700 also depicts that one or more access cavities (such as access cavity 742-a) can be used to divide the first array of electrodes (such as electrode 750-a) into more than two arrays of electrodes (such as electrode 750-a1, electrode 750-a2). Additionally, one or more access cavities (such as access cavity 742-b) can be used to divide the second array of electrodes (such as electrode 750-b) into more than two arrays of electrodes (such as electrode 750-b1, electrode 750-b2). In some cases, a set of access paths (such as the paths located between electrode 750-a and electrode 750-b) can be used to construct the first array of electrodes and the second array of electrodes. In this way, the first array of electrodes (such as electrode 750-a1) can be coupled to a first group of two TFTs (such as TFT 735-a1, TFT 735-b1), and the second array of electrodes (such as electrode 750-b1) can be coupled to a second group of two TFTs (such as TFT 735-c1, TFT 735-d1). In some cases, the TFTs (such as TFT 735-a1, TFT 735-b1) can be coupled to the electrode (such as electrode 750-a1) at a point (such as the midpoint, center point within the central region) between the two ends of the electrode (such as electrode 750-a1). Similarly, the TFTs (such as TFT 735-c1, TFT 735-d1) can be coupled to the electrode (such as electrode 750-b1) between the two ends of the electrode (such as electrode 750-b1) (such as the midpoint, center point within the central region).

[0203] In some cases, the first electrode segment (such as electrode 750-b2) can be located at the layer of a level (such as layer D1) and be shorter than the electrode (such as electrode 750-a1), where the electrode can be a first type of access line (such as a word line) and extend in a first direction at the layer of the level, and where a conductive plug (such as conductive plug 796-b) can be located between the electrode and the first electrode segment. In some cases, a second access line of the first type (such as electrode 750-b1) can extend in a first direction at the layer of the level, where the second access line (such as electrode 750-b1) can be coaxial with the first electrode segment (such as electrode 750-b2). In some cases, the second electrode segment (such as electrode 750-a2) can be located at the layer of the level and be shorter than the electrode (such as electrode 750-a1), where the second electrode segment can be coaxial with the electrode.

[0204] Thus, the TFT group can facilitate access operations (such as read operations, write operations) to memory cells associated with array electrodes in the active array region. For example, when the TFT 735-a1 is activated, the select node of the circuit system layer (such as the row decoder 120 constructed in the substrate 204) can be coupled to the electrode 750-a1 (and thus the memory cell associated with the electrode 750-a1) to perform an access operation. Additionally or alternatively, other TFTs (such as the TFT 735-d) can be activated to couple the inhibit node to a subgroup of array electrodes (such as the electrode 750-b1-containing electrodes not selected during the access operation) to maintain the leakage current level associated with the unselected memory cells below an acceptable threshold during the access operation.

[0205] Figure 7A Top views 700-a and 700-b of socket regions each including a group of TFTs are shown. The top view 700-a can be part of a word line socket region that includes array electrodes (such as the electrode 750-c in the D1 layer of the composite stack 705) that can correspond to word lines extending in a first direction. Additionally, the top view 700-a depicts a group of TFTs (such as the TFT 735-aa, TFT 735-bb) that includes conductive plugs (such as the conductive plug 796-c). As described herein, the TFT 735-aa can be coupled to the select node of the circuit system layer and the TFT 735-bb can be coupled to the inhibit node of the circuit system layer.

[0206] Similarly, the top view 700-b can be part of a bit line socket region that includes array electrodes (such as the electrode 751 in the D2 layer of the composite stack 705) that can correspond to bit lines extending in a second direction (such as a second direction that is substantially orthogonal to the first direction). Additionally, the top view 700-b depicts a group of TFTs (such as the TFT 735-ee, TFT 735-ff) that includes conductive plugs (such as the conductive plug 796-e). As described herein, the TFT 735-ee can be coupled to the select node of the circuit system layer and the TFT 735-ff can be coupled to the inhibit node of the circuit system layer.

[0207] In some cases, the socket region of the array layer can include a first socket region (such as the socket region associated with the word line) that includes a conductive plug (such as the conductive plug 796-c), where the electrode (such as the electrode 750-c) can include a first type of access line (such as a word line) extending into the first socket region. In some cases, the socket region of the array layer can include a second socket region (such as the socket region associated with the bit line) that includes a second conductive plug (such as the conductive plug 796-e), where the second electrode (such as the electrode 751-a) can include a second type of access line (such as a bit line) extending into the second socket region.

[0208] Figure 7B Illustrate a top view 701 of a socket area and another top view 702 of a vertical TFT that may be included in the socket area. The top view 701 depicts a set of array electrodes 750, a set of gate electrodes 760 (which may be an example of the gate electrode 360 described as a reference Figures 3A to 3L ), a set of vias 742, and a set of TFTs 735, where each TFT 735 is in contact with a corresponding conductive plug 796. In some cases, the top view 701 may be a variant of the socket area depicted in the top view 700.

[0209] For example, a subgroup of TFTs (e.g., a group of two TFTs) may be offset from the remaining TFTs. For example, TFTs 735-e1 and 735-e2 are offset relative to TFTs 735-e3 and 735-e4. Due to the offset of the subgroup of TFTs in a zigzag pattern, the distance between the conductive plugs in the socket depicted in the top view 701 (e.g., the distance between conductive plug 796-e2 and conductive plug 796-e3) may be greater than the corresponding distance in the socket depicted in the top view 700. This increase in distance can contribute to improved results during the lithography step. In some cases, each TFT (e.g., instead of a group of two TFTs) may be offset from adjacent TFTs such that the minimum distance between conductive plugs may be the diagonal distance between two conductive plugs. For example, although the top view 701 illustrates an example where the TFTs are offset in pairs (zigzag) (the TFT pairs are offset from each other), it should be understood that any number of other offset patterns are possible, including configurations where each TFT within the socket area is offset from each neighboring (adjacent) TFT within the socket area.

[0210] In some cases, the socket area may include a first gate electrode (e.g., gate electrode 760-b) that may surround conductive plugs (e.g., conductive layer plug 796-e3, conductive plug 796-e4) and a second gate electrode (e.g., gate electrode 760-a) that may surround a first additional conductive plug (e.g., conductive plug 796-e5) extending through the layer set and a second additional conductive plug (e.g., conductive plug 796-e2) extending through the layer set, where electrodes (e.g., electrodes 750-e, 750-f) may extend between the first additional conductive plug and the second additional conductive plug.

[0211] A top view 702 of a vertical TFT may depict a variation of the vertical TFT depicted in the top view 700. For example, the gate electrode 760-c may be configured to surround more than one conductive plug (e.g., four conductive plugs 796-f1 to 796-f4). Accordingly, the vertical TFT may generate a drive current that is nearly four (4) times greater than the drive current that individual TFTs (e.g., TFT 735-a1, TFT 735-c1 shown in the top view 700) may generate. For clarity, other features of the vertical TFT in the top view 702 have been omitted.

[0212] Figure 7C An example schematic cross-sectional side view 703 of an array layer including eight (8) memory cell levels is illustrated. In some cases, the eight (8) memory cell levels may include five (5) groups of word lines each extending along a first direction (e.g., the x direction) and four (4) groups of bit lines each extending along a second direction (e.g., the z direction). The memory cell levels (depicted as hatched rectangles in the cross-sectional side view 703) may be positioned between sub-groups of word lines (e.g., WL1) and sub-groups of bit lines (e.g., BL1). Some access lines (e.g., word lines, bit lines) may be shared by more than one memory cell level. For example, WL2 may be shared by two memory cell levels (i.e., a first memory cell level positioned between WL2 and BL1 and a second memory cell level positioned between WL2 and BL2). Similarly, BL4 may be shared by two memory cell levels (i.e., a third memory cell level positioned between BL4 and WL4 and a fourth memory cell level positioned between BL4 and WL5).

[0213] The cross-sectional side view 703 illustrates various layers of the composite stack 705. For example, the cross-sectional side view 703 depicts five (5) first layers 715 (e.g., the D1 layer, layer 315 as described with reference Figure 3A ), each of which may include a sub-group of word lines (e.g., WL1), eight (8) second layers 720 (e.g., the DM layer, layer 320 as described with reference Figure 3A ), each of which may include a memory cell level, and four (4) third layers 725 (e.g., the D2 layer, layer 325 as described with reference Figure 3A ).

[0214] Figure 7C A cross-sectional side view 704 of a socket region of the array layer is also illustrated. The cross-sectional side view 704-a may correspond to a cross-sectional side view of a word line socket region across the dashed line AA, as shown in the top view 700-a described with reference Figure 7A ). The cross-sectional side view 704-a may correspond to the composite stack 705 and illustrate five (5) array electrodes 750 (e.g., array electrodes 750-f1 to 750-f5 at the D1 layer, which may be referred to as word lines or a first type of access line).

[0215] Cross-sectional side view 704-a also depicts conductive plugs (e.g., conductive plug 796-c, conductive plug 796-d) each of which may be coupled to a conductive element (e.g., conductive element 785-a1, conductive element 785-b1). Each conductive element may be coupled to a node (e.g., a select node, an inhibit node) of a circuit system layer (e.g., a word line select driver, a word line inhibit driver). Cross-sectional side view 704-a also depicts eight (8) pairs of gate electrodes (e.g., a pair of gate electrodes at each layer 720), where each gate electrode surrounds a conductive electrode (e.g., conductive plug 796-c, conductive plug 796-d). Thus, cross-sectional side view 704-a depicts a total of sixteen (16) TFTs. In addition, cross-sectional side view 704-a illustrates current path 745-a, and a group of TFTs in the word line socket region may activate current path 745-a such that drive current may flow between conductive element 785 and word line 750 during an access operation.

[0216] Similarly, cross-sectional side view 704-b may correspond to a cross-sectional side view of the bit line socket region taken along dashed line BB, as shown in top view 700-b described in reference Figure 7A Cross-sectional side view 704-b may also correspond to composite stack 705 and illustrates four (4) array electrodes 751 (e.g., array electrodes 751-c1 to 751-c4 at D2 layer, which may be referred to as bit lines or a second type of access line). Cross-sectional side view 704-b also depicts conductive plugs (e.g., conductive plug 796-e, conductive plug 796-f) each of which may be coupled to a conductive element (e.g., conductive element 785-a2, conductive element 785-b2). Each conductive element may be coupled to a node (e.g., a select node, an inhibit node) of a circuit system layer (e.g., a bit line select driver, a bit line inhibit driver). Cross-sectional side view 704-b also depicts eight (8) pairs of gate electrodes (e.g., a pair of gate electrodes at each layer 720), where each gate electrode surrounds a conductive electrode (e.g., conductive plug 796-e, conductive plug 796-f). Thus, cross-sectional side view 704-b also depicts a total of sixteen (16) vertical TFTs. In addition, cross-sectional side view 704-b illustrates current path 745-b, and a group of TFTs in the bit line socket region may activate current path 745-b such that drive current may flow between conductive element 785 and bit line 751 during an access operation.

[0217] In some cases, a socket region of the memory device (e.g., as referenced in Figure 7CThe described line socket region) may include conductive plugs (such as conductive plug 796-c) extending through a set of memory cell levels and a set of transistors (such as eight (8) vertical TFTs in the word line socket region) each at least partially surrounding the conductive plug. In some cases, the memory device may include a driver (such as a word line selection driver) coupled to the conductive plug and configured to selectively couple, through the transistors of the set of transistors, to an electrode (such as word line 750-f1) included in a level of the set of levels. In some cases, a second socket region of the memory device (such as the bit line socket region described with reference to Figure 7C The described bit line socket region) may include a second conductive plug (such as conductive plug 796-e) extending through the set of levels, a second set of transistors (such as eight (8) vertical TFTs in the bit line socket region) each at least partially surrounding the second conductive plug, and a second driver (such as a bit line selection driver) coupled to the second conductive plug and configured to selectively couple, through the transistors of the second set, to a second electrode (such as bit line 751-c1) included in the level.

[0218] In some cases, an electrode (such as word line 750-f1) may be located at a first level (such as level 715 of composite stack 705) and the socket region may further include a gate electrode (such as gate electrode 760-a) for a transistor at a second level (such as level 720 of composite stack 705) of the levels, where the gate electrode at least partially surrounds the conductive plug. In some cases, the vertical TFTs of the socket region may be configured to include a gate electrode (such as the gate electrode 760-c described with reference to Figure 7B The described gate electrode 760-c) that surrounds a set of conductive plugs (such as 796-f1 to 796-f4 of conductive plug 796-f) extending through the set of levels and each coupled to a driver (such as a word line selection driver), where the set of conductive plugs may include a conductive plug (such as conductive plug 796-c). Figure 7B The described conductive plug 796-f1 to 796-f4) of conductive plug 796-f, where the set of conductive plugs may include a conductive plug (such as conductive plug 796-c).

[0219] In some cases, a socket region (e.g., a word line socket region) may include a third conductive plug (e.g., conductive plug 796-d) extending through a layer group and a third group of transistors (e.g., eight (8) TFTs within the word line socket region) each at least partially surrounding the third conductive plug. In some cases, the memory device may include a third driver coupled to the third conductive plug and configured to selectively couple with a first type of access line included in a layer subgroup of the group through a subgroup of the third group of transistors. In some cases, a socket region (e.g., a bit line socket region) may include a fourth conductive plug (e.g., conductive plug 796-f) extending through a layer group and a fourth group of transistors (e.g., eight (8) TFTs within the bit line socket region) each at least partially surrounding the fourth conductive plug. In some cases, the memory device may include a fourth driver coupled to the fourth conductive plug and configured to selectively couple with a second type of access line included in a layer subgroup of the group through a subgroup of the fourth group of transistors.

[0220] Figure 7D Explanation reference Figure 7C The circuit diagram 738 and the schematic cross-sectional side view 703 of the described array layer. The circuit diagram 738-a may correspond to a word line socket region including the sixteen (16) TFTs described with reference to the cross-sectional side view 704-a. Similarly, the circuit diagram 738-b may correspond to a bit line socket region including the sixteen (16) TFTs described with reference to the cross-sectional side view 704-b. The two circuit diagrams 738 depict n-type TFTs for illustration, but the present disclosure is not limited thereto. For example, the circuit diagram 738 may include n-type TFTs, p-type TFTs, or any combination thereof. In addition, the gates of the TFTs in the circuit diagram 738 may indicate activation or deactivation of the TFTs. For example, the gate of the TFT depicted as a gray rectangle indicates that the first gate voltage (e.g., Von) applied to the gate to activate the TFT is greater than the threshold voltage of the TFT, and the gate of the TFT depicted as a white rectangle indicates that the second gate voltage (e.g., Voff) applied to the gate to deactivate the TFT is less than the threshold voltage of the TFT.

[0221] The circuit diagram 738-a also depicts each corresponding to the reference Figure 7CThe common nodes 797 (such as nodes 797-c to 797-f) of the TFTs of the described conductive plugs 796. In some cases, the common node may correspond to the source (or drain) of the TFT. For example, the common node 797-c corresponds to the conductive plug 796-c coupled to the conductive element 785-a1. The conductive element 785-a1 may be coupled to a node of the driver (such as the selection node of the word line selection driver 736-a). Similarly, the common node 797-d corresponds to the conductive plug 796-d coupled to the conductive element 785-b1. The conductive element 785-b1 may be coupled to a node of the driver (such as the suppression node of the word line suppression driver 737-a). In addition, the common node 797-e corresponds to the conductive plug 796-e coupled to the conductive element 785-a2. The conductive element 785-a2 may be coupled to a node of the driver (such as the selection node of the bit line selection driver 736-b). Similarly, the common node 797-f corresponds to the conductive plug 796-f coupled to the conductive element 785-b2. The conductive element 785-b2 may be coupled to a node of the driver (such as the suppression node of the bit line suppression driver 737-b). Those skilled in the art should understand that the selection drivers (such as the word line selection driver 736-a, the bit line selection driver 736-b) and the suppression drivers (such as the word line suppression driver 737-a, the bit line suppression driver 737-b) may perform different functions (such as the word line selection driver 736-a performing a suppression function, the word line suppression driver 737-a performing a selection function) based on the access operations of the memory cell or memory technology (such as self-selecting memory, FeRAM, CBRAM).

[0222] Figure 7D Illustrating the TFTs in the word line socket region (such as circuit diagram 738-a) and the TFTs in the bit line socket region (such as circuit diagram 738-b) can facilitate access operations (such as read operations, write operations) at the memory cell level. For example, an access command can access a memory cell located at the sixth memory cell level between BL3 and WL4 (such as the memory cell located at the second layer 720-f), as indicated in the cross-sectional side view 703. The corresponding BL3 and WL4 in the circuit diagram 738 are highlighted (such as depicted as thick lines) to indicate which TFTs can be activated.

[0223] In some cases, WL4 in circuit diagram 738-a can be coupled to the selection node of word line selection driver 736-a by activating the TFT above WL4 (e.g., applying Von to gate electrode 760-c6), or activating the TFT below WL4 (e.g., applying Von to gate electrode 760-c7), or both. Similarly, BL3 in circuit diagram 738-b can be coupled to the selection node of bit line selection driver 736-b by activating the TFT above BL3 (e.g., applying Von to gate electrode 760-d5), or activating the TFT below BL3 (e.g., applying Von to gate electrode 760-d6), or both. In some cases, a driver (e.g., word line selection driver 736-a, bit line selection driver 736-b) can be configured to selectively couple to an electrode (e.g., word line, bit line) through at least two transistors of a group (e.g., two TFTs in the word line socket area, two TFTs in the bit line socket area).

[0224] Additionally or alternatively, the TFTs coupled to the suppression node of word line suppression driver 737-a (e.g., the TFTs coupled to common node 797-d) can be activated or deactivated (e.g., activating six TFTs and deactivating two TFTs, as depicted in circuit diagram 738-a), such that the activated TFTs can couple the unselected word lines (e.g., WL1, WL2, WL3, WL5) to the suppression node of word line suppression driver 737-a. Similarly, the TFTs coupled to the suppression node of bit line suppression driver 737-b (e.g., the TFTs coupled to common node 797-f) can be activated or deactivated (e.g., activating six TFTs and deactivating two TFTs, as depicted in circuit diagram 738-b), such that the activated TFTs can couple the unselected word lines (e.g., BL1, BL2, BL4) to the suppression node of bit line suppression driver 737-b. In this way, interference attributed to unselected word lines or bit lines can be mitigated during an access operation.

[0225] In some cases, a pair of gates of the TFTs can be configured to be electrically connected (e.g., shorted) during decoding of an access command, such that two TFTs (instead of one TFT) can provide a larger current driving capability to the selected memory cell tier. For example, a first subgroup of access lines (e.g., WL2, WL3, WL4) can be driven by a pair of TFTs instead of a single TFT. Such a pair of TFTs can be located above and below the access line (e.g., word line, bit line) and Figure 7DDouble arrows with gray lines are used to illustrate several instances of TFT pairs. In some cases, some gates of the TFTs (e.g., gate electrode 760-c1, gate electrode 760-c8) may lack adjacent gates to provide greater current drive capabilities. In such cases, a second subgroup of access lines (e.g., WL1, WL5) may be driven by a single TFT rather than a pair of TFTs. This configuration (e.g., selectively connecting two TFTs above and below the access line) may be implemented in the crossover region, as referenced Figure 10A and 10B described.

[0226] Figures 8A to 8C A diagram illustrating an exemplary socket region and decoding scheme that supports memory array decoding and interconnects according to an embodiment of the present disclosure. Figures 8A to 8C Describes various aspects of a socket region in which a group of TFTs can be simultaneously constructed within a composite stack 805 (e.g., one or more vertically integrated composite stacks 305 as described with reference to Figures 3A to 3L described herein). Figures 8A to 8C A top view of a portion of the socket region (e.g., the layout of the socket region) is included to illustrate that a subgroup of the group of TFTs can be configured to couple to a subgroup of array electrodes (e.g., access lines, word lines, bit lines) of an active array region in which memory cells are located.

[0227] Additionally, Figures 8A to 8C A cross-sectional side view of a different portion of the socket region is included to illustrate that the group of TFTs can couple the array electrodes to a circuit system layer (e.g., a row decoder 120 constructed in substrate 204). In some cases, the circuit system layer can be a portion of the substrate above which the array layer is located. Additionally, Figures 8A to 8C the group of TFTs described in Figures 7A to 7D can operate according to the circuit representation of the group of TFTs described with reference to Figures 8A to 8C Depicts a socket region that includes a group of wrap-around TFTs as an illustrative example, but the present disclosure is not limited thereto. For example, the socket region can include other types of TFTs described herein or any combination thereof. Figures 5A to 5N describes aspects of the manufacturing techniques and operation of wrap-around TFTs.

[0228] Figure 8AIllustrate a top view 801 of a socket region including two sets of wrap-around TFTs. The top view 801 may be a part of a word line socket region, which includes array electrodes (such as electrode 850-a in the D1 layer of the composite stack 805) that may correspond to word lines. Additionally, the top view 801 depicts a first conductive plug 896-a and a second conductive plug 896-b. In some cases, the first conductive plug may be coupled to a first node of a first driver (such as a selection node of a word line selection driver) and the second conductive plug may be coupled to a second node of a second driver (such as a suppression node of a word line selection driver). The top view 801 also depicts gate electrodes 860 (such as gate electrode 860-a including electrode material 861-a, gate electrode 860-b including electrode material 861-b) at the second layer of the composite stack 805.

[0229] In some cases, an electrode (such as electrode 850-a) may include a first portion (such as electrode piece 855-a) extending in a first direction between a conductive plug (such as conductive plug 896-a) and a second conductive plug (such as conductive plug 896-b), a second portion (such as electrode 850-a1) extending in a second direction and coupled to an end of the first portion, and a third portion (such as electrode 850-a2) extending in the second direction and coupled to a second end of the first portion. In some cases, the first portion (such as electrode piece 855-a) may be wider than the second portion (such as electrode 850-a1) and the third portion (such as electrode 850-a2).

[0230] Figure 8A Also illustrate a cross-sectional side view 802 of a socket region of an array layer. The cross-sectional side view 802-a may correspond to a cross-sectional side view of the word line socket region across the dashed line AA, as shown in the top view 801. For clarity, the cross-sectional side view 802-a omits dielectric plugs, such as dielectric plugs between the conductive plug 896-a and the conductive plug 896-b, and dielectric plugs surrounded by gate electrodes. The cross-sectional side view 802-a illustrates a composite stack 805 including five (5) array electrodes (such as word lines, array electrodes including electrode piece 855 at layer 815).

[0231] Cross-sectional side view 802-a also depicts conductive plugs (e.g., conductive plug 896-a) each of which can be coupled to a conductive element (e.g., conductive element 855-a1). The conductive plugs can serve as common nodes (e.g., source or drain) of the TFT group. Each conductive element can be coupled to a node (e.g., select node, inhibit node) of a circuit system layer (e.g., word line select driver, word line inhibit driver). Cross-sectional side view 802-a also depicts eight (8) pairs of gate electrodes (e.g., a pair of gate electrodes at each layer 820). Thus, cross-sectional side view 802-a depicts a total of sixteen (16) wrap-around TFTs. In addition, cross-sectional side view 802-a illustrates current path 845-a, and the TFT group in the word line socket region can activate current path 845-a such that drive current can flow between conductive element 885 and word line 850 during an access operation.

[0232] Similarly, cross-sectional side view 802-b can correspond to a cross-sectional side view of the bit line socket region. The top view of the bit line socket region can be the same as top view 801 depicting the word line socket region, except that the top view of the bit line socket region can be rotated by approximately 90° with respect to top view 801 depicting the word line socket region (since the bit lines can extend in a direction that can be substantially orthogonal to the word lines). Cross-sectional side view 802-b can also correspond to composite stack 805 and illustrates four (4) array electrodes (e.g., bit lines, array electrodes including electrode sheet 856 at layer 825).

[0233] Cross-sectional side view 802-b also depicts conductive plugs (e.g., conductive plug 896-c) each of which can be coupled to a conductive element (e.g., conductive element 855-a2). Each conductive element can be coupled to a node (e.g., select node, inhibit node) of a circuit system layer (e.g., bit line select driver, bit line inhibit driver). Cross-sectional side view 802-b also depicts eight (8) pairs of gate electrodes (e.g., a pair of gate electrodes at each layer 820). Thus, cross-sectional side view 802-b also depicts a total of sixteen (16) wrap-around TFTs. In addition, cross-sectional side view 802-b illustrates current path 845-b, and the TFT group in the bit line socket region can activate current path 845-b such that drive current can flow between conductive element 885 and bit line 851 (e.g., a bit line including electrode 856 at layer 825) during an access operation.

[0234] In some cases, the socket region of the memory device (e.g., refer to Figure 8AThe described line socket region may include conductive plugs (e.g., conductive plug 896-a) extending through a set of memory cell levels and a set of transistors (e.g., wrap-around TFTs) each having a source or drain in contact with the conductive plug. In some cases, the memory device may include a driver (e.g., word line selection driver) coupled to the conductive plug and configured to selectively couple, through the transistors of the set of transistors, to an electrode (e.g., word line 850) included in a level of the set of levels.

[0235] In some cases, the socket region may include a second conductive plug (e.g., conductive plug 896-b) extending through the set of levels and a second set of transistors (e.g., wrap-around TFTs) each having a source or drain in contact with the conductive plug. In some cases, the memory device may include a second driver (e.g., word line suppression driver) coupled to the second conductive plug and configured to selectively couple, through a subset of the second set of transistors, to a first type of access line included in a sub-set of levels of the set of levels.

[0236] In some cases, the socket region may include a first set of gate electrodes (e.g., gate electrode 860-a) of a set of transistors (e.g., wrap-around TFTs) coupled to a selection node and a second set of gate electrodes (e.g., gate electrode 860-b) of a second set of transistors (e.g., wrap-around TFTs) coupled to a suppression node, wherein the conductive plug (e.g., conductive plug 896-a) and the second conductive plug (e.g., conductive plug 896-b) may be located between the first set of gate electrodes (e.g., gate electrode 860-a) and the second set of gate electrodes (e.g., gate electrode 860-b).

[0237] Figure 8B Figure 803-a showing an array layer including an active array region and two socket regions (e.g., word line socket regions), each including a set of TFTs. Figure 803-a depicts some aspects (e.g., access lines and structural features of the set of TFTs) of a top view of the array layer and omits other aspects for visual clarity. In some cases, the active array region may include a set of memory cell levels constructed within a composite stack 805. As described herein, the set of TFTs may also be constructed in the socket regions of the composite stack 805. In some cases, the set of TFTs may include the wrap-around TFTs described Figures 5A to 5N The lines depicted in the composite figure 803-a (e.g., electrodes of word lines) (e.g., each word line is associated with a wider portion shorter than a narrower portion extending into the active array region, as referenced Figure 5A and 8Aas described) to create a space for the wrap-around TFT construction. For example, the wider portion of the word line extends over eight (8) word lines (e.g., eight (8) group configurations). In some cases, the TFTs can be positioned generally at the center of the word lines (e.g., center-tapped array electrodes).

[0238] Schema 803-a includes sixteen (16) word lines as an example and thus includes sixteen (16) sets of wrap-around TFTs, i.e., eight (8) on one side of the active array region and another eight (8) on the opposite side. Additionally, Schema 803-a depicts an inhibit driver 837 (which can be an example of the word line inhibit driver 737) that can be a word line inhibit driver. In some cases, the inhibit driver 837 can be shared by eight (8) sets of wrap-around TFTs. In other cases, each set of wrap-around TFTs can be separately coupled to a separate inhibit driver. Schema 803-a also depicts a group of eight (8) select drivers 836 (which can be an example of the word line select driver 736). Each select driver can be a word line select driver coupled to one of the eight (8) sets of wrap-around TFTs. In some cases, the inhibit driver 837 and the group of eight (8) select drivers 836 can be positioned below (or above) the memory cell level group. In some cases, the inhibit driver (e.g., inhibit driver 837) and the select driver (e.g., select driver 736) can perform different functions (e.g., the inhibit driver 837 performs a select function and the select driver 736 performs an inhibit function) based on the access operations of the memory cell or memory technology (e.g., self-selecting memory, FeRAM, CBRAM).

[0239] Schema 803-a also includes a common layer selection line 846 and a common layer suppression line 847 that can control the gate electrodes of the surrounding TFTs (such as the gate electrode 860 at layer 820 within the composite stack 805). The common layer selection line 846 can be configured to couple (such as short-circuit) all the gate electrodes of the surrounding TFTs associated with the selection signal of the layer (such as the surrounding TFTs configured to be coupled to the selection nodes of the word line selection driver). In addition, the common layer selection line 846 can be coupled to a first common gate driver located below (or above) the memory cell layer group. Similarly, the common layer suppression line 847 can be configured to couple (such as short-circuit) all the gate electrodes of the surrounding TFTs associated with the suppression signal of the layer (such as the surrounding TFTs configured to be coupled to the suppression nodes of the word line suppression driver). In addition, the common layer suppression line 847 can be coupled to a second common gate driver located below (or above) the memory cell layer group. In some cases, the common gate driver (which can be referred to as a layer selection driver) can be located in a position different from the socket area. In some cases, the common gate driver can be shared among a group of socket areas, where a part of the memory array includes a group of socket areas and one or more active array areas. In some cases, the socket area can include a group of gate electrodes (such as the gate electrode 860), which are included in the layer and are coupled to each other (such as the common layer selection line 846, the common layer suppression line 847) and to the common gate driver below (or above) the memory cell layer group. In some cases, the group of gate electrodes includes the gate electrodes of transistors (such as the surrounding TFTs in the socket area).

[0240] Figure 8CFIG. 803-b illustrating an array layer including an active array region and two socket regions (e.g., a word line socket region), each including a set of TFTs. FIG. 803-b depicts some aspects of a top view of the array layer, such as access lines and structural features of the set of TFTs (e.g., wrap-around TFTs). FIG. 803-b includes a word line select driver 836-a (which may be an instance of word line select driver 736-a) and a word line inhibit driver 837-a (which may be an instance of word line inhibit driver 737-a). Additionally, FIG. 803-b depicts a decoder circuitry 876. In some cases, the word line select driver 836-a, the word line inhibit driver 837-a, and the decoder circuitry 876 may be located below (or above) the memory cell tier group. Compared to FIG. 803-a, FIG. 803-b may depict an alternative configuration for controlling the gate electrodes (e.g., gate electrode 860 at layer 820 within composite stack 805) of the wrap-around TFTs. For example, instead of coupling all of the gate electrodes of the wrap-around TFTs (e.g., using common tier select line 846 and common tier inhibit line 847 as described with reference to FIG. 803-a), the decoder circuitry 876 may be configured to decode the control signals for each gate electrode. In the example depicted in FIG. 803-b, each of the sixty-four (64) TFTs in the two socket regions may be coupled to a driver for a gate electrode. In some cases, a memory device including the socket region may include a decoder circuitry located below the tier group and configured to activate transistors based on gate electrodes selected from a set of gate electrodes of transistors included in the tier.

[0241] Figure 9 FIG. 900 illustrating an exemplary decoding scheme that supports memory array decoding and interconnects in accordance with embodiments of the present disclosure. The TFT-based decoder circuitry depicted in FIG. 900 may be constructed within a composite stack (e.g., composite stack 305, composite stack 705, composite stack 805). This decoder circuitry constructed within the composite stack may perform at least a portion of the decoding functions that may otherwise be performed by a logic circuitry layer. For example, the decoder circuitry may perform additional functions other than selecting a tier from a set of memory cell tiers. In some cases, the logic circuitry layer may be located within a substrate above which the memory cell tier group may be constructed. In this manner, the logic circuitry within the substrate may be simplified to reduce the area corresponding to the logic circuitry or may support additional memory array tiers.

[0242] FIG. 900 depicts a decoder circuitry that may include planar TFTs for illustration, but the present disclosure is not limited thereto. For example, the decoder circuitry within the composite stack may include other types of TFTs described herein or any combination thereof. Figures 4A to 4AADescribes aspects of the manufacturing technology and operation of planar TFTs. Additionally, FIG. 900 depicts a single-ended driver scheme, e.g., the TFT provides drive current to an access line (e.g., word line) located at an end of the access line. Those skilled in the art will appreciate that different driver schemes (e.g., the TFT provides drive current between the two ends of the access line) or more complex driver circuitry can be used without loss of any functionality.

[0243] FIG. 900 depicts a cluster of layers stacked on top of each other (e.g., cluster 967 comprising eight (8) layers (i.e., layers 966-a to 966-h)), where each layer may include one or more tiles. FIG. 900 depicts a set of TFTs to perform a decoding function within a tile, e.g., activating an access line (e.g., word line) from a set of access lines (e.g., eight (8) word lines) within the tile. In the context of the decoder circuitry described herein, a cluster may refer to a group of tiles, and a tile may refer to an array decoding unit. Additionally, FIG. 900 depicts a select driver 936 (which may be an instance of word line select driver 736-a) and an inhibit driver 937 (which may be an instance of word line inhibit driver 737-a). In some cases, the select driver 936 and the inhibit driver 937 may be located within the logic circuitry layer.

[0244] In some cases, an electrode layer within a layer (e.g., layers 966-a to 966-h) (e.g., a layer comprising access lines (e.g., word lines and bit lines)) may include a first set of TFTs that provide a control signal to the gates of a second set of TFTs (e.g., a pair of TFTs coupled to a word line, as Figure 9 shown), where the source or drain of the first set of TFTs may be coupled to a third set of TFTs constructable at the electrode layer within the layer.

[0245] For example, FIG. 900 depicts that the decoder circuitry may perform one of eight (8) decodings within a tile in layer 966 (e.g., layers 966-a to 966-h), e.g., activating one of eight pairs of TFTs (e.g., two TFTs in a series configuration) to activate one of the eight access lines (e.g., word lines) within the tile. Additionally, FIG. 900 depicts that the decoder circuitry may perform one of sixty-four (64) decodings in conjunction with a layer-level decoder that can perform layer-level decoding, e.g., the layer-level decoder may select (or activate) one of the eight layers within cluster 967 (e.g., one of layers 966-a to 966-h).

[0246] Figure 10A and 10B A diagram illustrating an exemplary crossover region that supports memory array decoding and interconnects according to an embodiment of the present disclosure.

[0247] Figure 10AFIG. 1000 illustrates a top view of an array layer depicting an active array region (such as active arrays 1055-a to 1055-d) and socket regions (such as socket region 1065, socket region 1066) where TFT groups may be constructed, as described herein. FIG. 1000 may include some aspects of an example of the memory device 100 described with reference to Figure 1 . In some cases, FIG. 1000 may be part of a 3D memory device that includes more than two memory cell levels constructed within a composite stack 1005 (which may be an example of the composite stack 705 described with reference to Figure 7C ), as depicted in Figure 10B . In some examples, FIG. 1000 may be an example of a fill architecture described herein. The TFT groups may be constructed within the composite stack 1005 and may include vertical TFTs constructed as described with reference to Figures 3A to 3L , planar TFTs described with reference to Figures 4A to 4AA , wrap-around TFTs described with reference to Figures 5A to 5N , or hybrid TFTs described with reference to Figures 6A to 6R , or any combination thereof.

[0248] In addition, FIG. 1000 depicts that the active array 1055 may include a first set of access lines (such as word lines) of a first type extending in a first direction and a second set of access lines (such as bit lines) of a second type extending in a second direction that may be substantially orthogonal to the first direction. The first set of access lines may be located at a first layer of the composite stack 1005 (such as layer D1, layer 1015 described with reference to Figure 10B ). Similarly, the second set of access lines may be located at a third layer of the composite stack 1005 (such as layer D2, layer 1025 described with reference to Figure 10B ). FIG. 1000 depicts that the first set of access lines (such as word lines) may cross a boundary of the active array (such as the boundary between active arrays 1055-a and 1055-b). Similarly, the second set of access lines (such as bit lines) may cross a boundary of the active array (such as the boundary between active arrays 1055-a and 1055-c).

[0249] Additionally, the TFTs in the socket region 1065 may be configured to couple to the first set of access lines (such as word lines), and the TFTs in the socket region 1066 may be configured to couple to the second set of access lines (such as bit lines). In this manner, the TFTs in the socket region 1065 (such as word line socket) may couple nodes of the circuit system layer (such as select nodes, inhibit nodes) to one or more word lines of the active array 1055. Similarly, the TFTs in the socket region 1066 (such as bit line socket) may couple nodes of the circuit system layer (such as select nodes, inhibit nodes) to one or more bit lines of the active array 1055.

[0250] In addition, the layer selection line 1070 can be defined in a socket area (such as socket area 1065, socket area 1066) at the second layer of the composite stack 1005 (such as the DM layer, layer 1020 described in reference 10B). In some cases, the layer selection line 1070 can be coupled to the gate electrode of a TFT also constructed at the second layer (such as the DM layer, layer 1020), as described herein for various TFTs. Thus, the layer selection line 1070 can be coupled to the gate electrode of the TFT and can be referred to as the control line of the gate of the TFT within the socket area.

[0251] The layer selection line 1070 for two sets of access lines (such as word lines and bit lines) can be constructed at the second layer (such as the DM layer, layer 1020 of the composite stack 1005), and the crossover area 1075 can be defined to avoid short - circuiting of the layer selection lines 1070, where two layer selection lines can cross (such as crossover area 1075 - a where layer selection line 1070 - a crosses layer selection line 1070 - d, crossover area 1075 - b where layer selection line 1070 - b crosses layer selection line 1070 - d). Such crossover areas can be located at various positions based on the configuration of the active array arrangement (such as the fill architecture). As an example, FIG. 1000 depicts a crossover area at the corner of the active array 1055.

[0252] Figure 10B Illustrate FIG. 1001 depicting an enlarged top - view of the crossover area and FIG. 1002 depicting a cross - sectional side - view of the crossover area across various positions within the crossover area. FIG. 1001 includes a crossover area 1075 - d where a first set of layer selection lines (such as layer selection lines including layer selection line 1070 - f1) can cross a second set of layer selection lines (such as layer selection lines including layer selection line 1070 - g1). The first set of layer selection lines can be associated with a word - line socket (such as socket area 1065) and can be the control line of the gate of a TFT (such as a TFT configured to be coupled to the word line) within the word - line socket. Similarly, the second set of layer selection lines can be associated with a bit - line socket (such as socket area 1066) and can be the control line of the gate of a TFT (such as a TFT configured to be coupled to the bit line) within the bit - line socket.

[0253] Figure 10B Also illustrate FIG. 1002 depicting a cross - sectional side - view of a layer selection line (such as layer selection line 1070 - f1) across the dashed lines (such as dashed line AA to dashed line EE that transform layer selection line 1070 - f1 into crossover area 1075 - d) shown in FIG. 1001. FIG. 1002 depicts the composite stack 1005 including a first layer (such as D1 layer, layer 1015), a second layer (such as DM layer, layer 1020), and a third layer (such as D2 layer, layer 1025).

[0254] Cross-sectional view 1002-a taken across dashed line AA depicts array electrode 1050 constructed at D1 layer (e.g., layer 1015). Dashed line AA corresponds to a word line and the array electrode 1050 depicted in cross-sectional view 1002-a can be coupled to the word line. Cross-sectional view 1002-a also depicts a gate electrode (e.g., a gate electrode including electrode material 1061) constructed at DM layer (e.g., layer 1020). The gate electrode depicted in cross-sectional view 1002-a can be part of level select line 1070-f1 (e.g., a control line for the gate of a TFT within word line socket region 1065).

[0255] Cross-sectional view 1002-b taken across dashed line BB depicts a similar structure to cross-sectional view 1002-a, except that there is no array electrode 1050 because the first part of the crossover region including dashed line BB is away from the line depicted in cross-sectional view 1002-a.

[0256] Cross-sectional view 1002-c taken across dashed line CC depicts that a gate electrode (e.g., a gate electrode including electrode material 1061) can be constructed across both D1 layer (e.g., layer 1015) and DM layer (e.g., layer 1020) in the second part of the crossover region including dashed line CC. For example, electrode material 1061 spans the D1 layer and the DM layer. In this way, a pair of inner gate electrodes (e.g., the electrode corresponding to electrode material 1061-b and the electrode corresponding to electrode material 1061-c) can be connected (e.g., electrically shorted), as indicated by the grey arrows.

[0257] Cross-sectional view 1002-d taken across dashed line DD depicts that a gate electrode (e.g., a gate electrode including electrode material 1061) can be constructed at D1 layer (e.g., layer 1015) in the third part of the crossover region including dashed line DD. In this way, the gate electrode (e.g., a control line for the gate of a TFT within word line socket region 1065) can be converted from gate electrodes at eight (8) DM layers (e.g., layer 1020) to gate electrodes at five (5) D1 layers (e.g., layer 1015) while transitioning from the first part of the crossover region to the third part of the crossover region. As described herein, the inner electrode pair can be electrically connected during the transition. The pair of inner gate electrodes can correspond to the gate pair of the TFT described in the circuit diagram 738-a of reference Figure 7D (e.g., the gate pair represented by the grey arrows).

[0258] Similarly, the plane selection line 1070-g1 (e.g., the control line of the gate of the TFT within the bit line socket region 1066) can be constructed to have different structural configurations passing through different portions of the crossover region 1075-d. In this manner, the gate electrode (e.g., the control line of the gate of the TFT within the bit line socket region 1066) can be converted from the gate electrode at eight (8) DM layers (e.g., layer 1020) to the gate electrode at four (4) D2 layers (e.g., layer 1025) within the crossover region 1075-d, for example, by transitioning the plane selection line 1070-g1 into the crossover region 1075-d along an orthogonal direction with respect to the dashed lines AA to EE. During the transition, the inner gate electrode pairs can be electrically connected because the electrode material 1062 of the gate electrode can be constructed across the DM layer (e.g., layer 1020) and the D2 layer (e.g., layer 1025). For example, the electrode material 1062 spans the DM layer and the D2 layer at a portion of the crossover region 1075-d corresponding to the second portion of the crossover region that contains the dashed line CC of the plane selection line 1070-f1. The inner gate electrode pairs can correspond to the gate pairs of the TFTs described in the circuit diagram 738-b of reference Figure 7D (e.g., the gate pairs represented by the gray arrows).

[0259] In this manner, the cross-sectional view 1002-e across the dashed line EE depicts that the gate electrode of the plane selection line 1070-f1 can be constructed at the layer 1015 (e.g., the gate electrode including the electrode material 1061-a, the electrode material 1061-i, the electrode material 1061-j, the electrode material 1061-k, the electrode material 1061-h) and the gate electrode of the plane selection line 1070-g1 can be constructed at the layer 1025 (e.g., the gate electrode including the electrode material 1062-a, the electrode material 1062-b, the electrode electrode material 1062-c, the electrode material 1062-d). Thus, the plane selection line 1070-f1 and the plane selection line 1070-g1 can cross without being electrically shorted to each other.

[0260] The cross-sectional view of the schematic diagram 1002 can also represent the cross-sectional side view of the plane selection line 1070-f1 transitioning from the crossover region 1075-d. In other words, the cross-sectional view 1002-d across the dashed line DD can be the same as the cross-sectional view across the dashed line D'D'. Similarly, the cross-sectional view 1002-c across the dashed line CC can be the same as the cross-sectional view across the dashed line C'C'. In addition, the cross-sectional view across the dashed line A'A' is the same as the cross-sectional view 1002-a across the dashed line AA.

[0261] In some cases, the memory device (e.g., reference Figure 1The described memory device, 3D memory device, may include a set of memory cell levels, each including a first layer (e.g., D1 layer), a second layer (e.g., DM layer), a third layer (e.g., D2 layer), and a set of memory arrays, a set of first electrodes extending in a first direction, and a set of second electrodes extending in a second direction intersecting the first direction. In some cases, within the region (e.g., crossover region 1075) between the memory arrays of the set of memory arrays, each first electrode of the set of first electrodes includes a first portion at the second layer, a second portion at the first layer, and a third portion at the second layer, and each second electrode of the set of second electrodes includes a first portion at the second layer, a second portion at the third layer, and a third portion at the second layer.

[0262] In some cases, each first electrode of the set of first electrodes further includes a fourth portion spanning at least the second and first layers within the region, and each second electrode of the set of second electrodes further includes a fourth portion spanning at least the second and third layers within the region. In some cases, the fourth portions of at least two first electrodes of the set of first electrodes may be shared by the at least two first electrodes, and the fourth portions of at least two second electrodes of the set of second electrodes may be shared by the at least two second electrodes.

[0263] In some cases, each first electrode of the set of first electrodes further includes a fifth portion spanning at least the first and second layers within the region, and each second electrode of the set of second electrodes further includes a fifth portion spanning at least both the third and second layers within the region. In some cases, at least a subgroup of the first electrodes of the set of first electrodes may be coupled together within the region, and at least a subgroup of the second electrodes of the set of second electrodes may be coupled together within the region.

[0264] In some cases, the memory device may include a first set of transistors located within the set of memory arrays and configured to select a first type of access line, wherein the set of first electrodes may be coupled to the gates of the first set of transistors. In some cases, the memory device may include a second set of transistors located within the set of memory arrays and configured to select a second type of access line, wherein the set of second electrodes may be coupled to the gates of the second set of transistors. In some cases, the first set of transistors and the second set of transistors may be located within the set of levels.

[0265] Figure 11 FIG. 1100 illustrates a diagram of an exemplary memory device supporting memory array decoding and interconnects in accordance with an embodiment of the present disclosure. In some cases, the memory device may include reference Figure 1 and 2Two or more memory cell levels as described. The schematic 1100 includes a substrate 1156, one or more sets of array layers 1157 (each including an active array region and a socket region), and a layer of TFT circuitry 1158. The substrate 1156 may be an example of the substrate 204 as described. In some cases, the substrate 1156 may include a logic circuit system layer. The array layer 1157 may be an example of the array layer as described with reference to FIGS. 7, 8, and 10. The array layer 1157 may include a composite stack (such as the composite stack 705 as described with reference to Figure 2 an example of the substrate 204 as described. In some cases, the substrate 1156 may include a logic circuit system layer. The array layer 1157 may be an example of the array layer as described with reference to FIGS. 7, 8, and 10. The array layer 1157 may include a composite stack (such as the composite stack 705 as described with reference to Figure 7C the composite stack 705 as described, reference Figure 8A the composite stack 805 as described, reference Figure 10B the composite stack 1005 as described). Additionally, the array layer 1157 may include a set of memory cell levels in the active array region and a socket region in which a set of TFTs are positioned. In some cases, each array layer (such as array layer 1157-a, array layer 1157-b) may include a certain number of memory cell levels (such as eight (8) levels, sixteen (16) levels, thirty-two (32) levels, sixty-four (64) levels). The set of TFTs may include vertical TFTs, planar TFTs, wrap-around TFTs, or hybrid TFTs or any combination thereof. A layer of TFT circuitry 1158 may be an example of the TFT-based decoder circuitry as described with reference to Figure 9 the TFT-based decoder circuitry as described.

[0266] In some cases, the memory device may include a memory array that includes a set of electrodes at a first layer (such as the first layer 715 as described with reference to Figure 7C and a set of memory cells at a second layer (such as the second layer 720 as described with reference to Figure 7C The memory device may also include a set of transistors configured to select an electrode from the set of electrodes, each transistor in the set of transistors including a gate electrode at the second layer and a semiconductor material at the first layer. In some cases, the memory array may be located at a first level of the memory device (such as the first memory cell level of array layer 1157-a). In some cases, the memory device may also include a second level (such as the second memory cell level of array layer 1157-b), where the second level may include: a second memory array that includes a second set of electrodes at the first layer of the second level and a second set of memory cells at the second layer of the second level; and a second set of transistors configured to select an electrode from the second set of electrodes, each transistor in the second set of transistors including a gate electrode at the second layer of the second level and a semiconductor material at the first layer of the second level.

[0267] In some cases, a first tier of a memory device may be included in a first set of tiers (e.g., a first memory cell tier of array tier 1157-a that may include a number of memory cell tiers), and a second tier of the memory device may be included in a second set of tiers (e.g., a second memory cell tier of array tier 1157-b that may include a number of memory cell tiers). In some cases, the memory device may further include decoder circuitry (e.g., a layer of TFT circuitry 1158) between the first set of tiers (e.g., array tier 1157-a) and the second set of tiers (e.g., array tier 1157-b), where the decoder circuitry may be configured to select one or more tiers from the first set of tiers (e.g., array tier 1157-a) and the second set of tiers (e.g., array tier 1157-b).

[0268] In some cases, a memory array may be located at a tier (e.g., a memory cell tier of array tier 1157-a that may include a number of memory cell tiers) included in a set of tiers of a memory device, and the memory device may further include decoder circuitry (e.g., the decoder circuitry described with reference to Figure 9 ), which is included in the tier and configured to activate transistors of a group of transistors based on selection of gate electrodes of the transistors from a corresponding set of gate electrodes included in the tier.

[0269] Figure 12 Illustrates method 1200 for thin film transistors and related fabrication techniques that support memory array decoding and interconnects according to embodiments of the present disclosure. Operations of method 1200 may be implemented by the methods described herein (e.g., with reference to Figures 3A to 3L ).

[0270] In block 1205, a first set of vias and a second set of vias may be formed through a top tier of a stack including a first tier, a second tier, and a third tier. Operations of block 1205 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1205 may be performed as part of one or more processes described with reference to Figures 3A to 3L ).

[0271] In block 1210, gate electrodes of transistors may be formed using the first set of vias, and the gate electrodes are located at the second tier. Operations of block 1210 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1210 may be performed as part of one or more processes described with reference to Figures 3A to 3L ).

[0272] In block 1215, second electrodes of transistors may be formed using the second set of vias, and the second electrodes are located at the first tier. Operations of block 1215 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1215 may be performed as part of one or more processes described with reference toFigures 3A to 3L Parts of one or more of the processes described.

[0273] In block 1220, a via common to the first set of vias and the second set of vias may be used to form a third electrode of a transistor, the third electrode extending at least through a third layer. The operations of block 1220 may be performed according to the methods described herein. In a particular example, aspects of the operations of block 1220 may be performed as a reference Figures 3A to 3L Parts of one or more of the processes described.

[0274] In some examples of the method 1200 described herein, forming a gate electrode of a transistor may include: forming a channel aligned with a first set of vias at a second layer; forming an insulating material conformal to the channel; and filling the channel with an electrode material based on forming the insulating material. In some cases, method 1200 may further include using a via to remove a portion of the gate electrode to form a cavity at the second layer and using a via to form an oxide material within the cavity at the second layer and in contact with the gate electrode. In some cases, method 1200 may further include using a via to remove a portion of the second electrode to form a cavity at the first layer and using a via to form an ohmic material within the cavity at the first layer and in contact with the second electrode. In some cases, method 1200 may further include using a via to form a cavity spanning the first and second layers and using a via to form a semiconductor material within the cavity spanning the first and second layers.

[0275] In some cases, method 1200 may further include using a via to form an insulating material in contact with the semiconductor material. In some cases, method 1200 may further include using a via to form a cavity at the third layer and using a via to form an ohmic material within the cavity at the third layer and in contact with the third electrode. In some examples of the method 1200 described herein, forming a third electrode of a transistor may include using a via to form a hole through the stack to a logic circuit system layer and filling the hole with an electrode material. In some examples of the method 1200 described herein, forming a second electrode of a transistor may include: forming a channel aligned with a second set of vias at a first layer, where the second set of vias forms a second row of vias intersecting a first row of vias formed by the first set of vias; filling the channel at the first layer with an electrode material; and forming a set of dielectric plugs corresponding to the second set of vias, where the dielectric plugs extend through the electrode material in the channel at the first layer.

[0276] Figure 13 Illustrates method 1300 for thin film transistors and related fabrication techniques that support memory array decoding and interconnects according to embodiments of the present disclosure. The operations of method 1300 may be performed by the methods described herein (e.g., as a reference Figures 4A to 4AA described methods).

[0277] In block 1305, a first via, a second via, and a third via may be formed through the top layer of a stack including a first layer and a second layer. The operations of block 1305 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1305 may be performed as part of one or more of the processes referenced Figures 4A to 4AA as described.

[0278] In block 1310, the first via may be used to form a gate electrode of a transistor. The operations of block 1310 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1310 may be performed as part of one or more of the processes referenced Figures 4A to 4AA as described.

[0279] In block 1315, the second via may be used to form a second electrode of the transistor, and the second electrode extends through the first layer and the second layer. The operations of block 1315 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1315 may be performed as part of one or more of the processes referenced Figures 4A to 4AA as described.

[0280] In block 1320, at least the first via and the third via may be used to form a third electrode of the transistor. The operations of block 1320 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1320 may be performed as part of one or more of the processes referenced Figures 4A to 4AA as described.

[0281] In some instances of method 1300 described herein, forming the gate electrode of the transistor may include: using a set of vias including the first via to form a channel at the second layer; forming an insulating material conformal to the channel at the second layer; and filling the first channel with an electrode material that contacts the insulating material. In some cases, method 1300 may further include: using the first via to form a cavity at the first layer to expose at least a portion of the gate electrode; based on forming the cavity, using the first via to form an oxide material that contacts the gate electrode; and using the first via to form a semiconductor material located in the cavity at the first layer and in contact with the oxide material.

[0282] In some cases, method 1300 may further include: forming a second cavity at the first layer using at least a second via to expose at least a portion of the third electrode and the semiconductor material; forming a third cavity at the first layer using a third via to expose the semiconductor material; and filling the second cavity and the third cavity at the first layer with an ohmic material. In some examples of method 1300 described herein, forming the third electrode of a transistor may include: forming a first channel at the first layer using at least the first via and the third via; filling the first channel at the first layer with an electrode material; forming a second channel narrower than the first channel in the electrode material within the first channel at the first layer; and filling the second channel with a dielectric material. In some examples of method 1300 described herein, forming the second electrode of a transistor may include forming a via through the stack to a logic circuitry layer using the second via and filling the via with an electrode material.

[0283] Figure 14 Describe method 1400 for thin film transistors and related fabrication techniques that support memory array decoding and interconnects according to embodiments of the present disclosure. The operations of method 1400 may be implemented by the methods described herein (e.g., with reference to Figures 5A to 5N or Figures 6A to 6R as described).

[0284] In block 1405, a first set of vias, a second set of vias, and a third via may be formed through the top layer of a stack including a first layer, a second layer, and a third layer. The operations of block 1405 may be performed according to the methods described herein. In a particular example, aspects of the operations of block 1405 may be performed as part of one or more processes referenced Figures 5A to 5N or Figures 6A to 6R as described.

[0285] In block 1410, a gate electrode of a transistor may be formed using the first set of vias, the gate electrode being located at the second layer. The operations of block 1410 may be performed according to the methods described herein. In a particular example, aspects of the operations of block 1410 may be performed as part of one or more processes referenced Figures 5A to 5N or Figures 6A to 6R as described.

[0286] In block 1415, a second electrode of a transistor may be formed using the second set of vias, the second electrode being located at the first layer. The operations of block 1415 may be performed according to the methods described herein. In a particular example, aspects of the operations of block 1415 may be performed as part of one or more processes referenced Figures 5A to 5N or Figures 6A to 6R as described.

[0287] In block 1420, a third via may be used to form a third electrode of a transistor, the third electrode extending at least through a third layer. The operations of block 1420 may be performed in accordance with the methods described herein. In a particular instance, aspects of the operations of block 1420 may be performed as part of one or more of the processes referenced Figures 5A to 5N or Figures 6A to 6R described.

[0288] In some instances of method 1400 described herein, forming a gate electrode of a transistor may include: using a first set of vias to form a channel at a second layer; forming an insulating material in contact with the channel at the second layer; filling the channel at the second layer with an electrode material; and using the first set of vias to form a set of corresponding holes extending through the electrode material. In some cases, method 1400 may further include forming a third set of vias through a top layer of the stack and using the third set of vias to form a cavity spanning a first layer, a second layer, and a third layer, wherein the cavity spanning the first layer, the second layer, and the third layer exposes an insulating material conformal to the gate electrode.

[0289] In some cases, method 1400 may further include: using the third set of vias to remove a portion of the insulating material in contact with the gate electrode; after removing the portion of the insulating material, using the third set of vias to form an oxide material in contact with the gate electrode; and filling the cavity spanning the first layer, the second layer, and the third layer with a semiconductor material in contact with the oxide material. In some cases, method 1400 may further include forming a hole through the semiconductor material to a logic circuitry layer and filling the hole with an electrode material to form a fourth electrode of the transistor.

[0290] In some cases, method 1400 may further include: using a third via to form a cavity at a first layer to expose a semiconductor material and a second electrode; using the third via to fill the cavity at the first layer with an ohmic material in contact with the semiconductor material and the second electrode; using the third via to remove a portion of the ohmic material; using the third via to form an insulating material in contact with the ohmic material; and using the third via to form an ohmic material at a third layer in contact with the semiconductor material.

[0291] In some cases, method 1400 may further include: filling a cavity spanning the first, second, and third layers with an ohmic material; forming a second cavity spanning the first, second, and third layers using a subgroup of the third set of vias and a third via; and filling the second cavity spanning the first, second, and third layers with a semiconductor material. In some cases, method 1400 may further include: forming a hole through the first, second, and third layers using a third via; forming an insulating material in contact with the semiconductor material at the first and second layers using a third via; forming a cavity at the third layer using a third via; and filling the cavity at the third layer with an ohmic material. In some examples of method 1400 described herein, forming the third electrode of a transistor may include forming a hole through the stack to the logic circuitry layer using a third via and filling the hole with an electrode material.

[0292] Figure 15 Illustrate method 1500 for supporting memory array decoding and interconnects in accordance with embodiments of the present disclosure. Operations of method 1500 may be implemented by a controller or components thereof described herein. For example, operations of method 1500 may be performed by a controller (such as the memory controller 140 referenced Figure 1 ). In some instances, the controller may execute a set of instructions to control functional elements of the memory array to perform the functions described herein. Additionally or alternatively, the controller may use dedicated hardware to perform aspects of the functions described herein.

[0293] In block 1505, the controller may receive an indication of an access operation to a memory cell. Operations of block 1505 may be performed in accordance with methods described herein. In a particular instance, aspects of the operations of block 1505 may be performed as part of one or more of the processes referenced Figure 7C 、 7D 、8A through 8C, and 9.

[0294] In block 1510, the controller may identify a memory cell tier that includes the memory cell, the tier being included in a set of tiers. Operations of block 1510 may be performed in accordance with methods described herein. In a particular instance, aspects of the operations of block 1510 may be performed as part of one or more of the processes referenced Figure 7C 、 7D 、8A through 8C, and 9.

[0295] In block 1515, the controller may couple an electrode included in the tier to a conductive plug extending through the set of tiers based on the identification and using a first transistor included in the tier. Operations of block 1515 may be performed in accordance with methods described herein. In a particular instance, aspects of the operations of block 1515 may be performed as part of one or more of the processes referenced Figure 7C 、 7D, part of one or more processes described in FIGS. 8A - 8C and 9.

[0296] In block 1520, the controller may drive an electrode to a voltage associated with an access operation based on coupling the electrode to a conductive plug. The operations of block 1520 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1520 may be performed as reference Figure 7C , 7D , part of one or more processes described in FIGS. 8A - 8C and 9.

[0297] Describes an apparatus for performing one or more methods (e.g., method 1500). The apparatus may include features, circuitry, components, or instructions (e.g., a non - transitory computer - readable medium storing instructions executable by a processor) for: receiving an indication of an access operation of a memory cell; identifying a memory cell tier that includes the memory cell, the tier being included in a set of tiers; coupling an electrode included in the tier to a conductive plug extending through the set of tiers based on the identification and using a first transistor included in the tier; and driving the electrode to a voltage associated with the access operation based on coupling the electrode to the conductive plug.

[0298] Describes another apparatus for performing one or more methods (e.g., method 1500). The apparatus may include a memory array and a memory controller in electronic communication with the memory array, where the memory controller is operable to: receive an indication of an access operation of a memory cell; identify a memory cell tier that includes the memory cell, the tier being included in a set of tiers; couple an electrode included in the tier to a conductive plug extending through the set of tiers based on the identification and using a first transistor included in the tier; and drive the electrode to a voltage associated with the access operation based on coupling the electrode to the conductive plug.

[0299] Some examples of the method 1500 and apparatus described herein may further include processes, features, components, or instructions for coupling a second electrode included in a tier to a second conductive plug extending through a tier group based on identifying and using a second transistor included in the tier. Some examples of the method 1500 and apparatus described herein may further include processes, features, components, or instructions for driving the second electrode to a second voltage associated with an access operation based on coupling the second electrode to the second conductive plug. Some examples of the method 1500 and apparatus described herein may further include processes, features, components, or instructions for coupling an electrode included in a tier to a conductive plug based on identifying and using a third transistor included in a second tier of the tier group. Some examples of the method 1500 and apparatus described herein may further include processes, features, components, or instructions for coupling a second electrode included in a tier to a second conductive plug based on identifying and using a fourth transistor included in a third tier of the tier group, wherein the tier may be between the second tier and the third tier.

[0300] In some examples of the method 1500 and apparatus described herein, the electrode may include a first type of access line. Some examples of the method 1500 and apparatus described herein may further include processes, features, components, or instructions for coupling a first type of access line included in each tier of a subgroup of tiers of the tier group to a third conductive plug extending through the tier group based on identifying and using transistors included in the subgroup of tiers, wherein the subgroup does not include a tier. Some examples of the method 1500 and apparatus described herein may further include processes, features, components, or instructions for driving a first type of access line included in each tier of the subgroup of tiers to a third voltage associated with an access operation based on coupling the first type of access line included in each tier of the subgroup of tiers to the third conductive plug.

[0301] Figure 16 Illustrate a method 1600 that supports memory array decoding and interconnects, in accordance with an embodiment of the present disclosure. Operations of method 1600 may be implemented by the controller or components thereof described herein. For example, operations of method 1600 may be performed by a controller (such as the memory controller 140 described with reference to Figure 1 ). In some examples, the controller may execute a set of instructions to control functional elements of the memory array to perform the functions described herein. Additionally or alternatively, the controller may use special purpose hardware to perform aspects of the functions described herein.

[0302] In block 1605, the controller may receive an indication of an access operation to a memory cell. The operations of block 1605 may be performed in accordance with the methods described herein. In a particular example, aspects of the operations of block 1605 may be performed as reference Figure 7C 、7D Parts of one or more processes described in FIGS. 8A to 8C and 9.

[0303] In block 1610, the controller may identify a memory cell tier that includes a memory cell, the tier being included in a set of tiers. The operations of block 1610 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1610 may be performed as a reference Figure 7C , 7D Parts of one or more processes described in FIGS. 8A to 8C and 9.

[0304] In block 1615, the controller may couple an electrode included in the tier to a conductive plug that extends through the set of tiers based on identifying and using a first transistor included in the tier. The operations of block 1615 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1615 may be performed as a reference Figure 7C , 7D Parts of one or more processes described in FIGS. 8A to 8C and 9.

[0305] In block 1620, the controller may drive the electrode to a voltage associated with an access operation based on coupling the electrode to the conductive plug. The operations of block 1620 may be performed according to the methods described herein. In a particular instance, aspects of the operations of block 1620 may be performed as a reference Figure 7C , 7D Parts of one or more processes described in FIGS. 8A to 8C and 9.

[0306] Describes an apparatus for performing one or more methods (e.g., method 1600). The apparatus may include means for receiving an indication of an access operation to a memory cell, means for identifying a memory cell tier that includes the memory cell (the tier being included in a set of tiers), means for coupling an electrode included in the tier to a conductive plug that extends through the set of tiers based on identifying and using a first transistor included in the tier, means for driving the electrode to a voltage associated with the access operation based on coupling the electrode to the conductive plug, means for coupling a second electrode included in the tier to a second conductive plug that extends through the set of tiers based on identifying and using a second transistor included in the tier, and means for driving the second electrode to a second voltage associated with the access operation based on coupling the second electrode to the second conductive plug.

[0307] Describe another device for performing one or more methods (e.g., method 1600). The device may include a memory array and a memory controller in electronic communication with the memory array, where the memory controller is operable to: receive an indication of an access operation to a memory cell; identify a memory cell tier that includes the memory cell, the tier being included in a set of tiers; based on the identification and using a first transistor included in the tier, couple an electrode included in the tier to a conductive plug that extends through the set of tiers; based on coupling the electrode to the conductive plug, drive the electrode to a voltage associated with the access operation; based on the identification and using a second transistor included in the tier, couple a second electrode included in the tier to a second conductive plug that extends through the set of tiers; and based on coupling the second electrode to the second conductive plug, drive the second electrode to a second voltage associated with the access operation.

[0308] Note that the methods described herein describe viable embodiments, and the operations and steps may be rearranged or otherwise modified, and other embodiments are viable. Additionally, embodiments from more than two methods may be combined.

[0309] Any of a variety of different technologies may be used to represent the information and signals described herein. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to in the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may illustrate several signals as a single signal; however, one of ordinary skill in the art will understand that a signal may represent a bus of signals, where the bus may have various bit widths.

[0310] The terms "in electronic communication" and "coupled" refer to a relationship between components that supports the flow of electrons between the components. This may include a direct connection between the components or may include intermediate components. Components that are in electronic communication or coupled to each other may actively exchange electrons or signals (e.g., in a powered-on circuit system) or may not actively exchange electrons or signals (e.g., in a powered-off circuit system) but may be configured and operable to exchange electrons or signals after the circuit is powered on. For example, two components that are physically connected via a switch (e.g., a transistor) are in electronic communication or may be coupled, regardless of the state of the switch (i.e., open or closed).

[0311] As used herein, the term "substantially" means that the modified characteristic (e.g., a verb or adjective modified by the term "substantially") need not be absolute, but is close enough to achieve the advantages of the characteristic.

[0312] As used herein, the term "electrode" may refer to an electrical conductor and, in some cases, may serve as an electrical contact for other components of a memory cell or memory array. The electrode may include traces, wires, conductive lines, conductive layers, or the like that provide an electrically conductive path system between the elements or components of the memory device 100.

[0313] The chalcogenide material may be a material or alloy that includes at least one of the elements S, Se, and Te. The chalcogenide material may include an alloy of any of the following: S, Se, Te, Ge, As, Al, Si, Sb, Au, indium (In), gallium (Ga), tin (Sn), bismuth (Bi), palladium (Pd), cobalt (Co), oxygen (O), silver (Ag), nickel (Ni), platinum (Pt). Exemplary chalcogenide materials and alloys may include (but are not limited to) Ge-Te, In-Se, Sb-Te, Ga-Sb, In-Sb, As-Te, Al-Te, Ge-Sb-Te, Te-Ge-As, In-Sb-Te, Te-Sn-Se, Ge-Se-Ga, Bi-Se-Sb, Ga-Se-Te, Sn-Sb-Te, In-Sb-Ge, Te-Ge-Sb-S, Te-Ge-Sn-O, Te-Ge-Sn-Au, Pd-Te-Ge-Sn, In-Se-Ti-Co, Ge-Sb-Te-Pd, Ge-Sb-Te-Co, Sb-Te-Bi-Se, Ag-In-Sb-Te, Ge-Sb-Se-Te, Ge-Sn-Sb-Te, Ge-Te-Sn-Ni, Ge-Te-Sn-Pd, or Ge-Te-Sn-Pt. As used herein, a chemical composition symbol joined by a hyphen indicates the elements included in a particular compound or alloy and is intended to represent all stoichiometries involving the indicated elements. For example, Ge-Te may include Ge x Te y , where x and y may be any positive integers. Other examples of variable resistance materials may include binary metal oxide materials or mixed valence oxides that include more than two metals, such as transition metals, alkaline earth metals, and / or rare earth metals. The examples are not limited to one or several specific variable resistance materials associated with the memory components of the memory cell. For example, other examples of variable resistance materials may be used to form memory components and may include chalcogenide materials, giant magnetoresistive materials, or polymer-based materials, etc.

[0314] The term "isolated" refers to the relationship between components where electrons cannot currently flow between the components; if there is an open circuit between the components, then they are isolated from each other. For example, when a switch is open, two components physically connected by the switch may be isolated from each other.

[0315] The devices discussed herein, including memory device 100, may be formed on a semiconductor substrate such as silicon, germanium, silicon germanium alloy, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation or any other doping method during the initial formation or growth of the substrate.

[0316] One or more transistors discussed herein may represent field effect transistors (FETs) and include four-terminal devices that include a source, a drain, a gate, and a base (or substrate). The terminals may be connected to other electronic components by conductive materials such as metal. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or a channel, which may be part of the base. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0317] The descriptions set forth herein describe example configurations in conjunction with the drawings and do not represent all examples that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and does not mean "better than" or "superior to" other examples. Implementations include specific details for understanding the present disclosure. However, these techniques may be practiced without these specific details. In some examples, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0318] In the figures, similar components or features may have the same reference element symbols. Additionally, various components of the same type may be distinguished by following the reference element symbol with a dash and a second element symbol that differentiates the similar components. If only the first reference element symbol is used in the specification, the description applies to any of the similar components having the same first reference element symbol, regardless of the second reference element symbol.

[0319] Any of a variety of different technologies may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to in the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0320] A general-purpose processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein may be used to implement or execute the various illustrative blocks and modules described in connection with the present disclosure. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0321] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or program code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software, hardware, firmware, hardwiring, or any combination thereof executed by a processor. The features implementing the functions may also be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations. Additionally, as used herein (including in the claims), the "or" in a list of items (e.g., a list of items in conjunction with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of A, B, or C, for example, means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Further, as used herein, the phrase "based on..." should not be construed as referring to a set of closed conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on..." should be interpreted in the same manner as the phrase "at least partially based on...".

[0322] A computer-readable medium includes both a non-transitory computer storage medium and a communication medium including any medium that facilitates transfer of a computer program from one location to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, read only memory (ROM), electrically erasable programmable ROM (EEPROM), compact disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store the desired program code means in the form of instructions or data structures and that can be accessed by a general purpose or special purpose computer or a general purpose or special purpose processor. Additionally, any connection is properly termed a computer-readable medium. For example, if software is transmitted using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks typically reproduce data magnetically, while discs use lasers to optically reproduce data. Combinations of the above are also included within the scope of computer-readable media.

[0323] This disclosure is provided to enable a person having ordinary skill in the art to make or use the disclosure. Persons having ordinary skill in the art will readily appreciate various modifications to the disclosure, and the general principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein, but is to be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: A conductive plug extending through a plurality of memory cell levels; A plurality of transistors, each of the plurality of transistors comprising: A semiconductor material at least partially surrounding the conductive plug; and A gate electrode coupled to the semiconductor material; and A driver coupled to the conductive plug and configured to selectively couple, via the transistors of the plurality of transistors, to an electrode included in one of the plurality of levels, wherein the electrode is coupled to the semiconductor material of the transistor.

2. The memory device according to claim 1, further comprising: A second conductive plug extending through the plurality of levels; A second plurality of transistors, each of which at least partially surrounds the second conductive plug; And A second driver coupled to the second conductive plug and configured to selectively couple, via the transistors of the second plurality of transistors, to a second electrode included in the level.

3. The memory device according to claim 2, further comprising: A first socket region including the conductive plug, wherein the electrode includes a first type of access line extending into the first socket region; And A second socket region including the second conductive plug, wherein the second electrode includes a second type of access line extending into the second socket region.

4. The memory device according to claim 1, wherein the electrode includes a first type of access line, and the memory device further comprises: A third conductive plug extending through the plurality of levels; A third plurality of transistors, each of which at least partially surrounds the third conductive plug; And A third driver coupled to the third conductive plug and configured to selectively couple, via a sub-group of the transistors of the third plurality of transistors, to the first type of access line included in a sub-group of the levels among the plurality of levels.

5. A memory device, comprising: A conductive plug extending through a plurality of memory cell levels; A plurality of transistors, each of which at least partially surrounds the conductive plug; A driver coupled to the conductive plug and configured to selectively couple, via the transistors of the plurality of transistors, to an electrode included in one of the plurality of levels, wherein the electrode is located at a first layer of the level; And A gate electrode for the transistor at a second layer of the level, wherein the gate electrode at least partially surrounds the conductive plug.

6. A memory device, comprising: A conductive plug extending through a plurality of memory cell levels; A plurality of transistors, each of which at least partially surrounds the conductive plug; And A driver coupled to the conductive plug and configured to selectively couple, via the transistors of the plurality of transistors, to an electrode included in one of the plurality of levels, wherein the transistor is coupled to the electrode between two ends of the electrode.

7. A memory device, comprising: A conductive plug extending through a plurality of memory cell levels; A plurality of transistors, each of which at least partially surrounds the conductive plug; A driver, which is coupled to the conductive plug and configured to selectively couple, through the transistors of the plurality of transistors, to an electrode included in one of the plurality of levels; A first gate electrode, which surrounds the conductive plug; And A second gate electrode, which surrounds a first additional conductive plug extending through the plurality of levels and a second additional conductive plug extending through the plurality of levels, wherein the electrode extends between the first additional conductive plug and the second additional conductive plug.

8. A memory device, comprising: A conductive plug, which extends through a plurality of memory cell levels; A plurality of transistors, each of which at least partially surrounds the conductive plug; A driver, which is coupled to the conductive plug and configured to selectively couple, through the transistors of the plurality of transistors, to an electrode included in one of the plurality of levels; A gate electrode, which surrounds a plurality of conductive plugs extending through the plurality of levels and each coupled to the driver, wherein the plurality of conductive plugs includes the conductive plug extending through the plurality of levels.

9. A memory device, comprising: A conductive plug, which extends through a plurality of memory cell levels; A plurality of transistors, each of which at least partially surrounds the conductive plug; A driver, which is coupled to the conductive plug and configured to selectively couple, through the transistors of the plurality of transistors, to an electrode included in one of the plurality of levels; A first electrode segment, which is located at a layer of the level and is shorter than the electrode, wherein the electrode is an access line of a first type and extends in a first direction at the layer of the level, and wherein the conductive plug is located between the electrode and the first electrode segment; A second access line of the first type, which extends in the first direction at the layer of the level, wherein the second access line is coaxial with the first electrode segment; And A second electrode segment, which is located at the layer of the level and is shorter than the electrode, wherein the second electrode segment is coaxial with the electrode.

10. A memory device, comprising: A conductive plug, which extends through a plurality of memory cell levels; A plurality of transistors, each of which at least partially surrounds the conductive plug; A driver, which is coupled to the conductive plug and configured to selectively couple, through the transistors of the plurality of transistors, to an electrode included in one of the plurality of levels, wherein the transistors include: A semiconductor material, which is located at a first layer of the level and a second layer of the level, the semiconductor material surrounding the conductive plug; An oxide material, which is located at the second layer of the level and in contact with the semiconductor material; A gate electrode, which is located at the second layer of the level and in contact with the oxide material; and An ohmic material, which is located at the first layer of the level and a third layer of the level, wherein the ohmic material at the first layer is in contact with the semiconductor material and the electrode, and wherein the ohmic material at the third layer is in contact with the conductive plug.

11. A memory device, comprising: A conductive plug, which extends through a plurality of memory cell levels; A plurality of transistors, each of which at least partially surrounds the conductive plug; A driver coupled to the conductive plug and configured to selectively couple with an electrode in one of the plurality of levels through transistors of the plurality of transistors, wherein the driver is configured to selectively couple with the electrode through at least two transistors of the plurality of transistors.

12. A memory device comprising: A conductive plug extending through a plurality of memory cell levels; A plurality of transistors, each transistor of the plurality of transistors comprising: A gate electrode; and A semiconductor material at least partially surrounding the gate electrode; A source or drain in contact with the conductive plug, the source or drain including the semiconductor material; and A driver coupled to the conductive plug and configured to selectively couple with an electrode in one of the plurality of levels through transistors of the plurality of transistors, wherein the electrode is coupled to the semiconductor material of the transistor.

13. The memory device according to claim 12, further comprising: A second conductive plug extending through the plurality of levels; A second plurality of transistors, each having a source or drain in contact with the second conductive plug; And A second driver coupled to the second conductive plug and configured to selectively couple with a first type of access line in a subgroup of the levels included in the plurality of levels through a subset of transistors of the second plurality of transistors.

14. The memory device according to claim 12, further comprising: A plurality of gate electrodes included in the level and coupled to each other and to a common gate driver below the plurality of levels, wherein the plurality of gate electrodes includes the gate electrodes of the transistors.

15. The memory device according to claim 12, further comprising: A decoder circuit system located below the plurality of levels and configured to activate the transistors at least in part based on selecting the gate electrodes of the transistors from a plurality of gate electrodes included in the level.

16. The memory device according to claim 12, wherein the transistor comprises: A corresponding gate electrode located at a second layer of the level; And A corresponding semiconductor material coupled to the electrode through a first segment of ohmic material at a first layer of the level and coupled to the conductive plug through a second segment of ohmic material at a third layer of the level.

17. A memory device comprising: A conductive plug extending through a plurality of memory cell levels; A plurality of transistors, each having a source or drain in contact with the conductive plug; A driver coupled to the conductive plug and configured to selectively couple with an electrode in one of the plurality of levels through transistors of the plurality of transistors; A second conductive plug extending through the plurality of levels; A second plurality of transistors, each having a source or drain in contact with the second conductive plug; And A second driver, which is coupled to the second conductive plug and is configured to selectively couple to a first type of access line in a sub-group of levels included in the plurality of levels through a sub-group of transistors of the second plurality of transistors, wherein the electrode comprises: A first portion that extends in a first direction between the conductive plug and the second conductive plug; A second portion that is coupled to an end of the first portion, the second portion extending in a second direction; and A third portion that is coupled to a second end of the first portion, the third portion extending in the second direction.

18. The memory device according to claim 17, wherein the first portion is wider than the second portion and the third portion.

19. The memory device according to claim 17, further comprising: A first plurality of gate electrodes for the plurality of transistors; And A second plurality of gate electrodes for the second plurality of transistors, wherein the conductive plug and the second conductive plug are located between the first plurality of gate electrodes and the second plurality of gate electrodes.

20. A method for memory operation, comprising: Receiving an indication of an access operation of a memory cell; Identifying a memory cell level containing the memory cell, the level being included in a plurality of levels; At least partially based on the identification and using a first transistor included in the level to couple an electrode included in the level to a conductive plug extending through the plurality of levels, wherein the first transistor comprises: A gate electrode; and A semiconductor material coupled to the gate electrode, wherein the semiconductor material at least partially surrounds at least one of the gate electrode or the conductive plug; and At least partially based on coupling the electrode to the conductive plug, driving the electrode to a voltage associated with the access operation.

21. The method according to claim 20, further comprising: At least partially based on the identification and using a second transistor included in the level to couple a second electrode included in the level to a second conductive plug extending through the plurality of levels; And At least partially based on coupling the second electrode to the second conductive plug, driving the second electrode to a second voltage associated with the access operation.

22. The method according to claim 20, wherein the electrode comprises a first type of access line, and the method further comprises: At least partially based on the identification and using transistors included in a sub-group of levels in the plurality of levels to couple the first type of access line included in each level of the sub-group of levels to a third conductive plug extending through the plurality of levels, wherein the sub-group of levels does not include the identified level; and At least partially based on coupling the first type of access line included in each level of the sub-group of levels to the third conductive plug, driving the first type of access line included in each level of the sub-group of levels to a third voltage associated with the access operation.

23. A method for memory operation, comprising: Receiving an indication of an access operation of a memory cell; Identify a memory cell level that includes the memory cell, the level being included in a plurality of levels; At least partially based on the identification and using a first transistor included in the level, couple an electrode included in the level to a conductive plug that extends through the plurality of levels; At least partially based on coupling the electrode to the conductive plug, drive the electrode to a voltage associated with the access operation; At least partially based on the identification and using a second transistor included in the level, couple a second electrode included in the level to a second conductive plug that extends through the plurality of levels; At least partially based on coupling the second electrode to the second conductive plug, drive the second electrode to a second voltage associated with the access operation; At least partially based on the identification and using a third transistor included in a second level of the plurality of levels, couple the electrode included in the level to the conductive plug; and At least partially based on the identification and using a fourth transistor included in a third level of the plurality of levels, couple the second electrode included in the level to the second conductive plug, wherein the level is located between the second level and the third level.

Images