Sensor device and method for dark count elimination

Abstract

A sensor device for light sensing for light-to-frequency conversion. The sensor device includes a photodiode, an analog-to-digital converter (ADC) operable to perform a clipping technique in response to a first clock signal (CLK1) and convert a photocurrent (IPD) into a digital comparator output signal (LOUT). The ADC includes a sensor input coupled to the photodiode, an output for providing a digital comparator output signal (LOUT), an integrator including an integrator input coupled to the sensor input and operable to receive an integrator input signal, a first set of clipping switches coupled to a first amplifier, a second set of clipping switches electrically coupled to the output of the first amplifier and electrically coupled to an input terminal of a second amplifier, and an integrator output providing an integrator output signal (OPOUT).

Description

Background Art

[0001] Modern consumer electronics (e.g., smartphones) increasingly use many different sensors, often included in the same device. In one specific application, ambient light sensors are used for display management, where these sensors measure the ambient light brightness. Depending on the brightness of the ambient light, the display illumination can be adjusted and power can be saved. For example, if the ambient light is bright, then the display panel may need a higher backlight. However, if the ambient light is less, then a lower backlight may be sufficient for the display panel. By dynamically adjusting the display panel brightness, the ambient light sensor helps the display panel optimize the operating power.

[0002] Some ambient light sensors include a semiconductor junction to generate a sensor signal to detect incident light. Photo-to-electron conversion is typical for semiconductor junctions. Sometimes ambient light sensors use separate circuits for signal acquisition and processing. For example, an ambient light sensor may use a photodiode and a charge-balanced analog-to-digital converter. The light sensor is placed under dark glass, which requires a larger photodiode area to obtain the desired sensitivity from the light sensor for a given electrical gain. A larger diode area means a larger leakage current, with the result that the sensitivity of the light sensor is limited in low-light measurements. Summary of the invention

[0003] This specification describes techniques related to optimizing the cancellation of dark current in each ambient light sensor (ALS) measurement using a one-time auto-zero operation during initialization to accurately measure low light using a clip switch.

[0004] In general, an innovative aspect of the subject matter described in this specification can be implemented in a sensor device for light sensing and temperature sensing, the device comprising a photodiode; an analog-to-digital converter (ADC) operable to perform a clipping technique in response to a first clock signal (CLK1) and operable to convert a photocurrent (IPD) generated by the photodiode into a digital comparator output signal (LOUT), the ADC comprising a sensor input coupled to the photodiode, a result output for providing the digital comparator output signal (LOUT), an integrator comprising an integrator input coupled to the sensor input and operable to receive the integrator input signal, first and second amplifiers, a first set of clipping switches electrically coupled to an input terminal of the first amplifier, a second set of clipping switches electrically coupled to an output terminal of the first amplifier and electrically coupled to an input terminal of the second amplifier, and an integrator output providing an integrator output signal (OPOUT); and a signal processing unit coupled to the result output terminal of the analog-to-digital converter and configured to determine a digital output signal (ADC-COUNT) from the digital comparator output signal (LOUT). Certain embodiments include one or more of the following features.

[0005] In certain embodiments, the ADC is operable to perform an initialization phase prior to performing the clipping technique, the initialization phase comprising applying a coarse auto-zero operation before the start of an integration time (T_INT) for an integration cycle, and applying a first reset / initialization phase at the start of an integration time (T_INT) for an integration cycle to reset the ADC and initialize signal acquisition.

[0006] In certain embodiments, the ADC is operable to perform a first clipping technique after performing an initial phase, the first clipping technique comprising applying a first stage of clipping at a first set of clipping switches and a second set of clipping switches, wherein the first stage of clipping is applied with a first polarity, and applying a second stage of clipping at the first set of clipping switches and the second set of clipping switches at a halfway timestamp and without stopping an integration cycle, the halfway timestamp indicating a halfway point of an integration time (T_INT), wherein the second stage of clipping is applied with a second polarity, and wherein the second polarity is opposite to the first polarity.

[0007] In certain embodiments, the ADC is operable to perform a second clipping technique after performing the initialization phase, the second clipping technique comprising applying a first phase of clipping at a first set of clipping switches and a second set of clipping switches at a halfway timestamp, the halfway timestamp indicating a halfway point of an integration time (T_INT) for an integration cycle, wherein the first phase of clipping is applied with a first polarity; applying a second reset / initialization phase that resets the ADC and reinitializes signal acquisition at the halfway point of the integration time (T_INT) for the integration cycle, wherein the second reset / initialization phase stops the integration cycle and changes the polarity of the integrator output; and applying a second phase of clipping at the first set of clipping switches and the second set of clipping switches after the second reset / initialization phase, wherein the second phase of clipping is applied with the first polarity. In certain embodiments, changing the polarity of the integrator output from the first polarity to the second polarity comprises switching the output of the first set of clipping switches for the input terminal of the first amplifier, and switching the output of the second set of clipping switches for the input terminal of the second amplifier.

[0008] In some embodiments, the signal processing unit includes a first counter having a first clock input coupled to a result output and including a first reset input, a second counter including a second clock input and a second reset input, and a calculation input coupled to a first counter output of the first counter and a second counter output of the second counter, wherein the first counter is operable to receive a first clock signal (CLK1) at the first clock input and generate an asynchronous count (C1) depending on the first clock signal (CLK1), the second counter is operable to receive a second clock signal (CLK2) at the second clock input and generate a time count (C2) depending on the second clock signal (CLK2), and the logic / calculation engine is operable to receive the asynchronous count (C1) and the time count (C2) and calculate a digital output signal (ADC-COUNT) from the asynchronous count (C1) and the time count (C2).

[0009] In some embodiments, the sensor device further comprises a latching comparator operable to receive the integrator output signal (OPOUT) and provide a digital comparator output signal (LOUT). In some embodiments, the sensor device comprises a digital control circuit operable to control each switch to switch between an open state and a closed state depending on a clock cycle. In some embodiments, the digital output signal (ADC-COUNT) comprises an asynchronous count (C1) and a fractional time count (C2), the asynchronous count (C1) comprising an integer number of counts depending on a first clock signal (CLK1), and the fractional time count (C2) depending on a second clock signal (CLK2). In some embodiments, the digital output signal (ADC-COUNT) indicates a photocurrent generated by the photodiode. In some embodiments, the signal processing unit is configured to determine an average integration period indicating modulation in the digital comparator output signal (LOUT) based on the time count.

[0010] In general, one innovative aspect of the subject matter described in this specification can be implemented in a method, the method comprising generating a photocurrent (IPD) via an offset voltage across a photodiode, converting the photocurrent (IPD) into a digital comparator output signal (LOUT) based on a first clock signal (CLK1) via an analog-to-digital converter and based on a clipping technique performed during an integration cycle, wherein the ADC comprises an integrator, the integrator comprising a first set of clipping switches electrically coupled to an input terminal of a first amplifier, a second set of clipping switches electrically coupled to an output of the first amplifier and electrically coupled to an input terminal of a second amplifier, and an integrator output terminal providing an integrator output signal (OUTPUT). The method also comprises determining an asynchronous count (C1) comprising an integer number of counts based on the first clock signal (CLK1) based on the digital comparator output signal (LOUT), determining a fractional time count (C2) based on the digital comparator output signal (LOUT) based on the second clock signal (CLK2), and calculating a digital output signal (ADC-COUNT) indicating the photocurrent generated by the photodiode based on the asynchronous count (C1) and the fractional time count (C2).

[0011] Certain implementations include one or more of the following features.

[0012] In certain embodiments, converting the photocurrent based on a clipping technique cancels out the offset voltage across the photodiode.

[0013] In certain embodiments, the method further includes performing an initialization phase prior to performing the clipping technique, the initialization phase comprising applying a coarse auto-zero operation before the start of an integration time (T_INT) for the integration cycle, and applying a first reset / initialization phase at the start of the integration time (T_INT) for the integration cycle to reset the ADC and initialize signal acquisition.

[0014] In certain embodiments, after performing the initial phase, the clipping technique includes a first clipping technique, the first clipping technique including applying a first stage of clipping at a first set of clipping switches and a second set of clipping switches, wherein the first stage of clipping is applied with a first polarity, and applying a second stage of clipping at the first set of clipping switches and the second set of clipping switches at a halfway timestamp and without stopping the integration cycle, the halfway timestamp indicating a halfway point of the integration time (T_INT), wherein the second stage of clipping is applied with a second polarity, and wherein the second polarity is opposite to the first polarity.

[0015] In certain embodiments, after performing the initialization phase, the clipping technique includes a second clipping technique, the second clipping technique including applying a first phase of clipping at a first set of clipping switches and a second set of clipping switches at a halfway timestamp, the halfway timestamp indicating a halfway point of an integration time (T_INT) for an integration cycle, wherein the first phase of clipping is applied with a first polarity, applying a second reset / initialization phase to reset the ADC and reinitialize signal acquisition at the halfway point of the integration time (T_INT) for the integration cycle, wherein the second reset / initialization phase stops the integration cycle and changes the polarity of the integrator output, and applying a second phase of clipping at the first set of clipping switches and the second set of clipping switches after the second reset / initialization phase, wherein the second phase of clipping is applied with the first polarity. In certain embodiments, changing the polarity of the integrator output from the first polarity to the second polarity includes switching the output of the first set of clipping switches for the input terminal of the first amplifier, and switching the output of the second set of clipping switches for the input terminal of the second amplifier.

[0016] In certain embodiments, changing the polarity of the integrator output from a first polarity to a second polarity by switching the input from each set of clipping switches for each input terminal of each amplifier, respectively, cancels the offset voltage across the photodiode.

[0017] Certain embodiments of the subject matter described in this specification can be implemented to achieve one or more of the following advantages. By using the disclosed circuit device having two sets of chopping switches, dark current for each measurement can be canceled. In addition, this technique is useful for obtaining zero dark counts for the full temperature range with an auto-zero operation at the beginning of integration, which enables the sensor device to more accurately measure low light levels. In addition, in some cases, due to the lower auto-zero digital-to-analog conversion (DAC) resolution, the auto-zero time can be significantly reduced. Moreover, in some cases, due to the large DAC step size, the sensor device can also reduce the noise requirements of the auto-zero stage. The sensor device described in the present disclosure can also be easily integrated into existing system architectures.

[0018] The sensor device can be used for both light sensing and temperature sensing applications using the same signal path for sensor signal acquisition. By using the same signal path for both sensors, the silicon area of ​​the sensor device can be kept small. Therefore, in some cases, the sensor device can be produced at a lower cost.

[0019] Preferably, the method is run during the entire integration time to perform a continuous acquisition cycle, wherein the sensor signal is integrated, such as to accumulate a charge stored by means of an analog-to-digital converter, until the accumulated charge reaches a first reference potential. When the first reference potential has been reached, the accumulated charge is discharged with a reference charge during a determined time (e.g., a clock cycle). The number of counts provides a representation of the sensor signal.

[0020] The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other aspects, features, and advantages will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is an example implementation of a sensor device for light sensing.

[0022] Figure 2A-2B is an example implementation of a sensor device for light sensing having two sets of clipping switches.

[0023] Figures 3A-3C is a block diagram of three example ambient light sensor states for a sensor device for light sensing.

[0024] Figures 4A-4E is a timing diagram of a pulse width modulation control waveform for a sensor device for light sensing. DETAILED DESCRIPTION

[0025] The present disclosure describes a light sensor architecture for accurately measuring low light levels by using a clip switch during initialization to optimize the cancellation of dark current in each ambient light sensor (ALS) measurement with an auto-zero (AZ) operation. The light sensor architecture has applications such as ambient light sensors or color sensors, where the light sensor is used to measure light levels. Since the light sensor is placed under dark glass, a larger photodiode area is required to achieve a specified sensitivity for a given electrical gain from the light sensor. In turn, a larger photodiode area increases leakage current, and the increase in leakage current limits the ability to accurately detect low light levels.

[0026] Longer auto-zero times and higher dark currents cause problems in light sensor applications. These two factors limit light measurements in extremely low light conditions. Certain light-to-frequency architectures used in light sensor devices use different auto-zero digital-to-analog converters (DACs) to achieve improved dark current performance by reducing the voltage offset across the photodiode. At high temperatures, even a small residual μV offset across the photodiode can cause large dark counts. A 12-bit AZ DAC can have problems with repeatability of the AZ DAC code and have longer AZ times than expected. A repeatability issue for the AZ DAC is that the least significant bit (LSB) of the DAC is below the noise level. Therefore, increasing the number of DAC bits to reduce the voltage offset across the photodiode tends to exacerbate these problems.

[0027] This document describes a means to optimize the cancellation of dark current more accurately in a shorter time by reducing the resolution of the AZ-DAC. A larger DAC step size can improve the repeatability of the AZ code and the noise requirements of the AZ-DAC. In addition, the integrator amplifier using two sets of clipping switches allows the use of a larger LSB of the AZ DAC and cancels the dark counts for each measurement. Due to the clipping from the two sets of clipping switches, the offset voltage remaining after the AZ does not affect the dark counts with temperature and supply voltage changes, so the light sensor can measure low light very accurately.

[0028] These features, as well as additional features, are described in greater detail below.

[0029] Figure 1 is an exemplary embodiment of an optical sensor device 100. The sensor device 100 includes a photodiode 105 and an analog-to-digital converter (ADC) 101 (also referred to herein as converter 101). The sensor device 100 also includes a signal processing unit 102. The converter 101 and the signal processing unit 102 are combined into a light-to-frequency converter that can be implemented as an integrated circuit.

[0030] In some embodiments, the photodiode 105 is connected to the integrated circuit as an external component. Alternatively, in some embodiments, the photodiode 105 can be part of the integrated circuit. The light-to-frequency converter and the photodiode can be considered as an optical sensor device. In some embodiments, the optical sensor device is used as an ambient light sensor.

[0031] The photodiode 105 is coupled to the input 107 of the converter 101. The converter 101 comprises an integrator 120, which in turn comprises an amplifier 130, an integrator input 121 and an integrator output 122. The amplifier 130 comprises an amplifier input 131 connected to the input 107 of the converter 101, the input 107 of the converter 101 being connected to the integrator input 121. In certain embodiments, the amplifier input 131 is implemented as an inverting input. Alternatively, the amplifier input 131 may be implemented as a non-inverting input. The amplifier 130 comprises a further amplifier input 132, which is designed as a non-inverting input, for example. The photodiode 105 connects the input 107 of the converter device 101 to a reference potential terminal. The first bias source VREFIN couples the further amplifier input 132 to the reference potential terminal. The integration capacitor 104 of the integrator 120 connects the amplifier input 131 to an amplifier output 133 of the amplifier 130.

[0032] The converter 101 includes a comparator 136 having a comparator input 137 connected to the amplifier output 133. For example, the comparator input 137 is implemented as a non-inverting input. For example, another comparator input 138 of the comparator 136 is designed as an inverting input. A reference voltage source VREFC connects the other comparator input 138 to a reference potential terminal. An output 139 of the comparator 136 is connected to a digital control circuit 110. The digital control circuit 110 includes a control input 111 and a control logic and one or more clock generators.

[0033] In addition, the converter 101 comprises a reference capacitor 103. The reference capacitor 103 is coupled to the input 107 of the converter 101 via a reference switch 115 of the converter device 101. Thus, the reference capacitor 103 is coupled to the amplifier input 131 through the reference switch 115. The control output 113 of the digital control circuit 110 is connected to the control terminal of the reference switch 115. A first bias source VREFIN is coupled to the reference capacitor 103.

[0034] Reference capacitor 103 provides a variable capacitance value CREF. The capacitance value CREF of reference capacitor 103 is set by another capacitor control signal. For example, integrating capacitor 104 and reference capacitor 103 can be programmed for different ambient light sensor gains.

[0035] The converter 101 also includes several additional switches that participate in resetting and charge dumping during the integration process: a reference switch 115, and first to third reference switches 114, 116, 117. The first reference switch 114 couples the first bias source VREFIN to the first electrode of the reference capacitor 103. The reference switch 115 couples the first electrode of the reference capacitor 103 to the amplifier input 131. The second reference switch 116 couples the second electrode of the reference capacitor 103 to the reference potential terminal. The third reference switch 117 couples the node 106 to the second electrode of the reference capacitor 103. The reference source VREF generates a second reference voltage VGAIN at the node 106 through a voltage divider circuit formed by two resistors 108, 109. In order to charge the reference capacitor 103, the first and second reference switches 114, 116 are closed and the third reference switch 117 and the reference switch 115 are opened by the first and second reference switch signals S1, S2. For example, the first and second reference switch signals S1, S2 are non-overlapping clock signals. In order to dump the charge packet QREF to the amplifier input 131 , the first and second reference switches 114 , 116 are opened and the third reference switch 117 and the reference switch 115 are closed by the first and second reference switch signals S1 , S2 .

[0036] Comparator 136 can be implemented as a latch comparator, for example. Comparator 136 has an output 139 connected to a first latch input 143 of latch 140. Latch 140 includes a second latch input 141 to receive a first clock signal CLK1. Latch output 142 is connected to result output 112 of converter 101 and digital control circuit 110.

[0037] Comparator 136 and latch 140 operate as a latched comparator. In certain situations defined by the first clock signal CLK1, latch 140 outputs a comparator output signal LOUT at output terminal 112. Due to the first clock signal CLK1, the latched comparator compares the output voltage VOUT of amplifier 130 with the bias voltage VREF2 only at certain intervals of CLK1.

[0038] The signal processing unit 102 is connected to the result output 112 of the converter 101. The signal processing unit 102 also includes a first counter 150, a second counter 155 and a logic / computation engine 160. The first counter 150 has a first clock input 151 connected to the result output 112. In addition, the first counter 150 has a first reset input 152. Similarly, the second counter 155 has a second clock input 156 and a second reset input 157. The first counter output 153 of the first counter 150 and the second counter output 158 ​​of the second counter 155 are each connected to the calculation inputs 161 and 162 of the logic / computation engine 160, respectively. Finally, the logic / computation engine 160 includes a calculation output 163. The signal processing unit 102 can be implemented at least partially as a microcontroller.

[0039] The sensor signal acquisition is initialized by applying the input control signal ADC_ON and the integration time signal STINT to the control input terminal 111 of the digital control circuit 110. In addition, the first clock signal CLK1 can be provided to the control input terminal 111. The first clock signal CLK1 can be provided by a clock generator and / or generated by the digital control circuit 110. Preferably, the sensor device 100 is cleared before the signal acquisition is performed. When the input control signal ADC_ON is provided to the control input terminal 111, the operation of the converter 101 is triggered. The first bias source VREFIN provides an amplifier reference voltage VREFIN to the reference capacitor 103. The reference capacitor 103 generates a charge packet QREF. The charge packet QREF has a value according to the following formula

[0040] Q ref =V ref,in ·C ref

[0041] Among them C ref is the capacitance value of the reference capacitor 103, and V ref,in is the voltage value of the amplifier reference voltage. The digital control circuit 110 provides a reference switch signal S2 to the reference switch 115. After closing the reference switch 115, the charge packet QREF is applied to the integration node 134. In addition, the first and second counters 150, 155 are reset by applying a reset signal SRESET to the first and second reset input terminals 152, 157, respectively.

[0042] Depending on the input control signal ADC_ON, and after the sensor device 100 has been set or cleared to an initial condition, the photodiode 105 starts signal acquisition and generates a photocurrent IPD. The photocurrent value depends on the intensity of the light incident on the photodiode 105. The photocurrent IPD flows through the photodiode 105 and the input terminal 107 of the converter 101. Each of the photodiode 105, the amplifier input terminal 131 and the integration capacitor 104 is connected to the integration node 134. In addition, the reference capacitor 103 is coupled to the integration node 134 via the reference switch 115. The sensor current IPD flows from the integration node 134 to the reference potential terminal having a positive value. The input voltage VNEG is tapped at the amplifier input terminal 131 and is therefore also tapped at the integration node 134. The first bias source VREFIN provides the amplifier reference voltage VREFIN to the other amplifier input terminal 132. The amplifier 130 generates an output voltage VOUT at the amplifier output terminal 133.

[0043] With the reference switch 115 open, the photocurrent IPD is integrated on the integrating capacitor 104. The output voltage VOUT rises with time t as follows:

[0044] V OUT =I PD ·t·C INT

[0045] Among them I PD is the photocurrent value, and C INT represents the capacitance value of the integrating capacitor 104 .

[0046] The output voltage VOUT of the amplifier 130 is applied to the comparator input terminal 137. The reference voltage source VREF generates a bias voltage VREF2, which is then applied to the comparator input terminal 138 as a comparator reference voltage VREFC. The comparator 136 generates a comparator output signal LOUT based on the value of the output signal VOUT and the comparator reference voltage VREFC. If the output voltage VOUT is greater than the comparator reference voltage VREFC, the comparator output signal LOUT has a first logic value, and if the output voltage VOUT is less than the comparator reference voltage VREFC, the comparator output signal LOUT has a second logic value. The comparator output signal LOUT is provided to the digital control circuit 110.

[0047] During the signal acquisition process, the signal processing unit 102 counts the pulses of the comparator output signal LOUT. Basically, the counting is performed by the first counter 150. The converter 101 and the first counter 150 can be considered as a first-order modulator that generates an asynchronous count COUNT-1 (hereinafter abbreviated as C1). The asynchronous count C1 is proportional to the photocurrent IPD integrated on the integration capacitor 104 (within the error range). According to some embodiments, the asynchronous count C1 may be prone to errors, which is explained by the signal processing engine 40. The first counter 150 provides the asynchronous count C1. However, this count only includes an integer number of individual counts.

[0048] The second counter 155 can be considered as a free-running counter operating on the second clock signal CLK2 received at the second clock input 156. The second clock signal CLK2 can be provided by a clock generator (not shown) and / or by the digital control circuit 110. The second counter 155 is reset by receiving the comparator output signal LOUT at the second reset input 157. The second counter 155 generates a time count COUNT-2 (hereinafter abbreviated as C2) of the time period between adjacent cycles or time intervals of the resolution asynchronous count C1. In some embodiments, the second clock signal CLK2 is implemented at a higher frequency than the first clock signal CLK1. For example, the first clock signal CLK1 can have a rectangular function with a frequency of 737kHz, while the second clock signal CLK2 can have a rectangular function with a frequency of 2MHz. Alternatively, other clock signal frequencies can be used for the first clock signal CLK1 and the second clock signal CLK2.

[0049] In certain embodiments, the digital control circuit 110 initializes and also terminates the signal acquisition after the integration time (T_INT) has elapsed.The integration time (T_INT) is set at the digital control circuit 110 depending on the integration time signal.

[0050] In some implementations, the first bias source VREFIN is omitted and the amplifier reference voltage VREFIN is zero.

[0051] As discussed, ALS circuits (such as Figure 1 The basic operating principle of the sensor device 100 shown is that a charge-balanced analog-to-digital converter (ADC) collects the photocurrent from the photodiode and converts it into ALS counts (ADC-COUNT). The ALS counts are based on the charge conservation equation:

[0052] ADC_COUNT=(T int *I pd ) / (C ref *V ref )

[0053] Where T int is the total conversion time, I pd is the photocurrent value, C ref is the capacitance value of the reference capacitor, V ref is the reference voltage. In completely dark conditions, ideally, the photodiode will not generate any current and the number of ADC counts is zero. However, in actual implementations, if the voltage across the photodiode is not zero, then the photodiode PD will leak, and the leakage current is calculated based on the leakage current equation:

[0054] I leak =I S *[e^(V neg / (kT / q)) -1 ]

[0055] Among them I leak is the leakage current, I S is the reverse bias saturation current (or scale current), and V neg is the value of the input voltage. "kT / q" is the Boltzmann constant k multiplied by the temperature T divided by the electron charge q, also known as the thermal voltage V T Leakage current increases exponentially with temperature and can cause problems with ambient light sensors. For example, there may be a finite dark count (Dark_COUNT: ADC_COUNT when light is zero) and this will limit the lower performance of the sensor:

[0056] Dark_COUNT=(T int *I leak ) / (C ref *V ref )

[0057] This leakage current is very high at 70 degrees, with the highest gain (e.g., 512x). Leakage current can be a limiting factor in the performance of an ambient light sensor (ALS) such as sensor device 100. The total ALS measurement time for each ALS integration cycle can be calculated by the following equation:

[0058] ALS measurement time = AZ_Time + Init_Time + ALS_Integration_Time

[0059] Where Init_Time is the initialization time and is a fixed time (e.g., 100 μs) independent of gain, and AZ_DAC and ALS_Integration_Time are fixed times (e.g., 100 ms). AZ_Time is the auto-zero time, and the auto-zero time varies with the number of bits in the AZ DAC and the algorithm used to find the AZ code. For example, the higher the bit of the AZ DAC, the higher the AZ time. As the number of DAC bits increases, the overhead time in the ALS measurement increases and can be the starting point of the maximum overhead time in the ALS measurement.

[0060] In some embodiments, the user can program the integration time. For example, according to some embodiments, the range of the integration time (T_INT) can vary from 2.78ms to 1400ms. Alternatively, different ranges of integration times can be used.

[0061] A sensor arrangement (and corresponding timing diagrams) utilizing two sets of clipping switches and two different clipping techniques to cancel dark current and reduce auto-zero time with lower AZ DAC resolution is described below with reference to FIGS. 2-4 .

[0062] FIG. 2 is an exemplary embodiment of an optical sensor device 200. In addition to an analog-to-digital converter (ADC) 201 (also referred to herein as converter 201) including a Figure 1 In addition to the integrator 220 of the integrator 120 discussed above, the sensor device 200 has a similar Figure 1 2. For example, the sensor device 200 includes a photodiode 205, a converter 201 (different from the integrator 220), and a signal processing unit 202 (similar to the signal processing unit of the sensor device 100). Therefore, except for those components discussed herein with respect to the integrator 220, it can be assumed that the same components in FIG. 2 are the same as those in reference 2. Figure 1 Those components discussed are equivalent.

[0063] In some embodiments, the sensor device 200 is used for light-to-frequency conversion for light sensing. The converter 201 depends on a first clock signal (CLK1) and is configured to convert a photocurrent (IPD) generated by a photodiode 205 into a digital comparator output signal (LOUT). The ADC device 201 includes a sensor input terminal 207 for connecting the photodiode 205, a result output terminal 212 for providing a digital comparator output signal (LOUT) to a signal processing unit 202, and an integrator 220.

[0064] The signal processing unit 202 is similar to Figure 1The signal processing unit 102 is connected to the result output terminal 212 of the converter 201. The signal processing unit 202 also includes a first counter, a second counter and a logic / computation engine 260. The signal processing unit 202 can be at least partially implemented as a microcontroller. The signal processing unit 202 is configured to determine a digital output signal (ADC-COUNT) including an asynchronous count (C1) from the digital comparator output signal (LOUT), the asynchronous count (C1) including an integer number of counts depending on the first clock signal (CLK1), and including a fractional time count (C2) depending on the second clock signal (CLK2). The digital output signal (ADC-COUNT) indicates the photocurrent generated by the photodiode 205.

[0065] In certain embodiments, the integrator 220 includes an integrator input 221 electrically coupled to the sensor input 207 to receive an integrator input signal and an integrator output 222 for generating an integrator output signal (OPOUT). The integrator 220 includes a first set 270 of clipping switches connected to a first amplifier 275. The first set 270 of clipping switches is Figure 2B 2 and includes clip switches 223a, 223b, 224a and 224b. A first set of clip switches is adapted to clip the integrator input signal to the amplifier 275 input terminals 271, 272. The output terminals 273, 274 of the amplifier 275 are connected to the second amplifier 285.

[0066] Integrator 220 also includes a second set 280 of clipping switches connected to a second amplifier 285. The second set 280 of clipping switches is Figure 2C 2 and 3. The second set 280 of clipping switches is further shown in FIG. 2 and includes clipping switches 225a, 225b, 226a and 226b. The second set 280 of clipping switches is adapted to clip the output signal of the first amplifier 275 at the inputs 281, 282 of the second amplifier 285. The output of the amplifier 285 is connected to the integrator output 222, which is connected to the input 237 of the comparator 236. According to certain embodiments, the second set 280 of clipping switches is configured to switch the polarity of the output of the first set 270 of clipping switches. Switching polarity is referred to herein as clipping technique-2.

[0067] Comparator 236 and latch 240 operate as a latched comparator. In certain situations defined by the first clock signal CLK1, latch 240 outputs the comparator output signal LOUT to output terminal 212. Due to the first clock signal CLK1, the latched comparator compares the output voltage VOUT of integrator 220 with the bias voltage VREF2 only at certain intervals of CLK1.

[0068] In certain embodiments, the converter 201 operates using a clipping technique. According to certain embodiments, the clipping technique used may be controlled by the digital control circuit 210. The clipping technique described in the present disclosure is illustrated and discussed below with reference to FIG.

[0069] Figures 3A-3C is a block diagram of three example ambient light sensor states for a sensor device for light sensing. Specifically, Figure 3A Block diagram 310 is illustrated as an example of ambient light sensor states used by a sensor device that does not use a clipping circuit, such as sensor device 100 . Figure 3B and 3C Block diagrams 320 , 330 , respectively, illustrate examples of ambient light sensor states used by a sensor device, such as sensor device 200 , that uses a clipping circuit according to the clipping technique.

[0070] Figure 3A The ambient light sensor state in the Ambient Light Sensor Measurement Period (ALE) begins at start block 311 during one ambient light sensor measurement during the total integration time (T_INT). Next, at block 312, a mixed segmented (coarse) and binary weighted (fine) operation is applied by a DAC (such as converter 101 of sensor device 100) as an auto-zero operation at the beginning of integration prior to a reset / initialization phase.

[0071] At block 313, the reset / initialization phase of the ambient light sensor measurement occurs after the coarse and fine auto-zero operations. For example, by applying the input control signal ADC_ON and the integration time signal STINT to Figure 1 The sensor signal acquisition is initialized by the control input terminal 111 of the digital control circuit 110 of the converter 101 in the embodiment. According to some embodiments, after the converter is reset, the signal acquisition can be initialized by setting the input control signal ADC_ON from low to high. The integration time signal STINT changes from low to high at the same time and the converter (such as the converter device 101) starts to operate.

[0072] After the reset / initialization phase, the ambient light sensor integration operation begins at block 314. For example, the photocurrent IPD generated by the photodiode 105 is integrated by the integrator 120, which includes the amplifier 130 and the integrating capacitor 104, as described above with reference to FIG. Figure 1 The photocurrent IPD is integrated at the integration node 134 and the output voltage VOUT rises during the integration period. The comparator 136 monitors the output voltage VOUT of the integrator, that is, the output voltage VOUT of the amplifier 130. When the output voltage VOUT is greater than the comparator reference voltage VREFC, the comparator output signal LOUT is high and the charge packet (e.g., Q ref =Vref,in ·C ref ) are dumped into the integration node 134. The output signal LOUT is received at the first counter, and the asynchronous counter C1 is incremented by one count.

[0073] At block 315, a signal from a logic / computation engine such as Figure 1 The ADC_COUNT output measured by the ambient light sensor of the logic / computation engine 160 of the signal processing unit 102 is stored. Figure 3A The ambient light sensor state in the embodiment ends at the end block 316 after the integration time (T_INT) has expired, which indicates the end of one ambient light sensor measurement. For example, the digital control circuit 110 not only initializes, but also terminates the signal acquisition after the integration time (T_INT) is completed. According to some embodiments, the integration time (T_INT) is set at the digital control circuit 110 depending on the integration time signal STINT.

[0074] Figure 3B Block diagram 320 illustrates example ambient light sensor states used by a sensor device, such as sensor device 200 , that uses a clipping circuit according to the first clipping technique.

[0075] During one ambient light sensor measurement during the total integration time (T_INT), the ambient light sensor state for the first clipping technique begins at start block 321. Next, before the clipping technique is applied, the initialization phase begins at blocks 322 and 323. Specifically, at block 322, a segmentation (coarse) operation is applied by a DAC (such as converter 201 of sensor device 200) as an auto-zero operation at the beginning of integration before the reset / initialization phase.

[0076] At block 323, a reset / initialization phase of ambient light sensor measurement occurs after the coarse auto-zero operation. For example, sensor signal acquisition is initialized by applying the input control signal ADC_ON and the integration time signal STINT to the control input of the digital control circuit 210 of the converter 201 in FIG. 2. According to some embodiments, after the converter 201 is reset, signal acquisition can be initialized by setting the input control signal ADC_ON from low to high. The integration time signal STINT simultaneously transitions from low to high and the converter 201 begins operation.

[0077] According to some embodiments, the sensor device 200 uses an AZDAC with a higher LSB (e.g., 1 LSB = ~100 μV) for the clipping technique. An auto-zero is performed in the initialization phase of block 323, which can bring the offset voltage across the photodiode 205 to a reasonable level (e.g., below ~100 μV). Below the offset voltage, the diode VI characteristic is linear, so the clipping technique can be used to cancel the dark current during the integration time (T_INT).

[0078] After an initial phase including applying a coarse auto-zero operation (block 322) and applying a reset / initialization phase (block 323), the ambient light sensor integration operation for the first clipping technique begins at block 324. Each clipping technique described herein is based on an integration time (T_INT) for an integration cycle. This is a continuous process and applies a residual offset across the photodiode in both polarities and averages out the offset effect on the photodiode and eliminates the dark current for each measurement. The clipping technique is applied inside the integrator 220 loop and does not cause problems with the stable behavior of the integrator 220.

[0079] Specifically, for the first clipping technique, integration begins with a first stage of clipping performed by the integrator 220 at the first set 270 of clipping switches and the second set 280 of clipping switches at box 325. The first stage of clipping is referred to as "ALS integration with clipping 0" and is also referred to as "clipping 0" herein. The first stage of clipping is applied with a first polarity. For example, a +Ve offset across the input terminals of the first amplifier in clipping 0. Integration is initially similar to box 324 until halfway through the total integration time (T_INT). Clipping is then applied in the second half of the integration time (T_INT) without stopping integration at box 325. Due to the residual, the offset is applied across the diode for both polarities. For example, the photocurrent IPD generated by the photodiode 205 is integrated by the integrator 220 including the amplifier 230 and the integration capacitor 204. The photocurrent IPD is integrated at the integration node, and the output voltage VOUT rises during the integration. Comparator 236 monitors the output voltage VOUT of the integrator, that is, the output voltage VOUT of amplifier 230. When the output voltage VOUT is greater than the comparator reference voltage VREFC, the comparator output signal LOUT is high and the charge packet (eg, Q ref = Vref，in ·C ref ) is dumped into the integration node. The output signal LOUT is received at the first counter, and the asynchronous counter C1 is incremented by one count.

[0080] The signal processing unit 202 will continue counting throughout the conversion time (T_INT), however, halfway through the integration time (T_INT), a second stage of clipping (e.g., Clipping 1) is applied by the integrator 220 at the first set 270 of clipping switches and the second set 280 of clipping switches at box 325. The second stage of clipping is referred to as "ALS integration with Clipping 1" and is also referred to herein as "Clipping 1". The second stage of clipping is applied with a polarity different from the first polarity of the first stage of clipping. For example, a +Ve offset across the input terminals of the first amplifier in Clipping 0 during the first stage of clipping will result in a -Ve offset across the input terminals of the first amplifier in Clipping 1 during the second stage of clipping. Integration will continue at box 325, however, when clipping is applied after halfway through the integration time (T_INT), this will cause a small change in the output voltage and integration slope based on the integration of the leakage current, which will introduce dark counts below zero. Reference Figure 4D The first wave clipping technique is further described.

[0081] At block 326 , the ADC_COUNT output of the ambient light sensor measurement from a logic / computation engine, such as logic / computation engine 260 of signal processing unit 202 , is stored. Figure 3B The ambient light sensor state in the end block 327 ends after the integration time (T_INT) has expired, which indicates the end of one ambient light sensor measurement. For example, the digital control circuit 210 not only initializes, but also terminates the signal acquisition after the integration time (T_INT) is completed. According to some embodiments, the integration time (T_INT) is set at the digital control circuit 210 depending on the integration time signal STINT.

[0082] Figure 3C Block diagram 330 illustrates example ambient light sensor states used by a sensor device (eg, sensor device 200 ) using a clipping circuit according to the second clipping technique.

[0083] During one ambient light sensor measurement during the total integration time (T_INT), the ambient light sensor state for the first clipping technique begins at start block 331. Next, before the clipping technique is applied, the initialization phase begins at blocks 332 and 333. Specifically, at block 332, a segmentation (coarse) operation is applied by a DAC (such as converter 201 of sensor device 200) as an auto-zero operation at the beginning of integration before the reset / initialization phase.

[0084] The first reset / initialization phase of the ambient light sensor measurement occurs after the coarse auto-zero operation at block 333. For example, sensor signal acquisition is initialized by applying the input control signal ADC_ON and the integration time signal STINT to the control input of the digital control circuit 210 of the converter 201 in FIG. 2. According to some embodiments, after the converter 201 is reset, the signal acquisition can be initialized by setting the input control signal ADC_ON from low to high. The integration time signal STINT simultaneously transitions from low to high and the converter 201 begins operation.

[0085] According to some embodiments, the sensor device 200 uses a sensor with a higher LSB (e.g. ) is used for the clipping technique. An auto-zero is performed in the first initialization phase of block 333, which can bring the offset voltage across the photodiode 205 to a reasonable level (e.g., below ˜100 μV). Below the offset, the diode VI characteristic is linear, and therefore the clipping technique can be used to cancel the dark current during the integration time (T_INT).

[0086] After an initial phase including applying a coarse auto-zero operation (block 332) and applying a reset / initialization phase (block 333), the ambient light sensor integration operation for the second clipping technique begins at block 334. Each clipping technique described herein is based on an integration time (T_INT). This is a continuous process and applies a residual offset across the photodiode in both polarities and averages out the offset effect on the photodiode and eliminates the dark current for each measurement. The clipping technique is applied inside the integrator 220 loop and does not cause problems with the stable behavior of the integrator 220.

[0087] Specifically, for the second clipping technique, integration begins with a first stage of clipping performed by the integrator 220 at the first set 270 of clipping switches and the second set 280 of clipping switches at box 325. The first stage of clipping is referred to as "ALS integration with clipping 0" and is also referred to as "clipping 0" herein. The first stage of clipping is applied with a first polarity. For example, a +Ve offset across the input terminals of the first amplifier in clipping 0. Integration is initially similar to box 324 until halfway through the total integration time (T_INT). Clipping is then applied in the second half of the integration time (T_INT) without stopping integration at box 325. Due to the residual, the offset is applied across the diode for both polarities. For example, the photocurrent IPD generated by the photodiode 205 is integrated by the integrator 220 including the amplifier 230 and the integration capacitor 204. The photocurrent IPD is integrated at the integration node, and the output voltage VOUT rises during the integration. Comparator 236 monitors the output voltage VOUT of the integrator, that is, the output voltage VOUT of amplifier 230. When the output voltage VOUT is greater than the comparator reference voltage VREFC, the comparator output signal LOUT is high and the charge packet (eg, Q ref = Vref,in ·C ref ) is dumped into the integration node. The output signal LOUT is received at the first counter, and the asynchronous counter C1 is incremented by one count.

[0088] At block 335, a second reset / initialization phase of ambient light sensor measurement occurs halfway through the integration time (T_INT) before applying the second phase of clipping (e.g., Clip 1). For example, sensor signal acquisition is reinitialized by applying the input control signal ADC_ON and the integration time signal STINT to the control input of the digital control circuit 210 of the converter 201 in FIG. 2. According to some embodiments, after the converter 201 is reset, the signal acquisition can be reinitialized by setting the input control signal ADC_ON from low to high. The integration time signal STINT simultaneously transitions from low to high and the converter 201 begins operation.

[0089] After the second reset / initialization phase, a new ambient light sensor measurement is initiated and then a second phase of clipping (e.g., Clipping 1) is applied at block 336 for the second half of the integration time (T_INT). The second phase of clipping is referred to as “ALS integration with Clipping 1” and is also referred to herein as “Clipping 1”. Because the second reset / initialization phase was applied at block 335, the second phase of clipping is applied with the same polarity as the first phase of clipping. For example, a +Ve offset across the input terminals of the first amplifier in Clipping 0 during the first phase of clipping will result in a +Ve offset across the input terminals of the first amplifier in Clipping 1 during the second phase of clipping. Due to the residual, the offset is applied across the diode for both polarities. The signal processing unit 202 will continue counting during the entire conversion time T_INT. Integration will continue at block 336, however, by applying clipping after half the integration time (T_INT) after the second reset / initialization phase, the output change during the on-state output signal information when there is a switch in the clipping switch can be eliminated. Reference Figure 4E The second wave clipping technique is further described.

[0090] At block 337 , the ADC_COUNT output of the ambient light sensor measurement from a logic / computation engine, such as logic / computation engine 260 of signal processing unit 202 , is stored. Figure 3B The ambient light sensor state in the embodiment ends at the end block 338 after the integration time (T_INT) has expired, which indicates the end of one ambient light sensor measurement. For example, the digital control circuit 210 not only initializes, but also terminates the signal acquisition after the integration time (T_INT) has been completed. According to some embodiments, the integration time (T_INT) is set at the digital control circuit 210 depending on the integration time signal STINT.

[0091] Figure 4A Shown for Figure 1 400A is an exemplary timing diagram of signals of an exemplary embodiment of an ideal optical sensor device having ideal waveforms and ideal expected ADC code 4 of a circuit. The figure shows different signals and operations of a light-to-frequency converter. Depicted are a first clock signal CLK1 and a second clock signal CLK2. In the example shown, the clock signals are implemented as rectangular functions having frequencies of 737 kHz and 2 MHz, respectively. These values ​​should be considered as examples only and are not limited to these exact values. Typically, the frequency of the first clock signal CLK1 is selected to be lower than the frequency of the second clock signal CLK2. In addition, the figure shows the output voltage VOUT of an integrator (such as integrator 120 or 220). Finally, Figure 4AAn asynchronous count C1 and a time count C2 are shown. The signal is represented as a function of time (t). The integration time (T_INT) is shown as a mean of a reference as the signal acquisition proceeds for a specific integration time (T_INT).

[0092] The basic operating principle of the optical sensor device is based on the concept of a charge-balanced converter. The converter 101 collects light from the photodiode 105, which is converted into a photocurrent IPD, which is converted into counts through several steps. Ideally, the counts C1 measured during the integration time (T_INT) are a direct measurement of the photocurrent IPD. The resulting asynchronous counts C1 are supplemented with various error estimates that can be derived from the time counts C2.

[0093] The basic operating principle is implemented by various components of the optical sensor device. The converter 101 is designed as a charge balancing converter and is used to convert the photocurrent IPD into a digital count ADC-COUNT in the form of a digital output signal. The photocurrent IPD is integrated into the integration node 134 and the integration capacitor 104 generates an input voltage VNEG. If the charge integrated into the integration capacitor 104 is greater than the unit charge packet QREF, the charge on the integration capacitor 104 will be reduced by one unit charge packet and the first counter 150 will be incremented by one logic value. The integration time signal STINT determines the integration time (T_INT). By integrating the photocurrent IPD during the integration time (T_INT), the asynchronous count C1 will result in a measurement of the intensity of the light incident on the photodiode 105. For example, the integration time (T_INT) can be 100ms. Alternatively, the integration time (T_INT) can be a different time length (for example, a multiple of the period of the first clock signal CLK1). In this embodiment, the comparator reference voltage VREFC is constant and equal to the bias voltage VREF2.

[0094] An exemplary measurement cycle may involve the following operations. Initially, when the input control signal ADC_ON is low, the converter 101 is reset. Resetting the converter 101 may involve clearing the photodiode 105; clearing the integration capacitor 104; resetting the input voltage VNEG to the amplifier reference voltage VREFIN; resetting the output voltage VOUT to the first reference voltage VREF1, and thereby below the comparator reference voltage VREFC. Therefore, the comparator output signal LOUT is low. The reference capacitor 103 is fully charged by the charge packet QREF and disconnected from the integration node 134. The first and second counters 150, 155 are cleared so that the digital output signal at the calculation output terminal 163 is 0. The second reference switch signal S2 applied to the reference switch 115 is low.

[0095] After the converter is reset, signal acquisition can be initialized by setting the input control signal ADC_ON from low to high. The integration time signal STINT simultaneously changes from low to high and the converter 101 starts operating. The photocurrent IPD generated by the photodiode 105 is integrated by an integrator including an amplifier 130 and an integrating capacitor 104. The photocurrent IPD is integrated at the integration node 134 and the output voltage VOUT rises during the integration. The comparator 136 monitors the output voltage VOUT of the integrator (i.e., the output voltage VOUT of the amplifier 130). When the output voltage VOUT is greater than the comparator reference voltage VREFC, the comparator output signal LOUT is high and the charge packet (Q ref = Vref，in ·C ref ) is dumped into the integration node 134. The output signal LOUT is received at the first counter, and the asynchronous counter C1 is incremented by one count.

[0096] After charge dumping, the output voltage VOUT decreases by the value V ref,in ·C ref / C int . The output voltage VOUT returns to low, i.e., the level of the first reference voltage VREF1 is lower than the comparator reference voltage VREFC, and rises again. The charge packet circuit (e.g., reference capacitor 103) is disconnected from the integration node 134 and returns to recharge mode. The number of dumps N increases by one count. The output voltage VOUT swings between the first reference voltage VREF1 and the bias voltage VREF2. This process is characterized by a charge dumping period CDP and will be repeated until the integration time (T_INT) ends and the signal STINT changes from high to low. During the integration time (T_INT), the signal STINT is high and the number of counts is accumulated by the first counter 150. The counter value C1 is equal to the number of dumps N and provides a first measurement of the intensity of the incident light. The asynchronous count C1 is equal to the number of dumps N counted by the first counter 150. The number of charge dumps N is equal to the count of the first counter 150 of the converter 101 generated within the period defined by the integration time (T_INT).

[0097] like Figure 4A , four ideal integration cycles of C2 are shown to follow an expected ADC code of 4. Each time a full charge dumping cycle is completed, the time count C2 is reset via the second reset input 157. The second counter 155 resolves the period between adjacent counts in the asynchronous count C1. Therefore, each time an integration cycle is completed and charge is dumped, the number of dumps N is increased by one count in the asynchronous count C1 by the first counter 150. The second counter 155 generates a time count C2, which is a digital value that determines the time period or duration for the corresponding integration cycle.

[0098] Figure 4B Shown for Figure 1 400B is an exemplary timing diagram of signals of an exemplary embodiment of an optical sensor device with an ADC code of 5 and a +Ve offset condition for a circuit of FIG. The diagram illustrates different signals and operations of the light-to-frequency converter. Figure 4B Depicted in FIG. 1 is the output voltage VOUT of the integrator 120. In addition, an asynchronous count C1 and a time count C2 are shown. The signal is represented as a function of time t. As the signal is acquired for a specific integration time (T_INT), the integration time (T_INT) is shown as a mean value of the reference. Figure 4B As shown in , five integration cycles of C2p are shown to follow an ADC code of 5.

[0099] Figure 4B-4E The first clock signal CLK1 and the second clock signal CLK2 are not depicted in FIG. However, it can be assumed that for these example embodiments, the clock signals are also implemented as rectangular functions with frequencies of 737kHz and 2MHz, respectively. These values ​​should only be considered as examples and are not limited to these exact values. Typically, the frequency of the first clock signal CLK1 is selected to be lower than the frequency of the second clock signal CLK2.

[0100] Figure 4C Shown for Figure 1 400C is an exemplary timing diagram of signals of an exemplary embodiment of an optical sensor device with an ADC code of 3 and a -Ve offset condition. The diagram illustrates different signals and operations of the light-to-frequency converter. Figure 4C Depicted in FIG. 1 is the output voltage VOUT of the integrator 120. In addition, an asynchronous count C1 and a time count C2 are shown. The signal is represented as a function of time t. As the signal is acquired for a specific integration time (T_INT), the integration time (T_INT) is shown as a mean value of the reference. Figure 4C As shown in , three integration cycles of C2n are shown to follow an ADC code of 3.

[0101] Figure 4D An exemplary timing diagram 400D shows signals of an exemplary embodiment of an optical sensor device having an ADC code of 4 for the circuit of FIG. 2 operating in a first clipping technique. Specifically, using Figure 3B The first clipping technique of FIG. 400D illustrates the different signals and operations of the light-to-frequency converter. Figure 4D Depicted in FIG. 2 is the output voltage VOUT of the integrator 220. In addition, an asynchronous count C1 and a time count C2 are shown. The signal is represented as a function of time t. As the signal is acquired for a specific integration time (T_INT), the integration time (T_INT) is shown as a mean value of the reference. Figure 4DAs shown in , four integration cycles are shown to follow an ADC code of 4. Figure 4D A first clipping technique is implemented in which a first stage of clipping (Clipping 0) is implemented at the integrator 220 until a halfway point 404 of the integration time (T_INT). The first stage of clipping (Clipping 0) is applied with a first polarity (e.g., a +Ve offset across the input terminals of the first amplifier). Then a second stage of clipping (Clipping 1) is implemented at the integrator 220 at the halfway point 404 without stopping the integration cycle. The second stage of clipping is applied with a second polarity opposite to the first polarity (e.g., a -Ve offset across the input terminals of the first amplifier). Due to the change from the first stage of clipping (Clipping 0) to the second stage of clipping (Clipping 1), there is a small change in the output voltage and the integral slope based on the leakage current, and the small change in the output voltage will introduce dark counts below zero (see circle 402). Also because the second stage of clipping is implemented at the halfway point 404, the time length of the integration period is different. The first two integration periods C2p and the last integration period C2n are respectively different from each other. Figure 4B and 4C However, since the clipping occurs during the third integration period, this integration period can be expressed as:

[0102] (C2p+C2n) / 2.

[0103] Figure 4E An exemplary timing diagram 400E shows signals of an exemplary embodiment of an optical sensor device having an ADC code of 4 for the circuit of FIG. 2 operating in a second clipping technique. Specifically, using Figure 3C Figure 400E shows the different signals and operations of the light-to-frequency converter. Figure 4E Depicted in FIG. 2 is the output voltage VOUT of the integrator 220. In addition, an asynchronous count C1 and a time count C2 are shown. The signal is represented as a function of time t. As the signal is acquired for a specific integration time (T_INT), the integration time (T_INT) is shown as a mean value of the reference. Figure 4E As shown in , four integration cycles are shown to follow an ADC code of 4. Figure 4E A second clipping technique is implemented in which a first stage of clipping (e.g., Clip 0) is implemented at the integrator 220 until the halfway point 404 of the integration time (T_INT). A reset / initialization phase is then implemented, the ADC is reset, and signal acquisition is reinitialized at the halfway point 404, so that the system performs two ambient light sensor measurements: "Measurement 1" and "Measurement 2", as shown in FIG. Figure 4EAs shown in . The second reset / initialization phase stops the integration cycle and changes the polarity of the integrator output. The second stage of clipping (Clipping 1) is then implemented at the integrator 220 during "Measurement 2". Due to the change from the first stage of clipping, to the reset / initialization phase, and then to the second stage of clipping, the output change during the switching on the output signal information when there is a switching of the clipping switch is eliminated (for example, the slope change at the halfway point for the first clipping technique - circle 402). In addition, because the reset / initialization phase changes the polarity of the integrator output, the second stage of clipping (Clipping 1) at the first set of clipping switches and the second set of clipping switches is applied with the same polarity as the first stage of clipping. Moreover, due to the implementation of the reset / initialization phase and the two different stages of clipping, the time length of the integration period is different. The first two integration periods C2p in the first half of the integration time (T_INT) and the first integration period C2n in the second half of the integration time (T_INT) after the reset phase are respectively the same as the first integration period C2n. Figure 4B and 4C However, due to the reset / initialization phase, the last two periods of each measurement cycle are halved and can be expressed as: C2p / 2, C2n / 2 respectively.

[0104] According to some embodiments, changing the polarity of the integrator output from the first polarity to the second polarity includes switching the output of a first set of clipping switches for the input terminals of the first amplifier and switching the output of a second set of clipping switches for the input terminals of the second amplifier. Changing the polarity of the integrator output from the first polarity to the second polarity cancels the offset voltage across the photodiode by switching the input from each set of clipping switches for each input terminal of each amplifier, respectively.

[0105] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any feature or the scope that may be claimed, but rather as descriptions of features specific to a particular embodiment. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. Moreover, although the above features may be described as working in certain combinations, and may even be initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0106] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not necessarily be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed, to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of the various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together into a single software product or packaged into multiple software products.

[0107] Thus, specific embodiments of the present subject matter have been described. In some cases, the actions set forth in the claims may be performed in a different order and still achieve the desired results. Furthermore, the processes described in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing may be advantageous. Thus, other embodiments are within the scope of the following claims.

Claims

1. A sensor device for light-to-frequency conversion, comprising: Photodiode; an analog-to-digital converter (ADC) operable to perform a clipping technique in response to a first clock signal (CLK1) and operable to convert a photocurrent (IPD) generated by the photodiode into a digital comparator output signal (LOUT), the analog-to-digital converter comprising: a sensor input terminal coupled to the photodiode; A result output terminal, used for providing the digital comparator output signal (LOUT); Integrator, including: an integrator input coupled to the sensor input and operable to receive an integrator input signal; a first amplifier and a second amplifier; a first set of clipping switches electrically coupled to input terminals of the first amplifier; a second set of chopping switches electrically coupled to the output of the first amplifier and to the input terminal of the second amplifier; and an integrator output terminal, providing an integrator output signal (OPOUT); and a signal processing unit, coupled to the result output of the analog-to-digital converter and configured to determine a digital output signal (ADC-COUNT) from the digital comparator output signal (LOUT), The analog-to-digital converter is operable to perform an initialization phase prior to performing the clipping technique, the initialization phase comprising: Applying a coarse auto-zero operation before the start of the integration time (T_INT) for the integration cycle; and A first reset / initialization phase is applied at the beginning of the integration time (T_INT) for the integration cycle, which resets the analog-to-digital converter and initializes the signal acquisition.

2. The sensor device of claim 1 , wherein the analog-to-digital converter is operable to perform a first clipping technique after performing an initial phase, the first clipping technique comprising: applying a first stage of clipping at a first set of clipping switches and a second set of clipping switches, wherein the first stage of clipping is applied in a first polarity; as well as A second stage of clipping is applied at the first set of clipping switches and the second set of clipping switches at a halfway timestamp and without stopping the integration cycle, wherein the halfway timestamp indicates a halfway point of the integration time (T_INT), wherein the second stage of clipping is applied with a second polarity, wherein the second polarity is opposite to the first polarity.

3. The sensor device of claim 1 , wherein the analog-to-digital converter is operable to perform a second clipping technique after performing the initial phase, the second clipping technique comprising: applying a first stage of clipping at the first set of clipping switches and the second set of clipping switches at a halfway timestamp indicating a halfway point of an integration time (T_INT) for the integration cycle, wherein the first stage of clipping is applied with a first polarity; applying a second reset / initialization phase that resets the analog-to-digital converter and reinitializes signal acquisition at a halfway point of the integration time (T_INT) for the integration cycle, wherein the second reset / initialization phase stops the integration cycle and changes the polarity of the integrator output; as well as A second phase of clipping is applied at the first set of clipping switches and the second set of clipping switches after the second reset / initialization phase, wherein the second phase of clipping is applied with the first polarity.

4. The sensor device of claim 3, wherein changing the polarity of the integrator output comprises: switching outputs of a first set of clipping switches for input terminals of the first amplifier; as well as The output of the second set of clipping switches is switched for the input terminal of the second amplifier.

5. The sensor device according to claim 1, wherein the signal processing unit comprises: a first counter having a first clock input coupled to the result output and including a first reset input; A second counter including a second clock input terminal and a second reset input terminal; as well as a logic / computation engine including a computation input coupled to a first counter output of the first counter and a second counter output of the second counter; in: The first counter is operable to receive a first clock signal (CLK1) at the first clock input and to generate an asynchronous count (C1) dependent on the first clock signal (CLK1); The second counter is operable to receive a second clock signal (CLK2) at the second clock input and to generate a time count (C2) dependent on the second clock signal (CLK2); and The logic / computation engine is operable to receive the asynchronous count (C1) and the time count (C2) and calculate the digital output signal (ADC-COUNT) from the asynchronous count (C1) and the time count (C2).

6. The sensor device of claim 1, further comprising a latching comparator operable to receive the integrator output signal (OPOUT) and provide the digital comparator output signal (LOUT).

7. The sensor device of claim 1, further comprising a digital control circuit operable to control each switch to switch between an open state and a closed state depending on a clock cycle.

8. A sensor device as claimed in claim 1, wherein the digital output signal (ADC-COUNT) includes an asynchronous count (C1) and a time count (C2), the asynchronous count (C1) including an integer number of counts depending on the first clock signal (CLK1), and the time count (C2) depending on the second clock signal (CLK2).

9. The sensor device of claim 1, wherein the digital output signal (ADC-COUNT) is indicative of a photocurrent generated by the photodiode.

10. The sensor device of claim 1, the signal processing unit being configured to determine an average integration period indicative of a modulation in the digital comparator output signal (LOUT) based on a time count.

11. A method for light-to-frequency conversion, comprising: The photocurrent (IPD) is generated by the offset voltage across the photodiode. The photocurrent (IPD) is converted into a digital comparator output signal (LOUT) by an analog-to-digital converter (ADC) and depending on a first clock signal (CLK1) based on a clipping technique performed during an integration cycle, wherein the analog-to-digital converter comprises an integrator comprising: a first set of clipping switches electrically coupled to the input terminals of the first amplifier; a second set of chopping switches electrically coupled to the output of the first amplifier and to an input terminal of a second amplifier; and An integrator output terminal provides an integrator output signal (OPOUT); determining an asynchronous count (C1) comprising an integer number of counts dependent on a first clock signal (CLK1) based on the digital comparator output signal (LOUT); determining a time count (C2) dependent on a second clock signal (CLK2) based on the digital comparator output signal (LOUT); calculating a digital output signal (ADC-COUNT) indicative of a photocurrent generated by the photodiode based on the asynchronous count (C1) and the time count (C2), and Perform an initial phase before performing the wave-canceling technique, including: applying a coarse auto-zero operation before the integration time (T_INT) for the integration cycle begins; and A first reset / initialization phase is applied at the beginning of the integration time (T_INT) for the integration cycle, which resets the analog-to-digital converter and initializes the signal acquisition.

12. The method of claim 11, wherein converting the photocurrent based on a clipping technique cancels an offset voltage across the photodiode.

13. The method of claim 11, wherein: After performing the initial stage, the wave clipping technique includes a first wave clipping technique, wherein the first wave clipping technique includes: applying a first stage of clipping at the first set of clipping switches and the second set of clipping switches, wherein the first stage of clipping is applied in a first polarity; and A second stage of clipping is applied at the first set of clipping switches and the second set of clipping switches at a halfway timestamp and without stopping the integration cycle, wherein the halfway timestamp indicates a halfway point of the integration time (T_INT), wherein the second stage of clipping is applied with a second polarity, wherein the second polarity is opposite to the first polarity.

14. The method of claim 11, wherein: After performing the initial stage, the wave clipping technique includes a second wave clipping technique, wherein the second wave clipping technique includes: applying a first stage of clipping at the first set of clipping switches and the second set of clipping switches at a halfway timestamp indicating a halfway point of an integration time (T_INT) for the integration cycle, wherein the first stage of clipping is applied with a first polarity; applying a second reset / initialization phase that resets the analog-to-digital converter and reinitializes signal acquisition at a midpoint of the integration time (T_INT) for the integration cycle, wherein the second reset / initialization phase stops the integration cycle and changes the polarity of the integrator output; and A second phase of clipping is applied at the first set of clipping switches and the second set of clipping switches after the second reset / initialization phase, wherein the second phase of clipping is applied with the first polarity.

15. The method of claim 14, wherein changing the polarity of the integrator output from a first polarity to a second polarity comprises: switching outputs of a first set of clipping switches for input terminals of the first amplifier; as well as The output of the second set of clipping switches is switched for the input terminal of the second amplifier.

16. The method of claim 15, wherein changing the polarity of the integrator output from a first polarity to a second polarity by switching the input from each set of chopper switches for each input terminal of each amplifier, respectively, cancels the offset voltage across the photodiode.

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