Transistor structure and method for forming the same

Abstract

The present disclosure relates to transistor structures and methods of forming the same. One embodiment transistor includes: a semiconductor drain region defined by a first trench, and a first conductive element in the first trench, the first conductive element being electrically coupled to a node of application of a potential that is closer to a drain potential of the transistor than to a source potential of the transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of French patent application No. 2000669 filed on January 23, 2020, the contents of which are hereby incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic devices and methods, and more particularly, to transistors and methods of forming the same. Background Art

[0004] In certain electronic devices, field effect transistors are used to hold a high voltage in a non-conducting state (typically greater than 10 V, such as about 40 V, or even greater than 100 V). The smaller the transistor is and / or the higher the voltage it holds in the non-conducting state, the higher the resistance of the transistor in the conducting state. Summary of the invention

[0005] In transistors, there is a need to improve the trade-off between state resistance in the conducting state, size, and voltage maintained in the non-conducting state.

[0006] One embodiment overcomes all or part of the disadvantages of known transistors.

[0007] One embodiment enables reducing the resistance in the conductive state, and / or reducing the surface area occupied, and / or increasing the voltage held.

[0008] One embodiment provides a transistor comprising: a semiconductor drain region defined by a first trench, and a first conductive element in the first trench, the first conductive element being electrically coupled to a node applying a potential that is closer to a drain potential of the transistor than to a source potential of the transistor.

[0009] According to one embodiment, a transistor includes a gate located in a second trench, the second trench being co-linear with the first trench.

[0010] According to an embodiment, the transistor comprises an insulating region between the gate and the first conductive element, the insulating region having a thickness greater than a thickness of a gate insulator of the transistor, and preferably the transistor comprises a portion of a semiconductor drain region between the gate and the first conductive element.

[0011] According to one embodiment, the transistor includes a second conductive element located in the second trench.

[0012] According to one embodiment, a first trench extends in the substrate from a surface of the substrate, and a drain contact region of the transistor and a channel formation region of the transistor are located on the surface side of the substrate.

[0013] According to one embodiment, the channel formation region is electrically coupled to a node to which a source potential of the transistor is applied.

[0014] According to one embodiment, the transistor includes a semiconductor source region defined by the second trench, and the semiconductor source region is in contact with the channel formation region on an opposite side of the channel formation region from the semiconductor drain region.

[0015] According to one embodiment, the first trench extends in a region of the substrate partially beneath the semiconductor drain region.

[0016] According to one embodiment, the channel formation region is part of the region of the substrate.

[0017] According to one embodiment, the region of the substrate is insulated from another region of the substrate situated below the buried well by a buried well, the buried well preferably being situated entirely at a depth greater than the depth of the bottom of the first trench.

[0018] According to one embodiment, on a side opposite to the first trench side, the semiconductor drain region is bounded by an additional trench, and the additional conductive element is located in the additional trench.

[0019] According to one embodiment, an end of the first trench and an end of the additional trench are aligned in a trench width direction.

[0020] According to an embodiment, the semiconductor drain region has a doping level that decreases from the contact region in a direction parallel to the first trench.

[0021] One embodiment provides an electronic device comprising one or more transistors as defined above.

[0022] According to one embodiment, the device is monolithic and further comprises a CMOS type transistor and / or a vertical transistor comprising a trench having the same depth as the first trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above-described and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings.

[0024] Figure 1 A top view of one embodiment of a device including a transistor is partially and schematically shown. Figure 1 A and cross-sectional view Figure 1 B, 1C, 1D, and 1E;

[0025] Figure 2 Partially and schematically shown Figure 1 A perspective view of the device;

[0026] Figure 3 Partially and schematically illustrates the manufacturing Figure 1 A top view of an example of a method of apparatus and steps Figure 3 A and cross-sectional view Figure 3 B, 3C, 3D and 3E; and

[0027] Figure 4 A top view partially and schematically showing another step of the method Figure 4 A and cross-sectional view Figure 4 B, 4C, 4D and 4E. DETAILED DESCRIPTION

[0028] In different drawings, the same elements are designated by the same reference numerals. In particular, the common structural and / or functional elements of different embodiments may be designated by the same reference numerals and may have exactly the same structure, size and material properties.

[0029] For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, mask making steps, doping steps and steps for making terminals electrically connected to doped regions are not described in detail, the described embodiments being compatible with such conventional steps.

[0030] Throughout this disclosure, the term “connected” is used to designate a direct electrical connection between circuit elements, while the term “coupled” is used to designate an electrical connection between circuit elements that may be direct or may be via one or more other elements.

[0031] In the following description, when terms that modify absolute positions (such as terms "top", "bottom", "left", "right", etc.), or terms that modify relative positions (such as terms "above", "below", "upper", "lower", etc.), or terms that modify directions (such as terms "horizontal", "vertical", etc.) are mentioned, it refers to the orientation of the cross-sectional view.

[0032] The terms "approximately," "approximately," "substantially," and "about" are used herein to designate a tolerance of plus or minus 10% (preferably plus or minus 5%) of the value in question.

[0033] Unless otherwise specified, ordinal numbers (such as "first", "second", etc.) are only used to distinguish elements from each other. In particular, these adjectives do not limit the described embodiments to the specific order of these elements.

[0034] Figure 1 A top view of one embodiment of a device 100 including a transistor is partially and schematically shown. Figure 1 A and cross-sectional view Figure 1 B, 1C, 1D and 1E. Cross-sectional view Figure 1B, 1C, 1D and 1E have planes BB, CC, DD and EE as corresponding cross-sectional planes. Figure 1 A, 1B and 1C correspond to each other in the vertical direction of the drawing and are viewed as Figure 1 B and 1C, 1D and 1E correspond to each other in the horizontal direction of the drawings. Figure 2 A simplified partial perspective view of the device 100 is shown. In particular, Figure 2 The electrical insulator, semiconductor substrate and buried well are not shown.

[0035] The device 100 typically comprises an electronic integrated circuit chip defined by a semiconductor substrate 102 and elements (such as electronic components) located inside and on top of the substrate 102. The device 100 is preferably monolithic. A monolithic device means that all circuits of the device are integrated inside and on top of the same substrate or support, typically inside and on top of the same semiconductor wafer portion. Such a monolithic device or integrated circuit is preferably located in an integrated circuit package. An integrated circuit package means an assembly that has connection areas or connection pins to the electronic circuit external to, coming out of, a circuit (e.g., a printed circuit board PCB).

[0036] In one example, the substrate 102 is formed by a portion of a semiconductor wafer (e.g., a silicon wafer). In another example, the substrate 102 is formed by a layer located on a surface of the semiconductor wafer portion (e.g., an epitaxial layer on a semiconductor wafer). Preferably, the substrate 102 is a single crystal substrate. As an example, the substrate 102 is N-type doped, for example, with a doping level ranging from 2*10 16 Up to 4*10 16 Atom / cm 3 In the described embodiment, the N and P conductivity types or doping types may be swapped. Operations similar to those described are then obtained by swapping the voltage signs in the device 100.

[0037] Among the electronic components, the device 100 includes one or more transistors. In particular, the device 100 includes a transistor T110 or a plurality of transistors T110 electrically connected in parallel. The transistors T110 are preferably of the same type, for example, similar or identical within manufacturing tolerances. Figure 1 and Figure 2 In the example of an N-type doped substrate 102 , the transistor T110 preferably has a P-channel, in other words, the transistor T110 has a channel of a conductivity type opposite to that of the substrate 102 .

[0038] The transistor T110 includes a gate 120 and a channel formation region 130 separated by a gate insulator 122. The gate 120 includes at least one electrical conductor (such as, for example, metal and / or doped polysilicon). The gate insulator 122 contacts the channel formation region 130 and at least one electrical conductor of the gate 120. The gate insulator 122 is generally formed of one or more dielectric layers, for example, the gate insulator is formed of a silicon oxide layer. The thickness of the gate insulator 122 is generally less than 15 nm, preferably in the range of from 5 nm to 40 nm.

[0039] On one side of the channel formation region 130, the transistor T110 includes a semiconductor region 140 that is doped of P type in this example. The semiconductor region 140 is in contact with the channel formation region 130. For example, the semiconductor region 140 is produced by one or more doping steps on a portion of the substrate 102. The semiconductor region 140 is in contact with a more heavily doped contact region 142 of the same type as the region 140. The contact region 142 forms a region that is in electrical contact with the doped semiconductor region 140. More precisely, the contact region 142 forms an electrical connection between the doped semiconductor region 140 and a conductor that defines a drain terminal 145 of the transistor T110. The semiconductor region 140 is then referred to as a drain region.

[0040] On the side of the channel formation region 130 opposite to the drain region 140, the transistor T110 includes a doped semiconductor region 150 of the same conductivity type (here P-type) as the drain region 140. The semiconductor region 150 is in contact with the channel formation region 130. For example, the semiconductor region 150 is produced by one or more doping steps on a portion of the substrate 102. The semiconductor region 150 is in contact with a more heavily doped contact region 152 of the same type as the region 150. The contact region 152 forms a region in electrical contact with the semiconductor region 150. More precisely, the contact region 152 forms an electrical connection between the doped semiconductor region 150 and a conductor 155, which defines the source terminal of the transistor T110. The semiconductor region 150 is then referred to as a source region.

[0041] The transistor T110 defined by the above elements thus forms a field effect transistor, ie, an electronic element capable of forming a conductive channel in a channel formation region according to a control voltage applied between the gate 120 and the source terminal 155 , the conductive channel electrically connecting the drain region and the source region.

[0042] Preferably, the contact regions 142 and 152 are formed of a layer of the substrate 102 having a high doping level (ie, greater than 5*10 18 Atom / cm 3 , preferably greater than 10 19 Atom / cm 3The doping level of the channel formation region 130 is preferably less than 2*10 16 Atom / cm 3 , more preferably less than 5*10 15 Atom / cm 3 Preferably, the drain region 140 and the source region 150 have a low doping level, i.e., less than 2*10 17 Atom / cm 3 However, the doping level is preferably greater than 5*10 16 Atom / cm 3 .

[0043] In the depicted embodiment, transistor T110 further comprises a first trench 160. Trench 160 extends in substrate 102 from surface 104, which is referred to as the front surface (see FIG. 1 ) of substrate 102. Figure 1 The front surface and the visual field in the orientation of A Figure 1 B to 1E). Preferably, the depth of the trench 160 is in the range from 2 μm to 3 μm. Preferably, the trench 160 delimits part of the drain region 140, i.e., at least a part of the edge of the drain region 140 is formed by a part of the wall of the trench 160. In the example shown, the trench 160 completely delimits the drain region 140. Preferably, the trench 160 extends parallel to the front surface 104 in the main direction or longitudinal direction of the trench. As an example, in the lateral direction parallel to the front surface 104, the trench 160 has a constant width in the range from 100 nm to 500 nm.

[0044] Preferably, at least a portion of the drain region 140 extends from the drain contact region 142 to the channel formation region 130 in parallel with the edge of the first trench 160. This portion of the drain region 140 is called a drift region. As an example, the distance separating the channel formation region 130 from the contact region 142 is in the range of 1 μm to 5 μm, preferably in the range of 2 μm to 4 μm.

[0045] In the non-conductive state of the transistor T110, the drift region maintains a high voltage such as mentioned above between the channel formation region 130 and the contact region 142 due to its low doping level. In the conductive state of the transistor T110, the current flowing through the transistor T110 flows through the drift region, from the channel formation region 130 to the contact region 142.

[0046] The transistor T110 further comprises a first conductive element 170 located in the first trench 160. The conductive element 170 is positioned opposite to at least a portion of the drain region 140, i.e., at least a portion of the conductive element 170 is located in a portion of the trench 160 that defines at least a portion of the drain region 140. More precisely, the conductive element 170 is positioned opposite to at least a portion of the drift region. Preferably, the conductive element 170 is positioned against an electrical insulating layer 172 that is located in the trench 160 against at least a portion of the drain region 140, in particular against at least a portion of the drift region. Then, the insulating layer 172 separates the conductive element 170 from the drift region. The distance between the conductive element 170 and the drain region 140 (equal to the thickness of the insulating layer 172) is, for example, in the range from 100 nm to 210 nm, preferably in the range from 120 nm to 180 nm. The thickness of the insulating layer 172 is preferably greater than the thickness of the gate insulator 122. As an example, the insulating layer 172 is made of silicon oxide or silicon nitride.

[0047] Preferably, the first conductive element 170 is formed by a conductive wall located in the central part of the first trench 160. The wall is elongated in the same direction as the trench 160. The wall extends in the substrate 102 orthogonally to the front surface 104. As an example, the wall comprises, preferably is made of, a metallic material or preferably doped polysilicon. The width of the conductive wall taken in the width direction of the trench 160 is, for example, in the range from 30 nm to 210 nm.

[0048] The first conductive element 170 is electrically coupled (preferably electrically connected) to a node to which a potential is applied that is closer to the drain potential of the transistor T110 than to the source potential of the transistor T110. Preferably, the potential applied to the node is approximately equal to (more preferably equal to) the drain potential. Even more preferably, the node is defined by the drain terminal 145. In other words, the transistor T110 then includes an electrical coupling 175 (preferably an electrical connection) between the conductive element 170 and the drain terminal 145.

[0049] Thus, in operation, the conductive element 170 is biased to a potential closer to the drain potential of the transistor T110 than to the source potential of the transistor T110. In the example where the transistor T110 has a P-channel, the potential applied to the conductive element 170 is preferably less than or equal to the potential of the drain. In this example, for source, drain, and gate potentials that are positive relative to a reference potential (such as ground potential), the conductive element 170 may be optionally coupled or connected to ground instead of being connected to the drain terminal 145.

[0050] In the non-conductive state of the transistor T110, the first conductive element 170 shields part of the electric field generated due to the voltage between the channel formation region 130 and the contact region 142. Therefore, the electric field in the drift region is lower than the electric field in the case where the conductive element 170 is not provided. Relative to a transistor that does not include the conductive element 170, this makes it possible to increase the doping level of the drift region, and thus increase the conductivity type of the drift region in the conductive state, without reducing the maximum voltage that the transistor can hold. Therefore, the trade-off between the conductivity of the transistor in the conductive state and the maximum voltage that the transistor can hold is improved.

[0051] According to one embodiment, the drain contact region 142 and the channel formation region 130 and preferably the source contact region 152 are located on the front surface 104 side, i.e., they each have a surface on the front surface side that is not covered by part of the substrate. Preferably, the channel formation region 130 may be in electrical contact with a contact region (not shown) that forms an electrical connection between the channel formation region 130 and the terminal 135. The terminals 135, 145 and 155 may be defined by a conductor located on the contact region, such as a through hole that passes through an insulating layer (not shown) covering the device 100. Then, compared to the example in which the contact region 142 is located on the rear surface side (the surface of the substrate 102 opposite to the front surface 104), a connection that enables the transistor T110 to be electrically coupled to other components of the device or to an external device is easier to form.

[0052] Preferably, the source contact region 152 is electrically coupled (preferably connected) to the channel forming region 130. More preferably, this is obtained by coupling (preferably connecting) between the terminals 155 and 135. As a result, the formation of a conductive channel between the drain region 140 and the source region 150 is based on the voltage between the source terminal 155 and the gate 120 of the transistor T110.

[0053] According to one embodiment, drain region 140 is located on region 180 of substrate 102. Region 180 preferably has the same doping type (here N-type) as substrate 102, and before forming doped drain region 140 and source region 150 and contact regions 142 and 152, region 180 has the same doping level as the doping level of substrate 102. In other words, region 180 is then a portion of substrate 102 that is not doped or intentionally doped after substrate 102 is formed.

[0054] In particular, in the case where the transistor T110 has a channel of a conductivity type opposite to that of the substrate 102, the region 180 is partially located below the drain region 140. In this case, preferably, the region 180 also includes the channel formation region 130. In a variant, the transistor T110 may be formed with a channel of a conductivity type opposite to that of the substrate 102 inside and on top of a doped region that extends deeper than the transistor T110 in the substrate 102 and has a conductivity type opposite to that of the substrate 102. Compared to this variant, the fact that the region 180 includes the channel formation region 130 makes it easier to obtain the channel region and the drain region, in particular the desired doping level of the channel region.

[0055] According to one embodiment, first trench 160 extends from front surface 104 downward to a depth greater than the depth of drain region 140. For example, drain region 140 extends from front surface 104 downward to a depth in the range from 0.5 μm to 1 μm. The depth of trench 160 is, for example, 1 μm to 2 μm greater than the depth of drain region 140. More specifically, trench 160 extends in region 180.

[0056] It can be designed to form a transistor on a substrate (such as substrate 102) having a channel with a conductivity type opposite to that of the substrate without providing a conductive element (such as conductive element 170). Compared with such a transistor, the fact that a conductive element 170 coupled to a node to which a potential is applied (the potential is closer to the potential of the drain, rather than closer to the potential of the source) is provided makes it possible to limit the electric field borne by the PN junction between the drain region 140 and the region 180 of the substrate 102 in the non-conductive state of the transistor T110. More specifically, the conductive element 170 is biased to a potential substantially equal to (preferably equal to) the drain potential, so that the electric field borne by the PN junction can be minimized. This increases the maximum voltage that the transistor T110 can maintain.

[0057] In order to increase the maximum voltage that the transistor can hold, it can be designed to reduce the doping level of its drain region. However, this will increase the resistance of the drift region, and therefore increase the resistance of the transistor in the conductive state. The conductive element 170 biased to a potential closer to the drain potential rather than closer to the source potential enables the maximum voltage held by the transistor T110 to be increased without reducing the doping level of the drift region, and therefore does not increase the resistance of the transistor in the conductive state.

[0058] Thus, a transistor can be provided that does not include a conductive element (such as conductive element 170), or includes a conductive element similar to conductive element 170 but biased to a potential relatively close to the source potential (e.g., biased to the source potential). Compared to such a transistor, the fact that conductive element 170 is provided that is biased to a potential relatively close to the drain potential (e.g., biased to the drain potential) improves the trade-off between the conductivity of the transistor in the conductive state and the maximum voltage that the transistor can sustain.

[0059] According to one embodiment, the drain region 140 is delimited by an additional trench 160A on the side opposite to the first trench 160. The drain region 140 is then located between the trench 160 and the trench 160A. The additional trench 160A is parallel to the first trench 160, i.e. the trench 160 and the trench 160A have the same direction of elongation. More preferably, the additional trench 160A comprises the same elements as the first trench 160, arranged symmetrically with respect to the drain region 140, i.e. an additional conductive element 170A symmetrical to the first conductive element 170, which is positioned opposite to at least a portion of the drift region and is separated from the drain region 140 by the insulating layer 172A. Therefore, preferably, both conductive elements 170 and 170A penetrate into the region 180 of the substrate 102. The additional conductive element 170A is also coupled (preferably connected) to a node (e.g. the drain terminal 145) to which a drain potential is applied.

[0060] The additional conductive element 170A provides an additional improvement in the trade-off between the conductivity of the transistor in the conductive state and the maximum voltage that the transistor can sustain.

[0061] In the example of the additional groove 160A described above, the end of the additional groove 160A is aligned with the end of the first groove 160 in the groove width direction. Figure 1 In a variation shown by a dotted line 165 in FIG. 1A , the additional trench 160A may extend further than the first trench 160 from a portion thereof positioned opposite to the contact region 142 and toward the channel formation region 130. For example, the additional trench 160A defines the entire edge of the drain region 140 opposite to the first trench 160. In a variation, the first trench 160 is omitted, and only the additional trench 160A is provided.

[0062] According to one embodiment, the gate 120 is located inside the second groove 190. Preferably, the grooves 160 and 190 are collinear in the same elongated direction. More preferably, the grooves 160 and 190 have the same width and the same depth. Preferably, the gate 120 has a shape elongated in the longitudinal direction of the groove 190. Preferably, the gate 120 is located in the groove 190, on the side of the front surface 104 (i.e., on the side of the viewing surface 104). Figure 1B, 1C, 1D and 1E). For example, the gate 120 is flush with the front surface 104 of the substrate 102.

[0063] Thus, the second trench 190 delimits a channel formation region 130. More precisely, the channel formation region then has a lateral surface formed by a portion of the walls of the trench 190. The gate insulator 122 covers this portion of the walls of the trench 190. The channel formation region 130 preferably corresponds to a portion of the region 180 of the substrate 102 that is located opposite the gate 120.

[0064] Due to the fact that the gate 120 is in the second trench 190, the conductive channel formed in the conductive state is positioned against the wall of the trench 190. Compared with a variant in which the gate 120 is arranged on the channel formation region 130 (e.g., resting on the front surface 104), it is avoided that the conductive channel has the width of the trench 190. The trench width can then be reduced without reducing the width of the conductive channel and therefore without increasing the resistance of the transistor in the conductive state. Therefore, for the same current and the same conductive state resistance, the surface area occupied by the transistor T110 is smaller than the surface area of ​​the transistor whose gate is located on the channel region.

[0065] According to one embodiment, the transistor T110 includes an insulating region 200 between the gate 120 and the first conductive element 170. In the longitudinal direction of the trench 190, the thickness of the insulating region 200 is greater than the thickness of the gate insulator 122. For example, the thickness of the insulating region 200 is equal to the thickness of the insulating layer 172 covering the wall of the first trench 160. In the example shown, the insulating region 200 is formed by a portion of the insulating layer 204 covering the wall of the second trench 190. The insulating layer 204 of the second trench 190 may have the same thickness as the insulating layer 172 of the first trench 160, and may be made of the same material as the insulating layer 172.

[0066] When the transistor T110 is in a non-conductive state, the voltage between the gate 120 and the drain terminal 145 ends between the gate 120 and the first conductive element 170. The insulating region 200, which has a thickness greater than the thickness of the gate insulator 122 and is located between the gate 120 and the first conductive element 170, avoids the risk of breakdown of an insulator having a thickness, for example, of about the thickness of the gate insulator 122. For this reason, the thickness of the insulating region 200 is provided to withstand the high voltage defined above. For example, the thickness is in the range from 100 nm to 210 nm, preferably in the range from 120 nm to 180 nm. As an example, the insulating region 200 and preferably the insulating layer 204 are made of silicon oxide or silicon nitride.

[0067] Preferably, between the gate 120 and the first conductive element 170, a semiconductor region 202 is further provided which is doped P-type in the example shown. In other words, the semiconductor region 202 has the same conductivity type as the drain region 140. The semiconductor region 202 can be obtained in the same doping step as the drain region 140 and can have the same doping level. In other words, the semiconductor region 202 then forms part of the drain region 140. In the non-conductive state of the transistor, the semiconductor region 202 is depleted and therefore participates in the electrical insulation between the gate 120 and the first conductive element 170.

[0068] More preferably, between the gate 120 and the first conductive element 170, another insulating region 206 is also provided, more preferably, the other insulating region 206 is formed by a portion of the insulating layer 172 covering the wall of the first trench 160. In a variant, the trenches 160 and 190 are two parts of the same trench, and the insulating region 200 is an insulating element located in the trench. However, compared to this variant, the fact that two insulating regions 200 and 206 covering the walls of two different trenches 160 and 190 are provided makes it easy to form electrical insulation.

[0069] According to one embodiment, the drain region 140 has a doping level that is reduced from the contact region 142. In the example shown, the drain region 140 includes two sub-regions 140-1 and 140-2 (only in Figure 2 The sub-region 140-1 is in contact with the channel formation region.

[0070] In a preferred example, the subregion 140-2 separates the subregion 140-1 from the contact region 142. The subregion 140-2 extends from the contact region 142, for example, is located below and around the contact region 142. A portion of the subregion 140-2 extends from the contact region 142 toward the channel formation region 130 over a distance, for example, in the range from one-third to two-thirds of the distance between the contact region 142 and the channel formation region 130 (preferably substantially half of the distance between the contact region 142 and the channel formation region 130). The portion of the subregion 140-2 extends from the contact region 142 over a distance, for example, in the range from 0.5 μm to 1.5 μm, preferably about 1 μm. The doping level of the subregion 140-2 is in the range from the doping level of the region 140-1 to the doping level of the contact region 142. The doping level of the subregion 140-2 may be in the range from 10 17 Atom / cm 3 Up to 10 18 Atom / cm 3 within the range.

[0071] This preferred example is not restrictive, and the drain region 140 may include or be formed of a number N of semiconductor sub-regions 140-i, with the index i ranging from 1 to N. The sub-regions 140-N extend from the contact region 142. The sub-regions are placed according to the index i decreasing from the contact region 142, the doping level of the sub-region 140-i being an increasing function of the index i. As a variant, the semiconductor region 140 may have a doping level gradient from the contact region 142.

[0072] For i different from 1, the sub-region 140-i or the sub-region with the doping gradient forms a region with a doping level between the doping level of the sub-region 140-1 and the doping level of the contact region 142. The fact that the doping level of the drain region 140 is reduced from the contact region 142 provides an additional improvement in the trade-off between the conduction state conductivity of the transistor and the maximum voltage that the transistor can sustain.

[0073] According to one embodiment, the second trench 190 extends towards the source region 150 and delimits at least a portion of the source region 150. The transistor T110 then comprises a second conductive element 210 in the trench 190, the second conductive element 210 being positioned opposite to at least a portion of the source region 150. The second conductive element 210 is separated from the wall of the trench 190 by the insulating layer 204. The second conductive element 210 is preferably co-linear with the first conductive element 170. More preferably, in a plane orthogonal to the plane of the trench 190 and over at least a portion of the length of the trench 190, the second conductive element 210 has a cross section of the same shape and size as that of the cross section of the first conductive element 170. In the case where the gate 120 is located in the trench 190, the second conductive element 210 is preferably located partially below the gate 120. In this case, the conductive element 210 and the gate 120 are preferably separated by an insulator 212. The thickness of the insulator 212 is then preferably equal to or substantially equal to the thickness of the gate insulator 122.

[0074] Preferably, the second conductive element 210 further includes a portion 214 located between the gate 120 and the insulating region 200. Compared with a variant in which this portion is omitted, this enables various problems of aligning the gate 120 with the edge of the insulating region 200 to be solved when the gate 120 is formed after the insulating region 200. For example, when according to the following description Figure 3 and Figure 4 The described method avoids this alignment problem when forming transistor T110.

[0075] According to one advantage, a transistor (not shown) called a vertical transistor can be further provided in the device 100. In such a transistor, in the conductive state, the current flows vertically (i.e., orthogonally to the front surface of the substrate) between the channel formation region located on the front surface side and the drain contact region located on the rear surface. The vertical transistor may include a trench including a conductive element that is intended to shield the electric field in the drift region when the vertical transistor is in a non-conductive state. Preferably, the depth of the trench of the vertical transistor is the same as the first trench 160 and the possible second trench 190. Preferably, the trench of the vertical transistor is repeated at the same pitch as the pitch separating the first trench 160 from the additional trench 160A. Preferably, the trench of the vertical transistor has the same direction as the trench of the transistor T110. In order to obtain the transistor T110 and the vertical transistor in the same device, then, the steps of manufacturing the transistor T110 and the vertical transistor can be performed simultaneously. Then, the device including both the vertical transistor and the transistor such as the transistor T110 on the same substrate or the same semiconductor wafer is particularly simple to manufacture.

[0076] According to one embodiment, in addition to the transistor T110, the device 100 further comprises a transistor T112 which, within manufacturing tolerances, is symmetrical to the transistor T110 with respect to the first trench 160. The first trench 160 and the first conductive element 170 are then shared by the two transistors T110 and T112. The gate 120 may also be shared by the two transistors T110 and T112, and the element between the shared gate 120 and the first conductive element 170 may also be shared by the two transistors T110 and T112. A possible second trench 190 and a second conductive element 210 may also be shared by the two transistors T110 and T112.

[0077] According to one embodiment, the device 100 includes a well 220, which is buried in the substrate 102. In other words, the buried well 220 has a conductivity type (here P-type) opposite to the conductivity type of the substrate 102 (here N-type), and is located below the region 108 of the substrate 102 and on another region of the substrate 102. A doped region 222 of the same conductivity type as the buried well 220 extends from the periphery of the buried well 220 all the way to the front surface 104. Only one side of the doped region 222 is shown. The doped region 222 and the buried well 220 can be biased together. In the case where the substrate 102 is N-type, the bias potential of the buried well 220 and the doped region 222 is less than the bias potential of the region 180 of the substrate 102. For example, the doped region 222 and the buried well 220 are biased to a potential less than or equal to the drain potential, preferably to a ground potential. The doped region 222 and the buried well 220 thus make it possible to electrically insulate the region 180 from the rest of the substrate 102. The transistor T110 is then insulated from the other components of the device 100, for example from the other transistors.

[0078] Thus, according to one advantage, a complementary metal oxide semiconductor CMOS type transistor can further be provided in the device 100. It should be noted that the metal oxide semiconductor MOS type, at the origin of the name, was used to designate a transistor having a metal gate and an oxide gate insulator. However, due to the development of this type of transistor, the MOS type is now understood to cover a field effect transistor whose gate is made of any electrical conductor and whose gate insulator is made of any dielectric or electrical insulator. The manufacture of the transistor T110 may include steps common to the manufacture of CMOS transistors. In particular, the doped drain region 140 and the source region 150 and the contact regions 142 and 152 may be formed simultaneously with the doped regions and contact regions of the CMOS transistor. The buried well 220 may also be formed simultaneously with possible other wells buried under the CMOS transistor.

[0079] Preferably, the trench of transistor T110 does not reach buried well 220. Thus, the risk of creating a conductive channel in region 180 along the surface of first trench 160 opposite first conductive element 170 is avoided. Such a conductive channel would risk causing parasitic currents between drain region 140 and buried well 220.

[0080] Preferably, the device 100 comprises a plurality of transistors T110 and T112, more preferably a plurality of transistors repeated in an array. Thus, the transistors are repeated in a first direction parallel to the front surface 104 and in a second direction parallel to the front surface 104 and orthogonal to the first direction. A possible buried well 220 is preferably shared by the transistors T110 and / or T112.

[0081] In a preferred example, the drain terminals 145 of the transistors T110 and T112 of the array are interconnected, the source terminals 155 of the transistors T110 and T112 of the array are interconnected, and the gates 120 common to each pair of transistors T110 / T112 of the array are interconnected. Thus, the transistors T110 and / or T112 are electrically connected in parallel and controlled in parallel, which enables high currents to be conducted through the parallel association of the transistors, i.e., high currents greater than 1 A, for example greater than 5 A, or even greater than 50 A. This association corresponds to a transistor formed by the elementary transistors T110 and / or T112.

[0082] The transistor formed by the elementary transistors T110 and / or T112 thus enables a high current to flow and, as mentioned, enables an improvement in the trade-off between maximum holding voltage and resistance in the conducting state.

[0083] Figure 3 and Figure 4 Partially and schematically illustrates the manufacturing Figure 1 An example of the method of the device 100 includes the following steps. More specifically, Figure 3 Shows the top view at the same step Figure 3 A and cross-sectional view Figure 3 B, 3C, 3D and 3E, and Figure 4 A top view of another step is shown. Figure 4 A and cross-sectional view Figure 4 B, 4C, 4D and 4E. The cross-sectional planes are Figure 1 The cross-sectional planes are the same.

[0084] exist Figure 3 At the step of providing the substrate 102. Optionally, a buried well 220 is formed under the region 180. The buried well 220 may be formed at this step or at a subsequent step of the method.

[0085] The trenches 160, 160A and 190 are then etched in the substrate 102, preferably to a level in the substrate 102 where the depth is less than the buried well 220. Thereafter, an electrically insulating layer 310 is formed on the walls and bottom of the trenches, with portions of the future insulating layers 172, 172A and 204 that will form the future insulating regions 200 and 206, and the corresponding trenches 160, 160A and 190. As an example, the layer 310 is obtained by conformal deposition covering the structures resulting from the etching of the trenches. The insulating layer 310 is preferably made of silicon oxide or silicon nitride. The thickness of the insulating layer 310 is less than the half width of the trenches, so as to leave an unfilled space in the central part of the trenches.

[0086] Then, preferably, the remaining space of the trench is filled with doped polysilicon. This results in the conductive elements 170, 170A and 210 being located in the corresponding trenches. As an example, the entire structure resulting from the deposition of the insulating layer 310 is covered with polysilicon, and the polysilicon located above a given level is removed by etching. The given level is preferably the level of the front surface 104 of the substrate 102, or at a height below 10 nm above the front surface 104 of the substrate 102.

[0087] exist Figure 4 At the step of removing the insulating layer 310 and the conductive material of the second conductive element 210, at the position 420 of the gate 120 and the gate insulator 122, portions of the insulating layer 310 and portions of the conductive material of the second conductive element 210 are removed. Preferably, for this purpose, a mask 460 (shown in dashed lines) has previously been formed, which leaves a passage to a portion 464 of the upper surface of the structure. Preferably, the portion 464 has a stripe shape in a top view, the main direction or direction of elongation of which is orthogonal to the trench length direction. The portion of the conductive material of the second conductive element 210 located in the stripe 464 is selectively etched above the insulating layer 310, up to the upper level of the portion of the conductive element 210 located below the gate 120. During the etching of the conductive material of the second conductive element 210, the insulating layer 310 protects the substrate 102. Then, the accessible portions of the insulating layer 310, in particular those portions made accessible by etching the conductive material of the conductive element 210, are selectively etched above the substrate 102.

[0088] At a subsequent step (not shown), a gate insulator 122 is formed on the walls of the second trench 190 accessible in the strip 464. Preferably simultaneously with the gate insulator 122, an insulator 212 is formed, which is intended to insulate the second conductive element 210 from the future gate 120. This can be obtained by thermal oxidation. The gate 120 is then formed. The regions 140, 142, 150 and 152 can be formed by doping the substrate 102 before or after the above steps.

[0089] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0090] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

Claims

1. A transistor comprising: a semiconductor drain region defined by the first trench; A first conductive element is located in the first trench, wherein the semiconductor drain region surrounds three sides of the first conductive element; as well as A first node is electrically coupled to the first conductive element, the first node being configured to be coupled to a first potential that is closer to a drain potential of the transistor than to a source potential of the transistor. 2 . The transistor of claim 1 , further comprising a gate located in a second trench, the second trench being co-linear with the first trench. 3 . The transistor of claim 2 , further comprising an insulating region between the gate and the first conductive element, the insulating region having a first thickness, the first thickness being greater than a second thickness of a gate insulator of the transistor. The transistor of claim 2 , further comprising a second conductive element located in the second trench. 5 . The transistor according to claim 1 , wherein the first trench extends from a surface of a substrate into the substrate, and wherein a drain contact region of the transistor and a channel formation region of the transistor are located on the surface side of the substrate. 6 . The transistor according to claim 5 , wherein the channel formation region is electrically coupled to a second node configured to be coupled to the source potential of the transistor.

7. The transistor according to claim 5, further comprising: a gate located in a second trench collinear with the first trench; as well as A semiconductor source region is defined by the second trench and is in contact with the channel formation region on a side of the channel formation region opposite to the semiconductor drain region.

8. The transistor of claim 5, wherein the first trench extends into a region of the substrate that is partially beneath the semiconductor drain region. 9 . The transistor according to claim 8 , wherein the channel formation region is part of the region of the substrate.

10. The transistor of claim 8, wherein the region of the substrate is insulated from another region of the substrate below the buried well by a buried well. The transistor of claim 10 , wherein the buried well is entirely located at a depth greater than a depth of a bottom of the first trench. 12 . The transistor of claim 1 , wherein the semiconductor drain region is bounded by an additional trench on a side opposite to the first trench side, and wherein an additional conductive element is located in the additional trench. 13 . The transistor according to claim 12 , wherein an end portion of the first trench and an end portion of the additional trench are aligned in a trench width direction.

14. The transistor of claim 1, wherein the semiconductor drain region has a doping level that decreases from a contact region in a direction parallel to the first trench.

15. An electronic device, comprising: One or more transistors, each of the one or more transistors comprising: a semiconductor drain region defined by the first trench; a first conductive element located in the first trench, wherein the semiconductor drain region surrounds three sides of the first conductive element; and A first node is electrically coupled to the first conductive element, the first node being configured to be coupled to a first potential that is closer to a drain potential of the transistor than to a source potential of the transistor.

16. The electronic device of claim 15, wherein the electronic device is monolithic and further comprises: A transistor of the complementary metal oxide semiconductor (CMOS) type and / or a vertical transistor comprises a trench having the same depth as said first trench.

17. A method of forming a transistor, the method comprising: forming a buried well in a semiconductor substrate; etching a first trench and a second trench in the substrate to a depth shallower than the buried well, the first trench and the second trench being collinear with each other and spaced apart from each other; Conformally depositing an electrically insulating layer on the bottom and sidewalls of the first trench and the second trench and on the surface of the substrate; filling the first trench and the second trench with a conductive material to form a first conductive element and a second conductive element, respectively; etching a portion of the electrically insulating layer and a portion of the electrically conductive material over a segment of the second trench and partially into the segment of the second trench; forming a gate insulator in the section of the second trench on the electrically insulating layer, the conductive material and the sidewalls of the second trench; depositing a gate on the gate insulator in the section of the second trench; doping a first section of the substrate adjacent to the first trench to form a semiconductor drain region, wherein the semiconductor drain region surrounds three sides of the first conductive element; doping a second section of the substrate on a side of the second trench opposite to the first section of the substrate to form a semiconductor source region; forming a first drift region in the semiconductor drain region; as well as The first drift region is electrically coupled to the first conductive element.

18. The method according to claim 17, further comprising: Etching a third trench in the substrate, the third trench being on a side of the semiconductor drain region opposite to the first trench and defining the semiconductor drain region; conformally depositing the electrical insulating layer on the bottom and sidewalls of the third trench; filling the third trench with the conductive material, thereby forming a third conductive element in the third trench; as well as The third conductive element is electrically coupled to the first conductive element.

19. The method of claim 17, further comprising, before etching the portion of the electrically insulating layer and the portion of the electrically conductive material: A mask is formed, the mask having an opening exposing the section of the second trench, the opening of the mask having a stripe shape, an elongated direction of the stripe being orthogonal to the collinear first trench and the second trench.

20. The method of claim 17, further comprising forming a second drift region in the semiconductor source region.

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