Time digital conversion device and optical ranging sensor

Abstract

The present application provides a time-to-digital conversion device and an optical ranging sensor. The time-to-digital conversion device includes a clock network module, a fine-grained counting module, a coarse-grained counting module, and a duration calculation module. In the present application, the clock network module outputs a plurality of second timestamp signals to the fine-grained counting module according to the input first timestamp signal. Each second timestamp signal is a signal obtained by delaying the first timestamp signal by the same time. The fine-grained counting module samples each second timestamp signal at different moments, and determines the fine-grained count according to the sampling results of each second timestamp signal. The coarse-grained counting module determines the coarse-grained count of the second timestamp signal. The duration calculation module determines the timing value according to the fine-grained count and the coarse-grained count, so that the time-to-digital conversion device has high timing accuracy, is easy to implement, is flexibly scalable, and has low cost.

Description

Technical Field

[0001] This application belongs to the technical field of time measurement, and particularly relates to a time-to-digital conversion device and an optical ranging sensor. Background Art

[0002] In the technical fields of sensors, instruments, etc., many applications require precise measurement of the time interval between two events. Taking an optical ranging sensor as an example, a widely used ranging method is the pulsed Time-of-Flight (pulsed ToF), whose working principle is to emit a short optical pulse with a high instantaneous power, and then measure the time interval for the pulse to travel to the target and return, and calculate the distance between the target and the sensor in combination with the speed of light. Considering the extremely high propagation rate of light, in order to achieve an ideal distance resolution, such as 1 centimeter, the timing accuracy is required to be at least dozens of picoseconds, which poses a great challenge to the design of the timing scheme.

[0003] Current timing devices usually develop dedicated integrated timing circuits (Application Specific Integrated Circuit, ASIC). Although this method has good flexibility and can achieve high performance, the development cycle is long and the cost is relatively high. Summary of the Invention

[0004] The purpose of this application is to provide a time-to-digital conversion device, aiming to solve the problems of long development cycle and high product cost of traditional timing devices.

[0005] To achieve the above purpose, in the first aspect, the embodiments of this application provide a time-to-digital conversion device, including a clock network module, a fine-grained counting module, a coarse-grained counting module, and a duration calculation module;

[0006] The clock network module is configured to output a plurality of second timestamp signals to the fine-grained counting module according to the input first timestamp signal, and each of the second timestamp signals is a signal obtained by delaying the first timestamp signal by the same time;

[0007] The fine-grained counting module is configured to sample each of the second timestamp signals, and determine the fine-grained count according to the sampling results of each of the second timestamp signals, and the sampling points of each of the second timestamp signals are different;

[0008] The coarse-grained counting module is configured to determine the coarse-grained count of the second timestamp signal;

[0009] The duration calculation module is configured to determine the timing value according to the fine-grained count and the coarse-grained count.

[0010] In a possible implementation of the first aspect, the fine-grained counting module includes a multi-stage delay chain unit, a sampling unit, and a fine-grained counting encoder unit;

[0011] The multi-stage delay chain unit is configured to output each of the second timestamp signals after different delays to obtain a plurality of third timestamp signals;

[0012] The sampling unit is configured to sample each of the third timestamp signals at the same moment;

[0013] The fine-grained counting encoder unit is configured to determine the fine-grained count according to the sampling results of each of the third timestamp signals.

[0014] In another possible implementation of the first aspect, the multi-stage delay chain unit includes a plurality of delay chains, and the delay amounts of each of the delay chains are different.

[0015] In another possible implementation of the first aspect, the fine-grained counting module further includes a bit order rearrangement unit, and the bit order rearrangement unit is configured to reorder the sampling results of each of the third timestamp signals and output them to the fine-grained counting encoder unit.

[0016] In another possible implementation of the first aspect, the time-to-digital conversion device further includes a clock management module, and the clock management module is configured to provide a sampling clock for the fine-grained counting module and provide a system clock or a sampling clock for the coarse-grained counting module.

[0017] In another possible implementation of the first aspect, the clock network module is any one of the following clock networks or a variant network of any one of them: a global clock network, a regional clock network, a horizontal clock network, and an IO clock network.

[0018] In another possible implementation of the first aspect, the sampling unit is a serial-to-parallel converter, a double data rate register, or a general register.

[0019] In another possible implementation of the first aspect, there are a plurality of fine-grained counting modules, and the clock network module is specifically configured to output a plurality of second timestamp signals to each of the fine-grained counting modules according to the first timestamp signal;

[0020] The sampling points corresponding to each of the fine-grained counting modules are the same;

[0021] The duration calculation module is configured to determine the timing result by using the mean method according to the coarse-grained count and the fine-grained counts determined by each of the fine-grained counting modules.

[0022] In another possible implementation of the first aspect, there are multiple fine-grained counting modules, and the clock network module is specifically configured to output multiple second timestamp signals to each of the fine-grained counting modules according to the first timestamp signal;

[0023] The sampling points corresponding to each of the fine-grained counting modules are different;

[0024] The duration calculation module is configured to determine a timing result according to the coarse-grained count and the fine-grained counts determined by each of the fine-grained counting modules.

[0025] In a second aspect, an embodiment of the present application provides an optical ranging sensor, including the time-to-digital conversion device described above.

[0026] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: For the above time-to-digital conversion device, the clock network module outputs multiple second timestamp signals to the fine-grained counting modules according to the input first timestamp signal. Each second timestamp signal is a signal obtained by delaying the first timestamp signal by the same time. The fine-grained counting modules sample each second timestamp signal at different moments, and determine the fine-grained counts according to the sampling results of each second timestamp signal. The coarse-grained counting module determines the coarse-grained count of the second timestamp signal. The duration calculation module determines the timing value according to the fine-grained counts and the coarse-grained count, so that the time-to-digital conversion device has high timing accuracy, is easy to implement, is flexibly scalable, and has low cost. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 It is a schematic structural diagram of the time-to-digital conversion device provided by the embodiment of the present application;

[0029] Figure 2 It is a schematic structural diagram of the fine-grained counting module of the time-to-digital conversion device provided by the embodiment of the present application;

[0030] Figure 3 It is a schematic circuit diagram of the time-to-digital conversion device provided by the embodiment of the present application;

[0031] Figure 4 It is a schematic structural diagram of the clock network module of the time-to-digital conversion device provided by the embodiment of the present application;

[0032] Figure 5 Schematic diagram of the multi - stage delay chain unit and sampling unit of the time - to - digital conversion device provided by the embodiment of the present application;

[0033] Figure 6 Sampling waveform diagram of the time - to - digital conversion device provided by the embodiment of the present application;

[0034] Figure 7 Schematic diagram of multiple fine - grained counting modules of the time - to - digital conversion device provided by the embodiment of the present application.

[0035] Among them, the reference numerals in the figure:

[0036] 1 - clock network module, 2 - fine - grained counting module, 21 - multi - stage delay chain unit, 22 - sampling unit, 23 - fine - grained counting encoder unit, 24 - bit - order rearrangement unit, 3 - coarse - grained counting module, 4 - duration calculation module, 5 - clock management module. Detailed implementation manners

[0037] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0038] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0039] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application.

[0040] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more unless otherwise specifically defined.

[0041] To solve the problems of long development cycle and high product cost of traditional timing devices, one possible solution is to use a Field Programmable Gate Array (FPGA) chip to achieve high-precision time measurement, that is, to complete the high-precision measurement of the time interval based on the internal resources of the FPGA. In specific implementation, the time interpolation method can be adopted, using the FPGA clock signal as a counter to count and measure the time interval in coarse-grained units to obtain a coarse-grained count value. At the same time, with the help of the internal design resources of the FPGA, the coarse-grained time unit is further subdivided to obtain a fine-grained count value, and finally the coarse-grained count value and the fine-grained count value are integrated to output the final timing result.

[0042] Specifically, the time interpolation method can include the tapped delay line method and the multi-phase clock method. Among them, the tapped delay line method can use the carry chain inside the FPGA as the delay path, and judge the fine-grained time by analyzing the number of levels that the signal propagates on the delay path within the coarse-grained time unit. This method can achieve a relatively high resolution (such as dozens of picoseconds). However, due to the uneven delay distribution of the internal delay path of the FPGA, the measurement result of the fine-grained time is non-linear. At the same time, the delay duration of each stage on the delay path is affected by factors such as process, temperature, and voltage (PVT), resulting in fluctuations and requiring regular calibration, which makes the final solution complex and affects flexibility.

[0043] The multi-phase clock method can generate multiple clocks with the same frequency and equally spaced phases through the clock management module inside the FPGA, and use the phase differences of different clocks to sample events at different positions within the coarse-grained time unit, thereby achieving further division of the time granularity. However, this solution needs to properly handle the problems of multi-clock synchronous counting and cross-clock domain, and is limited by the maximum operating frequency of the FPGA clock resources and the number of output clocks of the clock management module. The time resolution can only reach hundreds of picoseconds, and it is difficult to further improve without combining other technical means.

[0044] Therefore, this application provides a time-to-digital conversion device. The clock network module outputs multiple second timestamp signals to the fine-grained counting module according to the input first timestamp signal. Each second timestamp signal is a signal obtained after the same delay of the first timestamp signal. The fine-grained counting module samples each second timestamp signal at different moments, and determines the fine-grained count according to the sampling results of each second timestamp signal. The coarse-grained counting module determines the coarse-grained count of the second timestamp signal. The duration calculation module determines the timing value according to the fine-grained count and the coarse-grained count, so that the time-to-digital conversion device has high timing accuracy, is easy to implement, is flexible and scalable, and has low cost.

[0045] Figure 1FIG. 0 is a schematic structural diagram of the time-to-digital conversion device provided in the first embodiment of the present application. For the sake of convenience of description, only the parts related to this embodiment are shown. As Figure 1 shown, the time-to-digital conversion device provided in the present application may include a clock network module 1, a fine-grained counting module 2, a coarse-grained counting module 3, and a duration calculation module 4.

[0046] Among them, the clock network module 1 is configured to output a plurality of second timestamp signals to the fine-grained counting module 2 according to the input first timestamp signal, and each second timestamp signal is a signal obtained by delaying the first timestamp signal by the same time; the fine-grained counting module 2 is configured to sample each of the second timestamp signals and determine the fine-grained count according to the sampling results of each of the second timestamp signals, and the sampling points of each of the second timestamp signals are different; the coarse-grained counting module 3 is configured to determine the coarse-grained count of the second timestamp signal; the duration calculation module 4 is configured to determine the timing value according to the fine-grained count and the coarse-grained count.

[0047] In the embodiment of the present application, after the first timestamp signal to be measured enters the FPGA through the input pin, the clock network module 1 divides the first timestamp signal into multiple paths and outputs the second timestamp signals after the same delay. The arrival times of the second timestamp signals at the internal multi-stage delay chain of the fine-grained counting module 2 are the same, so as to solve the problem of signal skew in different paths inside the FPGA. At the same time, because the arrival times of the multiple second timestamp signals at the internal multi-stage delay chain unit 21 of the fine-grained counting module are the same, and based on the calibration function of the multi-stage delay chain unit 21, it can further ensure that the delay lengths of each node on the link are evenly distributed and basically unchanged, so that the timing result has good linearity and consistency, and eliminates the influence of process-voltage-temperature factors on the delay duration.

[0048] Among them, the clock network module is a dedicated wiring resource inside the FPGA, usually used to transmit clock signals, and can be any one of the following clock networks or a variant network of any one: global clock network, regional clock network, horizontal clock network, and input / output (IN / OUT, IO) clock network. Using the clock network module 1 to transmit the first timestamp signal can make the arrival times of the first timestamp signals at the input end of the multi-stage delay chain unit 21 basically the same, avoiding the skew problem caused by the uncontrollable characteristics of ordinary wiring resources.

[0049] In this embodiment, the time-to-digital conversion device may further include a clock management module 5, configured to provide a sampling clock for the fine-grained counting module 2 and provide a system clock or a sampling clock for the coarse-grained counting module 3; the sampling clock output by the clock management module 5 may be the same as the system clock or different (for example, the two are in a frequency doubling relationship).

[0050] Figure 2A structural diagram of a fine-grained counting module of a time-to-digital conversion device provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the fine-grained counting module 2 may include a multi-stage delay chain unit 21 , a sampling unit 22 and a fine-grained counting encoder unit 23 .

[0051] The multi-stage delay chain unit 21 is used to output each second timestamp signal after different delays to obtain multiple third timestamp signals; the sampling unit 22 is used to sample each third timestamp signal at the same time; the fine-grained counting encoder unit 23 is used to determine the fine-grained count according to the sampling results of each third timestamp signal.

[0052] Specifically, a multi-stage delay chain resource (i.e., a multi-stage delay chain unit 21) is usually built into the IO port of the FPGA. In this embodiment, the multi-stage delay chain unit 21 may include multiple delay chains, each delay chain may correspond one-to-one to the second timestamp signal, and each second timestamp signal output by the clock network module 1 is sent to the corresponding delay chain.

[0053] For each delay chain, a fixed number of delay stages can be set using parameters during instantiation, or the number of delay stages of the delay chain can be dynamically adjusted through a configuration interface during runtime. Based on the feature that the number of delay stages of the delay chain unit 21 is adjustable, in this embodiment, several delay chains can be set to a structure with increasing numbers of delay stages, so that after the multiple second time stamp signals are delayed respectively by the delay chain unit 21, multiple third time stamp signals with different delays can be obtained at the output end of the delay chain unit 21.

[0054] The sampling unit 22 may include multiple sampling registers. The third timestamp signals with different delay amounts output from the delay chain unit 21 are respectively sent to the input ends of the multiple sampling registers in the sampling unit 22. The sampling registers, under the control of the sampling clock output by the clock management module 5, sample the third timestamp signals at the input ends, store and output the instantaneous level state of the signals. Each sampling register may use the same sampling clock to sample the input third timestamp signal. Since the third timestamp signals input by each sampling register have delay amounts that increase in sequence, each sampling register uses the same sampling clock to sample the third timestamp signal, which is actually equivalent to using multiple sampling clocks to sample at different times of the second timestamp signal, thereby further subdividing the timing granularity within one cycle of the sampling clock.

[0055] In this embodiment, the sampling register can be located near the corresponding delay chain, which can avoid the skew problem caused by inconsistent routing delays. The specific implementation forms of the sampling register include, but are not limited to, deserializers (i.e., serializer / deserializers (SERDES)), double data rate registers, and general register resources within the IO logic unit; among them, the deserializer can operate in multiple sampling rate modes, including but not limited to single data rate (SDR), dual data rate (DDR), and oversampling (OVERSAMPLE).

[0056] The sampling result of the timestamp signal obtained by integrating the outputs of the sampling registers can be a bit vector in the form of a thermometer code, and its binary form consists of consecutive 0s and / or consecutive 1s, where the positions of the transitions from 0 to 1 and / or from 1 to 0 correspond to the relative moments of the rising edge and / or falling edge of the second timestamp signal within the system clock cycle, and the time granularity of each 0 and 1 corresponds to the delay difference between two levels of the delay chain, that is, the fine-grained time unit. The fine-grained counting encoder unit 23 takes this bit vector as input and outputs the corresponding fine-grained count, which represents the fractional position of the rising edge and / or falling edge of the second timestamp signal within the corresponding system clock cycle.

[0057] The coarse-grained counting module 3 can include a coarse-grained counter that counts at the frequency of the system clock or the sampling clock. When the fine-grained counting encoder outputs a valid value (e.g., a non-zero value) in a certain clock cycle, it indicates that there is a rising edge and / or falling edge of the second timestamp signal within this clock cycle. At this time, the coarse-grained counter can output the current count as the coarse-grained count for time measurement, and its coarse-grained time unit is the clock cycle used by the coarse-grained counter (i.e., the system clock or the sampling clock).

[0058] The duration calculation module 4 can obtain the final timing result based on the coarse-grained count and the fine-grained count, in combination with the coarse-grained time unit and the fine-grained time unit. For example, the coarse-grained count can be multiplied by the coarse-grained time unit to obtain the coarsely measured time interval, the fine-grained count can be multiplied by the fine-grained time unit to obtain the fractionally measured time interval, and then the coarsely measured time interval is added to the fractionally measured time interval to obtain the final timing result.

[0059] When the sampling clock of the clock management module 5 is different from the system clock, the fine-grained counting module 2 can further include a bit order rearrangement unit 24 for reordering the bit vector obtained by each sampling register sampling the input signal and sending it to the fine-grained counting encoder unit 23.

[0060] Specifically, the third timestamp signal sampling status obtained by each sampling register is sent to the bit order rearrangement module 24. The bit order rearrangement module 24 can, within the system clock domain, re-adjust the bit order and integrate according to the interleaving rule between the bit vectors output by each sampling register driven by a high-frequency sampling clock, so as to obtain a bit vector with the difference in the delay amount of the delay chain as the granularity, which reflects the relative moment position of the rising edge and / or falling edge of the second timestamp signal within the system clock cycle.

[0061] Taking the Xilinx 7 series FPGA as an example, a specific circuit structure of the time-to-digital conversion device is exemplarily shown below.

[0062] Figure 3 It is a schematic diagram of the circuit structure of the time-to-digital conversion device provided in this embodiment. Figure 4 It is a schematic diagram of the clock network module of the time-to-digital conversion device provided in this embodiment. As Figure 3 and Figure 4 shown, the first timestamp signal to be measured enters the FPGA through the global input buffer device (IBUFG) at the IO pin. First, it reaches the global clock buffer (BUFG) along the general routing resources, and then is sent to the global clock network through the BUFG to obtain multiple second timestamp signals with the same delay.

[0063] Figure 5 It is a schematic diagram of the multi-stage delay chain unit and sampling unit of the time-to-digital conversion device provided in the embodiment of the present application. As Figure 5 shown, in the Xilinx 7 series FPGA, the delay chain unit 21 located in the IO block may include multiple IDELAYE2s. The IDELAYE2 is a device for delaying input signals, and a 32-stage delay chain is built therein. When the IDELAYE2 works in cooperation with the delay calibration device (IDELAYCTRL), the IDELAYCTRL will perform real-time feedback calibration on the delay chain inside each IDELAYE2 based on the clock cycle of the reference clock, ensuring that the delay amount of each node inside the delay chain is basically equal, and the total delay duration of the entire delay chain remains unchanged. Under the action of the calibration mechanism of the delay calibration device (IDELAYCTRL), the step size of the IDELAYE2 delay chain (i.e., the granularity for further subdividing time within the sampling period) is fixed at 1 / 64 of the clock cycle of the reference clock, which is not affected by process-voltage-temperature and has good consistency.

[0064] Taking the reference clock CLK_REF frequency output by the clock management module 5 (MMCM) as 200 MHz as an example, the step size of IDELAYE2 is 78.125 ps. The delay stages of each IDELAYE2 can be set statically or adjusted dynamically. Taking static setting as an example, when instantiating IDELAYE2 in the hardware description language, the delay stages can be set through the corresponding parameter values. Exemplarily, as Figure 5 shown, a total of 16 IDELAYE2 devices are used: IDELAYE2#1 to IDELAYE2#16, and the delay stages are statically set to 1, 2, …, 16 in sequence.

[0065] The first timestamp signal arrives at the input ends of 16 IDELAYE2s along the global clock network to obtain the second timestamp signal. After being delayed by the internal delay chain of IDELAYE2, 16 third timestamp signals with different delay degrees are obtained at the output ends. The delay difference between two adjacent third timestamp signals is the step size of the delay chain, that is, 78.125 ps. These signals are then sent to the sampling unit 22 (ISERDESE2, specifically including ISERDESE2#1 to ISERDESE2#16) adjacent to the corresponding IDELAYE2. The sampling unit 22 (ISERDESE2) is a serializer / deserializer built into the Xilinx 7 series FPGA IO block, which is used to convert the high-speed serial signal in the high-frequency clock domain into parallel data in the low-frequency clock domain. The sampling unit 22 (ISERDESE2) supports multiple serializer / deserializer modes. Exemplarily, in this embodiment, dual-edge sampling (DATA_RATE = DDR) and a 2:1 serializer / deserializer ratio (DATA_WIDTH = 4) are adopted. In this setting, the sampling unit 22 (ISERDESE2) will sample the input signal once at the rising edge and the falling edge of each sampling clock cycle, and output a bit vector with a length of 4 every 2 sampling clock cycles.

[0066] To match this serializer / deserializer mode, the clock management module 5 (MMCM) can output two clocks, namely the sampling clock CLK_SAMPLE and the system clock CLK_SYS. Among them, taking the sampling clock CLK_SAMPLE with a frequency of 400 MHz as an example, it is connected to the CLK pin of each sampling unit 22 (ISERDESE2) for dual-edge sampling of its input end; among them, taking the system clock CLK_SYS with a frequency of 200 MHz as an example, it is connected to the CLKDIV pin of each sampling unit 22 (ISERDESE2) to output a bit vector with a total bit width of 4 from the O1 / O2 / O3 / O4 ports once every two CLK_SAMPLE cycles.

[0067] Since the inputs of 16 ISERDESE2s are the third timestamp signals with sequentially increasing delay lengths, and the increasing step is the step of the IDELAYE2 delay chain (i.e., 78.125 ps), while the sampling clock frequency of ISERDESE2 is 400 MHz and the corresponding sampling period is 2500 ps. If the same sampling clock is used to sample the 16 third timestamp signals with sequentially increasing delays, it is actually equivalent to using 16 sampling clocks with an interval of 78.125 ps to sample the second timestamp signal.

[0068] Figure 6 This is the sampling waveform diagram of the time-to-digital conversion device provided by the embodiment of the present application. As Figure 6 shown, the sampling clock of the 16th ISERDESE2 (sampling clock #16) samples the third timestamp signal with the most delay (16 levels of delay), so the sampling position is the earliest among all ISERDESE2s; while the sampling clock of the 1st ISERDESE2 (sampling clock #1) samples the third timestamp signal with the least delay (1 level of delay), so the sampling position is the last among all ISERDESE2s.

[0069] The sampling position interval of each sampling clock is 78.125 ps (i.e., the step of the delay chain), which exactly divides the half period of the 400 MHz sampling clock, that is, 1250 ps, into 16 equal parts, equivalent to achieving further time granularity subdivision on the basis of the half period of the sampling clock.

[0070] The bit vectors (bit vector #1 to bit vector #16) output by 16 ISERDESE2s in the system clock domain have a time interleaving relationship in their sampling positions. For example, the bit vector with a length of 4 output by the 16th ISERDESE2 has corresponding sampling edges as edge 1, edge 17, ……, while the bit vector with a length of 4 output by the 1st ISERDESE2 has corresponding sampling edges as edge 16, edge 32, ……. Therefore, for the 16 groups of bit vectors with a length of 4 obtained in each system clock cycle, the order of each bit needs to be re-adjusted, and finally integrated into a bit vector with a length of 64, and the order of its bits corresponds to the time sequence of the sampling edges.

[0071] After the bit order rearrangement, a bit vector with a length of 64, in the form of 000001111111100000……000 can be obtained, where the jump positions from 0 to 1 and / or from 1 to 0 correspond to the rising edge and / or falling edge of the second timestamp signal in the system clock cycle, and the granularity of the subdivision is 78.125 ps. Therefore, by encoding the jump positions from 0 to 1 and / or from 1 to 0 into binary values through a priority encoder (i.e., a fine-grained counting encoder), the fine-grained count value at the edge moment of the corresponding signal can be obtained.

[0072] Meanwhile, the coarse-grained counter counts the system clock cycles; when the fine-grained count value corresponding to a certain system clock cycle is non-zero, it indicates that the rising edge and / or falling edge of the timestamp signal is captured within this system clock cycle. At this time, the value of the coarse-grained counter is recorded as the coarse-grained count. By multiplying the coarse-grained count by the coarse-grained time unit (5000 ps) and adding the fine-grained count multiplied by the fine-grained time unit (78.125 ps), the final timing result is obtained.

[0073] The above takes the single fine-grained counting module 2 as an example and exemplarily illustrates the fine-grained counting module 2. Figure 7 The structural schematic diagram of multiple fine-grained counting modules of the time-to-digital conversion device provided by the embodiment of the present application is as Figure 7 shown. In this embodiment, there may also be multiple fine-grained counting modules 2. This solution may include but is not limited to the following implementation manners:

[0074] The first: Multiple fine-grained counting modules 2 simultaneously measure the time of multiple concurrent first timestamp signals input from multiple clock network modules 1. That is, each fine-grained counting module 2 may correspond to a different first timestamp signal. For each fine-grained counting module 2, the duration calculation module 4 can determine the timing result corresponding to this time-to-digital conversion device according to the coarse-grained count and the fine-grained count determined by this fine-grained counting module 2.

[0075] The second: The clock network module 1 is specifically configured to output multiple second timestamp signals to each fine-grained counting module 2 according to the first timestamp signal respectively.

[0076] The sampling points corresponding to each fine-grained counting module 2 are the same.

[0077] The duration calculation module 4 is used to determine the timing result by using the mean method according to the coarse-grained count and the fine-grained count determined by each fine-grained counting module 2.

[0078] That is, multiple fine-grained counting modules 2 simultaneously measure the time of a single first timestamp signal input on the same clock network module 1. The sampling points corresponding to each fine-grained counting module 2 are the same. After averaging the measurement results of multiple fine-grained counting modules 2, the average fine-grained count is output. The duration calculation module 4 can determine the timing result corresponding to this time-to-digital conversion device according to the coarse-grained count and the average fine-grained count determined by each fine-grained counting module 2, thereby reducing the jitter of the measured value.

[0079] The third: The clock network module 1 is specifically configured to output multiple second timestamp signals to each fine-grained counting module 2 according to the first timestamp signal respectively;

[0080] The sampling points corresponding to each fine-grained counting module 2 are different;

[0081] The duration calculation module 4 is used to determine the timing result according to the coarse-grained count and the fine-grained counts determined by each fine-grained counting module 2.

[0082] That is, multiple fine-grained counting modules 2 are used to simultaneously measure the time of a single first timestamp signal input on the same clock network module 1. The sampling points corresponding to each fine-grained counting module 2 are different. Each fine-grained counting module 2 uses the same sampling clock frequency but different phases, and the phases have a slight offset, so as to further subdivide the fine-grained time unit. For example, Figure 7 As shown, the duration calculation module 4 can determine the timing result corresponding to the time-to-digital conversion device according to the coarse-grained count and the further subdivided fine-grained counts determined by each fine-grained counting module 2, further improving the time resolution.

[0083] The optical ranging sensor provided in this application includes a time-to-digital conversion device.

[0084] In the embodiments of this application, the first timestamp signal is distributed to multiple-stage delay chains through the clock network module. By using the characteristic that the delays of each branch of the clock network module are equal, it is ensured that the input signals of each delay chain (i.e., the second timestamp signals) correspond to the same moment of the first timestamp signal, solving the skew problem of signal transmission on different paths inside the FPGA. Furthermore, the multiple-stage delay chains of common FPGA models support the calibration function and are built with a compensation circuit, which can eliminate the influence of process-voltage-temperature (PVT) factors on the delay time, ensuring that the delay lengths of each node on the link are equal and basically unchanged, making the timing result have good linearity and consistency. Based on the multiple-sampling timing method of this application, it has a small dead time (at most not exceeding the coarse-grained time unit), and can perform fast and continuous timing on high-frequency timestamp signals. By simultaneously using multiple fine-grained counting modules, the performance parameters of the entire timing device can be further improved. For example, using the average of multiple fine-grained counting modules to reduce the jitter of the timing value, or using sampling clock phase shift to further improve the time resolution of the timing result.

[0085] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application.

[0086] Those skilled in the art can clearly understand that, for the convenience and conciseness of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of the functional units and modules are only for the convenience of mutual distinction and do not limit the protection scope of this application. The specific working process of the units and modules in the above-mentioned primary side quasi-resonant control system can refer to the corresponding process in the foregoing method embodiment and will not be elaborated herein.

[0087] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not described in detail or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0088] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0089] In the embodiments provided in this application, it should be understood that the disclosed time-to-digital conversion device and method can be implemented in other ways. For example, the time-to-digital conversion device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another primary side quasi-resonant control system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.

[0090] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0091] In addition, in each embodiment of the present application, each functional unit may be integrated in a processing unit, may exist separately as individual physical units, or two or more units may be integrated in one unit. The above-mentioned integrated units may be implemented in the form of hardware or in the form of software functional units.

[0092] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A time-to-digital conversion device, comprising a clock network module (1), a fine-grained counting module (2), a coarse-grained counting module (3), and a duration calculation module (4); The clock network module (1) is configured to output a plurality of second timestamp signals to the fine-grained counting module (2) according to an input first timestamp signal, and each of the second timestamp signals is a signal obtained by delaying the first timestamp signal by the same time; The fine-grained counting module (2) is configured to sample each of the second timestamp signals and determine a fine-grained count according to the sampling results of each of the second timestamp signals, and the sampling points of each of the second timestamp signals are different; The coarse-grained counting module (3) is configured to determine a coarse-grained count of the second timestamp signal; The duration calculation module (4) is configured to determine a timing value according to the fine-grained count and the coarse-grained count; The fine-grained counting module (2) includes a multi-stage delay chain unit (21), a sampling unit (22), and a fine-grained counting encoder unit (23); The multi-stage delay chain unit (21) is configured to output each of the second timestamp signals after different delays to obtain a plurality of third timestamp signals; The sampling unit (22) is configured to sample each of the third timestamp signals at the same moment; The fine-grained counting encoder unit (23) is configured to determine a fine-grained count according to the sampling results of each of the third timestamp signals; The time-to-digital conversion device further includes a clock management module (5), and the clock management module (5) is configured to provide a sampling clock for the fine-grained counting module (2) and provide a system clock or a sampling clock for the coarse-grained counting module (3).

2. The time-to-digital conversion device according to claim 1, wherein The multi-stage delay chain unit (21) includes a plurality of delay chains, and the delay amounts of each of the delay chains are different.

3. The time digital conversion device according to claim 1, characterized in that, The fine-grained counting module (2) further includes a bit order rearrangement unit (24), and the bit order rearrangement unit (24) is configured to reorder the sampling results of each of the third timestamp signals and output them to the fine-grained counting encoder unit (23).

4. The time digital conversion device according to any one of claims 1-3, characterized in that, The clock network module (1) is any one of the following clock networks: a global clock network, a regional clock network, a horizontal clock network, and an IO clock network.

5. The time digital conversion device according to any one of claims 1 to 3, characterized in that, The sampling unit (22) is a serial-to-parallel converter, a double data rate register, or a general register.

6. The time digital conversion device according to any one of claims 1 to 3, characterized in that, The fine-grained counting module (2) includes a plurality of modules, and the clock network module (1) is specifically configured to output a plurality of second timestamp signals to each of the fine-grained counting modules (2) according to the first timestamp signal; The sampling points corresponding to each of the fine-grained counting modules (2) are the same; The duration calculation module (4) is configured to determine a timing result by using the mean method according to the coarse-grained count and the fine-grained counts determined by each of the fine-grained counting modules (2).

7. The time digit conversion device according to any one of claims 1 to 3, characterized in that The fine-grained counting module (2) includes a plurality of modules, and the clock network module (1) is specifically configured to output a plurality of second timestamp signals to each of the fine-grained counting modules (2) according to the first timestamp signal; The sampling points corresponding to each of the fine-grained counting modules (2) are different; The duration calculation module (4) is configured to determine a timing result according to the coarse-grained count and the fine-grained counts determined by each of the fine-grained count modules (2).

8. An optical ranging sensor, characterized in that, Comprising the time digital conversion device according to any one of claims 1-7.

Images