Microelectronic device with symmetrically distributed stair steps and related systems and methods

Abstract

The present application relates to a microelectronic device having symmetrically distributed stair steps and related systems and methods. The microelectronic device includes a stair structure that is substantially symmetrically distributed between a first column structure and a second column structure within a stacked structure, each of which extends vertically through the stacked structure. The stacked structure includes a vertical alternating sequence of insulating material and conductive material arranged in layers. Each of the stair structures includes a stair structure having steps, the steps including lateral ends of some of the layers. The stair structures and the substantially symmetrical distribution of filler materials adjacent to such structures can substantially balance material stresses to avoid or minimize bending of the adjacent columns. Related methods and systems are also disclosed.

Description

[0001] Priority claim

[0002] This application claims the benefit of the filing date of U.S. patent application serial number 16 / 790,148, filed on February 13, 2020, for "Microelectronic Devices with Symmetrically Distributed Staircase Stadiums and Related Systems and Methods." Technical Field

[0003] Embodiments of the present invention relate to the field of microelectronic device design and fabrication. More particularly, the present invention relates to microelectronic devices (e.g., memory devices, such as 3D NAND memory devices) having staircase structures arranged in substantially symmetrically distributed steps, related methods, and systems incorporating such devices. Background Art

[0004] Memory devices provide data storage for electronic systems. Flash memory devices are one of various memory device types and have numerous uses in modern computers and other electronic devices. Conventional flash memory storage devices may include a memory array having a large number of charge storage devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In NAND architecture type flash memory, the memory cells arranged in columns are coupled in series, and the first memory cell of the column is coupled to a data line (e.g., a bit line). In a "three-dimensional NAND" memory device (which may also be referred to herein as a "3D NAND" memory device), that is, a type of vertical memory device, not only are the memory cells arranged in rows and columns in a horizontal array, but the layers of the horizontal array are stacked on top of each other (e.g., as a vertical string of memory cells) to provide a "three-dimensional array" of memory cells. The stacking of the layers vertically alternates conductive material with insulating (e.g., dielectric) material. The conductive material is used as, for example, a control gate for an access line (e.g., a word line) of the memory cell. A vertical structure (e.g., a column including a channel structure) extends along the vertical string of memory cells. The drain terminal of the string is adjacent to one of the top and bottom of the vertical structure (e.g., pillar), while the source terminal of the string is adjacent to the other of the top and bottom of the pillar. The drain terminal is operably connected to the bit line, while the source terminal is operably connected to the source line. The 3D NAND memory device also includes electrical connections such as access lines (e.g., word lines) and other conductive structures of the device so that the memory cells of the vertical string can be selected for write, read, and erase operations. The string driver drives the access line (e.g., word line) voltage to write to or read from the memory cells of the vertical string.

[0005] One method of forming such electrical connections includes forming a so-called "staircase" structure having "steps" (or otherwise referred to as "rungs") at the edges (e.g., lateral ends) of the levels of the stacked structure. The steps define contact areas for conductive structures of the device, such as access lines (e.g., word lines), which may be formed from the layered stack of conductive materials. Contact structures may be formed in contact with the steps to provide electrical access to the conductive structures (e.g., word lines) associated with each respective step.

[0006] An ongoing goal in the microelectronic device manufacturing industry is to improve the performance of devices (e.g., 3D NAND memory devices) by reducing the resistance and / or capacitance of word lines. However, efforts to reduce the resistance and / or capacitance of word lines may negatively impact other aspects of device design and manufacturing, such as by introducing pillar bending in areas of the device adjacent to staircase structures. Thus, designing and manufacturing microelectronic devices (e.g., 3D NAND memory devices) with reduced resistance and / or capacitance and without pillar bending continues to be challenging. Summary of the invention

[0007] A microelectronic device is disclosed, comprising a stacked structure including a vertically alternating sequence of insulating materials and conductive materials arranged in layers. A first pillar structure extends vertically through the stacked structure. A second pillar structure extends vertically through the stacked structure. A step structure is distributed within the stacked structure and generally symmetrically between the first pillar structure and the second pillar structure. Each of the step structures includes a staircase structure having steps, the steps including lateral ends of some of the layers.

[0008] A memory device is also disclosed, comprising at least two memory cell arrays extending vertically through a stacked structure. The stacked structure comprises layers. Each of the layers comprises a conductive structure and an insulating structure. A staircase structure is substantially symmetrically distributed within the stacked structure and horizontally positioned between the at least two memory cell arrays.

[0009] In addition, a method of forming a microelectronic device is disclosed. The method includes forming a stacked structure including a vertically alternating sequence of materials arranged in layers. A stepped structure is formed to extend vertically to different depths within the stacked structure. A filling material is formed within a groove defined in the stepped structure. A volume of the filling material in the groove defined by the stepped structure to a first lateral side of a centerline of a distribution of the stepped structure is substantially equal to a volume of the filling material in the groove defined by the stepped structure to a second lateral side of the centerline of the distribution.

[0010] In addition, a system is disclosed, which includes a three-dimensional memory; at least one processor that is in operable communication with the three-dimensional memory device; and at least one peripheral device that is in operable communication with the at least one processor. The three-dimensional memory device includes: a vertical memory cell array along a pillar structure that extends vertically through a stacked structure including a vertical alternating sequence of insulating material and conductive material. Step structures are distributed within the stacked structure and generally symmetrically between the vertical memory cell arrays. Each of the step structures extends to a different depth within the stacked structure. Filling material is adjacent to each of the step structures. The total volume of the filling material disposed to a first lateral side of a centerline of the distribution of the step structures is generally equal to the total volume of the filling material disposed to a second lateral side of the centerline. The centerline is between the vertical memory cell arrays and equidistant from the vertical memory cell arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is a cross-sectional, top, and plan view of a microelectronic device structure having substantially symmetrically distributed steps according to an embodiment of the present invention.

[0012] Figure 1B yes Figure 1A A schematic cross-sectional, front, and elevation view of a microelectronic device structure, wherein the step depth increases with the lateral distance from the center line, and wherein the step has an offset opposed stair structure, wherein the right stair structure is offset downward from the left stair structure.

[0013] Figure 1C yes Figure 1A and Figure 1B An enlarged schematic diagram of a portion of a stacked structure of a microelectronic device structure, the portion being composed of Figure 1B The dotted box indicates the part.

[0014] Figure 2A According to an embodiment of the present invention Figure 1B A schematic cross-sectional, front and top perspective view of a staircase of a microelectronic device structure, the staircase having offset opposing staircase structures, wherein the right staircase structure is offset downward from the left staircase structure.

[0015] Figure 2B 1 is a schematic diagram of a cross-section, front and top perspective view of a step of a microelectronic device structure according to an embodiment of the present invention, wherein the step and Figure 2A The ladder level is reversed, so that Figure 2B The stairs have an offset opposed stair structure, with the left stair structure being offset downwardly from the right stair structure.

[0016] Figure 3 1 is a schematic diagram of a cross-sectional, front, and elevation view of a microelectronic device structure according to an embodiment of the present invention, which has substantially symmetrically distributed steps, wherein the step depth increases with the lateral distance from the center line, and wherein the steps have offset opposed stair structures, wherein the center line side stair structures are offset downward from the outer side stair structures, and the steps on the left side of the center line have the same Figure 2A An offset opposed stair structure with the steps to the right of the centerline having the same Figure 2B Offset opposed stair structure.

[0017] Figure 4 1 is a schematic diagram of a cross-sectional, front, and elevation view of a microelectronic device structure according to an embodiment of the present invention, which has substantially symmetrically distributed steps, wherein the step depth decreases with the lateral distance from the center line, and the steps have the same Figure 2A Offset opposed stair structure.

[0018] Figure 5 1 is a schematic diagram of a cross-section, front view and elevation of a microelectronic device structure according to an embodiment of the present invention, which has substantially symmetrically distributed steps, wherein shallower steps are interspersed with deeper steps, and the steps have the same Figure 2A Offset opposed stair structure.

[0019] FIG. 6A to FIG. 9 is manufactured according to an embodiment of the present invention Figure 1B Schematic cross-sections and elevations during various stages of processing of the microelectronic device structure described in. Fig. 6A and Figure 6B , these figures together illustrate the stages of processing, where Figure 6B yes Fig. 6A part of the structure (i.e. Fig. 6A An enlarged schematic diagram of the portion indicated by the dotted box in FIG.

[0020] Fig.10 A block diagram of an electronic system including a microelectronic device including a microelectronic device structure of an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0021] Structures (e.g., microelectronic device structures), apparatus (e.g., microelectronic devices), and systems (e.g., electronic systems) according to embodiments of the present invention include steps having different depths, wherein the steps are substantially symmetrically distributed between laterally adjacent pillars (e.g., between laterally adjacent vertical memory cell arrays). This substantially symmetrical distribution of the steps enables the microelectronic device structure to be configured to achieve low resistance and low capacitance of the word line while also balancing the centerline of the distribution, the volume of fill material, and the material stress so that bending of adjacent pillars is avoided or minimized and consistent, thereby achieving minimal and consistent mitigation of pillar bending on both sides of the step distribution.

[0022] As used herein, the term "opening" means a volume extending through at least one structure or at least one material, thereby leaving a gap in the at least one structure or at least one material, or a volume extending between structures or materials, thereby leaving a gap between structures or materials. Unless otherwise described, an "opening" is not necessarily lacking material. In other words, an "opening" is not necessarily an empty space. An "opening" formed in or between a structure or material may include a structure or material different from the structure or material in which or between which the opening is formed. Moreover, the structure or material "exposed" in the opening is not necessarily in contact with the atmosphere or non-solid environment. The structure or material "exposed" in the opening may be adjacent to or in contact with other structures or materials placed in the opening.

[0023] As used herein, the term "substrate" means and includes a base material or other structure on which components, such as components within a memory cell, are formed. The substrate may be a semiconductor substrate, a base semiconductor material on a support structure, a metal electrode, or a semiconductor substrate on which one or more materials, structures, or regions are formed. The substrate may be a conventional silicon substrate or other bulk substrate including semiconductor materials. As used herein, the term "bulk substrate" means and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates, such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon germanium (Si 1-x Ge x , where x is a mole fraction, for example, between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. In addition, when reference is made to a "substrate" in the following description, previous process stages may have been used to form materials, structures, or junctions in the base semiconductor structure or foundation.

[0024] As used herein, the terms "horizontal" or "lateral" mean and include a direction parallel to a major surface of a substrate on which a reference material or structure is located. The width and length of the corresponding material or structure may be defined as dimensions in a horizontal plane. With reference to the drawings, the "horizontal" direction may be perpendicular to the indicated "Z" axis, and may be parallel to the indicated "X" axis and the indicated "Y" axis.

[0025] As used herein, the term "vertical" or "longitudinal" means and includes a direction perpendicular to a major surface of a substrate on which a reference material or structure is located. The height of the corresponding material or structure can be defined as the dimension in the vertical plane. With reference to the drawings, the "vertical" direction can be parallel to the indicated "Z" axis, and can be perpendicular to the indicated "X" axis and the indicated "Y" axis.

[0026] As used herein, the terms "thickness" or "thinness" mean and include a dimension in a linear direction perpendicular to the nearest surface of an immediately adjacent material or structure that has a different composition or is otherwise distinguishable from the material or structure whose thickness, thinness, or height is being discussed.

[0027] As used herein, the term "between" is a spatially relative term used to describe the relative placement of a material, structure, or substructure relative to at least two other materials, structures, or substructures. The term "between" can encompass the placement of a material, structure, or substructure directly adjacent to other materials, structures, or substructures, as well as the placement of a material, structure, or substructure indirectly adjacent to other materials, structures, or substructures.

[0028] As used herein, the term "proximate" is a spatially relative term used to describe the placement of one material, structure, or substructure close to another material, structure, or substructure. The term "proximate" includes placement indirectly adjacent to, directly adjacent to, and within.

[0029] As used herein, the term "adjacent" when referring to a material or structure means and refers to the next, closest material or structure to the identified component or characteristic. Materials or structures of other components or characteristics besides the identified component or characteristic may be disposed between a material or structure and its "adjacent" material or structure having the identified component or characteristic. For example, a structure of material X "adjacent" to a structure of material Y is, for example, the first material X structure among a plurality of material X structures that is next closest to a particular structure of material Y. An "adjacent" material or structure may be directly or indirectly adjacent to a structure or material of the identified component or characteristic.

[0030] As used herein, the terms "about" and "approximately" when used with reference to a numerical value for a particular parameter include numerical values ​​and degrees of deviation from numerical values ​​that one of ordinary skill in the art would understand to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" with respect to a numerical value may include additional numerical values ​​within a range from 90.0% to 110.0% of the numerical value, such as within a range from 95.0% to 105.0% of the numerical value, within a range from 97.5% to 102.5% of the numerical value, within a range from 99.0% to 101.0% of the numerical value, within a range from 99.5% to 100.5% of the numerical value, or within a range from 99.9% to 100.1% of the numerical value.

[0031] As used herein, the term "substantially" when referring to a parameter, property, or condition, means and includes that the parameter, property, or condition is equal to a given value or is within a certain degree of variation from a given value, such that a person of ordinary skill in the art would understand that this given value is acceptably met, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be "substantially" a given value when the value is met by at least 90.0%, met by at least 95.0%, met by at least 99.0%, or even met by at least 99.9%.

[0032] As used herein, referring to an element as being "on" or "over" another element means and includes the element being directly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) another element, below other elements, or in direct contact with other elements. It also includes the element being indirectly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to) another element, below other elements, or near other elements with other elements in between. In contrast, when an element is referred to as being "directly on" or "directly adjacent to" another element, there are no intervening elements.

[0033] As used herein, for ease of description, other spatially relative terms such as "under," "lower," "bottom," "over," "upper," "top," and the like may be used to describe the relationship of one element or feature to another element or feature, as illustrated in the drawings. Unless otherwise stated, spatially relative terms are intended to encompass different orientations of the material in addition to the orientation depicted in the drawings. For example, if the material in the figure is inverted, an element described as "under" or "under" or "on the bottom" of another element or feature would then be oriented "over" or "on top" of the other element or feature. Thus, the term "under" may encompass both the above and below orientations, depending on the context in which the term is used, as will be apparent to one of ordinary skill in the art. The material may be oriented in other ways (rotated ninety degrees, inverted), and the spatially relative descriptors used herein interpreted accordingly.

[0034] As used herein, the terms "level" and "elevation" are spatially relative terms used to describe the relationship of one material or feature to another material or feature, as illustrated in the drawings, using - as a reference point - a major surface of a substrate on which the reference material or structure is located. As used herein, "level" and "elevation" are each defined by a horizontal plane parallel to the major surface. "Lower levels" and "lower elevations" are closer to the major surface of the substrate, while "higher levels" and "higher elevations" are farther from the major surface. Unless otherwise specified, these spatially relative terms are intended to cover different orientations of the material other than the orientation depicted in the drawings. For example, the material in the drawings may be inverted, rotated, etc., wherein the spatially relative "elevation" descriptor remains unchanged, because the referenced major surface will also be reoriented accordingly.

[0035] As used herein, the terms "comprising," "including," "having," and their grammatical equivalents are inclusive or open terms that do not exclude additional, unreferenced elements or method steps, but these terms also encompass the more restrictive terms "consisting of" and "consisting essentially of," and their grammatical equivalents. Thus, structures described as "comprising," "including," and / or "having" a material may be structures that also include additional materials in some embodiments and / or structures that do not include any other materials in some embodiments. Similarly, a component (e.g., a gas) described as "comprising," "including," and / or "having" a species may be a component that also includes additional species in some embodiments and / or a component that does not include any other species in some embodiments.

[0036] As used herein, the term "may" with respect to a material, structure, feature, or method act indicates that it is contemplated for use in implementing an embodiment of the invention, and this term is used in preference to the more restrictive term "is" so as to avoid any suggestion that other, compatible materials, structures, features, and methods that may be used in combination therewith should or must be excluded.

[0037] As used herein, "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0039] As used herein, the terms "configured" and "configuration" mean and refer to the size, shape, material composition, orientation, and arrangement of a reference material, structure, assembly, or device so as to facilitate the reference operation or properties of the reference material, structure, assembly, or device in a predetermined manner.

[0040] The illustrations presented herein are not intended to be actual views of any particular material, structure, substructure, region, subregion, device, system, or manufacturing stage, but are merely idealized representations used to describe embodiments of the present invention.

[0041] Embodiments are described herein with reference to cross-sectional views as schematic diagrams. Therefore, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or structures as illustrated, but may include shape deviations resulting from, for example, manufacturing techniques. For example, a structure illustrated or described as box-shaped may have rough and / or nonlinear features. In addition, the illustrated sharp angles may be rounded. Therefore, the materials, features, and structures illustrated in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the materials, features, or structures, and do not limit the scope of the claims.

[0042] The following description provides specific details, such as material types and processing conditions, in order to provide a thorough description of the embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, one of ordinary skill in the art will understand that the embodiments of the apparatus and methods may be practiced without employing these specific details. In fact, the embodiments of the apparatus and methods may be practiced in conjunction with conventional semiconductor manufacturing techniques employed in the industry.

[0043] The manufacturing processes described herein do not form a complete process flow for processing an apparatus (e.g., device, system) or its structure. The remainder of the process flow is known to a person of ordinary skill in the art. Therefore, only methods and structures necessary for understanding embodiments of the present apparatus (e.g., device, system) and method are described herein.

[0044] Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition ("CVD"), atomic layer deposition ("ALD"), plasma enhanced ALD, physical vapor deposition ("PVD") (e.g., sputtering), or epitaxial growth. Depending on the particular material to be formed, one of ordinary skill in the art may select the technique for depositing or growing the material.

[0045] Unless the context indicates otherwise, removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (eg, dry etching, wet etching, vapor etching), ion milling, grinding planarization, or other known methods.

[0046] In referring to the drawings, like numbers refer to like components throughout. The drawings are not necessarily drawn to scale.

[0047] Figure 1A and Figure 1B as well as Figure 1C A device structure 100 is illustrated in accordance with an embodiment of the present invention. The device structure 100 includes substantially symmetrically distributed steps 102A through L. As used herein, in association with the distributed steps, "A" represents the step of the shallowest depth, "B" represents the step of the second shallowest depth, and so on, until "L" represents the step of the deepest depth.

[0048] The device structure 100 includes a base material 104 (e.g., a material in and / or supported on a substrate). The base material 104 may include or be configured as a drain / source material, and may include or be operably connected to a bit line. Within the base material 104 may be a conductive region for making electrical connections to other conductive structures of a device including the device structure 100.

[0049] The base material 104 supports a stacked structure 106 having layers 108 of vertically alternating conductive material 110 and insulating material 112. Each layer 108 includes a conductive layer of conductive material 110 and an insulating layer of insulating material 112. The insulating material 112 includes one or more dielectric materials, such as an oxide material (e.g., silicon oxide). The conductive material 110 includes one or more conductive materials, such as metals (e.g., tungsten), metal-based materials (e.g., tungsten-based materials), conductive doped materials (e.g., conductive doped polysilicon), or combinations thereof. In some embodiments, a liner (e.g., nitride) is included along the conductive material 110.

[0050] Steps 102A-L are formed in stacked structure 106 and extend vertically downward from the upper surface of device structure 100 into stacked structure 106. At the bottom of each of steps 102A-L is at least one stair structure that defines a step (e.g., rung) at at least one lateral end of layer 108. The step at each elevation exposes at least one surface of a conductive layer (e.g., of conductive material 110) of layer 108 of stacked structure 106.

[0051] Each of the steps 102A-L defines a trench filled with a filling material 114 (e.g., a non-conductive material such as a dielectric material and / or a polysilicon material). For example, the filling material 114 may be formed of an oxide dielectric material (e.g., silicon dioxide). Conductive contacts may extend through portions of the filling material 114 and / or some or all of the conductive material 110 and the insulating material 112 of the stacked structure 106 to electrically connect with the steps of the staircase structure, such as the steps 102A-L.

[0052] Each of the steps 102A-L has a different depth. The different depths of the steps 102A-L enable each conductive layer (eg, conductive material 110) having a step in the stairway of the steps 102A-L to be independently electrically contacted, such as by a conductive contact (not shown).

[0053] Each of the steps 102A-L is separated from its neighbor by a top 116, and a bridge 118 extends along each of the steps 102A-L and forms a continuous back side of each of the steps 102A-L. The tops 116 and bridges 118 are formed by and include portions of the layers 108 of vertically alternating conductive material 110 and insulating material 112 of the stacked structure 106. Thus, at each conductive layer (e.g., of conductive material 110), the tops 116 are electrically connected to each other via bridges 118.

[0054] Within each of the steps 102A-L, each conductive layer (e.g., of conductive material 110) and its steps form a "U" shape that extends from one side adjacent to one of the tops 116 along a portion of the bridge 118 to an opposite side adjacent to another of the tops 116. This top and bridge configuration for the steps 102A-L (e.g., bidirectional word lines in the steps 102A-L) enables operation of the word lines using a center string driver. That is, the device structure 100 is configured in a so-called "center bidirectional staircase" (CBSC) arrangement, in which one string driver is positioned and configured to drive word lines in the level 108 disposed on both sides of the string driver. Using this center string driver enables low resistance and low capacitance of the conductive levels (e.g., word lines formed by the conductive material 110 of the level 108) in the steps 102A-L, compared to 3D microelectronic device structures with non-center driven unidirectional word lines.

[0055] On the lateral sides of the distribution of steps 102A-L, one or more operationally active (e.g., electrically functional) pillars (e.g., left pillar 120 and right pillar 124) are disposed, each extending through stacked structure 106. A vertical array of memory cells may extend along each of these so-called "active" pillars. Steps 102A-L are generally symmetrically distributed between left pillar 120 and right pillar 124, for example, over the width of device structure 100. Therefore, steps 102A-L are also generally symmetrically distributed between the vertical array of memory cells. Steps 102A-L generally balance the volume of fill material 114 occupying steps 102A-L between pillars (e.g., left pillar 120 and right pillar 124) and across centerline C. The balance of the volume of fill material 114 generally balances material stress between pillars (e.g., left pillar 120 and right pillar 124) and across centerline C.

[0056] As used herein, the term "centerline" (as in "centerline C") means and includes a vertical line that is laterally located in the middle of the distribution along steps 102A to L and / or is laterally equidistant from adjacent active columns (e.g., left column 120 and right column 124) that are laterally disposed relative to the distribution of steps (e.g., steps 102A to J).

[0057] Figure 1A and Figure 1BThe device structure 100 includes a distribution of steps 102A through J, wherein the deepest of the steps (e.g., step 102K and step 102L) are disposed farthest from a centerline C (e.g., closest to an active pillar, and thus, closest to a vertical memory cell array), wherein the step depth steadily decreases with lateral proximity to the centerline C (e.g., with increasing lateral distance from the active pillar and the vertical memory cell array). A left portion 126 of the distribution includes—in lateral order from farthest from the centerline C to closest to the centerline C—steps 102K, 102I, 102G, 102E, 102C, and 102A, wherein step 102A is the shallowest step of the entire step distribution, and wherein step 102K is the second deepest step of the entire step distribution. Correspondingly, the right side portion 128 includes—in lateral order from furthest from the centerline C to closest to the centerline C—steps 102L, 102J, 102H, 102F, 102D, and 102B, wherein step 102B is the second shallowest step of the entire step distribution, and wherein step 102L is the deepest step of the entire step distribution. Thus, the step distribution may present a so-called “W” shape. The volume of fill material 114 occupying steps 102K, 102I, 102G, 102E, 102C, and 102A in the left side portion 126 is substantially equal to (e.g., substantially balanced with) the volume of fill material 114 occupying steps 102L, 102J, 102H, 102F, 102D, and 102B in the right side portion 128.

[0058] By distributing the steps 102A to L generally symmetrically between the effective columns (e.g., the left column 120 and the right column 124) and about the centerline C, and thereby generally balancing the material stresses between the effective columns and about the centerline C, the left column 120 and the right column 124 experience generally equal amounts of stress (e.g., material stress), if any.

[0059] In some embodiments, the substantially equal balance of material stresses, such as between the active pillars (e.g., the left pillar 120 and the right pillar 124) and about the centerline C, effectively cancels out the material stresses that would otherwise be experienced by the adjacent active pillars (e.g., the left pillar 120 and the right pillar 124), leaving a substantially "net zero" stress. Thus, the active pillars (e.g., the left pillar 120 and the right pillar 124) may not exhibit any bending even without any additional mitigation features. For example, the device structure 100 may not have so-called "dummy" pillars between the distribution of steps 102A to L and the adjacent active pillars (e.g., the left pillar 120 and the right pillar 124).

[0060] In other embodiments, for example, a substantially equal balance of material stresses between the effective posts (e.g., the left post 120 and the right post 124) and about the centerline C can substantially reduce the material stresses experienced by the effective posts, such that any bending of the effective posts (without additional relief) can be minimized. This bending can also be substantially equal in both lateral directions of the distribution of steps 102A to L. In other words, the left post 120 can bend a certain amount toward or away from the steps 102A to L (without additional relief), and the right post 124 can bend the same specific amount toward or away from the steps 102A to L, respectively (without additional relief). Therefore, to further mitigate bending, an equal number of dummy posts 122 can be disposed between the distribution of steps 102A to L and laterally adjacent effective posts (e.g., between the steps 102A to L and the left post 120 and between the steps 102A to L and the right post 124). Thus, the substantially symmetrical distribution of steps 102A to L about centerline C and between effective columns (e.g., left column 120 and right column 124) can avoid column bending without including dummy column 122, or can minimize column bending that can be alleviated by equal amounts on both lateral sides of the distribution of steps 102A to L (e.g., by including dummy column 122).

[0061] The configuration of the stairs of the steps of the microelectronic device structure of the embodiments of the present invention can be customized according to the operational needs of the device including such stairs. For example, in some embodiments, the stairs at the bottom of the stairs are stairs formed and arranged as opposing stairs that meet at the base of each stair, thereby forming a "V" shaped opposing stair. In this configuration, (for example, level 108 ( Figure 1C ) defines a step in each of the stairs, and a contact can be formed to one of the steps to electrically connect the conductive layer to another conductive structure of the device.

[0062] In other embodiments, for example, Figure 1B As illustrated in FIG. 1 , steps 102A to L include stairs that are opposite to each other but offset. More specifically, Figure 2A The microelectronic device structure (eg, Figure 1B The base of a staircase (e.g., staircase 102B) of the device structure 100 of FIG. 102B includes stairs (e.g., staircase SC1, staircase SC2) at its bottom, which define steps 202 (e.g., combined with Figure 1B exist Figure 1C Each step 202 exposes a layer 108 ( Figure 1C )'s conductive layer comprises a portion of the upper surface of the conductive material 110.

[0063] Unless otherwise specified, Figure 2A The description of step 102B may also apply to Figure 1B All other stairs 102A to L of and other figures of the present invention having the illustrated stair configuration. For example, Figure 2A The description of step 102B is similar to the description of Figure 1B At least the bottom portion of any one of the steps 102A to L of the staircase SC1, SC2, the difference being that the other of the steps 102A to L has a different number of levels 108 ( Figure 1C ), which depends on the relative depths of the other steps 102A to L.

[0064] In the staircase 102B, the stairs SC1, SC2 are opposite to each other so that the stairs descend toward each other. The stairs SC1, SC2 are also offset from each other. For example, the bottom step 202 of one staircase (e.g., staircase SC1) is at a higher elevation of the stacked structure 106 than the top step 202 of the opposite staircase (e.g., staircase SC2).

[0065] The bridge 118 extends along the rear portion of the ladder 102B, thereby "bridging" each step 202 of the stairs SC1, SC2 and the opposite portion of the top 116 or other portion of the stacked structure 106. Due to the bridge 118, each corresponding level 108 ( Figure 1C ) extends from the left side of step 102B along bridge 118 to the right side of step 102B, thereby forming a continuous electrical path 204 around the perimeter of step 102B. Thus, electrical connection at one of the steps 202 in the first staircase SC1 also provides access to the same level 108 ( Figure 1C ) of the conductive material 110, for example, within the right side top 116. Similarly, electrical connection is also provided at one of the steps 202 in the second staircase SC2 to the same level 108 ( Figure 1C ), for example, under the step 202 of the first staircase SC1. Thus, each step 202 of the stairs SC1, SC2 of this offset stair arrangement can be independently contacted by a contact for electrically connecting the step 202 to another conductive structure of the device. In contrast, in the aforementioned "V" shaped opposing stairs, a pair of steps of the elevation of the non-offset opposing stairs can not be independently electrically contacted by a contact.

[0066] Although Figure 2AThe stair 102B of FIG. 102B is offset to the left from its opposite stair SC1, SC2, with the first stair SC1 having a base (e.g., the lowest point of the stair 202) at a higher elevation than the top (e.g., the highest point of the stair 202) on the right, but in other embodiments, the stair SC1 and SC2 may be opposed and offset in other ways. For example, Figure 2B The stairs 102B' is illustrated with a first higher staircase SC1 on the right side of the stairs 102B' and a second lower staircase SC2 on the left side of the stairs 102B'. Figure 2A The mirror image of ladder 102B Figure 2B The ladder 102B′ of the embodiment of the present invention may replace any or all of the ladders of the embodiment of the present invention (for example, replace Figure 1B Any or all of steps 102A to L).

[0067] The disclosed microelectronic device structure (e.g., having Figure 2A The steps 102A to L of the step 102B described in the configuration have Figure 2B 102B′ as described in the device structure 100 or any of the other step distributions of embodiments of the present invention are advantageously used in, for example, a 3D NAND with a CBSC arrangement. The top and bridge (e.g., top 116 and bridge 118) configuration of the steps 102A to L enables a bidirectional word line that can be centrally driven by a single string driver. This centrally driven bidirectional word line (e.g., of a CBSC arrangement) enables reduced word line resistance and capacitance. At the same time, the generally symmetrical distribution of the steps (e.g., steps 102A to L) of embodiments of the present invention mitigates pillar bending with no or fewer and equal numbers of “dummy” pillars on each side of the distribution of the steps.

[0068] In contrast, it is conceivable that the stairs in a 3D NAND device with a CBSC arrangement (e.g., Figure 1B The asymmetric distribution of the steps 102A to L) is shown in FIG. Figure 2A The offset opposite staircase will also experience unbalanced material stress. In addition, the active column on one lateral side of the step distribution may experience a large amount of material stress manifested as a large degree of column bending, while the other lateral side of the step distribution may experience a smaller amount of material stress manifested as a smaller degree of column bending. For example, by placing a dummy column 122 ( Figure 1B) to mitigate this imbalance and the large amount of pillar bending would require different mitigation treatment (e.g., a different number of dummy pillars 122) for one lateral side of the distribution than for the other lateral side. Also, in structures without symmetrically distributed steps, the mitigation features (e.g., dummy pillars 122) required to mitigate otherwise significant pillar bending may occupy a large area of, for example, the base material 104 (e.g., a wafer), leaving less valuable space for the electrical functional features of the device.

[0069] Thus, a microelectronic device is disclosed, comprising a stacked structure including a vertical alternating sequence of insulating material and conductive material arranged in layers. A first pillar structure and a second pillar structure extend vertically through the stacked structure. A step structure is within the stacked structure and is generally symmetrically distributed between the first pillar structure and the second pillar structure. Each of the step structures includes a staircase structure having steps, the steps including lateral ends of some of the layers.

[0070] refer to Figure 3 , illustrates an embodiment of the present invention in which the stairs of the stairs to the left of the centerline C are horizontally inverted from the stairs of the stairs to the right of the centerline C (e.g., are substantially mirror images thereof). Such a mirrored stair arrangement can increase the general symmetry of the distribution of stairs on both sides. More specifically, Figure 3 The device structure 300 is described, which has Figure 1B The "W"-shaped, generally symmetrically distributed steps are similar in manner, but wherein the steps in the left portion 126 (e.g., steps 102A, 102C, 102E, 102G, 102I, and 102K) are configured similar to Figure 2A 102B, but the steps in the right portion 128 (e.g., steps 102B′, 102D′, 102F′, 102H′, 102J′, and 102L′) are configured with similar Figure 2B The staircase arrangement of steps 102B′.

[0071] As with other device structure embodiments of the present invention, Figure 3 The device structure 300 further includes a top 116 and a bridge 118 ( Figure 1A , Figure 2A , Figure 2B ), so that Figure 1A The top plan cross-sectional view can be compared with Figure 3 300, but with an alternative configuration of stairs having the steps discussed above (e.g., steps 102K, 102I, 102G, 102E, 102C, 102A, 102B′, 102D′, 102F′, 102H′, 102J′, and 102L′, respectively, spanning from left to right).

[0072] and Figure 1B The device structure 100 is the same as that of FIG. Figure 3 The device structure 300 includes steps that are generally symmetrically distributed around the centerline C (and between laterally adjacent effective pillars, such as between the left pillar 120 and the right pillar 124), which have a generally balanced volume of fill material 114 and have a generally balanced material stress. The generally symmetrical distribution of the volume of the fill material 114 can relieve material stress alone, so that dummy pillars 122 may not be required to prevent bending of effective pillars (e.g., the left pillar 120, the right pillar 124). In other embodiments, a minimum and equal number of dummy pillars 122 may be included between the left pillar 120 and its adjacent steps (e.g., step 102K) and between the right pillar 124 and its adjacent steps (e.g., step 102L′).

[0073] Although in other embodiments, Figure 1B The device structure 100 and Figure 3 The device structure 300 of the embodiment of the present invention has generally symmetrically distributed steps, wherein the deepest step is farthest from the center line C (e.g., closest to the active pillar, and thus closest to the vertical array of memory cells), and wherein the step depth decreases with decreasing lateral distance from the center line C (e.g., with increasing lateral distance from the active pillar and thus the vertical array of memory cells), but the steps can be arranged alternately in depth and still be generally symmetrically distributed around the center line C and between adjacent active pillars (e.g., left pillar 120 and right pillar 124), and thus between the vertical array of memory cells. In other words, any other generally symmetrical distribution of the steps can generally balance the volume of the filling material 114 around the center line C (and between adjacent active pillars) so that the material stresses will also be balanced, and the pillar bending can be relieved or mitigated and further mitigated by equal measures on both sides of the step distribution.

[0074] For example, Figure 4The device structure 400 is illustrated wherein steps 402A-L are generally symmetrically distributed about a centerline C (and between adjacent active pillars, e.g., between the left pillar 120 and the right pillar 124), wherein the deepest steps of the distribution are closest to the centerline C, and the shallowest steps of the distribution are closest to the active pillars (e.g., between the left pillar 120 and the right pillar 124). Thus, the left portion 126 includes—in lateral order from the outside to the inside (e.g., from farthest from the centerline C to closest to the centerline C)—steps 402A, 402C, 402E, 402G, 402I, and 402K, wherein step 402A is the shallowest step in the entire step distribution of the device structure 400, and wherein step 402K is the second deepest step in the entire step distribution. Correspondingly, the right portion 128 includes—in lateral order from the outside to the inside (e.g., from farthest from the centerline C to closest to the centerline C)—steps 402B, 402D, 402F, 402H, 402J, and 402L, wherein step 402B is the second shallowest step in the entire step distribution of the device structure 400, and step 402L is the second deepest step in the entire step distribution. Thus, the step distribution may exhibit a so-called “V” shape, wherein the volume of the filling material 114 occupying the steps 402A, 402C, 402E, 402G, 402I, and 402K in the left portion 126 is substantially equal to the volume of the filling material 114 occupying the steps 402B, 402D, 402F, 402H, 402J, and 402L in the right portion 128.

[0075] Any or all of the steps 402A to L may be configured with Figure 2A Ladder 102B or Figure 2B Therefore, Figure 2A Ladder 102B or Figure 2B The description of step 102B′ can also be applied to Figure 4 Any or all of steps 402A to L.

[0076] The device structure 400 also includes the above-mentioned Figure 1B The top 116 and bridge 118 ( Figure 1A ).therefore, Figure 1A The top plan cross-sectional view can be compared with Figure 4 The top plan cross-sectional view of the device structure 400 is the same, but with an alternative arrangement of step depths.

[0077] and Figure 1B The device structure 100 and Figure 3 The device structure 300 is the same as that of the device structure 300. Figure 4The device structure 400 includes steps (e.g., steps 402A to L) that are generally symmetrically distributed around the centerline C (and between laterally adjacent effective pillars, such as between the left pillar 120 and the right pillar 124), which have a generally balanced volume of fill material 114 and have a generally balanced material stress. The generally symmetrical distribution of the steps 402A to L can alleviate material stress alone, so that dummy pillars 122 may not be required to prevent bending of effective pillars (e.g., the left pillar 120, the right pillar 124). In other embodiments, a minimum and equal number of dummy pillars 122 may be included between the left pillar 120 and its adjacent steps (e.g., step 402A) and between the right pillar 124 and its adjacent steps (e.g., step 402B).

[0078] Is to choose and implement Figure 1B and Figure 3 W-shaped ladder distribution or selection and implementation Figure 4 The V-shaped step profile of the step may depend on the relative material stress of the fill material 114 compared to the material stress of the stack structure 106. The profile selected and implemented may be the one that best reduces the amount of residual material stress at the lateral sides of the step profile (e.g., along the Figure 1B The deepest steps 102K and 102L of the device structure 100; along Figure 3 The deepest steps 102K and 102L′ of the device structure 300; or along Figure 4 The shallowest steps 402A and 402B of the device structure 400 are shown in FIG.

[0079] Although Figure 1B , Figure 3 and Figure 4 Embodiments include a distribution in which the steps in each of the left portion 126 and the right portion 128 are arranged in an order of increasing or decreasing depth, but in other embodiments, the step depth may vary (e.g., increase, decrease, and increase again; or decrease, increase, and decrease again) along the width of its distribution or portion (e.g., the left portion 126, the right portion 128), provided that the volume of the filling material 114 within the step in the left portion 126 is substantially equal to the volume of the filling material 114 within the step in the right portion 128.

[0080] For example, Figure 5Device structure 500 is illustrated in which relatively shallow steps are interspersed with relatively deep steps. As illustrated, left portion 126 includes—in lateral order from farthest to closest to centerline C—steps 502K, 502E, 502I, 502C, 502G, and 502A; while right portion 128 includes—in lateral order from farthest to closest to centerline C—steps 502L, 502F, 502J, 502D, 502H, and 502B. As with other embodiments of the present invention, "A" (associated with the step designation) indicates the shallowest step of the distribution, "B" indicates the second shallowest step of the distribution, and so on.

[0081] As with other embodiments of the present invention, the volume of the filling material 114 occupying the steps 502K, 502E, 502I, 502C, 502G, and 502A in the left portion 126 is substantially equal to the volume of the filling material 114 occupying the steps 502L, 502F, 502J, 502D, 502H, and 502B in the right portion 128. Therefore, material stresses can be substantially equal and balanced between the left portion 126 and the right portion 128, and bending of adjacent effective pillars (e.g., the left pillar 120, the right pillar 124) can be avoided or at least alleviated by a minimum and equal number of dummy pillars 122 adjacent to the left portion 126 and adjacent to the right portion 128.

[0082] Any or all of the steps 502A to L may be configured with Figure 2A Ladder 102B or Figure 2B Therefore, Figure 2A Ladder 102B or Figure 2B The description of step 102B′ can also be applied to Figure 5 Any or all of steps 502A to L.

[0083] The device structure 500 also includes the above-mentioned Figure 1A and Figure 1B The top 116 and bridge 118 ( Figure 1A ).therefore, Figure 1A The top plan cross-sectional view can be compared with Figure 5 The top plan cross-sectional view of the device structure 500 is the same, but with an alternative arrangement of step depths.

[0084] Thus, a memory device is disclosed that includes at least two memory cell arrays extending vertically through a stacked structure including layers. Each of the layers includes a conductive structure and an insulating structure. A staircase structure is substantially symmetrically distributed within the stacked structure and horizontally positioned between the at least two memory cell arrays.

[0085] Therefore, according to an embodiment of the present invention, the steps are formed in a stacked structure of vertically alternating insulating and conductive materials. The steps are generally symmetrically distributed; therefore, the volume and material stress of the filling material within the steps (and the material of the stacked structure in which the steps are formed) are generally balanced. Due to the generally balanced material stress, in some embodiments, the laterally adjacent operational effective columns may not exhibit bending at all, thereby avoiding the need to include dummy columns (e.g., non-operating columns) in the device to relieve the material stress that may otherwise cause the column to bend. Therefore, the valuable occupied space that the dummy columns will occupy can be used instead to form a structure or material configured to make a positive contribution to the function and operation of the device. In other embodiments, if—in the case of a symmetrical distribution of steps—the effective columns still exhibit bending in the absence of dummy columns, then due to the generally equal material stress on the two lateral sides of the step distribution, the bending may be minimal and may at least have a generally equal amount of bending. Therefore, in such embodiments, a minimum and equal number of dummy columns may be included on the two lateral sides of the step distribution to alleviate column bending. Therefore, through the embodiments of the present invention, the inclusion of dummy pillars can be avoided, or if the inclusion of dummy pillars cannot be avoided, the dummy pillars can be minimized and kept consistent on both lateral sides of the step distribution, thereby simplifying device design and manufacturing.

[0086] refer to FIG. 6A to FIG. 9 , illustrating various stages of a method of forming a device structure of an embodiment of the present invention, such as Figure 1A , Figure 1B and Figure 1C Device structure 100; Figure 3 The device structure 300, Figure 4 Device structure 400; and / or Figure 5 Device structure 500.

[0087] By vertically alternating insulating material 112 and another material 604 ( Figure 6B ) forms (eg, deposits) a stack of alternating materials 602. The insulating material 112 and the other materials 604 may be formed (eg, deposited) one after another in a repeating sequence to form a layer 606 of the stack of alternating materials 602.

[0088] In some embodiments, another material 604 of the stack of alternating materials 602 may be a material that will eventually be conductive (eg, Figure 1C In other embodiments, the other material 604 is conductive and non-sacrificial when initially formed, so that it is formed as the conductive material 110 ( Figure 1CIn any such embodiment, the insulating material 112 of the stack of alternating materials 602 may be non-sacrificial, such that it remains a component of the final structure of the fabricated device. Figure 1C Insulating material 112.

[0089] A capping material 608 may be formed on the stack of alternating materials 602. The capping material 608 may include, for example, a semiconductor material such as polysilicon.

[0090] Stairs 610 form steps where they are to be located (e.g., Figure 1B Each of the steps 102A to L, Figure 3 Each of the steps 102A to 102L′, Figure 4 Each of the steps 402A to L or Figure 5 The stack of alternating materials 602 is formed (e.g., etched) at each of a number of horizontal positions P1 to P12 of the steps 502A to L of FIG. 602A (e.g., each of the steps 502A to L of FIG. 602A). At this stage, the stairs 610 may be formed as opposing stairs having a "V" shaped arrangement, wherein the bases of each of the opposing stairs meet at the same elevation. A portion of the capping material 608 may remain between each of the positions P1 to P12, the portion of the capping material 608 defining the top portion 612.

[0091] The stairs in which the steps are to be formed will be offset opposite stairs (e.g., similar to Figure 2A Ladder 102B or Figure 2B In the embodiment of the step 102B′), Fig. 6A One side of the stair 610 is further formed (e.g., etched) to lower one of the opposing stairs so that it is vertically offset from the other of the opposing stairs, as in Figure 7 , thereby forming an offset step shape 702 in each of the horizontal positions P1 to P12. The vertical offset also forms Fig. 6A The top portion 612 slightly extends the top portion 704. Therefore, Figure 7 The stage defines the staircase configuration to be included at the bottom of each of the steps to be formed, if not already defined by Fig. 6A If the stages are defined then the stair configuration does not matter.

[0092] refer to Figure 8 , the depth of the steps (e.g., steps 102A to L) can then be defined, for example, by etching to an appropriate respective depth for each of the steps (e.g., steps 102A to L), thereby forming a distribution of trenches at different depths from one another. Fig. 6A ) in each of Figure 7 The corresponding offset step shapes 702 are etched into different depths of the stack of alternating materials 602.

[0093] In some embodiments, each of the steps 102A-L may be deepened to its final depth sequentially, with the first step (e.g., Fig. 6A The shallowest step (e.g., step 102A) is formed (e.g., etched) to a depth of at least one step (e.g., at a horizontal position P6) and then (e.g., at Fig. 6A The depth of the second shallow step (e.g., step 102B) is formed at the horizontal position P7 of Fig. 6A The depth of the deepest step (eg, step 102L) is formed at the horizontal position P12 of the embodiment.

[0094] In other embodiments, all of the steps 102A through L may be simultaneously etched to the depth of the shallowest step (e.g., step 102A). Then, all of the deeper steps (e.g., steps 102B through L) may be simultaneously etched to the depth of the second shallowest step (e.g., step 102B). Then, all of the deeper steps (e.g., steps 102C through L) may be simultaneously etched to the depth of the third shallowest step (e.g., step 102C), and so on, until only the deepest step (e.g., step 102L) is etched to its final depth.

[0095] In other embodiments, the shallowest step (e.g., step 102A) may be Figure 7 The stage is not further etched after, for example, when defining the offset step shape 702 ( Figure 7 ) has formed the shallowest step (e.g., step 102A) at its final depth.

[0096] As in Figure 8 As described in FIG. 1 , the extension depth can define the final shape of the steps (e.g., steps 102A to L) while also forming the top 116 and bridge 118 ( FIG. 14 ) of the microelectronic device for a CBSC arrangement with a 3D NAND Figure 1A ).

[0097] Although Figure 8 Description Formation Figure 1B The W-shaped distribution of steps 102A to L of the device structure 100 of the present invention, but an alternative order or arrangement of the steps of any of the other device structures of the embodiments of the present invention can be formed by adjusting the relative horizontal positions for the respective step depths (e.g., in Figure 7 For example, to form Figure 4 The V-shaped distribution of the steps 402A to L of the device structure 400 is for Figure 1B The shallowest step 102A of the device structure 100 will be at the horizontal position P1 ( Figure 7 ) instead of being formed (e.g., etched) at position P6.

[0098] refer to Fig. 9 , a filling structure 900 may then be formed by filling each of the steps (e.g., steps 102A to L) by forming (e.g., depositing) a filling material 114. In some embodiments, the filling material 114 may be formed (e.g., deposited) to overfill the steps (e.g., steps 102A to L), and then planarized (e.g., by CMP) to expose the capping material 608 at the top of each of the tops 116 through the filling material 114.

[0099] As discussed above, the volume of the fill material 114 in the left portion 126 (e.g., in steps 102A, 102C, 102E, 102G, 102I, and 102K) is substantially equal to the volume of the fill material 114 in the right portion 128 (e.g., in steps 102B, 102D, 102F, 102H, 102J, and 102L) due to the substantially symmetrical distribution of the steps (e.g., steps 102A through L) about the centerline C. Thus, any material stress imbalance between the fill material 114 and the stack of alternating materials 602 in the left portion 126 will be substantially equal to any material stress imbalance between the fill material 114 and the stack of alternating materials 602 in the right portion 128.

[0100] In the formation Fig. 9 After the filling structure 900 is completed, the microelectronic device structure (eg, Figure 1B The device structure 100 is fabricated by alternating a stack of materials 602 with another material 604 ( Figure 6B ) is a sacrificial material, the other material 604 may be removed and replaced with the conductive material 110 ( Figure 1C ) to form a stacked structure 106, wherein the conductive material 110 provides a "replacement gate" for the device structure 100. The so-called "replacement gate" manufacturing process is known in the art and is therefore not described in detail here. Figure 1B The device structure 100 may include a replacement gate structure formed of a conductive material 110, which has replaced Figures 6B to 9 604 of other materials.

[0101] In it Figures 6B to 9 In embodiments where the other material 604 is non-sacrificial, Fig. 9 The filling structure 900 is equivalent to Figure 1B The device structure 100 has a stepped distribution.

[0102] Effective columns (e.g. Figure 1B The left column 120 and the right column 124) and any dummy column 122 (e.g., Figure 1B) may be formed before, during, or after forming the distribution of steps (e.g., steps 102A to L). The contacts may be formed to extend to the steps 202 (e.g., Figure 2A , Figure 2B ), such as by passing through the fill material 114 and / or through a portion of the stack of alternating materials 602 (or such as Figure 1B A contact opening is formed in the stack structure 106 , and then a conductive material is formed (eg, deposited) in the contact opening.

[0103] Thus, a method of forming a microelectronic device is disclosed. The method includes forming a stacked structure. The stacked structure includes a vertically alternating sequence of materials arranged in layers. A step structure is formed and extends vertically to different depths within the stacked structure. Filling material is formed within a trench defined by the step structure. The volume of the filling material in the trench defined by the step structure to a first lateral side of a centerline of a distribution of the step structure is substantially equal to the volume of the filling material in the trench defined by the step structure to a second lateral side of the centerline of the distribution.

[0104] Fig.10 A block diagram of a system 1000 is shown according to an embodiment of the invention, the system 1000 comprising a memory 1002 comprising an array of vertical strings of adjacent substantially symmetrically distributed steps of memory cells (e.g., adjacent active pillars, such as Figure 1B , Figure 3 , Figure 4 and / or Figure 5 Therefore, according to an embodiment of the present invention, the architecture and structure of the memory 1002 may include Figure 1A to Figure 1C The device structure 100, Figure 3 The device structure 300, Figure 4 The device structure 400 and / or Figure 5 One or more of the device structures 500 and may be based on the above, for example, reference FIG. 6A to FIG. 9 The invention can be manufactured by one or more of the methods described.

[0105] The system 1000 may include a controller 1004 operatively coupled to the memory 1002. The system 1000 may also include another electronic device 1006 and one or more peripheral devices 1008. In some embodiments, the other electronic device 1006 may include a device manufactured according to an embodiment of the present invention and according to one or more of the methods described above. Figure 1A to Figure 1C The device structure 100, Figure 3 The device structure 300, Figure 4 The device structure 400 and / or Figure 5One or more of the device structure 500. One or more of the controller 1004, the memory 1002, the other electronic devices 1006, and the peripheral devices 1008 may be in the form of one or more integrated circuits (ICs).

[0106] The bus 1010 provides electrical conductivity and operable communication between and / or among the various components of the system 1000. The bus 1010 may include an address bus, a data bus, and a control bus, each of which is independently configured. Alternatively, the bus 1010 may use wires to provide one or more of address, data, or control, the use of which may be regulated by the controller 1004. The controller 1004 may be in the form of one or more processors.

[0107] Other electronic devices 1006 may include additional memory (e.g., having a memory device manufactured according to an embodiment of the present invention and according to one or more of the methods described above). Figure 1A to Figure 1C The device structure 100, Figure 3 The device structure 300, Figure 4 The device structure 400 and / or Figure 5 1002 and / or other memory structures of the electronic device 1006 may be configured in an architecture other than 3D NAND, such as dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), synchronous graphic random access memory (SGRAM), double data rate dynamic memory ram (DDR), double data rate SDRAM, and / or magnetic-based memory (e.g., spin transfer torque magnetic RAM (STT-MRAM)).

[0108] Peripheral devices 1008 may include displays, imaging devices, printing devices, wireless devices, additional storage memory, and / or control devices that may operate in conjunction with controller 1004 .

[0109] System 1000 may include, for example, fiber optic systems or devices, electro-optical systems or devices, optical systems or devices, imaging systems or devices, and information handling systems or devices (eg, wireless systems or devices, telecommunication systems or devices, and computers).

[0110] Thus, a system is disclosed that includes a three-dimensional memory; at least one processor that is in operable communication with the three-dimensional memory device; and at least one peripheral device that is in operable communication with the at least one processor. The three-dimensional memory device includes: a vertical memory cell array along a pillar structure that extends vertically through a stacked structure that includes a vertical alternating sequence of insulating material and conductive material. Step structures are within the stacked structure and are generally symmetrically distributed between the vertical memory cell arrays. Each of the step structures extends to a different depth within the stacked structure. Filling material is adjacent to each of the step structures. The total volume of the filling material disposed to a first lateral side of a centerline of the distribution of the step structures is generally equal to the total volume of the filling material disposed to a second lateral side of the centerline. The centerline is between the vertical memory cell arrays and equidistant from the vertical memory cell arrays.

[0111] Non-limiting example embodiments may include the following, alone or in combination:

[0112] Embodiment 1: A microelectronic device, comprising: a stacked structure comprising a vertically alternating sequence of insulating materials and conductive materials arranged in layers; a first column structure extending vertically through the stacked structure; a second column structure extending vertically through the stacked structure; and a step structure within the stacked structure and substantially symmetrically distributed between the first column structure and the second column structure, and each of the step structures comprises a stair structure having steps, wherein the steps include lateral ends of some of the layers.

[0113] Embodiment 2: The microelectronic device of Embodiment 1, wherein each of the stepped structures extends to a different depth within the stacked structure than each other of the stepped structures.

[0114] Embodiment 3: A microelectronic device according to any one of Embodiments 1 or 2, wherein each of the step structures includes a first one of the stair structures, the first one of the stair structures being vertically offset from a second one of the stair structures.

[0115] Embodiment 4: The microelectronic device according to any one of Embodiments 1 to 3, further comprising a bridge structure, the bridge structure comprising some of the insulating materials and some of the conductive materials of the stacked structure, the bridge structure extending horizontally along a rear portion of the stepped structure.

[0116] Embodiment 5: A microelectronic device according to any one of embodiments 1 to 4, wherein some of the step structures adjacent to the center line of the substantially symmetrical distribution are relatively shallower than other of the step structures adjacent to the first column structure, and relatively shallower than other of the step structures adjacent to the second column structure.

[0117] Embodiment 6: A microelectronic device according to any one of embodiments 1 to 4, wherein some of the step structures adjacent to the center line of the substantially symmetrical distribution are relatively deeper than other of the step structures adjacent to the first column structure, and relatively deeper than other of the step structures adjacent to the second column structure.

[0118] Embodiment 7: The microelectronic device of any one of Embodiments 1 to 6, further comprising a dielectric filling material adjacent to the staircase structure of each of the step structures.

[0119] Embodiment 8: A memory device comprising: at least two memory cell arrays extending vertically through a stacked structure comprising layers, each of the layers comprising a conductive structure and an insulating structure; and a substantially symmetrical distribution of step structures positioned within the stacked structure and horizontally between the at least two memory cell arrays.

[0120] Embodiment 9: The memory device of Embodiment 8, further comprising a filling material within the trenches defined by the stepped structure.

[0121] Embodiment 10: A memory device according to any one of Embodiments 8 or 9, wherein, in the distributed stepped structures, the stepped structures of an array relatively close to the at least two arrays have a relatively larger vertical depth than the stepped structures relatively far from the at least two memory cell arrays.

[0122] Embodiment 11: A memory device according to any one of Embodiments 8 or 9, wherein, in the distributed stepped structures, the stepped structures of an array relatively close to the at least two arrays have a relatively smaller vertical depth than the stepped structures relatively far from the at least two memory cell arrays.

[0123] Embodiment 12: The memory device according to any one of embodiments 8 or 9, wherein, in the distributed step structures, step structures with relatively smaller vertical depths are horizontally interspersed with step structures with relatively larger vertical depths.

[0124] Embodiment 13: The memory device of any of Embodiments 8-12, further comprising an electrically inoperable pillar structure adjacent to the substantially symmetrical distribution of the step structures.

[0125] Embodiment 14: The memory device of Embodiment 13, wherein the number of the electrically inoperable pillar structures adjacent to the substantially symmetrically distributed first lateral side of the step structure is equal to the number of the electrically inoperable pillar structures adjacent to the substantially symmetrically distributed second lateral side.

[0126] Embodiment 15: A method for forming a microelectronic device, the method comprising: forming a stacked structure comprising a vertically alternating sequence of materials arranged in layers; forming a stepped structure extending vertically to different depths within the stacked structure; and forming a filling material within a groove defined by the stepped structure, the volume of the filling material in the groove defined by the stepped structure to a first lateral side of a center line of a distribution of the stepped structure being substantially equal to the volume of the filling material in the groove defined by the stepped structure to a second lateral side of the center line of the distribution.

[0127] Embodiment 16: The method of Embodiment 15, wherein forming the stacked structure comprising the vertically alternating sequence of materials arranged in layers comprises forming insulating materials that vertically alternate with sacrificial materials.

[0128] Embodiment 17: The method of Embodiment 16, further comprising replacing the sacrificial material with a conductive material to form a conductive structure.

[0129] Embodiment 18: The method of Embodiment 17, wherein replacing the sacrificial material with the conductive material follows forming the fill material within the trench defined by the stepped structure.

[0130] Embodiment 19: A method according to any one of embodiments 15 to 18, wherein forming the step structure extending vertically to the different depths within the stacked structure comprises: forming a stair structure at different horizontal positions along the stacked structure; and extending the stair structure to the different depths at at least some of the different horizontal positions.

[0131] Embodiment 20: The method of Embodiment 19, wherein forming the stair structure comprises forming a pair of opposing stair structures at each of the different horizontal locations along the stair structure.

[0132] Embodiment 21: A method according to Embodiment 20, wherein forming the stair structure further comprises extending one of the pair of opposing stair structures at at least some of the different horizontal positions along the stair structure so that the one stair structure is vertically offset from the other of the pair.

[0133] Embodiment 22: The method of Embodiment 20, wherein said extending said one of said pair of opposing stair structures to vertically offset said one stair structure from the other of said pair is prior to said extending said stair structure to said different depth.

[0134] Embodiment 23: The method of any one of Embodiments 15 to 22, wherein forming the stacked structure comprising the vertically alternating sequence of the materials arranged in layers comprises forming an oxide material vertically interleaved with a nitride material.

[0135] Embodiment 24: A system comprising: a three-dimensional memory; at least one processor in operable communication with the three-dimensional memory device; and at least one peripheral device in operable communication with the at least one processor. The three-dimensional memory device comprises: a vertical memory cell array along a pillar structure extending vertically through a stack structure comprising a vertical alternating sequence of insulating material and conductive material; a step structure within the stack structure and substantially symmetrically distributed between the vertical memory cell arrays, each of the step structures extending to a different depth within the stack structure; and a fill material adjacent to each of the step structures, the total volume of the fill material disposed to a first lateral side of a center line of the distribution of the step structures being substantially equal to the total volume of the fill material disposed to a second lateral side of the center line, the center line being between and equidistant from the vertical memory cell arrays.

[0136] Embodiment 25: The system of Embodiment 24, wherein the three-dimensional memory device further comprises dummy pillar structures, the number of the dummy pillar structures disposed to the first lateral side of the centerline being equal to the number of the dummy pillars disposed to the second lateral side of the centerline.

[0137] Embodiment 26: The system according to any one of Embodiments 24 or 25, wherein, in the step structures, the step structures relatively close to the center line are relatively shallower than the step structures relatively far from the center line.

[0138] Embodiment 27: The system according to any one of Embodiments 24 or 25, wherein, in the step structures, the step structures relatively close to the center line are relatively deeper than the step structures relatively far from the center line.

[0139] Although the disclosed structures, apparatuses (e.g., devices), systems, and methods are susceptible to various modifications and alternative forms of implementation, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the present invention is not intended to be limited to the specific forms disclosed. Rather, the present invention encompasses all modifications, combinations, equivalents, variations, and substitutes that fall within the scope of the present invention as defined by the following appended claims and their legal equivalents.

Claims

1. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of insulating and conductive materials arranged in layers; a first column structure extending vertically through the stacked structure; a second column structure extending vertically through the stacked structure; and At least one row of step structures, within the stacked structure, the step structures in each row of the at least one row are spaced apart from each other in the horizontal direction by the top portion of the stacked structure, the step structures are collectively and substantially symmetrically distributed between the first column structure and the second column structure in the horizontal direction, each of the step structures includes a stair structure having steps, and the steps include lateral ends of some of the levels. 2 . The microelectronic device of claim 1 , wherein each of the stepped structures extends to a different depth within the stacked structure than each other of the stepped structures. 3 . The microelectronic device of claim 1 , wherein each of the step structures comprises a first one of the stair structures that is vertically offset from a second one of the stair structures. 4 . The microelectronic device of claim 1 , further comprising a bridge structure including some of the insulating material and some of the conductive material of the stacked structure, the bridge structure extending horizontally along a rear portion of the stepped structure.

5. A microelectronic device according to any one of claims 1 to 4, wherein some of the step structures adjacent to the center line of the substantially symmetrical distribution are relatively deeper than other of the step structures adjacent to the first pillar structure, and relatively deeper than other of the step structures adjacent to the second pillar structure.

6. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of insulating and conductive materials arranged in layers; a first column structure extending vertically through the stacked structure; a second column structure extending vertically through the stacked structure; at least one row of step structures, within the stacked structure, the step structures of each row of the at least one row being spaced apart from each other in the horizontal direction by a top portion of the stacked structure, the step structures being collectively and substantially symmetrically distributed between the first column structure and the second column structure in the horizontal direction, each of the step structures comprising a staircase structure having steps, the steps comprising lateral ends of some of the levels; and A dielectric fill material is adjacent to the stair structure of each of the step structures.

7. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of insulating and conductive materials arranged in layers; a first column structure extending vertically through the stacked structure; a second column structure extending vertically through the stacked structure; and step structures within the stacked structure and generally symmetrically distributed between the first column structure and the second column structure, each of the step structures comprising a staircase structure having steps, the steps comprising lateral ends of some of the levels, Some of the step structures adjacent to the centerline of the substantially symmetrical distribution are relatively shallower than others of the step structures adjacent to the first pillar structure, and relatively shallower than others of the step structures adjacent to the second pillar structure.

8. A memory device comprising: at least two memory cell arrays extending vertically through a stacked structure comprising layers, each of the layers comprising a conductive structure and an insulating structure; and The stair structures are substantially symmetrically distributed, located within the stack structure and along a horizontal direction and extending between the at least two memory cell arrays, and the stair structures are spaced apart from each other in the horizontal direction by a top portion of the stack structure.

9. A memory device comprising: at least two memory cell arrays extending vertically through a stacked structure comprising layers, each of the layers comprising a conductive structure and an insulating structure; a substantially symmetrical distribution of stair structures positioned within the stacked structure and in a horizontal direction and extending between the at least two memory cell arrays, the stair structures being spaced apart from each other in the horizontal direction by a top portion of the stacked structure; and A filling material is provided in the trench defined by the step structure.

10. The memory device according to claim 8, wherein: In the distributed stepped structures, the stepped structure of an array relatively close to the at least two arrays has a relatively greater vertical depth than the stepped structure relatively far from the at least two memory cell arrays.

11. The memory device according to claim 8, wherein: In the distributed stepped structures, the stepped structure of an array relatively close to the at least two arrays has a relatively smaller vertical depth than the stepped structure relatively far from the at least two memory cell arrays.

12. The memory device according to claim 8, wherein: In the distributed step structures, step structures with relatively smaller vertical depths are horizontally interspersed with step structures with relatively larger vertical depths.

13. The memory device of any one of claims 8-12, further comprising an electrically inoperable pillar structure adjacent the substantially symmetrical distribution of the step structures.

14. A memory device comprising: at least two memory cell arrays extending vertically through a stacked structure comprising layers, each of the layers comprising a conductive structure and an insulating structure; a substantially symmetrical distribution of staircase structures within the stacked structure and horizontally positioned between the at least two memory cell arrays; an electrically inoperable pillar structure adjacent said substantially symmetrical distribution of said step structures, The number of the electrically inoperable pillar structures adjacent to the substantially symmetrically distributed first lateral side of the step structure is equal to the number of the electrically inoperable pillar structures adjacent to the substantially symmetrically distributed second lateral side.

15. A method of forming a microelectronic device, the method comprising: forming a stacked structure comprising a vertically alternating sequence of materials arranged in layers; forming a stepped structure extending vertically to different depths within the stacked structure; and A filling material is formed in the groove defined by the step structure, and the volume of the filling material in the groove defined by the step structure to a first lateral side of a center line of the distribution of the step structure is substantially equal to the volume of the filling material in the groove defined by the step structure to a second lateral side of the center line of the distribution. 16 . The method of claim 15 , wherein forming the stacked structure comprising the vertically alternating sequence of materials arranged in layers comprises forming insulating materials that vertically alternate with sacrificial materials.

17. The method of claim 16, further comprising replacing the sacrificial material with a conductive material to form a conductive structure.

18. The method of claim 17, wherein replacing the sacrificial material with the conductive material follows forming the fill material within the trench defined by the stepped structure.

19. The method of any one of claims 15 to 18, wherein forming the stepped structure extending vertically to the different depths within the stacked structure comprises: forming stair structures at different levels along the stacked structure; and At at least some of the different horizontal positions, the stair structure is extended to the different depths.

20. The method of claim 19, wherein forming the stair structure comprises forming a pair of opposing stair structures at each of the different horizontal locations along the stacked structure.

21. The method of claim 20, wherein forming the stair structure further comprises extending one of the pair of opposing stair structures at at least some of the different horizontal locations along the stacked structure so that the one stair structure is vertically offset from the other of the pair of opposing stair structures.

22. The method of claim 20, wherein said extending one of said pair of opposing stair structures to vertically offset said one stair structure from the other of said pair of opposing stair structures is prior to said extending said stair structures to said different depths.

23. The method of any one of claims 15 to 18, wherein forming the stacked structure comprising the vertically alternating sequence of the materials arranged in layers comprises forming an oxide material vertically interleaved with a nitride material.

24. An electronic system comprising: A three-dimensional memory device comprising: a vertical array of memory cells along a pillar structure extending vertically through a stacked structure comprising a vertical alternating sequence of insulating material and conductive material; stair structures within the stacked structure and substantially symmetrically distributed between the vertical memory cell arrays, each of the stair structures extending to a different depth within the stacked structure; and a fill material adjacent to each of the stepped structures, a total volume of the fill material disposed to a first lateral side of a centerline of a distribution of the stepped structures being substantially equal to a total volume of the fill material disposed to a second lateral side of the centerline, the centerline being between and equidistant from the vertical memory cell arrays; at least one processor in operable communication with the three-dimensional memory device; and At least one peripheral device is in operable communication with the at least one processor.

25. The electronic system of claim 24, wherein the three-dimensional memory device further comprises dummy pillar structures, the number of the dummy pillar structures disposed to the first lateral side of the centerline being equal to the number of the dummy pillars disposed to the second lateral side of the centerline.

26. The electronic system according to any one of claims 24 or 25, wherein: In the step structures, the step structures relatively close to the center line are relatively shallower than the step structures relatively far from the center line.

27. The electronic system according to any one of claims 24 or 25, wherein: In the step structures, the step structures relatively close to the center line are relatively deeper than the step structures relatively far from the center line.

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