Semiconductor device and method of integrating a passive device

Abstract

The application discloses a kind of integrated passive device semiconductor devices, comprising: substrate;At least one integrated passive device, including one or more formed in the resistance, capacitance or inductance of substrate surface;RDL (redistribution layer) is arranged on the surface of substrate and at least one integrated passive device;Wherein, RDL includes at least one metal layer to form layer winding inductance.The present application combines the existing semiconductor integrated passive device process with the packaging RDL (redistribution layer) process, breaks through the limit of mature process thick metal layer of integrated circuit, and the limit of limited metal thickness, and the combination of RDL process increases 1-3 layers of wireable metal layer and the metal thickness can be thicker, forms more abundant laminated structure, to realize layer winding inductance and connection wiring function, improves the design flexibility of passive integrated device, improves the performance and integration of integrated passive device.

Description

Technical Field

[0001] This invention relates to the field of integrated passive device technology, and more particularly to a semiconductor device and method for integrating passive devices. Background Technology

[0002] like Figure 5 As shown, existing integrated passive device processes employ semiconductor back-end-of-line (BILO) technology to fabricate resistors, capacitors, and inductors, thereby realizing passive devices such as filters, power dividers, and couplers. However, this process involves a limited number of metal layers, typically 1-2 layers, resulting in excessively large areas for winding planar two-dimensional inductors or insufficient turns for winding longitudinal helical inductors. This makes it impossible to fabricate high-performance inductors. Furthermore, the limited thickness of the electroplated metal, based on existing mature integrated circuit processes, leads to small metal cross-sections, high unit resistance, and high line losses, resulting in poor inductor performance and thus affecting the overall performance of passive devices.

[0003] Therefore, it is necessary to propose further solutions to the above problems. Summary of the Invention

[0004] The present invention aims to provide a semiconductor device and method for integrating passive components to overcome the shortcomings of the prior art.

[0005] To solve the above-mentioned technical problems, one technical solution of the present invention is:

[0006] A semiconductor device integrating passive components, comprising:

[0007] Substrate;

[0008] At least one integrated passive device includes one or more of a resistor, capacitor, or inductor formed on the surface of the substrate;

[0009] A redistribution layer is disposed on the surface of the substrate on which the at least one integrated passive device is disposed;

[0010] The redistribution layer includes at least one metal layer to form a layer-wound inductor.

[0011] In a preferred embodiment of the present invention, the substrate is high-resistivity silicon or glass.

[0012] In a preferred embodiment of the present invention, the rewiring layer uses wire bonding, balling, or BUMP processes to bring out signals.

[0013] In a preferred embodiment of the present invention, the integrated passive device includes an inductor, and the metal layer of the redistribution layer is located directly above the inductor, with a deviation not exceeding 10% of the minimum linewidth of the inductor wound on the metal layer.

[0014] In a preferred embodiment of the present invention, the thickness of the dielectric layer closest to the integrated passive device and the redistribution layer is 3-5 μm.

[0015] Another technical solution of the present invention is:

[0016] An integrated passive device process utilizing a redistribution layer to enhance performance includes:

[0017] S100 forms at least one integrated passive device on the substrate;

[0018] S200 forms a redistribution layer on the surface of the substrate where an integrated passive device is formed;

[0019] The redistribution layer includes at least one metal layer to form a layer-wound inductor.

[0020] In a preferred embodiment of the present invention, S100 forms at least one integrated passive device on a substrate, including:

[0021] S101 forms a resistive layer on a substrate through metal sputtering, photolithography, and ion etching processes, and then deposits a first dielectric layer on it.

[0022] S102 etches a first via on the first dielectric layer using photolithography and etching processes, wherein the first via exposes a portion of the substrate and a portion of the resistive layer.

[0023] S103 deposits a first metal layer on the first dielectric layer, and the first metal layer is connected to the substrate and the resistor layer through a first via. The pattern of the first metal layer is etched out by photolithography and etching processes to serve as the bottom plate of the capacitor. A second dielectric layer is deposited on the surface of the first metal layer to serve as the dielectric layer of the capacitor.

[0024] S104 deposits a second metal layer on the second dielectric layer, and etches the pattern of the second metal layer as the bottom plate of the capacitor through photolithography and etching processes, and deposits a third dielectric layer on it.

[0025] S105 etches a second via on the third dielectric layer using photolithography and etching processes, wherein the second via exposes part of the second metal layer, and the third metal layer pattern is further etched on it using photolithography and etching processes.

[0026] S106 sputters the second through-hole and the third metal layer seed layer through a metal sputtering process, completes the second through-hole and the third metal layer together through an electroplating process, and finally completes the wafer surface flattening through chemical mechanical polishing and deposits the fourth dielectric layer on it.

[0027] S107 repeats S105-S106 to complete the fabrication of the third via and the fourth metal layer. A fifth dielectric layer is deposited on the surface of the fourth metal layer. The fourth via is etched on the fifth dielectric layer through photolithography and etching processes.

[0028] In a preferred embodiment of the present invention, step S200, which involves forming a redistribution layer on the surface of the substrate where an integrated passive device is formed, includes:

[0029] S201 forms the seventh dielectric layer by spin coating on the fifth dielectric layer, and etches the fifth through hole at the corresponding position of the fourth through hole by photolithography.

[0030] S202 performs metal electroplating on the seventh dielectric layer to form a thicker metal layer, and completes the fabrication of the sixth metal layer through photolithography, development and etching processes. The sixth metal layer is connected to the fourth metal layer through the fifth through hole and the fourth through hole.

[0031] S203 spin-coated an eighth dielectric layer on the surface of the sixth metal layer, and etched the sixth through hole at the corresponding location of the fourth through hole by photolithography.

[0032] S204 repeats S202 to form the seventh metal layer. The bonding process is then transferred to S205, and the ball-planting process is transferred to S206.

[0033] S205 spin-coats a ninth dielectric layer on the surface of the seventh metal layer and etches a seventh via, in which a portion of the seventh metal layer is exposed. An eighth metal layer is then fabricated within the seventh via using metal plating and etching processes to serve as a pad.

[0034] The S206BUMP process uses the seventh metal layer as a UBM, and copper pillars, BUMPs, or implanted beads are electroplated onto the seventh metal layer through an electroplating process.

[0035] In a preferred embodiment of the present invention, the back side of the substrate is further thinned in step S207.

[0036] In a preferred embodiment of the present invention, the seventh, eighth and ninth dielectric layers are made of PI or BCB.

[0037] In a preferred embodiment of the present invention, the substrate is made of high-resistivity silicon or glass.

[0038] In a preferred embodiment of the present invention, the sixth metal layer is located directly above the fourth metal layer, and the deviation does not exceed 10% of the minimum linewidth of the inductor wound on the sixth metal layer.

[0039] In a preferred embodiment of the present invention, the thickness of the fifth dielectric layer is 3-5 μm.

[0040] In a preferred embodiment of the present invention, the thickness of the seventh dielectric layer and the eighth dielectric layer is 5-10 μm.

[0041] Compared with the prior art, the beneficial effects of the present invention are:

[0042] This invention combines existing semiconductor integrated passive device technology with packaging RDL (rewiring layer) technology, overcoming the limitations of mature integrated circuit technology in terms of the limited number of thick metal layers and the limited metal thickness. The combination with RDL technology adds 1-3 wireable metal layers with a relatively thicker metal thickness, forming a richer stack-up structure. This enables layer-wound inductors and connection wiring functions, improving the design flexibility of passive integrated devices and enhancing the performance and integration density of integrated passive devices. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of a semiconductor device integrating passive components according to an embodiment of the present invention;

[0045] Figure 2 This is a schematic diagram of a semiconductor device integrating passive components according to another embodiment of the present invention;

[0046] Figure 3 This is a process flow diagram of the S100 process of the integrated passive device process utilizing the redistribution layer to enhance performance according to the present invention.

[0047] Figure 4 This is an S200 process flow diagram of the integrated passive device process utilizing the redistribution layer to enhance performance according to the present invention.

[0048] Figure 5 A schematic diagram of a traditional integrated passive device;

[0049] Figure 6 A schematic diagram of an integrated passive device fabricated using the integrated passive device process for enhancing performance with a rewiring layer according to the present invention;

[0050] Figure 7 This is a comparison chart of insertion loss, where the solid line represents the process using the present invention, and the dashed line represents the process using IPD.

[0051] Figure 8 The diagram shows a comparison of frequency band suppression, where the solid line represents the process of this invention and the dashed line represents the process of IPD.

[0052] Specifically, 100, substrate;

[0053] 200. Integrated passive device;

[0054] 300. Rewire layer;

[0055] 211. Resistive layer;

[0056] 221. First dielectric layer; 222. Second dielectric layer; 223. Third dielectric layer; 224. Fourth dielectric layer; 225. Fifth dielectric layer; 327. Seventh dielectric layer; 328. Eighth dielectric layer; 329. Ninth dielectric layer;

[0057] 231. First through hole; 232. Second through hole; 233. Third through hole; 234. Fourth through hole; 335. Fifth through hole; 336. Sixth through hole; 337. Seventh through hole;

[0058] 241. First metal layer; 242. Second metal layer; 243. Third metal layer; 244. Fourth metal layer; 346. Sixth metal layer; 347. Seventh metal layer; 348. Eighth metal layer;

[0059] 361. BUMP. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein. Therefore, the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0062] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0063] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0064] Example 1: As Figure 1 As shown, a semiconductor device integrating passive components includes:

[0065] Substrate 100 may be high-resistivity silicon or glass, but is not limited thereto.

[0066] At least one integrated passive device 200 includes one or more of a resistor, capacitor or inductor formed on the surface of the substrate 100.

[0067] A redistribution layer 300 is disposed on the surface of a substrate 100 on which at least one integrated passive device 200 is formed. The redistribution layer 300 includes at least one metal layer to form a layer-wound inductor. It is understood that to form a layer-wound inductor, the metal layer is in a horizontally coiled spiral shape, for example... Figure 7 .

[0068] like Figure 1 and Figure 2 As shown, the redistribution layer 300 can use wire bonding, ball bonding, or BUMP technology to bring out signals.

[0069] Preferably, the integrated passive device 200 includes an inductor, and the metal layer of the redistribution layer 300 is located directly above the inductor. The integrated passive device 200 and the redistribution layer 300 must be vertically aligned, and the process alignment error should not exceed 10% of the minimum linewidth of the inductor wound on the sixth metal layer 346 of the redistribution layer 300, in order to reduce the impact on the consistency of device performance. Furthermore, the thickness of the dielectric layer closest to the integrated passive device 200 and the redistribution layer 300 is 3-5 μm.

[0070] like Figure 1 and Figure 2As shown, specifically, this device includes, from bottom to top, a substrate 100, a resistor layer 211, a first dielectric layer 221, a first metal layer 241, a second dielectric layer 222, a second metal layer 242, a third dielectric layer 223, a third metal layer 243, a fourth dielectric layer 224, a fourth metal layer 244, a fifth dielectric layer 225, a seventh dielectric layer 327, a sixth metal layer 346, an eighth dielectric layer 328, a seventh metal layer 347, and a BUMP (bump) 361 or a ninth dielectric layer 329 or an eighth metal layer 348 disposed on the seventh metal layer 347.

[0071] The first metal layer 241 is connected to the substrate 100 and the resistor through a first through-hole 231 disposed on the first dielectric layer 221; the third metal layer 243 is connected to the second metal layer 242 through a second through-hole 232 disposed on the third dielectric layer 223; the fourth metal layer 244 is connected to the third metal layer 243 through a third through-hole 233 disposed on the fourth dielectric layer 224; the sixth metal layer 346 is connected to the fourth metal layer 244 through a fifth through-hole 335 and a fourth through-hole 234 disposed on the seventh dielectric layer 327; the seventh metal layer 347 is connected to the sixth metal layer 346 through a sixth through-hole 336 disposed on the eighth dielectric layer 328; and the eighth metal layer 348 is connected to the seventh metal layer 347 through a seventh through-hole 337 disposed on the ninth dielectric layer 329, and the eighth metal layer 348 is disposed within the seventh through-hole 337.

[0072] Example 2:

[0073] First, a brief introduction to some of the processes used.

[0074] Photolithography: Photolithography is a process technology that uses the principles of optical-chemical reaction and chemical and physical etching methods to transfer circuit patterns to the surface of a dielectric layer to form effective graphic windows or functional patterns.

[0075] Sputtering process: Magnetron sputtering is a type of physical vapor deposition. Ar ions are accelerated towards the cathode target under the influence of an electric field, and bombard the target surface with high energy. This gives the atoms or molecules near the solid surface enough energy to eventually escape from the solid surface, causing the target material to be sputtered. In the sputtered particles, neutral target atoms or molecules are deposited on the substrate to form a thin film.

[0076] Electroplating process: Copper electroplating is the process of depositing a layer of copper onto certain solid surfaces using the principle of electrolysis. A metal wire is used to interconnect the positive and negative terminals of a power supply with the anode and cathode of the plating tank, creating an electric field between the two electrodes. Under the influence of this electric field, cations flow to the cathode, and anions flow to the anode. The cations are deposited on the cathode surface to form a plating layer. Generally, before electroplating, a seed layer needs to be sputtered onto the substrate surface to facilitate the loading of current onto the plating electrodes. First, a seed layer of Ti / Cu is sputtered onto the wafer surface, followed by thick photoresist lithography to serve as the electroplating mold. Copper is then electroplated to form copper wires. After removing the photoresist and etching the seed layer, the copper wiring is obtained.

[0077] An integrated passive device process utilizing a redistribution layer 300 to enhance performance includes:

[0078] S100 forms at least one integrated passive device 200 on substrate 100.

[0079] In this process, surface treatment is performed on a wafer 100 with a substrate such as high-resistivity silicon or glass. The integrated passive device 200 includes one or more of a resistor, capacitor, or inductor formed on the surface of the substrate 100.

[0080] S200 forms a redistribution layer 300 on the surface of the integrated passive device 200 formed on the substrate 100.

[0081] The redistribution layer 300 includes at least one metal layer to form a layer-wound inductor. It is understood that to form the layer-wound inductor, the metal layer is in a horizontally coiled spiral shape, for example... Figure 5 and Figure 6 .

[0082] The redistribution layer 300 can use wire bonding, ball bonding, or BUMP technology to bring out signals.

[0083] The integrated passive device 200 includes an inductor, and the metal layer of the redistribution layer 300 is located directly above the inductor, with a deviation not exceeding 10% of the minimum linewidth of the inductor wound on the sixth metal layer 346 of the redistribution layer 300.

[0084] like Figure 3 As shown, preferably, S100 forms at least one integrated passive device 200 on the substrate 100, including:

[0085] S101 forms a resistive layer 211 on the substrate 100 through metal sputtering, photolithography and ion etching processes, and deposits a first dielectric layer 221 on it.

[0086] Specifically, the resistive target material is bombarded with ions using a metal sputtering process, causing the resistive material to fall uniformly and be densely deposited on the surface of the substrate 100. The resistive layer 211 pattern is transferred to the wafer surface using a photolithography process, and then the resistive layer 211 is etched using an ion etching method. An oxide dielectric layer is then deposited on it to form the first dielectric layer 221.

[0087] S102 etches a first via 231 on the first dielectric layer 221 through photolithography and etching processes, wherein the first via 231 exposes part of the substrate 100 and part of the resistor layer 211, that is, the first via 231 of the resistor and the first metal layer 241 is etched.

[0088] S103 deposits a first metal layer 241 on the first dielectric layer 221, and the first metal layer 241 is connected to the substrate 100 and the resistor layer 211 through the first via 231. The pattern of the first metal layer 241 is etched out by photolithography and etching processes to serve as the bottom plate of the capacitor, and a second dielectric layer 222 is deposited on the surface of the first metal layer 241 to serve as the dielectric layer of the capacitor.

[0089] Specifically, a thin metal is deposited on the wafer surface, and the metal layer pattern is etched out by photolithography and etching processes to serve as the bottom plate of the capacitor, namely the first metal layer 241. A dense dielectric layer is deposited on the metal surface to serve as the dielectric layer of the capacitor, namely the second dielectric layer 222.

[0090] S104 deposits a second metal layer 242 on the second dielectric layer 222, and etches the pattern of the second metal layer 242 as the bottom plate of the capacitor through photolithography and etching processes, and deposits a third dielectric layer 223 on it.

[0091] Specifically, a thin metal is deposited on the wafer surface, and the metal layer pattern is etched out by photolithography and etching processes to form the bottom plate of the capacitor, that is, to form the second metal layer 242, and a thicker dielectric layer is deposited on it to form the third dielectric layer 223.

[0092] S105 etches a second via 232 on the third dielectric layer 223 using photolithography and etching processes. The second via 232 exposes part of the second metal layer 242, and the third metal layer 243 pattern is further etched on it using photolithography and etching processes.

[0093] Specifically, the second through-hole 232 of the second metal layer 242-the third metal layer 243 is etched on the third dielectric layer 223 by photolithography and etching processes, and the pattern of the third metal layer 243 is further etched on it by photolithography and etching processes.

[0094] S106 sputters the second via 232 and the third metal layer 243 seed layer through a metal sputtering process, completes the second via 232 and the third metal layer 243 together through an electroplating process, and finally completes the wafer surface flattening through chemical mechanical polishing, and deposits the fourth dielectric layer 224 on it.

[0095] Specifically, the second via 232 and the third metal layer 243 seed layer are sputtered by metal sputtering process, and the second via 232 and the third metal layer 243 are completed by electroplating process. Finally, the wafer surface is flattened by CMP (chemical mechanical polishing), and a thicker dielectric layer is deposited on it as the fourth dielectric layer 224.

[0096] S107 repeats S105-S106 to complete the fabrication of the third via 233 and the fourth metal layer 244. A fifth dielectric layer 225 is deposited on the surface of the fourth metal layer 244, and the fourth via 234 is etched on it.

[0097] Specifically, S105-S106 are repeated to complete the fabrication of the third via 233 and the fourth metal layer 244 of the third metal layer 243-fourth metal layer 244. A dense dielectric layer is deposited on the surface of the fourth metal layer 244 as the fifth dielectric layer 225, and the fourth via 234 is etched on it.

[0098] The above steps can be used to manufacture passive integrated circuit devices (IPDs) that include high-precision resistors, capacitors, and inductors.

[0099] like Figure 4 As shown, preferably, in step S200, a redistribution layer 300 is formed on the surface of the integrated passive device 200 on the substrate 100, including the following steps. For clarity, the substrate 100 is used instead of the product before step S107. It is worth noting that the fifth dielectric layer 225 in the IPD step S107 needs to be improved accordingly, specifically by increasing the thickness of the fifth dielectric layer 225 from less than 1 μm to 3 μm to 5 μm, while strictly controlling the error to be less than 10% of the fifth dielectric layer thickness, in order to reduce the impact on performance consistency. It can be understood that this step continues manufacturing after improving the thickness of the fifth dielectric layer 225 on the chip surface based on the previous step S107. Improving the thickness of the fifth dielectric layer 225 on the chip surface has the following advantages: First, a thicker surface dielectric layer can protect the wafer surface of the integrated passive device S100, which is terminated earlier. To avoid damage to the circuits fabricated in the S100 process on the wafer surface during the switching between integrated circuit process IPD and packaging redistribution RDL processes; secondly, to increase the thickness of the fifth dielectric layer 225, which, together with the seventh dielectric layer 327, can increase the dielectric thickness between the fourth metal layer 244 and the sixth metal layer 346, thereby controlling parasitic coupling between metals.

[0100] S201 forms a seventh dielectric layer 327 by spin coating on the fifth dielectric layer 225, and etches a fifth through hole 335 at the corresponding position of the fourth through hole 234 by photolithography.

[0101] S202 performs metal electroplating on the seventh dielectric layer 327 to form a thicker metal layer, and completes the fabrication of the sixth metal layer 346 through photolithography, development and etching processes. The sixth metal layer 346 is connected to the fourth metal layer 244 through the fifth through hole 335 and the fourth through hole 234.

[0102] S203 spin-coats an eighth dielectric layer 328 on the surface of the sixth metal layer 346, and etches the sixth through hole 336 at the corresponding position of the fourth through hole 234 by photolithography.

[0103] S204 repeats S202 to form the seventh metal layer 347. The bonding process is then transferred to S205, and the ball-planting process is transferred to S206.

[0104] S205 spin-coats a ninth dielectric layer 329 on the surface of the seventh metal layer 347 and etches a seventh via 337, in which a portion of the seventh metal layer 347 is exposed. An eighth metal layer 348 is fabricated within the seventh via 337 as a pad through metal electroplating and etching processes.

[0105] The S206BUMP361 process uses the seventh metal layer 347 as the UBM (Under BUMP361 Metallurgy). Copper pillars, BUMPs 361, or embedded beads are electroplated onto the seventh metal layer 347 through an electroplating process.

[0106] Preferably, the process further includes step S207 of thinning the back side of the substrate 100. Thinning the substrate 100 after all processes are completed can prevent breakage of the wafer due to excessive thinness during processing, while also reducing the size of the finished device.

[0107] More preferably, the seventh dielectric layer 327, the eighth dielectric layer 328 and the ninth dielectric layer 329 are made of PI (polyimide) or BCB (benzocyclobutene).

[0108] More preferably, the sixth metal layer 346 needs to be aligned with the fourth metal layer 244, and the alignment accuracy deviation shall not exceed 10% of the linewidth of the sixth metal layer 346. Alignment error will affect the inductance accuracy of the inductor wound using the combined RDL sixth metal layer 346, IPD third metal layer 243, and IPD fourth metal layer 244.

[0109] The thickness of the sixth metal layer 346 is preferably greater than 3 μm.

[0110] Traditional RDL (Redistribution Layer) processes typically involve repositioning the pads in WLCSP (Wafer-Lobed Packaging) packages before ball placement, primarily serving to redistribute pad locations. In traditional RDL processes, the seventh dielectric layer (327) and the eighth dielectric layer (328) act as metal isolation layers and stress buffers, with thickness control accuracy being relatively low. This process requires precise error control over the thickness of the seventh and eighth dielectric layers (327 and 328), which should be between 5μm and 10μm. The error should be controlled to be less than 10% of the dielectric thickness; excessive error will affect performance consistency. The thickness of the seventh and eighth dielectric layers (327 and 328) is a parameter that can be adjusted during device design and can impact device performance. This process utilizes RDL technology to increase the number of thick metal layers compared to traditional integrated circuit processes, allowing for the winding of more turns of inductors. This results in a smaller inductor area for the same inductance value, reducing the area and increasing device integration density. Meanwhile, this process utilizes the fact that the metal layer in the RDL process can be relatively thick, and the precision of photolithography and metal deposition is relatively poor compared to chip processes. At the same time, it can achieve better metal connection loss at low cost, thereby improving the performance of integrated passive devices.

[0111] Compared to traditional integrated passive device (IPD) processes for fabricating a low-pass filter, this process... Figure 5 A schematic diagram of a traditional integrated passive device fabricated using the IPD process. Figure 6 This is a schematic diagram of the integrated passive device fabricated using this process. Figure 7 and Figure 8 As shown, this process improves the insertion loss performance of the pass filter by >10% and the suppression performance by >10%.

[0112] In summary, this invention combines existing semiconductor integrated passive device technology with RDL (rewiring layer) packaging technology, overcoming the limitations of mature integrated circuit processes, such as the limited number of thick metal layers (1-2 layers) and the relatively large metal thickness. The combination with RDL technology adds 1-3 wireable metal layers with a relatively large metal thickness, forming a richer stack-up structure. This enables the winding of low-loss, high-inductance-per-unit-area inductors and connection wiring functions, improving the design flexibility of passive integrated devices and enhancing the performance and integration density of integrated passive devices.

[0113] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0114] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A semiconductor device integrating passive components, characterized in that, include: Substrate; At least one integrated passive device includes one or more of a resistor, capacitor, or inductor formed on the surface of the substrate; A redistribution layer is disposed on the surface of the substrate on which the at least one integrated passive device is disposed; The redistribution layer includes at least one metal layer to form a layer-wound inductor; The integrated passive device includes an inductor, and the metal layer of the redistribution layer is located directly above the inductor and interconnected with the inductor of the integrated passive device through a via, with a deviation not exceeding 10% of the minimum linewidth of the inductor wound on the metal layer; A fifth dielectric layer is provided between the integrated passive device and the rewiring layer, and the thickness of the fifth dielectric layer is 3-5 μm. The layer-wound inductor formed by the rewiring layer is provided with a seventh dielectric layer and an eighth dielectric layer on both sides, and the thickness of the seventh dielectric layer and the eighth dielectric layer is 5-10 μm. The thickness of the layer-wound inductor formed by the rewire layer is greater than 3 μm.

2. The semiconductor device integrating passive components according to claim 1, characterized in that, The substrate is high-resistivity silicon or glass.

3. The semiconductor device integrating passive components according to claim 1, characterized in that, The rewiring layer uses wire bonding, balling, or BUMP processes to bring out signals.

4. A method for fabricating a semiconductor device with an integrated passive device as described in any one of claims 1 to 3, characterized in that, include: S100 forms at least one integrated passive device on the substrate; The integrated passive device includes an inductor; S200 forms a redistribution layer on the surface of the substrate where an integrated passive device is formed; The redistribution layer includes at least one metal layer to form a layer-wound inductor; S200 forms a redistribution layer on the surface of the substrate where an integrated passive device is formed, including: S201 forms a seventh dielectric layer by spin coating on the fifth dielectric layer, and etches the fifth via at the corresponding position of the fourth via by photolithography. The thickness of the fifth dielectric layer is 3-5 μm. The fourth via is located on the fifth dielectric layer. S202 performs metal electroplating on the seventh dielectric layer to form a relatively thick metal layer, and completes the fabrication of the sixth metal layer through photolithography, development, and etching processes. The sixth metal layer is connected to the fourth metal layer through the fifth and fourth through-holes. The thickness of the sixth metal layer is greater than 3μm. The fourth metal layer is the top metal layer of the inductor of the integrated passive device and is located below the fifth dielectric layer. The sixth metal layer is located directly above the fourth metal layer, and the deviation does not exceed 10% of the minimum linewidth of the inductor wound on the sixth metal layer. S203 spin-coats an eighth dielectric layer on the surface of the sixth metal layer, and etches the sixth through hole at the corresponding position of the fourth through hole by photolithography, and the thickness of the seventh dielectric layer and the eighth dielectric layer is 5-10 μm; S204 repeats S202 to form the seventh metal layer. The bonding process is then transferred to S205, and the ball-planting process is transferred to S206. S205 spin-coats a ninth dielectric layer on the surface of the seventh metal layer and etches a seventh via, in which a portion of the seventh metal layer is exposed. An eighth metal layer is then fabricated within the seventh via using metal plating and etching processes to serve as a pad. The S206BUMP process uses the seventh metal layer as a UBM, and copper pillars, BUMPs, or implanted beads are electroplated onto the seventh metal layer through an electroplating process.

5. The preparation method according to claim 4, characterized in that, The substrate is made of high-resistivity silicon or glass.

6. The preparation method according to claim 4, characterized in that, S100 forms at least one integrated passive device on the substrate, including: S101 forms a resistive layer on a substrate through metal sputtering, photolithography, and ion etching processes, and then deposits a first dielectric layer on it. S102 etches a first via on the first dielectric layer using photolithography and etching processes, wherein the first via exposes a portion of the substrate and a portion of the resistive layer. S103 deposits a first metal layer on the first dielectric layer, and the first metal layer is connected to the substrate and the resistor layer through a first via. The pattern of the first metal layer is etched out by photolithography and etching processes to serve as the bottom plate of the capacitor. A second dielectric layer is deposited on the surface of the first metal layer to serve as the dielectric layer of the capacitor. S104 deposits a second metal layer on the second dielectric layer, and etches the pattern of the second metal layer as the bottom plate of the capacitor through photolithography and etching processes, and deposits a third dielectric layer on it. S105 etches a second via on the third dielectric layer using photolithography and etching processes, wherein the second via exposes part of the second metal layer, and the third metal layer pattern is further etched on it using photolithography and etching processes. S106 sputters the second through-hole and the third metal layer seed layer through a metal sputtering process, completes the second through-hole and the third metal layer together through an electroplating process, and finally completes the wafer surface flattening through chemical mechanical polishing and deposits the fourth dielectric layer on it. S107 repeats S105-S106 to complete the fabrication of the third via and the fourth metal layer. A fifth dielectric layer is deposited on the surface of the fourth metal layer. The fourth via is etched on the fifth dielectric layer using photolithography and etching processes.

7. The preparation method according to claim 4, characterized in that, The materials of the seventh, eighth, and ninth dielectric layers are PI or BCB.

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