Nonvolatile memory device having resistance change layer and operation method thereof

Abstract

A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layer disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer disposed in the substrate and contacting different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies and movable metal ions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0017891, filed on February 13, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to a nonvolatile memory device, and more particularly, to a nonvolatile memory device having a resistance change layer and a method of operating the same. Background Art

[0004] According to the trend of reducing design rules and increasing integration, research on the structure of semiconductor devices that can ensure structural stability and reliability of signal storage operations continues. Currently, in non-volatile memory devices such as flash memory, a three-layer stacked structure of a charge tunneling layer, a charge trap layer, and a charge blocking layer as a charge storage structure has been widely used.

[0005] Recently, various nonvolatile memory devices having structures different from those of conventional flash memory devices have been proposed. An example of a nonvolatile memory device is a resistance change memory device. While a flash memory device implements a storage function by charge storage, a resistance change memory device variably changes the resistance state of a storage layer in a storage cell between a high resistance state and a low resistance state, and stores the changed resistance state in a nonvolatile manner, thereby writing predetermined signal information into the storage cell. Summary of the invention

[0006] A nonvolatile memory device according to one aspect of the present disclosure may include a substrate, a resistance change layer disposed on the substrate, a gate electrode layer disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer, the first and second electrode pattern layers being disposed in the substrate and contacting different portions of the resistance change layer. The resistance change layer may include movable oxygen vacancies and movable metal ions.

[0007] A nonvolatile memory device according to another aspect of the present disclosure may include a substrate and a gate structure disposed on the substrate. The gate structure may include at least one gate electrode layer and at least one interlayer insulating layer alternately stacked. The nonvolatile memory device may further include: a hole pattern penetrating the gate structure on the substrate, a resistance change layer covering the sidewall surface of the gate structure in the hole pattern and including a variable resistance material, and a channel layer arranged in the hole pattern to cover the resistance change layer.

[0008] A nonvolatile memory device according to another aspect of the present disclosure may include a substrate and a gate structure disposed on the substrate. The gate structure may include at least one gate electrode layer and at least one interlayer insulating layer alternately disposed in a first direction perpendicular to the substrate, and the gate structure may extend in a second direction perpendicular to the first direction. The nonvolatile memory device may further include: a resistance change layer covering a sidewall surface of the gate structure disposed on the substrate and including a variable resistance material; and a channel layer disposed on the substrate and disposed to cover the resistance change layer.

[0009] A method for operating a nonvolatile memory device according to another aspect of the present disclosure is disclosed. In the operating method, a nonvolatile memory device may be provided, the nonvolatile memory device comprising: a substrate, a resistance change layer and a gate electrode layer sequentially arranged on the substrate, and a first electrode pattern layer and a second electrode pattern layer arranged in the substrate to contact different parts of the resistance change layer, the gate electrode layer comprising a plurality of gate pattern layers arranged to be spaced apart from each other between the first electrode pattern layer and the second electrode pattern layer. A first gate voltage may be applied to the plurality of gate pattern layers to move oxygen vacancies or movable metal ions in the resistance change layer to a filament formation region of the resistance change layer and form a conductive channel in the substrate. The first gate voltage applied to a target gate pattern layer among the plurality of gate pattern layers may be removed to disconnect the conductive channel while maintaining the first gate voltage of the plurality of gate pattern layers other than the target gate pattern layer. A setting voltage may be applied between the first electrode pattern layer and the second electrode pattern layer to form a conductive filament in the resistance change layer to electrically connect the two ends of the disconnected conductive channel.

[0010] A method for operating a nonvolatile memory device according to another aspect of the present disclosure is disclosed. In the operating method, a nonvolatile memory device may be provided, the nonvolatile memory device comprising: a substrate, a gate structure disposed on the substrate and having a plurality of gate electrode layers spaced apart from each other in a first direction perpendicular to the substrate, and a resistance change layer covering the sidewall surface of the gate structure, a channel layer disposed to cover the resistance change layer, and a channel lower contact layer and a channel upper contact layer disposed at opposite ends of the channel layer. A first gate voltage may be applied to the plurality of gate electrode layers to move oxygen vacancies or movable metal ions in the resistance change layer to an area adjacent to the channel layer and form a conductive channel in the channel layer. The first gate voltage applied to a target gate electrode layer among the plurality of gate electrode layers may be removed to disconnect the conductive channel while maintaining the first gate voltage to the plurality of gate electrode layers other than the target gate electrode layer. A setting voltage may be applied between the channel lower contact layer and the channel upper contact layer to form a conductive filament in the resistance change layer to electrically connect the two ends of the disconnected conductive channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1is a cross-sectional view schematically illustrating a nonvolatile memory device according to an embodiment of the present disclosure.

[0012] Figures 2 to 7 is a view schematically illustrating a method of operating a nonvolatile memory device according to an embodiment of the present disclosure.

[0013] Figure 8 is a cross-sectional view of a nonvolatile memory device having a resistance change layer according to a comparative example.

[0014] Fig. 9 is a cross-sectional view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure.

[0015] Fig.10 is a cross-sectional view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure.

[0016] Fig.11 and Fig.12 2 is a view schematically illustrating a set operation and a reset operation of a nonvolatile memory device according to an embodiment of the present disclosure.

[0017] Fig.13 is a cross-sectional view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure.

[0018] Fig.14 and Fig.15 is a view schematically illustrating a set operation and a reset operation of a nonvolatile memory device according to another embodiment of the present disclosure.

[0019] Fig.16 is a cross-sectional view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure.

[0020] Fig.17 yes Fig.16 Circuit diagram of a nonvolatile memory device.

[0021] Figures 18 to 21 is a view schematically illustrating an operation of a nonvolatile memory device according to another embodiment of the present disclosure.

[0022] Fig.22A is a perspective view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure.

[0023] Fig. 22B It is along Fig.22A A cross-sectional view of a nonvolatile memory device taken along line II′.

[0024] Fig.23 yes Fig.22A and Fig. 22BCircuit diagram of a nonvolatile memory device.

[0025] Figure 24 to Figure 27 is a view schematically illustrating an operation of a nonvolatile memory device according to another embodiment of the present disclosure.

[0026] Fig.28A is a perspective view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure.

[0027] Fig.28B It is along Fig.28A A cross-sectional view of a nonvolatile memory device taken along line II-II′.

[0028] Fig.28C It is along Fig.28A 2 is a cross-sectional view of a nonvolatile memory device taken along line III-III′. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, in order to clearly represent the components of each device, the size of the components, such as the width and thickness of the components, is enlarged. The terms used herein may correspond to words selected in consideration of the functions in the embodiments, and the meanings of these terms may be interpreted differently according to those of ordinary skill in the art to which the embodiments belong. If clearly defined in detail, these terms may be interpreted according to the definitions. Unless otherwise defined, the terms (including technical terms and scientific terms) used herein have the same meaning as those generally understood by those of ordinary skill in the art to which the embodiments belong.

[0030] In addition, unless otherwise clearly used in the context, expressions in the singular form of a word should be understood to include the plural form of the word. It will be understood that the terms "include", "comprises" or "having" are intended to specify the presence of a feature, number, step, operation, component, element, part or combination thereof, but are not used to exclude the presence of one or more other features, numbers, steps, operations, components, elements, parts or combinations thereof or exclude the possibility of adding it / them.

[0031] In addition, when performing a method or manufacturing method, unless a specific order is clearly described in the context, each process constituting the method can be performed in a different order than the specified order. In other words, each process can be performed in the same manner as the described order, and each process can be performed substantially simultaneously. In addition, at least a portion of each of the above processes can be performed in the reverse order.

[0032] In this specification, the term "predetermined direction" may refer to a direction including a direction determined in a coordinate system and a direction opposite to the direction. As an example, in an xyz coordinate system, the x direction may include a direction parallel to the x direction. That is, the x direction may refer to all directions in which the absolute value of the x-axis increases in the positive direction along the x-axis from the origin 0 and the absolute value of the x-axis increases in the negative direction along the x-axis from the origin 0. In the xyz coordinate system, the y direction and the z direction may be interpreted in substantially the same manner, respectively.

[0033] Figure 1 2 is a cross-sectional view schematically showing a nonvolatile memory device 1 according to an embodiment of the present disclosure. Figure 1 The nonvolatile memory device 1 may include a substrate 110, a resistance change layer 120 disposed on the substrate 110, a gate electrode layer 130 disposed on the resistance change layer 120, and a first electrode pattern layer 140 and a second electrode pattern layer 150 disposed to contact different portions of the resistance change layer 120 on the substrate 110.

[0034] Reference Figure 1 , a substrate 110 may be provided. The substrate 110 may include a semiconductor material. Specifically, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), black phosphorus, indium gallium zinc oxide (IGZO) or a combination of two or more thereof.

[0035] The resistance change layer 120 may be provided on the substrate 110 . The resistance change layer 120 may have a first surface LS120 and a second surface US120 opposite to the first surface LS120 . The first surface LS120 may be bonded to the substrate 110 , and the second surface US120 may be bonded to the gate electrode layer 130 .

[0036] The resistance change layer 120 may include a variable resistance material. In the variable resistance material, the internal resistance state may change according to the polarity or magnitude of the applied voltage. In addition, after the applied voltage is removed, the changed internal resistance state may be stored in the variable resistance material non-volatilely. As an example, a high resistance state and a low resistance state distinguished from each other may be selectively stored in the variable resistance material. In other words, the variable resistance material may have a predetermined first resistance value corresponding to the high resistance state and a predetermined second resistance value corresponding to the low resistance state. The first resistance value and the second resistance value may be determined according to the type or property of the variable resistance material.

[0037] In one embodiment, the variable resistance material may include mobile oxygen vacancies or mobile metal ions. The oxygen vacancies may have a positive charge. The metal ions may be cations with a positive charge or anions with a negative charge. In one embodiment, the variable resistance material may include titanium oxide, aluminum oxide, nickel oxide, copper oxide, zirconium oxide, manganese oxide, hafnium oxide, tungsten oxide, tantalum oxide, niobium oxide, iron oxide, or a combination of two or more thereof. In another embodiment, the variable resistance material may include PCMO (Pr 1-x Ca x MnO3, 0 < x < 1), LCMO (La 1-x Ca x MnO3, 0 < x < 1), BSCFO (Ba 0.5 Sr 0.5 Co 0.8 Fe 0.2 O 3-δ ), YBCO (YBa2Cu3O 7-x , 0 < x < 1), (Ba, Sr)TiO3 doped with chromium (Cr) or niobium (Nb), SrZrO3 doped with chromium (Cr) or vanadium (V), (La, Sr)MnO3, Sr 1-x La x TiO3 (0 < x < 1), La 1-x Sr x FeO3 (0 < x < 1), La 1-x Sr x CoO3 (0 < x < 1), SrFeO 2.7 , LaCoO3, RuSr2GdCu2O3, YBa2Cu3O7, or a combination of two or more thereof. In another embodiment, the variable resistance material may include germanium-antimony-tellurium (GST), arsenic-antimony-tellurium (As-Sb-Te), tin-antimony-tellurium (Sn-Sb-Te), tin-indium-antimony-tellurium (Sn-In-Sb-Te), arsenic-germanium-antimony-tellurium (As-Ge-Sb-Te), Ge x Se 1-x (0 < x < 1), silver sulfide (Ag2S), copper sulfide (Cu2S), cadmium sulfide (CdS), zinc sulfide (ZnS), and cerium oxide (CeO2), or a combination of two or more thereof.

[0038] The gate electrode layer 130 may be disposed on the resistance change layer 120. The gate electrode layer 130 may be a pattern of a conductive film. The gate electrode layer 130 may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, n-type doped silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0039] Reference Figure 1 , the first electrode pattern layer 140 and the second electrode pattern layer 150 may be spaced apart from each other in the substrate 110. Upper surfaces of the first electrode pattern layer 140 and the second electrode pattern layer 150 may be located at the same height as an upper surface of the substrate 110.

[0040] Each of the first electrode pattern layer 140 and the second electrode pattern layer 150 may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, n-type doped silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0041] In one embodiment, the first electrode pattern layer 140 and the second electrode pattern layer 150 may be regions of the substrate 110. As an example, when the substrate 110 is a semiconductor substrate, the first electrode pattern layer 140 and the second electrode pattern layer 150 may be regions of the semiconductor substrate doped with an n-type dopant. In another embodiment, the first electrode pattern layer 140 and the second electrode pattern layer 150 may be formed of different materials. As an example, when the substrate 110 is a semiconductor substrate, the first electrode pattern layer 140 and the second electrode pattern layer 150 may be conductive material layers.

[0042] Meanwhile, the substrate 110 may further include a channel formation region (not shown) disposed between the first electrode pattern layer 140 and the second electrode pattern layer 150. Figure 3 As described, when a gate voltage equal to or higher than a predetermined threshold voltage is applied to the gate electrode layer 130 , the channel formation region may be a region in which the conductive channel 1000 is formed.

[0043] Refer again Figure 1, the first electrode pattern layer 140 may have a first pattern edge portion 140A located in a boundary region contacting the resistance channel layer 120 and the substrate 110. Similarly, the second electrode pattern layer 150 may include a second pattern edge portion 150A located in a boundary region contacting the resistance change layer 120 and the substrate 110. Figure 1 Not shown, the first pattern edge portion 140A and the second pattern edge portion 150A may extend in the y direction. When a voltage is applied between the first electrode pattern layer 140 and the second electrode pattern layer 150, an electric field generated by the voltage may be concentrated on the first pattern edge portion 140A and the second pattern edge portion 150A.

[0044] Figures 2 to 7 is a view schematically illustrating a method of operating a nonvolatile memory device according to an embodiment of the present disclosure. Figures 2 to 4 is a view schematically illustrating a set operation of a nonvolatile memory device according to an embodiment of the present disclosure. Figure 5 Schematically illustrates a voltage applied during a set operation of a nonvolatile memory device according to an embodiment of the present disclosure. When a resistance change layer of the nonvolatile memory device has a high resistance state or a low resistance state, the set operation may be an operation of converting the resistance state of the resistance change layer from a high resistance state to a low resistance state. Figure 6 is a view schematically illustrating a reset operation of a nonvolatile memory device according to an embodiment of the present disclosure. Figure 7 Schematically illustrates a voltage applied during a reset operation of a nonvolatile memory device according to an embodiment of the present disclosure. The reset operation may be an operation of converting the resistance state of the resistance change layer from a low resistance state to a high resistance state. Figure 1 The nonvolatile memory device 1 described in the description will refer to Figures 2 to 7 An operating method of a nonvolatile memory device is described.

[0045] Reference Figure 2 , can provide the above reference Figure 1 The nonvolatile memory device 1 described above is provided. The resistance change layer 120 may have movable oxygen vacancies or movable metal ions 125. In one embodiment, the movable oxygen vacancies and the movable metal ions 125 may be uniformly distributed inside the resistance change layer 120. Hereinafter, an embodiment in which the resistance change layer 120 is provided with oxygen vacancies 125 having positive charges will be described. In another embodiment, when the resistance change layer 120 includes the movable metal ions 125, substantially the same operation method may be used.

[0046] Reference Figure 3, a first gate voltage may be applied to the gate electrode layer 130. The first gate voltage may include a bias voltage of positive polarity. Due to the first gate voltage, the oxygen vacancies 125 may move to the filament formation region adjacent to the first surface LS120. The filament formation region may be a region of the resistance change layer 120 where the conductive filaments ( Figure 4 In some embodiments, due to the application of the first gate voltage, a conductive channel 1000 may be formed in a region of the substrate 110 near the contact with the resistance change layer 120.

[0047] According to one embodiment, the concentration of oxygen vacancies 125 that move to the filament formation region can be controlled by controlling the magnitude of the first gate voltage. As described below, the concentration of oxygen vacancies 125 can determine the diameter of the formed conductive filament.

[0048] Reference Figure 4 , the first gate voltage applied to the gate electrode layer 130 may be removed, and a setting voltage may be applied between the first electrode pattern layer 140 and the second electrode pattern layer 150. As a result, an electric field generated by the setting voltage may be formed inside the resistance change layer 120, and a conductive filament 10 electrically connecting the first electrode pattern layer 140 and the second electrode pattern layer 150 may be formed in the resistance change layer 120.

[0049] Reference Figure 5 , along the time axis t, a first gate voltage may be applied between the initial time t0 and the first time t1, the first gate voltage being a pulse voltage Pa having a first amplitude Vg. Subsequently, a setting voltage may be applied between the first time t1 and the second time t2, the setting voltage being a pulse voltage Pb having a second amplitude Vp. That is, at the first time t1, the first gate voltage may be removed, and the setting voltage may be applied simultaneously or substantially simultaneously. Figure 5 The shape of the amplitude Vg of the pulse voltage Pa and the time interval between the initial time t0 and the first time t1 shown in are merely examples, and various modifications are possible depending on the physical properties of the thin film used in the structure of the nonvolatile memory device 1 and the electrical characteristics of the device implemented by the thin film. In addition, the shape of the amplitude Vp of the pulse voltage Pb and the time interval between the first time t1 and the second time t2 are merely examples, and various modifications are possible.

[0050] Refer again Figure 4, when the setting voltage is applied, the electric field may be concentrated on the first pattern edge portion 140A of the first electrode pattern layer 140 and the second pattern edge portion 150A of the second electrode pattern layer 150, respectively. Therefore, the oxygen vacancies 125 may be more actively gathered or combined with each other in the region adjacent to the first pattern edge portion 140A and the second pattern edge portion 150A of the resistance change layer 120, so that the first trigger filament 125t1 and the second trigger filament 125t2 may be formed. The first trigger filament 125t1 and the second trigger filament 125t2 may be formed to contact the first electrode pattern layer 140 and the second electrode pattern layer 150. Each of the first trigger filament 125t1 and the second trigger filament 125t2 may be a starting position or a seed from which the conductive filament 10 is generated. In addition, the first trigger filament line 125t1 and the second trigger filament line 125t2 are stably formed on the pattern edge portions 140A and 150A, so that errors in the setting operation of the nonvolatile memory device 1 described later may be prevented. That is, the first trigger filament 125t1 and the second trigger filament 125t2 structurally stabilize the connection or short-circuit state of the conductive filament 10 in the first pattern edge portion 140A and the second pattern edge portion 150A, thereby improving the retention and durability of signal information.

[0051] In addition, the oxygen vacancies 125 may be aggregated or bonded to the first trigger filament 125t1 and the second trigger filament 125t2, so that the connecting filament 125c may grow from the first trigger filament 125t1 and the second trigger filament 125t2. The connecting filament 125c may connect the first trigger filament 125t1 and the second trigger filament 125t2 to form the conductive filament 10. The conductive filament 10 electrically connects the first electrode pattern layer 140 and the second electrode pattern layer 150, so that the resistance of the resistance change layer 120 may be reduced. Even after the setting voltage and the gate voltage are removed, the conductive filament 10 remains inside the resistance change layer 120, so that the resistance change layer 120 may maintain a reduced resistance. That is, the resistance change layer 120 may actually store a low resistance state as signal information.

[0052] In one embodiment, because the concentration of oxygen vacancies aggregated or combined in the first and second pattern edge portions 140A and 150A is higher due to the electric field being concentrated in those areas, the diameters of the first and second trigger filaments 125t1 and 125t2 may be greater than the diameter of the connecting filament 125c.

[0053] In some embodiments, the concentration of oxygen vacancies 125 induced into the filament formation region by the first gate voltage may determine the diameter of the conductive filament 10. As the concentration of the induced oxygen vacancies 125 increases, the number of oxygen vacancies 125 aggregated or combined by the set voltage may increase. Therefore, the diameter of the conductive filament 10 formed by the set voltage may be increased. In addition, as the diameter of the conductive filament 10 increases, the resistance value of the resistance change layer 120 may decrease. As described above, according to the resistance value of the resistance change layer 120 that varies according to the diameter of the conductive filament 10, multiple resistance values ​​may be written in the resistance change layer 120. Therefore, a non-volatile memory device that stores multiple signal information in the resistance change layer 120 may be realized.

[0054] Figure 6 and Figure 7 The reset operation according to another embodiment of the present disclosure is schematically shown. A second gate voltage may be applied to the gate electrode layer 130. The second gate voltage may include a bias voltage of negative polarity. In addition, when the second gate voltage is applied, a reset voltage may be applied between the first electrode pattern layer 140 and the second electrode pattern layer 150. The reset voltage may have a different polarity from the set voltage.

[0055] Reference Figure 7 , along the time axis t, a second gate voltage may be applied between the initial time t0 and the reset time tr, the second gate voltage being a negative pulse voltage Ea having a first amplitude Vg. In the same time period, a reset voltage may be applied, the reset voltage being a negative pulse voltage Eb having a second amplitude Ve.

[0056] Refer again Figure 6 , the energy provided by the reset voltage decomposes the conductive filament 10. As an example, the energy may be thermal energy or electrical energy formed by an electric field. The oxygen vacancies 125 may be released from the conductive filament 10 and then distributed in the resistance change layer 120. In addition, under the effect of the attraction generated by the second gate voltage, the oxygen vacancies 125 may escape from the filament formation region. That is, the oxygen vacancies 125 may move away from the region where the resistance change layer 120 is adjacent to the first surface LS120. For example, the oxygen vacancies 125 may move from the filament formation region near the first surface LS120 to the region where the resistance change layer 120 is adjacent to the second surface US120.

[0057] In one embodiment, in the connection filament 125c having a relatively low concentration of aggregated or bonded oxygen vacancies, the degree of decomposition of the conductive filament 10 caused by the reset voltage may be greater. Therefore, the portions of the first trigger filament 125t1 and the second trigger filament 125t2 having a relatively high concentration of aggregated or bonded oxygen vacancies may be less degraded and remain in the pattern edge portions 140A and 150A of the first electrode pattern layer 140 and the second electrode pattern layer 150.

[0058] The decomposition may continue until at least a portion of the conductive filament 10 is disconnected, thereby increasing the resistance of the resistance change layer 120. Therefore, the internal resistance state of the resistance change layer 120 may be changed from a low resistance state to a high resistance state. Even after the second gate voltage and the reset voltage are removed, the disconnected state of the conductive filament 10 remains, so that the resistance change layer 120 may maintain a high resistance state. That is, the resistance change layer 120 may store the high resistance state as signal information.

[0059] Figure 7 The shape of the amplitude Vg of the pulse voltage Ea and the shape of the time interval between the initial time t0 and the reset time tr shown in are merely examples, and various modifications are possible depending on the physical properties of the thin film used in the structure of the nonvolatile memory device 1 and the electrical characteristics of the device implemented by the nonvolatile memory device. In addition, the shape of the amplitude Ve of the pulse voltage Eb and the time interval between the initial time t0 and the reset time tr are also merely examples, and various modifications are possible.

[0060] In the read operation of the nonvolatile memory device 1, a read voltage may be applied between the first electrode pattern layer 140 and the second electrode pattern layer 150. During operation, no voltage is applied to the gate electrode layer 130, or a third gate voltage having a magnitude less than a threshold voltage capable of forming the conductive channel 1000 is applied to the gate electrode layer 130. Then, the current flowing between the first electrode pattern layer 140 and the second electrode pattern layer 150 due to the applied read voltage may be measured. The magnitude of the read voltage may be selected so that the conductive filament 10 is not formed inside the resistance change layer 120 and the conductive filament 10 is not decomposed.

[0061] When the conductive filament 10 is formed inside the resistance change layer 120 between the first electrode pattern layer 140 and the second electrode pattern layer 150, a relatively high current can be measured passing through the conductive filament 10. Conversely, when the conductive filament 10 is not formed or is disconnected inside the resistance change layer 120 between the first electrode pattern layer 140 and the second electrode pattern layer 150, a relatively low current can be measured. In this way, signal information stored in the resistance change layer 120 of the nonvolatile memory device 1 can be read.

[0062] According to the above-described embodiment of the present disclosure, when a set operation is performed on the nonvolatile memory device 1, the first trigger filament 125t1 and the second trigger filament 125t2 may be formed in the resistance change layer 120 and adjacent to the first pattern edge portion 140A and the second pattern edge portion 150A, where the first pattern edge portion 140A and the second pattern edge portion 150A are portions where the electric field is concentrated. Then, the connecting filament 125c is formed to connect the first trigger filament 125t1 and the second trigger filament 125t2, so that the conductive filament 10 may be completed. As a result, by controlling the positions of the first trigger filament 125t1 and the second trigger filament 125t2 from which the connecting filament is generated, the density and distribution of the conductive filament 10 may be effectively restricted or controlled.

[0063] In some embodiments, the conductive filaments 10 of the nonvolatile memory device may be formed by movable metal ions 125 distributed in the resistance change layer 120. In one embodiment, when the resistance change layer 120 includes positive metal ions 125, the conductive filament generation or decomposition of the conductive filaments 10 in the resistance change layer 120 may be performed by the same method as described above. Figures 2 to 5 Setting operations and references Figure 6 and Figure 7 The same operation as described for the reset operation is generated.

[0064] In another embodiment, when the resistance change layer 120 includes negative metal ions 125, a first gate voltage including a negative polarity bias may be applied to the gate electrode layer 130. Thus, the negative metal ions 125 may move to a filament formation region of the resistance change layer 120 adjacent to the first surface LS120. Subsequently, the first gate voltage may be removed, and a setting voltage may be applied between the first electrode pattern layer 140 and the second electrode pattern layer 150 to form a conductive filament 10 in the resistance change layer 120. In this embodiment, the setting voltage may have a voltage that is in combination with the above. Figures 2 to 5 The described embodiments set the voltages to different polarities.

[0065] During the reset process, a second gate voltage including a positive polarity bias may be applied to the gate electrode layer 130, and a reset voltage may be applied between the first electrode pattern layer 140 and the second electrode pattern layer 150. The reset voltage in this embodiment may have the same Figure 6 and Figure 7 The reset voltages of the described embodiments have different polarities. Therefore, the negative metal ions 125 generated by the decomposition of the conductive filaments due to the reset voltage can be effectively dissipated from the filament formation region.

[0066] Figure 8 is a cross-sectional view of a nonvolatile memory device having a resistance change layer according to a comparative example. Figure 8, the nonvolatile memory device 1A may include a first electrode layer a and a second electrode layer b facing each other and spaced apart in the z direction. The nonvolatile memory device 1A may include a resistance change layer c disposed between the first electrode layer a and the second electrode layer b. Because the first electrode layer a and the second electrode layer b are disposed to face each other in the z direction, when a setting voltage is applied, a plurality of conductive filaments CB may be randomly grown between the interface of the resistance change layer c and the first electrode layer a or the second electrode layer b. That is, in the comparative example, it may be relatively difficult to control the density and distribution of the conductive filaments CB. In contrast, in the embodiment of the present disclosure, the first electrode pattern layer 140 and the second electrode pattern layer 150 do not face each other. In addition, in the embodiment of the present disclosure, the first trigger filament 125t1 and the second trigger filament 125t2 formed on the first pattern edge portion 140A and the second pattern edge portion 150A may determine the starting position of the conductive filament 10. Therefore, the density and distribution of the conductive filament 10 may be effectively controlled.

[0067] Fig. 9 2 is a cross-sectional view schematically showing a nonvolatile memory device according to another embodiment of the present disclosure. Fig. 9 , and the above reference Figure 1 Compared with the nonvolatile memory device 1 described above, the nonvolatile memory device 2 may further include a gate insulating layer 160 . The gate insulating layer 160 may be disposed between the resistance change layer 120 and the gate electrode layer 130 .

[0068] During operation of the nonvolatile memory device 2, the gate insulating layer 160 can prevent oxygen vacancies or movable metal ions inside the resistance change layer 120 from moving to the gate electrode layer 130. In some cases, the formation of parasitic filaments that electrically connect the gate electrode layer 130 and the first electrode pattern 140 or the gate electrode layer 130 and the second electrode pattern layer 150 can be suppressed. The gate insulating layer 160 may include an insulating material. The gate insulating layer 160 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc.

[0069] Fig.10 2 is a cross-sectional view schematically showing a nonvolatile memory device according to another embodiment of the present disclosure. Fig.10 Regarding the structure of the resistance change layer 320, the nonvolatile memory device 3 may be similar to the above reference Fig. 9 The configuration of the substrate 310, the gate electrode layer 330, the first electrode pattern layer 340 and the second electrode pattern layer 350, the first pattern edge portion 340A and the second pattern edge portion 350A, and the gate insulating layer 360 of the nonvolatile memory device 3 may be the same as that of the above reference 1. Fig. 9The configurations of the substrate 110 , the gate electrode layer 130 , the first and second electrode pattern layers 140 and 150 , the first and second pattern edge portions 140A and 150A, and the gate insulating layer 160 of the described nonvolatile memory device 2 are substantially the same.

[0070] In one embodiment, the resistance change layer 320 may include a first resistance material layer 320a and a second resistance material layer 320b sequentially disposed on the first electrode pattern layer 340 and the second electrode pattern layer 350 and the substrate 310. The first resistance material layer 320a may contact the first electrode pattern layer 340 and the second electrode pattern layer 350 and the substrate 310, and the second resistance material layer 320b may contact the first resistance material layer 320a and the gate insulating layer 360.

[0071] Each of the first resistive material layer 320a and the second resistive material layer 320b may include a variable resistive material. The variable resistive material may include movable oxygen vacancies and movable metal ions. The metal ions may be positive ions or negative ions. The variable resistive material may be the same as the above reference Figure 1 The variable resistance material of the resistance change layer 120 of the described nonvolatile memory device 1 is substantially the same.

[0072] The first resistive material layer 320a and the second resistive material layer 320b may be different from each other. For example, the first resistive material layer 320a and the second resistive material layer 320b may include different variable resistance materials. The first resistive material layer 320a may have a lower oxygen vacancy concentration or a lower movable metal ion concentration than the second resistive material layer 320b. The first resistive material layer 320a may be a high resistor compared to the second resistive material layer 320b. In addition, the thickness of the first resistive material layer 320a may be less than the thickness of the second resistive material layer 320b.

[0073] Fig.11 and Fig.12 1 and 2 are views respectively illustrating a setting operation and a reset operation of a nonvolatile memory device according to an embodiment of the present disclosure. Fig.10 The nonvolatile memory device 3 is combined as an example Fig.11 and Fig.12 To describe the set operation and the reset operation. Hereinafter, for ease of explanation, an embodiment in which the resistance change layer 320 has oxygen vacancies with positive charges will be described, but the embodiment is not limited thereto, and the present disclosure includes a resistance change layer that may include movable metal ions with positive or negative charges. If the resistance change layer 320 includes movable metal ions with negative charges, the disclosed operation may be substantially the same except for the difference between the polarities of the first gate voltage and the second gate voltage and between the polarities of the set voltage and the reset voltage.

[0074] Reference Fig.11 , for a set operation, a first gate voltage having a positive polarity may be applied to the gate electrode layer 330, and oxygen vacancies in the first resistance material layer 320a and the second resistance material layer 320b may move toward the substrate 310. Subsequently, the first gate voltage applied to the gate electrode layer 330 may be removed, and a set voltage equal to or higher than a predetermined threshold voltage may be applied between the first electrode pattern layer 340 and the second electrode pattern layer 350. Thus, an electric field caused by the set voltage may be formed inside the resistance change layer 320.

[0075] The electric field generated by the setting voltage may be concentrated on the pattern edge portions 340A and 350A of the first electrode pattern layer 340 and the second electrode pattern layer 350, respectively. If the first resistive material layer 320a is a high resistor compared to the second resistive material layer 320b, a relatively large voltage may be applied to the first resistive material layer 320a when the setting voltage is applied across the first resistive material layer 320a and the second resistive material layer 320b between the first electrode pattern layer 340 and the second electrode pattern layer 350. As a result, the first trigger filament 325t1 and the second trigger filament 325t2 adjacent to the pattern edge portions 350A and 360A, respectively, may be formed in the first resistive material layer 320a.

[0076] The first trigger filament 325t1 and the second trigger filament 325t2 may be formed to contact the first electrode pattern layer 340 and the second electrode pattern layer 350, respectively. In addition, a connecting filament 325c connected to the first trigger filament 325t1 and the second trigger filament 325t2 may be formed in the second resistive material layer 320b. The connecting filament 325c connects the first trigger filament 325t1 and the second trigger filament 325t2 to form a conductive filament 30.

[0077] Reference Fig.12 For the reset operation, a second gate voltage including a bias voltage of negative polarity may be applied to the gate electrode layer 330. In addition, when the second gate voltage is applied, a reset voltage equal to or greater than a predetermined threshold voltage may be applied between the first electrode pattern layer 340 and the second electrode pattern layer 350. The reset voltage may have a different polarity from the set voltage.

[0078] According to one embodiment, the conductive filament 30 may decompose due to the Joule heat generated by the reset voltage. As a result of the decomposition, the oxygen vacancies 325 may be released from the conductive filament 30 and then distributed in the resistance change layer 320. The release of the oxygen vacancies 325 may occur frequently in the connecting filament 325c of the second resistive material layer 320b at a relatively high frequency. In addition, due to the second gate voltage, the released oxygen vacancies 325 may escape from the filament formation region. With the release of the oxygen vacancies 325, at least a portion of the conductive filament 30 may be disconnected. As a result, the resistance of the resistance change layer 320 may be increased. Therefore, the internal resistance state of the resistance change layer 320 may be converted from a low resistance state to a high resistance state.

[0079] According to the present embodiment, the resistance change layer 320 may include a first resistance material layer 320a and a second resistance material layer 320b. The first resistance material layer 320a may be a high resistor having a relatively low oxygen vacancy concentration, and the second resistance material layer 320b may be a low resistor having a relatively high oxygen vacancy concentration. Therefore, when the oxygen vacancies inside the first resistance material layer 320a and the second resistance material layer 320b move toward the substrate 310 under the first gate voltage, at least in part because the first resistance material layer 320a contains fewer oxygen vacancies, the frequency of the oxygen vacancies in the conductive channel at the interface between the first resistance material layer 320a and the substrate 310 and the electrons can be reduced. That is, the undesirable charge flow caused by the recombination of the vacancies and electrons between the first resistance material layer 320a and the substrate 310 can be prevented. In addition, when the setting voltage is applied, the electric field is more concentrated in the first resistance material layer 320a adjacent to the pattern edge portions 340A and 340B, thereby promoting the generation of the first trigger filament 325t1 and the second trigger filament 325t2.

[0080] Fig.13 2 is a cross-sectional view schematically showing a nonvolatile memory device according to another embodiment of the present disclosure. Fig.13 , except for the resistance change layer 420, the nonvolatile memory device 4 may have the same Fig.10 The configuration of the nonvolatile memory device 3 described above is substantially the same configuration. That is, the configuration of the substrate 410, the gate electrode layer 430, the first electrode pattern layer 440 and the second electrode pattern layer 450, the first pattern edge portion 440A and the second pattern edge portion 450A, and the gate insulating layer 460 can be the same as that of the above reference. Fig.12 The described configurations of the substrate 310 , the gate electrode layer 330 , the first and second electrode pattern layers 340 and 350 , the first and second pattern edge portions 340A and 350A, and the gate insulating layer 360 are substantially the same.

[0081] In one embodiment, the resistance change layer 420 may include a first resistance material layer 420a and a second resistance material layer 420b sequentially disposed on the first electrode pattern layer 440 and the second electrode pattern layer 450 and the substrate 410. That is, the first resistance material layer 420a may contact and be disposed on the first electrode pattern layer 440 and the second electrode pattern layer 450 and the substrate 410. The second resistance material layer 420b may contact and be disposed on the gate insulating layer 460.

[0082] Each of the first resistive material layer 420a and the second resistive material layer 420b may include a variable resistive material. The variable resistive material may have movable oxygen vacancies and movable metal ions. The metal ions may be positive ions or negative ions. The variable resistive material may be composed of the above reference Figure 1 The variable resistance material of the resistance change layer 120 of the described nonvolatile memory device 1 is substantially the same.

[0083] In one embodiment, the first resistive material layer 420a and the second resistive material layer 420b may include the same variable resistance material, however, the first resistive material layer 320a and the second resistive material layer 320b may be different from each other in other ways. For example, the first resistive material layer 420a may have a lower oxygen vacancy concentration than the second resistive material layer 420b or a lower movable metal ion concentration than the second resistive material layer 420b. The first resistive material layer 420a may be a high resistor compared to the second resistive material layer 420b. Moreover, the thickness of the first resistive material layer 420a may be less than the thickness of the second resistive material layer 420b.

[0084] In the manufacturing method according to the embodiment, as described above and in Fig.13 As described in, the first resistive material layer 420a and the second resistive material layer 420b can be formed on the first electrode pattern layer 440 and the second electrode pattern layer 450 and the substrate 410 using the same source material. During this process, a relatively high oxygen concentration can be provided first, so that a first resistive material layer 420a including an oxide with a low oxygen vacancy concentration can be formed. Subsequently, when the concentration of the injected oxygen is reduced, a second resistive material layer 420b including an oxide with a higher oxygen vacancy concentration can be formed. In some embodiments, the oxygen vacancies formed in the first resistive material layer 420a and the second resistive material layer 420b can be formed to have a concentration gradient, respectively. In some embodiments, the concentration of oxygen vacancies in the resistance change layer 420 can increase from the lower surface LS420 of the first resistive material layer 420a to the upper surface US420 of the second resistive material layer 420b.

[0085] In a manufacturing method according to another embodiment, the same source material can be used to form a first resistive material layer 420a and a second resistive material layer 420b on a first electrode pattern layer 440, a second electrode pattern layer 450 and a substrate 410. A relatively low concentration of movable metal ions can be provided in the first resistive material layer 420a. Subsequently, the concentration of the provided movable metal ions can be increased in the second resistive material layer 420b. In some embodiments, the movable metal ions formed inside the first resistive material layer 420a and the second resistive material layer 420b can be formed to have a concentration gradient, respectively. In some embodiments, the concentration of the movable metal ions distributed in the resistance change layer 420 can increase from the lower surface LS420 of the first resistive material layer 420a to the upper surface US420 of the second resistive material layer 420b.

[0086] Fig.14 and Fig.15 Schematically illustrates a set operation and a reset operation of a nonvolatile memory device according to another embodiment of the present disclosure. Fig.13 The non-volatile memory device 4 is combined Fig.14 and Fig.15 To describe the set operation and the reset operation. For ease of description, the case where the resistance change layer 420 is provided with oxygen vacancies having a positive charge is used as an example for explanation. However, the embodiments contemplated by the present disclosure are not limited thereto, and the operation may be substantially the same even when, for example, the resistance change layer 420 has movable metal ions with a positive charge or movable metal ions with a negative charge. In the latter case, the following description of the operation also applies, except that the polarities of the first and second gate voltages and the polarities of the set voltage and the reset voltage may be reversed.

[0087] Reference Fig.14 For a set operation, a first gate voltage including a bias voltage of a positive polarity may be applied to the gate electrode layer 430, and oxygen vacancies in the first resistance material layer 420a and the second resistance material layer 420b may move toward the substrate 410. Subsequently, the first gate voltage applied to the gate electrode layer 430 may be removed, and a set voltage equal to or greater than a predetermined threshold voltage may be applied between the first electrode pattern layer 440 and the second electrode pattern layer 450. Thus, an electric field from the set voltage may be formed inside the resistance change layer 420.

[0088] The electric field generated by the setting voltage may be concentrated on the pattern edge portions 440A and 450A of the first electrode pattern layer 440 and the second electrode pattern layer 450, respectively. In addition, the first resistive material layer 420a is a high resistor compared to the second resistive material layer 420b, so that when the setting voltage is applied to the first resistive material layer 420a and the second resistive material layer 420b, a relatively large voltage may be applied to the first resistive material layer 420a. As a result, the first trigger filament 425t1 and the second trigger filament 425t2 adjacent to the pattern edge portions 440A and 450A, respectively, may be formed in the first resistive material layer 420a.

[0089] Subsequently, a connecting filament 425c connected to the first trigger filament 425t1 and the second trigger filament 425t2 may be formed in the second resistive material layer 420b. The connecting filament 425c may connect the first trigger filament 425t1 and the second trigger filament 425t2, thereby completing the conductive filament 40.

[0090] Reference Fig.15 In the reset operation, a second gate voltage including a bias voltage of a negative polarity may be applied to the gate electrode layer 430. In addition, when the second gate voltage is applied, a reset voltage equal to or greater than a predetermined threshold voltage may be applied between the first electrode pattern layer 440 and the second electrode pattern layer 450. The reset voltage may have a different polarity from the set voltage.

[0091] According to one embodiment, the conductive filament 40 may be decomposed due to Joule heat generated by the reset voltage. As a result of the decomposition, the oxygen vacancies 425 are released from the conductive filament 40 and then distributed in the resistance change layer 420. The release of the oxygen vacancies 425 may occur at a relatively high frequency in the connecting filament 425c of the second resistive material layer 420b. In addition, due to the second gate voltage, the released oxygen vacancies 425 may escape from the filament formation region. With the release of the oxygen vacancies 425, at least a portion of the conductive filament 40 may be disconnected. As a result, the resistance of the resistance change layer 420 increases. Therefore, the internal resistance state of the resistance change layer 420 may be converted from a low resistance state to a high resistance state.

[0092] Fig.16 is a cross-sectional view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure. Fig.17 yes Fig.16 Circuit diagram of a nonvolatile memory device.

[0093] Reference Fig.16, the nonvolatile memory device 6 may include a substrate 610, a resistance change layer 620 disposed on the substrate 610, a gate insulating layer 660 disposed on the resistance change layer 620, a gate electrode layer 630 disposed on the gate insulating layer 660, and a first electrode pattern layer 640 and a second electrode pattern layer 650 disposed in the substrate 610 for contacting different parts of the resistance change layer 620, respectively. In the present embodiment, the gate electrode layer 630 may include first to fourth gate pattern layers 630a, 630b, 630c, and 630d disposed between the first electrode pattern layer 640 and the second electrode pattern layer 650 to be spaced apart from each other. The gate voltages applied to the first to fourth gate pattern layers 630a, 630b, 630c, and 630d may be independently controlled. In other words, different gate voltages may be applied to the first to fourth gate pattern layers 630a, 630b, 630c, and 630d. In other embodiments, the number of the gate pattern layers 630 a , 630 b , 630 c , and 630 d may not be limited to four, and the gate electrode layer 630 may have various other numbers of gate pattern layers.

[0094] The configurations of the substrate 610, the resistance change layer 620, the gate electrode layer 630, the first electrode pattern layer 640, the second electrode pattern layer 650, and the gate insulating layer 660 of the nonvolatile memory device 6 may be the same as those described above. Fig. 9 The described nonvolatile memory device 2 has substantially the same configuration of the substrate 110, resistance change layer 120, gate electrode layer 130, first and second electrode pattern layers 140 and 150, and gate insulating layer 160. In some embodiments, the gate insulating layer 660 of the nonvolatile memory device 6 may be omitted.

[0095] Fig.17 Can be Fig.16 A circuit diagram of a nonvolatile memory device 6 is shown. Fig.17 , the first to fourth memory cells MC1, MC2, MC3 and MC4 may be arranged between the source electrode SL and the drain electrode DL. Each of the first to fourth memory cells MC1, MC2, MC3 and MC4 may include a transistor-type nonvolatile memory element. The first to fourth memory cells MC1, MC2, MC3 and MC4 may include first to fourth resistance element layers VR1, VR2, VR3 and VR4 disposed between the gate insulating layer and the conductive channel of the corresponding transistor, respectively. The first to fourth memory cells MC1, MC2, MC3 and MC4 may constitute a transistor string connected in series.

[0096] Fig.16 The first electrode pattern layer 640 and the second electrode pattern layer 650 may correspond to Fig.17 The source electrode SL and the drain electrode DL. Fig.16The first to fourth gate pattern layers 630a, 630b, 630c and 630d may correspond to Fig.17 The first to fourth gate electrodes GL1, GL2, GL3 and GL4 are Fig.16 The portions of the resistance change layer 620 controlled by the first to fourth gate pattern layers 630a, 630b, 630c, and 630d may correspond to Fig.17 The first to fourth resistance element layers VR1, VR2, VR3 and VR4.

[0097] Figures 18 to 21 Schematically illustrates the operation of a nonvolatile memory device according to another embodiment of the present disclosure. Specifically, Figures 18 to 20 is a diagram showing a setting operation of a nonvolatile memory device, Fig.18 , 19 21 are views showing a reset operation of a nonvolatile memory device. Figures 18 to 21 The operation method of the nonvolatile memory device described will refer to the above reference Fig.16 As an example, the non-volatile memory device 6 described above will be used. Fig.17 The third memory cell MC3 having the third resistance element layer VR3 is used in the circuit diagram of FIG. 1 to describe the setting operation and the reset operation. The third resistance element layer VR3 may be a memory cell MC3 having the third resistance element layer VR3. Fig.16 The third gate pattern layer 630 c controls a portion of the resistance change layer 620 .

[0098] Reference Fig.18 , for the setting operation, a predetermined first gate voltage including a bias voltage of a positive polarity may be applied to the first to fourth gate pattern layers 630a, 630b, 630c, and 630d. Due to the first gate voltage, a conductive channel 2000 may be generated in a region of the substrate 610 adjacent to the resistance change layer 620. The electric field generated by the first gate voltage may also act on a region of the substrate 610 that does not overlap with the first to fourth gate pattern layers 630a, 630b, 630c, and 630d in the z direction and on a region of the substrate 610 that overlaps with the first to fourth gate pattern layers 630a, 630b, 630c, and 630d in the z direction. In a region of the substrate 610 that does not overlap with the first to fourth gate pattern layers 630a, 630b, 630c, and 630d in the z direction, the electric field formed by the gate pattern layers adjacent to each other extends in the x direction, thereby generating a driving force for forming the conductive channel 2000. As a result, the conductive channel 2000 may be formed in a continuous form from the first electrode pattern layer 640 to the second electrode pattern layer 650. In addition, movable oxygen vacancies or movable positive metal ions inside the resistance change layer 620 may move to a region adjacent to the substrate 610 due to the repulsive force generated by the first gate voltage.

[0099] Reference Fig.19 , while maintaining the first gate voltage applied to the first gate pattern layer 630a, the second gate pattern layer 630b, and the fourth gate pattern layer 630d, the first gate voltage applied to the third gate pattern layer 630c may be removed. Therefore, a portion of the conductive channel 2000 controlled by the third gate pattern layer 630c is degraded or removed, so that the conductive channel 2000 may be disconnected. Therefore, the conductive channel 2000 may be transformed into a disconnected conductive channel 2000C, and the ends 615E1 and 615E2 of the disconnected conductive channel 2000C may be electrically insulated from each other.

[0100] Reference Fig. 20 , when the first gate voltage is applied to the first gate pattern layer 630a, the second gate pattern layer 630b, and the fourth gate pattern layer 630d and the first gate voltage is removed from the third gate pattern layer 630c, a setting voltage may be applied between the first electrode pattern layer 640 and the first electrode pattern layer 650. Here, the setting voltage may be concentrated on both ends 615E1 and 615E2 of the disconnected conductive channel 2000C.

[0101] The set operation electric field formed by the set voltage may be applied to the resistance change layer 620 located between the two ends 615E1 and 615E2 of the disconnected conductive channel 2000C. Movable oxygen vacancies and movable metal ions inside the resistance change layer 620 may aggregate or combine under the electric field brought about by the set operation to form a conductive filament 60. The conductive filament 60 may connect the two ends 615E1 and 615E2 of the disconnected conductive channel 2000C.

[0102] In one embodiment, the conductive filament 60 may include trigger filaments 625t1 and 625t2 formed on the ends 615E1 and 615E2 of the disconnected conductive channel 2000C, respectively, and a connecting filament 625c connecting the trigger filaments 625t1 and 625t2. The method of forming the trigger filaments 625t1 and 625t2 and the connecting filament 625c may be the same as that described above with reference to Figures 2 to 5 The described method of forming the trigger filaments 125t1 and 125t2 and the connecting filament 125c is substantially the same. Through the above setting operation, the third memory cell MC3 can store signal information in a low resistance state.

[0103] Next, we will refer to Fig.18 , 19 and 21 describe the reset operation of the third storage unit. Fig.18 As described above, a first gate voltage may be applied to the first to fourth gate pattern layers 630 a , 630 b , 630 c , and 630 d to form a conductive channel 2000 in the substrate 610 .

[0104] Next, as above combined Fig.19 As described above, the first gate voltage applied to the first gate pattern layer 630a, the second gate pattern layer 630b, and the fourth gate pattern layer 630d can be maintained, and the first gate voltage applied to the third gate pattern layer 630c can be removed. Therefore, the portion of the conductive channel 2000 controlled by the third gate pattern layer 630c can be degraded or removed, so that the conductive channel 2000 can be disconnected. As a result, the conductive channel 2000 can be transformed into a disconnected conductive channel 2000C, and the ends 615E1 and 615E2 of the disconnected conductive channel 2000C can be electrically insulated from each other.

[0105] Then, if Fig.21 As shown in , when the first gate voltage is applied to the first gate pattern layer 630a, the second gate pattern layer 630b and the fourth gate pattern layer 630d, a predetermined second gate voltage may be applied to the third gate pattern layer 630c. The second gate voltage may have a polarity opposite to the first gate voltage. That is, the second gate voltage may include a bias voltage of negative polarity. In addition, a reset voltage may be applied between the first electrode pattern layer 640 and the second electrode pattern layer 650. The reset voltage may have a polarity opposite to the set voltage.

[0106] Reference Fig.21 , if there is a conductive filament 60 connecting the two ends 615E1 and 615E2 of the disconnected conductive channel 2000C in the resistance change layer 620, the conductive filament 60 can be decomposed due to the reset voltage and the oxygen vacancy 625 can be released from the conductive filament 60. In addition, the oxygen vacancy 625 can move toward the third gate pattern layer 630c under the attraction generated by the second gate voltage. Therefore, the ends 615E1 and 615E2 of the disconnected conductive channel 2000C can be electrically insulated from each other again. Through the above-mentioned reset operation, the third memory cell MC3 can store signal information of the high resistance state.

[0107] Fig.22A is a perspective view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure. Fig. 22B It is along Fig.22A A cross-sectional view of a nonvolatile memory device taken along line II′. Fig.23 yes Fig.22A and 22B Circuit diagram of a nonvolatile memory device.

[0108] Reference Fig.22A and 22B, the nonvolatile memory device 7 may include a substrate 701 and a gate structure 710 disposed on the substrate 701. In addition, the nonvolatile memory device 7 may include a first hole pattern 71a and a second hole pattern 71b penetrating the gate structure 710 over the substrate 701. The nonvolatile memory device 7 may include a first resistance change layer 730a and a second resistance change layer 730b and a first channel layer 740a and a second channel layer 740b, which sequentially cover sidewall surfaces of the gate structure 710 inside the first hole pattern 71a and the second hole pattern 71b, respectively.

[0109] The nonvolatile memory device 7 may further include a first gate insulating layer 720a and a second gate insulating layer 720b, the first gate insulating layer 720a and the second gate insulating layer 720b being respectively located between the sidewall surface of the gate structure 710 inside the first hole pattern 71a and the second hole pattern 71b and the first resistance change layer 730a and the second resistance change layer 730b. The nonvolatile memory device 7 may further include a channel lower contact layer 705 contacting an end of each of the first channel layer 740a and the second channel layer 740b on the substrate 701. The nonvolatile memory device 7 may include a first channel upper contact layer 760a and a second channel upper contact layer 760b contacting the other end of each of the first channel layer 740a and the second channel layer 740b. The first and second channel upper contact layers 760a and 760b may contact the other end portions of the first and second channel layers 740a and 740b disposed away from the end portions of each of the first and second channel layers 740a and 740b in a direction perpendicular to the substrate 701 (ie, the z direction).

[0110] Reference Fig.22A and 22B The substrate 701 may include a semiconductor material. Specifically, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), black phosphorus, indium gallium zinc oxide (IGZO), or a combination of two or more thereof.

[0111] The base insulating layer 702 may be disposed on the substrate 701. The base insulating layer 702 may electrically insulate the under-channel contact layer 705 from the substrate 701. The base insulating layer 702 may include an insulating material. The insulating material may include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof.

[0112] The channel lower contact layer 705 may be disposed on the base insulating layer 702. The channel lower contact layer 705 may be electrically connected to the first channel layer 740a and the second channel layer 740b. Although not shown, the channel lower contact layer 705 may be electrically connected to the source electrode. The channel lower contact layer 705 may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof, doped with n-type dopants or p-type dopants.

[0113] The gate structure 710 may be disposed on the lower channel contact layer 705. The gate structure 710 may include first to fourth gate electrode layers 712a, 712b, 712c, and 712d and first to fifth interlayer insulating layers 713a, 713b, 713c, 713d, and 713e, which are alternately stacked along a first direction (i.e., z direction) perpendicular to the substrate 701. The first interlayer insulating layer 713a may be disposed to contact the lower channel contact layer 705. The fifth interlayer insulating layer 713e may be disposed as the uppermost layer of the gate structure 710.

[0114] Each of the first to fourth gate electrode layers 712a, 712b, 712c and 712d may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide or a conductive metal oxide. The conductive material may include, for example, silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide or a combination of two or more thereof, which are doped with n-type dopants or p-type dopants. Each of the first to fifth interlayer insulating layers 713a, 713b, 713c, 713d and 713e may include an insulating material. The insulating material may include, for example, an oxide, a nitride, an oxynitride or a combination of two or more thereof.

[0115] In some embodiments, the number of gate electrode layers of the gate structure 710 is not necessarily limited to four. The gate electrode layers may be arranged in various other numbers, and the interlayer insulating layer may insulate the gate electrode layers from each other along the first direction (ie, the z direction).

[0116] Reference Fig.22A and 22B, a first hole pattern 71a and a second hole pattern 71b may be formed to penetrate the gate structure 710 on the lower contact layer 705. In one embodiment, the first hole pattern 71a and the second hole pattern 71b may be spaced apart from each other in the y direction. The first hole pattern 71a and the second hole pattern 71b may be formed, for example, by known photolithography and etching processes.

[0117] The first gate insulating layer 720a and the second gate insulating layer 720bb may be disposed inside the first hole pattern 71a and the second hole pattern 71b, respectively, to cover the sidewall surface of the gate structure 710. Each of the first gate insulating layer 720a and the second gate insulating layer 720bb may include an insulating material. Each of the first gate insulating layer 720a and the second gate insulating layer 720b may include, for example, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc.

[0118] The first resistance change layer 730a and the second resistance change layer 730b may be disposed on the first gate insulating layer 720a and the second gate insulating layer 720b, respectively. The first resistance change layer 730a and the second resistance change layer 730b may cover the sidewall surface of the gate structure 710 inside the first hole pattern 71a and the second hole pattern 71b, respectively, and the first gate insulating layer 720a and the second gate insulating layer 720b are located therebetween. Each of the first resistance change layer 730a and the second resistance change layer 730b may include a variable resistance material. The variable resistance material may include movable oxygen vacancies and movable metal ions. The metal ions may be positive ions or negative ions. The variable resistance material may be composed of the above reference Figure 1 The variable resistance material of the resistance change layer 120 of the described nonvolatile memory device 1 is substantially the same.

[0119] The first channel layer 740a and the second channel layer 740b may be disposed on the first resistance change layer 730a and the second resistance change layer 730b, respectively. The first channel layer 740a and the second channel layer 740b may cover the first resistance change layer 730a and the second resistance change layer 730b inside the first hole pattern 71a and the second hole pattern 71b, respectively. Each of the first channel layer 740a and the second channel layer 740b may include a semiconductor material. As an example, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs) and similar materials. As another example, the semiconductor material may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include transition metal disulfide (TMDC), black phosphorus, etc. Transition metal disulfide (TMDC) may include, for example, molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), etc. The semiconductor material may include, for example, a metal oxide, such as indium gallium zinc oxide (IGZO).

[0120] Meanwhile, the first filling insulating layer 750a and the second filling insulating layer 750b may be disposed in the first hole pattern 71a and the second hole pattern 71b, respectively, and the first gate insulating layer 720a and the second gate insulating layer 720b, the first resistance change layer 730a and the second resistance change layer 730b, and the first channel layer 740a and the second channel layer 740b may be formed in the first hole pattern 71a and the second hole pattern 71b, respectively. The first filling insulating layer 750a and the second filling insulating layer 750b may include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof.

[0121] The first channel contact layer 760a and the second channel contact layer 760b may be disposed on the first filling insulating layer 750a and the second filling insulating layer 750b inside the first hole pattern 71a and the second hole pattern 71b, respectively. Each of the first channel contact layer 760a and the second channel contact layer 760b may contact the end of each of the first channel layer 740a and the second channel layer 740b, respectively. The first channel contact layer 760a and the second channel contact layer 760b may be electrically connected to the drain electrode (not shown). In some embodiments, the first channel contact layer 760a and the second channel contact layer 760b may be disposed outside the first hole pattern 71a and the second hole pattern 71b, respectively. As an example, the first channel contact layer 760a and the second channel contact layer 760b may be disposed on the first channel layer 740a and the second channel layer 740b, and are electrically connected to the first channel layer 740a and the second channel layer 740b, respectively.

[0122] Each of the first channel upper contact layer 760a and the second channel upper contact layer 760b may include a conductive material. The conductive material may include, for example, a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a conductive metal oxide. The conductive material may include, for example, n-type doped silicon (Si), tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

[0123] As described above, in the nonvolatile memory device 7 according to the embodiment, the first hole pattern 71a and the second hole pattern 71b penetrating the gate structure 710 on the channel lower contact layer 705 may be formed. The first gate insulating layer 720a and the second gate insulating layer 720bb, the first resistance change layer 730a and the second resistance change layer 730b, and the first channel layer 740a and the second channel layer 740b may be disposed in the first hole pattern 71a and the second hole pattern 71b, respectively. In addition, the first and second channel upper layers 760a and 760b may be disposed at the upper portions of the first hole pattern 71a and the second hole pattern 71b to contact portions of the first channel layer 740a and the second channel layer 740b, respectively.

[0124] The first to fourth gate electrode layers 712a, 712b, 712c, and 712d and the first to fifth interlayer insulating layers 713a, 713b, 713c, 713d, and 713e of the gate structure 710 may be disposed on the lower channel contact layer 705 to surround the first gate insulating layer 720a, the first resistance change layer 730a, and the first channel layer 740a in the first hole pattern 71a. Similarly, the first to fourth gate electrode layers 712a, 712b, 712c, and 712d and the first to fifth interlayer insulating layers 713a, 713b, 713c, 713d, and 713e of the gate structure 710 may be disposed on the lower channel contact layer 705 to surround the second gate insulating layer 720b, the second resistance change layer 730b, and the second channel layer 740b in the second hole pattern 71b.

[0125] In some embodiments, the number of hole patterns penetrating the gate structure 710 is not necessarily limited to two. Various numbers of hole patterns may be formed, and a gate insulation, a resistance change layer, a channel layer, a filling insulation layer, and an upper channel contact layer may be disposed in each hole pattern.

[0126] In some embodiments, the first and second gate insulating layers 720 a and 720 bb may be omitted, and the first and second resistance change layers 730 a and 730 b may be directly disposed on the sidewall surfaces of the gate structure 710 .

[0127] In some embodiments, the configurations of the first resistance change layer 730a and the second resistance change layer 730b may be the same as those described above. Fig.10 The configuration of the resistance change layer 320 of the nonvolatile memory device 3 described above is substantially the same, or may be respectively the same as that of the above reference 1. Fig.13The configuration of the resistance change layer 420 of the described non-volatile memory device 4 is substantially the same. That is, each of the first resistance change layer 730a and the second resistance change layer 730b may have a plurality of resistance material layers, and the resistance material layers may have different concentrations of oxygen vacancies or metal ions. For example, the first resistance change layer 730a may include a first resistance material layer in contact with the first channel layer 740a and a second resistance material layer disposed on the first resistance material layer and in contact with the first gate insulating layer 720a. In this case, the first resistance material layer may have a lower oxygen vacancy concentration than the second resistance material layer or a lower movable metal ion concentration than the second resistance material layer. In addition, the first resistance material layer may be a high resistor compared to the second resistance material layer. Similarly, the second resistance change layer 730b may have a configuration substantially the same as the first resistance change layer 730a.

[0128] Refer again Fig.22A In one embodiment, the nonvolatile memory device 7 may include separate first and second storage element units U71 and U72 that perform operations independently of each other for the first hole pattern 71a and the second hole pattern 71b, respectively. The channel lower contact layer 705 may be shared by the first storage element unit U71 and the second storage element unit U72. In addition, the first and second storage element units U71 and U72 may include a first channel upper contact layer 760a and a second channel upper contact layer 760b, respectively.

[0129] Fig.23 7 is a circuit diagram of a first storage element unit U71 of a nonvolatile memory device 7, the first storage element unit U71 including first to fourth gate electrode layers 712a, 712b, 712c, and 712d and a first gate insulating layer 720a, a first resistance change layer 730a, and a first channel layer 740a inside a first hole pattern 71a. The first storage element unit U71 may include first to fourth storage cells MC1, MC2, MC3, and MC4 of a transistor type. Although not shown, the second storage element unit U72 may have a circuit diagram substantially the same as that of the first storage element unit U71.

[0130] Reference Fig.23 , the first to fourth memory cells MC1, MC2, MC3 and MC4 may be connected in series between the source electrode SL and the drain electrode DL in the form of a string. Each of the first to fourth memory cells MC1, MC2, MC3 and MC4 may include a nonvolatile memory element in the form of a transistor. The first to fourth memory cells MC1, MC2, MC3 and MC4 may have first to fourth resistance element layers VR1, VR2, VR3 and VR4, respectively, which are disposed between the gate insulating layer and the conductive channel of the corresponding transistor.

[0131] exist Fig.22A and 22B In the embodiment, the lower channel contact layer 705 and the first upper channel contact layer 760a may be electrically connected to a source electrode (not shown) and a drain electrode (not shown), respectively. The source electrode and the drain electrode may correspond to Fig.23 The source electrode SL and the drain electrode DL. Fig.22A and 22B The first to fourth gate electrode layers 712a, 712b, 712c, and 712d may correspond to the first to fourth gate electrodes GL1, GL2, GL3, and GL4, respectively. Fig.22A and 22B The regions of the first resistance change layer 730a controlled by the first to fourth gate electrode layers 712a, 712b, 712c, and 712d may correspond to Fig.23 The first to fourth resistance element layers VR1, VR2, VR3 and VR4.

[0132] Figure 24 to Figure 27 Schematically illustrates the operation of a nonvolatile memory device according to another embodiment of the present disclosure. Specifically, Figure 24 to Figure 26 is a diagram showing a setting operation of a nonvolatile memory device, Fig.24 , 25 27 are views showing a reset operation of a nonvolatile memory device. Figure 24 to Figure 27 The operation method of the nonvolatile memory device described will refer to the above reference Fig.22A and 22B The non-volatile memory device 7 described herein. For ease of explanation, the Fig.23 The third memory cell MC3 having the third resistance element layer VR3 in the circuit diagram of FIG. 1 is used as an example to explain the setting operation and the reset operation. The third resistance element layer VR3 may correspond to the third memory cell MC3 having the third resistance element layer VR3. Fig.22A and 22B The third gate electrode layer 712c controls a portion of the first resistance change layer 730a.

[0133] Reference Fig.24, for the set operation, a predetermined first gate voltage including a bias voltage of a positive polarity may be applied to the first to fourth gate electrode layers 712a, 712b, 712c, and 712d. Due to the first gate voltage, a conductive channel 3000 may be formed in a region of the first channel layer 740a adjacent to the first resistance change layer 730a. The electric field generated by the first gate voltage may also act on a region of the first channel layer 740a that does not overlap with the first to fourth gate electrode layers 712a, 712b, 712c, and 712d in the x direction and on a region of the first channel layer 740a that overlaps with the first to fourth gate electrode layers 712a, 712b, 712c, and 712d in the x direction. In a region of the first channel layer 740a that does not overlap with the first to fourth gate electrode layers 712a, 712b, 712c, and 712d in the x direction, an electric field generated by an adjacent gate electrode layer may extend in the z direction, thereby generating a driving force for forming the conductive channel 3000. As a result, the conductive channel 3000 may be formed in a continuous form across the first channel layer 740a in the z direction. In addition, due to the repulsive force generated by the first gate voltage, movable oxygen vacancies or movable positive metal ions in the first resistance change layer 730a may move to a region adjacent to the first channel layer 740a.

[0134] Reference Fig.25 , while maintaining the first gate voltage applied to the first gate electrode layer 712a, the second gate electrode layer 712b, and the fourth gate electrode layer 712d, the first voltage applied to the third gate electrode layer 712c may be removed. Therefore, a portion of the conductive channel 3000 controlled by the third gate electrode layer 712c may be degraded or removed, so that the conductive channel 3000 may be disconnected. Therefore, the conductive channel 3000 may be transformed into a disconnected conductive channel 3000C, and the ends 740E1 and 740E2 of the disconnected conductive channel 3000C may be electrically insulated from each other.

[0135] Reference Fig.26 , when the first gate voltage is applied to the first gate electrode layer 712a, the second gate electrode layer 712b, and the fourth gate electrode layer 712d and the first gate voltage is removed from the third gate electrode layer 712c, a setting voltage may be applied between the channel lower contact layer 705 and the first channel upper contact layer 760a. In this case, the setting voltage may be concentrated on the two end portions 740E1 and 740E2 of the disconnected conductive channel 3000C.

[0136] The setting operation electric field formed by the setting voltage may be applied to the first resistance change layer 730a located between the two ends 740E1 and 740E2 of the disconnected conductive channel 3000C. The movable oxygen vacancies or movable positive metal ions in the first resistance change layer 730a may be aggregated or combined under the electric field generated by the setting operation to form a conductive filament 70. The conductive filament 70 may connect the two ends 740E1 and 740E2 of the disconnected conductive channel 3000C.

[0137] In one embodiment, the conductive filament 70 may include a trigger filament formed on the two ends 740E1 and 740E2 of the disconnected channel 3000C and a connecting filament connecting the trigger filament. The trigger filament and the connecting filament may be combined with the above Figures 2 to 5 The trigger filaments 125t1 and 125t2 and the connection filament 125c are formed by substantially the same method as described above. Through the above-described setting operation, the third memory cell MC3 can store signal information of a low resistance state.

[0138] Next, the reset operation of the third storage cell MC3 will be described. Fig.24 As described, the first gate voltage may be applied to the first to fourth gate electrode layers 712 a , 712 b , 712 c , and 712 d to form the conductive channel 3000 in the first channel layer 740 a .

[0139] Next, as above combined Fig.25 As described above, the first gate voltage applied to the first gate electrode layer 712a, the second gate electrode layer 712b, and the fourth gate electrode layer 712d can be maintained, and the first gate voltage applied to the third gate electrode layer 712c can be removed. Therefore, a portion of the conductive channel 3000 controlled by the third gate electrode layer 712c can be degraded or removed, so that the conductive channel 3000 can be disconnected. Therefore, the conductive channel 3000 can be transformed into a disconnected conductive channel 3000C, and the two ends 740E1 and 740E2 of the disconnected conductive channel 3000C can be electrically insulated from each other.

[0140] Then, if Fig. 27 As shown in , when the first gate voltage is applied to the first gate electrode layer 712a, the second gate electrode layer 712b and the fourth gate electrode layer 712d, a predetermined second gate voltage can be applied to the third gate electrode layer 712c. The second gate voltage can have a polarity opposite to the first gate voltage. That is, the second gate voltage can include a bias voltage of negative polarity. Then, a reset voltage can be applied between the lower channel contact layer 705 and the first channel upper contact layer 760a. The reset voltage can have a polarity opposite to the set voltage.

[0141] If there is a conductive filament 70 connecting the two ends 740E1 and 740E2 of the disconnected conductive channel 3000C in the first resistance change layer 730a, the conductive filament 70 may be decomposed due to the second gate voltage and the reset voltage and the oxygen vacancy 735 may be released from the conductive filament 70. The released oxygen vacancy 735 may move toward the third gate electrode layer 712c under the effect of the attraction generated by the second gate voltage. Therefore, the two ends 740E1 and 740E2 of the disconnected conductive channel 3000C may be electrically insulated from each other again. Through the above-mentioned reset operation, the third storage cell MC3 may store signal information of a high resistance state.

[0142] Fig.28A is a perspective view schematically illustrating a nonvolatile memory device according to another embodiment of the present disclosure. Fig.28B It is along Fig.28A A cross-sectional view of a nonvolatile memory device taken along line II-II′. Fig.28C It is along Fig.28A 2 is a cross-sectional view of a nonvolatile memory device taken along line III-III′.

[0143] Reference FIG. 28A to FIG. 28C , the nonvolatile memory device 8 may include a substrate 801 and a first gate structure 810 and a second gate structure 910 disposed on or over the substrate 801. The nonvolatile memory device 8 may have first to third gate insulating layers 820a, 820b, and 820c covering the sidewall surface S1 of the first gate structure 810 on the substrate 801, first to third resistance change layers 830a, 830b, and 830c sequentially covering the first to third gate insulating layers 820a, 820b, and 820c, and first to third channel layers 840a, 840b, and 840c. In addition, the nonvolatile memory device 8 may have first to third gate insulation layers 920a, 920b and 920c covering the side wall surface S2 of the second gate structure 910 on the substrate 801, first to third resistance change layers 930a, 930b and 930c sequentially covering the first to third gate insulation layers 920a, 920b and 920c, and first to third channel layers 940a, 940b and 940c.

[0144] In some embodiments, the first to third gate insulating layers 820a, 820b, 820c, 920a, 920b, and 920c of the first gate structure 810 and the second gate structure 910 may be omitted. The first to third resistance change layers 830a, 830b, 830c, 930a, 930b, and 930c may be disposed to directly contact the sidewall surfaces S1 and S2 of the first gate structure 810 and the second gate structure 910, respectively.

[0145] Reference FIG. 28A to FIG. 28C, a substrate 801 may be provided, and the substrate 801 may be combined with the above Fig.22A and 22B The substrate 701 of the described non-volatile memory device 7 is substantially the same.

[0146] The base insulating layer 802 and the lower channel contact layer 805 may be sequentially disposed on the substrate 801. The configuration of the base insulating layer 802 and the lower channel contact layer 805 may be combined with the above Fig.22A and 22B The configurations of the base insulating layer 702 and the under-channel contact layer 705 of the described nonvolatile memory device 7 are substantially the same.

[0147] The first gate structure 810 may be disposed on the under-channel contact layer 805. The first gate structure 810 may include first to fourth gate electrode layers 812a, 812b, 812c, and 812d and first to fifth interlayer insulating layers 813a, 813b, 813c, 813d, and 813e, which are alternately disposed or stacked along a first direction (i.e., z direction) perpendicular to the substrate 801. The first gate structure 810 may extend along a second direction (i.e., y direction) perpendicular to the first direction (i.e., z direction).

[0148] Each of the first to fourth gate electrode layers 812a, 812b, 812c, and 812d may include a conductive material. The conductive material of each of the first to fourth gate electrode layers 812a, 812b, 812c, and 812d may be combined with the above Fig.22A and 22B The conductive materials of the first to fourth gate electrode layers 712a, 712b, 712c, and 712d of the described nonvolatile memory device 7 are substantially the same. Each of the first to fifth interlayer insulating layers 813a, 813b, 813c, 813d, and 813e may include an insulating material. The insulating materials of the first to fifth interlayer insulating layers 813a, 813b, 813c, 813d, and 813e may be combined with the above Fig.22A and 22B The insulating materials of the first to fifth interlayer insulating layers 713 a , 713 b , 713 c , 713 d , and 713 e of the described nonvolatile memory device 7 are substantially the same.

[0149] In some embodiments, the number of gate electrode layers of the first gate structure 810 may not necessarily be limited to four. Various other numbers of gate electrode layers may be configured, and the interlayer insulating layer may insulate the gate electrode layers from each other along the first direction (ie, the z direction).

[0150] Reference FIG. 28A to FIG. 28C, the first to third gate insulating layers 820a, 820b and 820c may be disposed on the lower channel contact layer 805 to cover the sidewall surface S1 of the first gate structure 810. The first to third gate insulating layers 820a, 820b and 820c may be separated from each other by the first and second unit insulating structures 872 and 874 relative to the second direction (i.e., the y direction). That is, the first to third gate insulating layers 820a, 820b and 820c may be spaced apart from each other relative to the second direction (i.e., the y direction). Each of the first to third gate insulating layers 820a, 820b and 820c may include an insulating material. The insulating material of each of the first to third gate insulating layers 820a, 820b and 820c may be combined with the above Fig.22A and 22B The insulating materials of the first gate insulating layer 720 a and the second gate insulating layer 720 b of the described nonvolatile memory device 7 are substantially the same.

[0151] The first to third resistance change layers 830a, 830b and 830c and the first to third channel layers 840a, 840b and 840c may be disposed on the channel lower contact layer 805 to sequentially cover the first to third gate insulation layers 820a, 820b and 840c. The first to third resistance change layers 830a, 830b and 830c may be separated from each other by the first and second unit insulation structures 872 and 874 relative to the second direction (i.e., the y direction). Similarly, the first to third channel layers 840a, 840b and 840c may be separated from each other by the first and second unit insulation structures 872 and 874 relative to the second direction (i.e., the y direction).

[0152] Each of the first to third resistance change layers 830a, 830b, and 830c may include a variable resistance material. The variable resistance material of each of the first to third resistance change layers 830a, 830b, and 830c may be combined with the above Fig.22A and 22B The variable resistance materials of the first resistance change layer 730a and the second resistance change layer 730b of the nonvolatile memory device 7 described above are substantially the same. Each of the first to third channel layers 840a, 840b, and 840c may include a semiconductor material. The semiconductor material of each of the first to third channel layers 840a, 840b, and 840c may be combined with the above Fig.22A and 22B The semiconductor materials of the first channel layer 740 a and the second channel layer 740 b of the described nonvolatile memory device 7 are substantially the same.

[0153] Meanwhile, the second gate structure 910 may be disposed on the under-channel contact layer 805 in a third direction (i.e., the x direction) spaced apart from the first gate structure 810. The second gate structure 910 may include first to fourth gate layers 912a, 912b, 912c, and 912d and first to fifth interlayer insulating layers 913a, 913b, 913c, 913d, and 913e alternately disposed or stacked along the first direction (i.e., the z direction). The construction of the first to fourth gate electrode layers 912a, 912b, 912c and 912d and the first to fifth interlayer insulating layers 913a, 913b, 913c, 913d and 913e may be substantially the same as the construction of the first to fourth gate electrode layers 812a, 812b, 812c and 812d and the first to fifth interlayer insulating layers 813a, 813b, 813c, 813d and 813e of the first gate structure 810.

[0154] Reference FIG. 28A to FIG. 28C , the first to third gate insulating layers 920a, 920b, and 920c may be disposed on the lower channel contact layer 805 to cover the sidewall surface S2 of the second gate structure 910. The first to third gate insulating layers 920a, 920b, and 920c may be separated from each other relative to the second direction (i.e., the y direction) by the first and second unit insulating structures 872 and 874. That is, the first to third gate insulating layers 920a, 920b, and 920c may be spaced apart from each other relative to the second direction (i.e., the y direction).

[0155] The first to third resistance change layers 930a, 930b and 930c and the first to third channel layers 940a, 940b and 940c may be disposed on the channel lower contact layer 805 to sequentially cover the first to third gate insulation layers 920a, 920b and 920c. The first to third resistance change layers 930a, 930b and 930c may be separated from each other by the first and second unit insulation structures 872 and 874 relative to the second direction (i.e., the y direction). Similarly, the first to third channel layers 940a, 940b and 940c may be separated from each other by the first and second unit insulation structures 872 and 874 relative to the second direction (i.e., the y direction).

[0156] The construction of the first to third gate insulation layers 920a, 920b and 920c, the first to third resistance change layers 930a, 930b and 930c, and the first to third channel layers 940a, 940b and 940c may be substantially the same as the construction of the first to third gate insulation layers 820a, 820b and 820c, the first to third resistance change layers 830a, 830b and 830c, and the first to third channel layers 840a, 840b and 840c of the first gate structure 810, respectively.

[0157] Reference FIG. 28A to FIG. 28C, the first to third filling structures 850a, 850b, and 850c may be disposed between the first to third channel layers 840a, 840b, and 840c of the first gate structure 810 and the first to third channel layers 940a, 940b, and 940c of the second gate structure 910. Each of the first to third filling structures 850a, 850b, and 850c may include an insulating material. The insulating material may include, for example, an oxide, a nitride, an oxynitride, or a combination of two or more thereof.

[0158] The first to third channel upper contact layers 860a, 860b, and 860c may be disposed on the first to third filling structures 850a, 850b, and 850c, respectively. The first to third channel upper contact layers 860a, 860b, and 860c may be separated from each other by the first unit insulating structure 872 and the second unit insulating structure 874. The first channel upper contact layer 860a may be disposed to contact the first channel layer 840a of the first gate structure 810 and the first channel layer 940a of the second gate structure 910. The second channel upper contact layer 860b may be disposed to contact the second channel layer 840b of the first gate structure 810 and the second channel layer 940b of the second gate structure 910. The third channel upper contact layer 860c may be disposed to contact the third channel layer 840c of the first gate structure 810 and the third channel layer 940c of the second gate structure 910.

[0159] The first unit insulating structure 872 and the second unit insulating structure 874 may be disposed on the lower channel contact layer 805 to extend in the first direction (i.e., the z direction). The first unit insulating structure 872 and the second unit insulating structure 874 may be disposed to contact the first gate structure 810 and the second gate structure 910 in the third direction (i.e., the x direction), respectively. Each of the first unit insulating structure 872 and the second unit insulating structure 874 may include an insulating material. The insulating material may include, for example, an oxide, a nitride, an oxynitride, or a combination of two or more thereof.

[0160] Refer again Fig.28A, the nonvolatile memory device 8 may include first to sixth storage element units U81, U82, U83, U84, U85 and U86 that perform operations independently of each other. The first storage element unit U81 may include a portion of the first gate structure 810, a first gate insulation layer 820a, a first resistance change layer 830a, a first channel layer 840a and a first channel upper contact layer 860a. The second storage element unit U82 may include a portion of the first gate structure 810, a second gate insulation layer 820b, a second resistance change layer 830b, a second channel layer 840b and a second channel upper contact layer 860b. The third storage element unit U83 may include a portion of the first gate structure 810, a third gate insulation layer 820c, a third resistance change layer 830c, a third channel layer 840c and a third channel upper contact layer 860c. The fourth storage element unit U84 may include a portion of the second gate structure 910, a first gate insulating layer 920a, a first resistance change layer 930a, a first channel layer 940a, and a first channel upper contact layer 860a. The fifth storage element unit U85 may include a portion of the second gate structure 910, a second gate insulating layer 920b, a second resistance change layer 930b, a second channel layer 940b, and a second channel upper contact layer 860b. The sixth storage element unit U86 may include a portion of the second gate structure 910, a third gate insulating layer 920c, a third resistance change layer 930c, a third channel layer 940c, and a third channel upper contact layer 860c. The first to sixth storage element units U81, U82, U83, U84, U85, and U86 may share a channel lower contact layer 805. Furthermore, the first and fourth storage element units U81 and U84 may share a first channel upper contact layer 860a, the second and fifth storage element units U82 and U85 may share a second channel upper contact layer 860b, and the third and sixth storage element units U83 and U86 may share a third channel upper contact layer 860c.

[0161] The operation methods of the first to sixth storage element units U81, U82, U83, U84, U85 and U86 can be combined with the above Fig.22A and 22B The operation method of the nonvolatile memory device 7 described is basically the same. As an example, the circuit diagram of any one of the first to sixth storage element units U81, U82, U83, U84, U85 and U86 may be the same as Fig.23 In addition, the setting operation and the reset operation of any one of the first to sixth storage element units U81, U82, U83, U84, U85 and U86 can be combined with the above Fig.24 and Fig. 27 The set operation and the reset operation of the described nonvolatile memory device 7 are substantially the same.

[0162] The embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure and the appended claims.

Claims

1. A nonvolatile memory device, comprising: substrate; a gate structure disposed on the substrate, the gate structure comprising at least one gate electrode layer and at least one interlayer insulating layer alternately stacked, a hole pattern penetrating the gate structure on the substrate; a resistance change layer covering a sidewall surface of the gate structure in the hole pattern and including a variable resistance material; and a channel layer arranged to cover the resistance change layer in the hole pattern; Wherein, the resistance change layer includes conductive filaments extending in a vertical direction along the channel layer; Wherein, the resistance change layer includes a first resistance material layer contacting the channel layer, and a second resistance material layer disposed on the first resistance material layer; wherein the first resistive material layer has a lower oxygen vacancy concentration than the second resistive material layer or a lower mobile metal ion concentration than the second resistive material layer; Wherein, the conductive filaments include: first and second trigger filaments vertically spaced from each other in the first resistive material layer; and a connecting filament in the second resistive material layer connecting the first trigger filament to the second trigger filament; The diameters of the first and second trigger filaments are greater than the diameter of the connecting filament.

2. The nonvolatile memory device according to claim 1, further comprising: a lower channel contact layer contacting one end of the channel layer and electrically connected to the source electrode; and A channel contact layer contacts the other end of the channel layer in a direction perpendicular to the substrate and is electrically connected to the drain electrode. 3 . The nonvolatile memory device according to claim 1 , further comprising a gate insulating layer disposed between the sidewall surface of the gate structure in the hole pattern and the resistance change layer.

4. The nonvolatile memory device according to claim 1, wherein: The resistance change layer includes movable oxygen vacancies and movable metal ions.

5. The nonvolatile memory device according to claim 1, wherein: The first resistance material layer has a higher resistance than the second resistance material layer.

6. The nonvolatile memory device according to claim 4, wherein: The resistance change layer has an oxygen vacancy concentration or a metal ion concentration that increases from a region adjacent to an interface with the channel layer to a region adjacent to an interface with the gate structure.

7. A nonvolatile memory device, comprising: substrate; a gate structure disposed on the substrate, the gate structure comprising at least one gate electrode layer and at least one interlayer insulating layer alternately disposed in a first direction perpendicular to the substrate, and the gate structure extending in a second direction perpendicular to the first direction; a resistance variable layer, which covers the sidewall surface of the gate structure, is disposed on the substrate and includes a variable resistance material; and a channel layer disposed on the substrate and arranged to cover the resistance change layer; Wherein, the resistance change layer includes conductive filaments extending in a vertical direction along the channel layer; Wherein, the resistance change layer includes a first resistance material layer contacting the channel layer, and a second resistance material layer disposed on the first resistance material layer; wherein the first resistive material layer has a lower oxygen vacancy concentration than the second resistive material layer or a lower mobile metal ion concentration than the second resistive material layer; Wherein, the conductive filaments include: first and second trigger filaments vertically spaced from each other in the first resistive material layer; and a connecting filament in the second resistive material layer connecting the first trigger filament to the second trigger filament; The diameters of the first and second trigger filaments are greater than the diameter of the connecting filament.

8. The nonvolatile memory device according to claim 7, further comprising: a lower channel contact layer contacting one end of the channel layer and electrically connected to the source electrode; and An on-channel contact layer contacts the other end of the channel layer disposed away from the end of the channel layer in the first direction and is electrically connected to the drain electrode. 9 . The nonvolatile memory device according to claim 7 , further comprising a gate insulating layer disposed between the sidewall surface of the gate structure and the resistance change layer.

10. The nonvolatile memory device according to claim 7, further comprising a plurality of cell insulation structures disposed on the substrate and spaced apart from each other along the second direction, in, The plurality of unit insulating structures extend along the first direction on the substrate and extend in a third direction perpendicular to the first direction and the second direction to separate the resistance change layer and the channel layer with respect to the second direction.

Images