EUV photomask and method for manufacturing the same

Abstract

The present disclosure relates to an EUV photomask and a method for manufacturing the same. A reflective mask includes: a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, and an absorber layer disposed on the cap layer. The absorber layer includes a base material made of one or more of a Cr-based material, an Ir-based material, a Pt-based material, or a Co-based material, and further includes one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se, and Bi.

Description

Technical Field

[0001] The present disclosure generally relates to EUV photomasks and methods of making the same. Background Art

[0002] Photolithography is one of the key operations in the semiconductor manufacturing process. Photolithography technology includes ultraviolet lithography, deep ultraviolet lithography, and extreme ultraviolet lithography (EUVL). Photomask is an important component in photolithography. It is crucial to manufacture EUV photomasks with high contrast, including high reflectivity parts and high absorption parts. Summary of the invention

[0003] According to one embodiment of the present disclosure, a reflective mask is provided, comprising: a substrate; a reflective multilayer disposed on the substrate; a cap layer disposed on the reflective multilayer; and an absorber layer disposed on the cap layer, wherein the absorber layer comprises a base material made of one or more of a Cr-based material, an Ir-based material, a Pt-based material or a Co-based material, and further comprises one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

[0004] According to another embodiment of the present disclosure, a reflective mask is provided, comprising: a substrate; a reflective multilayer disposed on the substrate; a cap layer disposed on the reflective multilayer; an intermediate layer disposed on the cap layer; and an absorber layer disposed on the intermediate layer, wherein the intermediate layer is a layer comprising one or more metalloid elements.

[0005] According to another embodiment of the present disclosure, a method for manufacturing a reflective mask is provided, the method comprising: forming a photoresist layer on a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an absorber layer on the cap layer, and a hard mask layer; patterning the photoresist layer; patterning the hard mask layer by using the patterned photoresist layer as a mask; patterning the absorber layer by using the patterned hard mask layer as a mask; and removing the hard mask layer, wherein, during patterning the absorber layer, a protective layer is formed on the etched sidewalls of the absorber layer, wherein the protective layer inhibits lateral etching of the absorber layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration purposes. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A , Figure 1B and Figure 1C An EUV photo mask blank according to an embodiment of the present disclosure is shown.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E and Figure 2F A method for manufacturing an EUV photomask according to an embodiment of the present disclosure is schematically illustrated.

[0009] Figure 3A , Figure 3B , Figure 3C and Figure 3D A method for manufacturing an EUV photomask according to an embodiment of the present disclosure is schematically illustrated.

[0010] Figure 4A , Figure 4B and Figure 4C Cross-sectional views showing various states of manufacturing an EUV photomask according to an embodiment of the present disclosure are shown.

[0011] Figure 5A , Figure 5B , Figure 5C and Figure 5D Cross-sectional views showing various states of manufacturing an EUV photomask according to an embodiment of the present disclosure are shown.

[0012] Fig. 6A and Figure 6B Cross-sectional views showing various states of manufacturing an EUV photomask according to an embodiment of the present disclosure are shown.

[0013] Fig. 7A and Figure 7B A cross-sectional view of an EUV photomask according to an embodiment of the present disclosure is shown.

[0014] Fig. 8A A flowchart showing a method of manufacturing a semiconductor device, and Figure 8B , Figure 8C , Fig.8D and Fig. 8E Sequential manufacturing operations of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0015] It should be understood that the following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, the size of the element is not limited to the disclosed range or value, but may depend on the process conditions and / or desired characteristics of the device. In addition, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an additional feature that may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. For simplicity and clarity, various features may be arbitrarily drawn in different proportions.

[0016] In addition, for ease of description, spatially related terms (e.g., "below," "below," "below," "above," "upper," etc.) may be used herein to describe the relationship of an element or feature shown in the figure to another (one or more) element or (one or more) feature. These spatially related terms are intended to cover different orientations of the device in use or operation other than the orientation shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may also be interpreted accordingly. In addition, the term "made of..." may mean "including" or "consisting of..." In the present disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), rather than indicating that one element is from A, one element is from B, and one element is from C, unless otherwise specified.

[0017] Embodiments of the present disclosure provide a method for manufacturing an EUV photomask. More specifically, the present disclosure provides a technique for preventing or suppressing damage to a back conductive layer of an EUV photomask.

[0018] EUV lithography (EUVL) uses scanners that use light with a wavelength in the extreme ultraviolet (EUV) region (about 1 nm to about 100 nm, for example, 13.5 nm). The mask is a key component of the EUVL system. Since the optical material is not transparent to EUV radiation, the EUV photomask is a reflective mask. The circuit pattern is formed in an absorber layer disposed above the reflective structure. The absorber has a low EUV reflectivity, for example, less than 3-5%.

[0019] The present disclosure provides an EUV reflective photomask having a low reflective (high absorption) absorber structure.

[0020] Figure 1A and Figure 1B An EUV reflective photomask blank according to an embodiment of the present disclosure is shown. Figure 1Ais a plan view (seen from the top), and Figure 1B It is a cross-sectional view along the X direction.

[0021] In some embodiments, an EUV photomask having a circuit pattern is formed from an EUV photomask blank 5. The EUV photomask blank 5 includes a substrate 10, a multilayer Mo / Si stack 15 of a plurality of alternating layers of silicon and molybdenum, a cap layer 20, an absorber layer 25, and a hard mask layer 30. Figure 1B As shown, a back conductive layer 45 is formed on the back side of the substrate 10 .

[0022] In some embodiments, the substrate 10 is formed of a low thermal expansion material. In some embodiments, the substrate is a low thermal expansion glass or quartz, for example, quartz glass or fused quartz. In some embodiments, the low thermal expansion glass substrate transmits light of visible wavelengths, a portion of infrared wavelengths (near infrared) near the visible spectrum, and a portion of ultraviolet wavelengths. In some embodiments, the low thermal expansion glass substrate absorbs extreme ultraviolet wavelengths and deep ultraviolet wavelengths close to the extreme ultraviolet. In some embodiments, the size of the substrate 10 is 152 mm×152 mm and the thickness is about 20 mm. In other embodiments, the size of the substrate 10 is less than 152 mm×152 mm and is equal to or greater than 148 mm×148 mm. The shape of the substrate 10 is square or rectangular.

[0023] In some embodiments, the width of the functional layers (multilayer Mo / Si stack 15, cap layer 20, absorber layer 25, and hard mask layer 30) above the substrate is less than the width of the substrate 10. In some embodiments, the size of the functional layer is in the range of from about 138 mm×138 mm to 142 mm×142 mm. The shape of the functional layer is square or rectangular.

[0024] In other embodiments, the absorber layer 25 and the hard mask layer 30 have smaller dimensions than the substrate 10, the multilayer Mo / Si stack 15, and the cap layer 20, which are in the range of from about 138 mm×138 mm to 142 mm×142 mm, as shown in FIG. Figure 1C When each functional layer is formed by, for example, sputtering, a frame-shaped cover having an opening ranging from about 138 mm×138 mm to 142 mm×142 mm can be used to form a smaller size of one or more functional layers. In other embodiments, all layers above the substrate 10 have the same size as the substrate 10.

[0025] In some embodiments, the Mo / Si multilayer stack 15 includes about 30 layers of silicon and molybdenum alternating layers to about 60 layers of silicon and molybdenum alternating layers. In certain embodiments, about 40 to about 50 layers of silicon and molybdenum alternating layers are formed. In some embodiments, for a wavelength of interest, such as 13.5nm, the reflectivity is higher than about 70%. In some embodiments, the silicon layer and the molybdenum layer are formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), or any other suitable method of forming a film. Each layer of silicon and molybdenum is about 2nm to about 10nm thick. In some embodiments, the silicon layer and the molybdenum layer have approximately the same thickness. In other embodiments, the silicon layer and the molybdenum layer have different thicknesses. In some embodiments, the thickness of each silicon layer is about 4nm, and the thickness of each molybdenum layer is about 3nm.

[0026] In other embodiments, the multilayer stack 15 includes alternating layers of molybdenum and beryllium. In some embodiments, the number of layers in the multilayer stack 15 ranges from about 20 to about 100, but any number of layers is allowed as long as sufficient reflectivity is maintained for imaging the target substrate. In some embodiments, the reflectivity is greater than about 70% for wavelengths of interest, such as 13.5 nm. In some embodiments, the multilayer stack 15 includes about 30 to about 60 alternating layers of Mo and Be. In other embodiments of the present disclosure, the multilayer stack 15 includes about 40 to about 50 alternating layers of Mo and Be.

[0027] In some embodiments, the cap layer 20 is disposed on the Mo / Si multilayer stack 15 to prevent oxidation of the multilayer stack 15. In some embodiments, the cap layer 20 is formed of ruthenium, a ruthenium alloy (e.g., RuNb, RuZr, RuZrN, RuRh, RuNbN, RuRhN, RuV, or RuVN), or a ruthenium-based oxide (e.g., RuO2, RuNbO, RiVO, or RuON), and has a thickness ranging from about 2 nm to about 10 nm. In some embodiments, the thickness of the cap layer 20 is in the range from about 2 nm to about 5 nm. In some embodiments, the thickness of the cap layer 20 is 3.5 nm ± 10%. In some embodiments, the cap layer 20 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition (e.g., sputtering), or any other suitable method of forming a film. In other embodiments, a Si layer is used as the cap layer 20.

[0028] The absorber layer 25 is disposed on the cap layer 20. In some embodiments, the absorber layer 25 is a Ta-based material. In some embodiments, the absorber layer 25 is made of TaN, TaO, TaB, TaBO or TaBN, and has a thickness of about 25 nm to about 100 nm. In certain embodiments, the thickness of the absorber layer 25 is in the range from about 50 nm to about 75 nm. In other embodiments, the absorber layer 25 includes a Cr-based material, for example, CrN, CrO, CrON, CrB and / or CrBN. In some embodiments, the absorber layer 25 has a multilayer structure of Cr, CrO, CrON, CrB and / or CrBN. In other embodiments, the absorber layer 25 includes an Ir-based material, including elemental iridium (non-compound) or an iridium alloy, for example, IrPt, IrAl, IrRu, IrB, IrN, IrSi and / or IrTi. In other embodiments, the absorber layer 25 comprises a Pt-based material, including elemental platinum (not a compound) or a Pt alloy, such as PtAl, PtRu, PtB, PtSi, PtN and / or PtTi. In other embodiments, the absorber layer 25 comprises a Co-based material, including elemental cobalt (not a compound) or a Co alloy, such as CoO, CoB, CoBN, CoN and / or CoSi.

[0029] In some embodiments, the absorber layer 25 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film forming method. In some embodiments, one or more layers are disposed between the cap layer 20 and the absorber layer 25 as described below.

[0030] In some embodiments, the absorber layer 25 also includes one or more elements, for example, Si, B, Ge, Al, As, Sb, Te, Se, and / or Bi, as described below.

[0031] In some embodiments, an anti-reflection layer (not shown) is optionally disposed on the absorber layer 25. In some embodiments, the anti-reflection layer is formed of silicon oxide and has a thickness from about 2 nm to about 10 nm. In other embodiments, a TaBO layer or a Ta2O5 layer having a thickness ranging from about 2 nm to about 20 nm is used as the anti-reflection layer. In some embodiments, the thickness of the anti-reflection layer is about 3 nm to about 10 nm. In some embodiments, the anti-reflection layer is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable method of forming a film.

[0032] In some embodiments, the hard mask layer 30 is disposed on the absorber layer 25. In some embodiments, the hard mask layer 30 is formed on the anti-reflective layer. In some embodiments, the hard mask layer 30 is made of a Cr-based material, for example, CrN, CrO, CrON, or CrCON. In other embodiments, the hard mask layer 30 is made of a Ta-based material, for example, TaB, TaO, TaBO, or TaBN. In other embodiments, the hard mask layer 30 is made of silicon, a silicon-based compound (for example, SiN or SiON), ruthenium, or a ruthenium-based compound (Ru or RuB). In some embodiments, the thickness of the hard mask layer 30 is about 4 nm to about 20 nm. The material of the hard mask layer 30 is selected to have a sufficiently high etching selectivity for the absorber layer 25, and an etching rate that is the same or similar to that of the cap layer 20. In some embodiments, the hard mask layer 30 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable method of forming a film.

[0033] In some embodiments, the back conductive layer 45 is disposed on a second main surface of the substrate 10, which is opposite to the first main surface of the substrate 10 on which the Mo / Si multilayer stack 15 is formed. In some embodiments, the back conductive layer 45 is made of TaB (tantalum boride) or other Ta-based conductive materials. In some embodiments, tantalum boride is crystalline. Crystalline tantalum boride includes TaB, Ta5B6, Ta3B4 and TaB2. In other embodiments, tantalum boride is polycrystalline or amorphous. In other embodiments, the back conductive layer 45 is made of a Cr-based conductive material (CrN or CrON). In some embodiments, the sheet resistance of the back conductive layer 45 is equal to or less than 20Ω / □. In some embodiments, the sheet resistance of the back conductive layer 45 is equal to or greater than 0.1Ω / □. In some embodiments, the surface roughness Ra of the back conductive layer 45 is equal to or less than 0.25nm. In some embodiments, the surface roughness Ra of the back conductive layer 45 is equal to or greater than 0.05nm. In addition, in some embodiments, the flatness of the back conductive layer 45 (within the EUV photomask) is equal to or less than 50nm. In some embodiments, the flatness of the back conductive layer 45 is greater than 1nm. In some embodiments, the thickness of the back conductive layer 45 is in the range from about 50nm to about 400nm. In other embodiments, the back conductive layer 45 has a thickness of about 50nm to about 100nm. In certain embodiments, the thickness is in the range from about 65nm to about 75nm. In some embodiments, the back conductive layer 45 is formed by atmospheric chemical vapor deposition (CVD), low pressure CVD, plasma enhanced CVD, laser enhanced CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), physical vapor deposition (including thermal deposition, pulsed laser deposition, electron beam evaporation, ion beam assisted evaporation and sputtering), or any other suitable method of forming a film. In some embodiments, in the case of CVD, the source gas includes TaCl5 and BCl3.

[0034] In some embodiments, a photocatalytic layer (not shown) is provided on the cap layer 20, which can catalyze hydrocarbon residues formed on the photomask into CO2 and / or H2O using EUV radiation. Thus, in-situ self-cleaning of the mask surface is performed. In some embodiments, in the EUV scanner system, oxygen and hydrogen are injected into the EUV chamber to maintain the chamber pressure (e.g., about 2 Pa). The chamber background gas can be a source of oxygen. In addition to the photocatalytic function, the photocatalytic layer has sufficient durability and resistance to various chemicals and various chemical processes (e.g., cleaning and etching). In some examples, the ozonated water used to manufacture the EUV reflective mask in the subsequent process can damage the cap layer 20 made of Ru and cause a significant decrease in EUV reflectivity. In some embodiments, after Ru oxidation, the Ru oxide is easily etched away by an etchant such as C12 or CF4 gas. In some embodiments, the photocatalytic layer includes one or more of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO), and cadmium sulfide (CdS). In some embodiments, the thickness of the photocatalytic layer is in a range from about 2 nm to about 10 nm, and in other embodiments, in a range from about 3 nm to about 7 nm. When the thickness is too thin, the photocatalytic layer may not be sufficient to serve as an etch stop layer. When the thickness is too large, the photocatalytic layer may absorb EUV radiation.

[0035] Figure 2A-2F and Figure 3A-3D The method for manufacturing an EUV photomask for extreme ultraviolet lithography (EUVL) is schematically shown. It should be understood that in Figure 2A-Figure 3D Additional operations are provided before, during, and after the illustrated processes, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of these operations / processes may be interchangeable.

[0036] In the manufacture of the EUV photomask, a first photoresist layer 35 is formed on the hard mask layer 30 of the EUV photomask blank. Figure 2A As shown, the photoresist layer 35 is selectively exposed to actinic radiation EB, such as Figure 2B In some embodiments, before forming the first photoresist layer 35, the EUV photomask blank is inspected. The selectively exposed first photoresist layer 35 is developed to form a pattern 40 in the first photoresist layer 35, as shown in FIG. Figure 2C As shown. In some embodiments, the actinic radiation EB is an electron beam or an ion beam. In some embodiments, pattern 40 corresponds to a pattern of semiconductor device features to be formed using an EUV photomask in a subsequent operation.

[0037] Next, the pattern 40 in the first photoresist layer 35 is extended into the hard mask layer 30, thereby forming a pattern 41 in the hard mask layer 30, the pattern 41 exposing portions of the absorber layer 25, such as Figure 2D In some embodiments, the pattern 41 extending into the hard mask layer 30 is formed by etching using a suitable wet or dry etchant that is selective to the absorber layer 25. After the pattern 41 is formed in the hard mask layer 30, the first photoresist layer 35 is removed using a photoresist stripper to expose the upper surface of the hard mask layer 30, as shown in FIG. Figure 2E shown.

[0038] Then, the pattern 41 in the hard mask layer 30 is extended into the absorber layer 25, thereby forming a pattern 42 in the absorber layer 25, exposing portions of the cap layer 20, such as Figure 2F As shown, and then the hard mask layer 30 is removed, as shown Figure 3A In some embodiments, the pattern 42 extending into the absorber layer 25 is formed by etching using a suitable wet or dry etchant that is selective to the absorber layer 25. In some embodiments, plasma dry etching is used.

[0039] like Figure 3B As shown, a second photoresist layer 50 is formed on the absorber layer 25, and the second photoresist layer 50 fills the pattern 42 in the absorber layer 25. The second photoresist layer 50 is selectively exposed to actinic radiation, such as an electron beam, an ion beam, or UV radiation. The selectively exposed second photoresist layer 50 is developed to form a pattern 55 in the second photoresist layer 50, as shown in FIG. Figure 3B As shown. Pattern 55 corresponds to a black edge surrounding the circuit pattern. The black edge is a frame-shaped area created by removing all the multiple layers on the EUV photomask in the area around the circuit pattern area. The frame-shaped area is created to prevent exposure of adjacent fields when printing the EUV photomask onto the wafer. In some embodiments, the width of the black edge is in the range from about 1 mm to about 5 mm.

[0040] Next, the pattern 55 in the second photoresist layer 50 is extended into the absorber layer 25, the cap layer 20 and the Mo / Si multilayer stack 15 to form a pattern 57 in the absorber layer 25, the cap layer 20 and the Mo / Si multilayer stack 15 (see Figure 3D ), the pattern 57 exposes multiple portions of the substrate 10, such as Figure 3C As shown. In some embodiments, pattern 57 is formed by etching using one or more suitable wet or dry etchants that are selective to each layer being etched. In some embodiments, plasma dry etching is used.

[0041] Then, the second photoresist layer 50 is removed using a suitable photoresist stripper to expose the upper surface of the absorber layer 25, such as Figure 3D In some embodiments of the present disclosure, the absorber layer 25, the cap layer 20, and the black edge pattern 57 in the Mo / Si multilayer stack 15 define a black edge of the photomask.

[0042] Typically, Cr-based materials, Ir-based materials, Pt-based materials, or Co-based materials (materials other than Ta-based materials) have a high EUV absorption (extinction) coefficient k. For example, the k value of CrN is 0.0387, which is higher than the k value of TaBN (0.031) and the k value of TaBO (0.027). Therefore, the thickness of the absorber layer can be reduced (for example, from 70nm of TaBN to 46nm of CrN), which can suppress the three-dimensional effect of the patterned absorber layer. However, Cr-based materials, Ir-based materials, Pt-based materials, or Co-based materials are difficult to etch due to their low etching rates, and it is difficult to control the shape of the patterned absorber layer. For example, the side of the patterned absorber layer may have a concave shape or a tapered shape, which causes a three-dimensional effect.

[0043] In an embodiment of the present disclosure, one or more elements are added to the absorber layer to control the profile of the patterned absorber layer 25. Specifically, the element is selected so that a protective (or passivation) layer is formed on the side of the patterned or etched absorber layer due to the reaction between the element and the etching gas. In some embodiments, the protective layer is an oxide.

[0044] In some embodiments, the absorber layer 25 further includes one or more additional metalloid elements, such as Si, B, Ge, Al, As, Sb, Te, Se, and / or Bi. In some embodiments, the additional elements are different from the elements constituting the absorber layer 25 as a base material.

[0045] In some embodiments, additional elements 25A are doped in the absorber layer 25, such as Figure 4A In some embodiments, the concentration of the additional element is from about 1×10 20 Atom / cm 3 Up to 1×10 22 Atom / cm 3 In other embodiments, the range is from about 5×10 20 Atom / cm 3 Up to 5×10 21 Atom / cm 3In some embodiments, the additional element 25A is uniformly distributed in the absorber layer 25. In other embodiments, the distribution of the additional element is non-uniform in the absorber layer. In some embodiments, the concentration of the additional element increases from the bottom (the interface between the cap layer 20 and the absorber layer) to the top (the interface between the absorber layer 25 and the hard mask layer 30). In other embodiments, the concentration of the additional element decreases from the bottom to the top. In other embodiments, the concentration of the additional element increases from the bottom to the top and then decreases, and in other embodiments, the concentration of the additional element decreases from the bottom to the top and then increases. In some embodiments, the concentration of the additional element is substantially uniform (within ±5%) in the lateral direction. In some embodiments, the concentration of the additional element 25A is in the range from 0.5 atomic % to 30 atomic %, and in other embodiments, in the EUV mask in the range from about 1 atomic % to 10 atomic %. When the amount of the additional element is less than these ranges, the protective effect described below may not be obtained, and when the amount of the additional element is greater than these ranges, absorption of EUV light by the absorber layer 25 may be reduced or etching of the absorber layer 25 may be difficult.

[0046] In some embodiments, the absorber layer 25 doped with the additional element 25A is formed by CVD, ALD or PVD including sputtering. In some embodiments, the sputtering process uses a sputtering target made of a material for the absorber layer (e.g., TaBN) and an additional element (e.g., Si). The sputtering target for the absorber layer can be set next to the sputtering target for the additional element, and the absorber layer doped with the additional element is formed by sputtering the two targets with an ion beam or an electron beam. By adjusting the ion beam or the electron beam, the concentration of the additional element can be adjusted. In some embodiments, these targets are sputtered by corresponding ion beams or electron beams. In some embodiments, in the case of CVD or ALD, an in-situ doping technique is adopted.

[0047] like Figure 4B and Figure 4CAs shown, during the etching of the absorber layer 25, a protective layer 29 is formed on the etched side of the absorber layer to inhibit lateral etching of the absorber layer. In some embodiments, the etching gas includes a chlorine-containing gas (e.g., Cl2, HCl, CCl4, etc.) and an oxygen-containing gas (e.g., O2). In some embodiments, a fluorine-containing gas (e.g., F2, SF6, fluorocarbons (CF4, CHF3, etc.), etc.) is used. In some embodiments, the oxygen in the etching gas reacts with the additional element 25A to form a protective layer 29 as a by-product of etching. In some embodiments, the protective layer is an oxide of the additional element 25A, such as silicon oxide, germanium oxide, boron oxide, etc. In some embodiments, the average thickness of the protective layer 29 is in a range from about 0.2 nm to about 2 nm. In other embodiments, a polymer containing carbon, fluorine and / or hydrogen is formed as the protective layer 29.

[0048] like Figure 4B and Figure 4C As shown, since the protective layer 29 is formed on the etched side of the absorber layer during the patterning of the absorber layer 25, the profile of the patterned absorber layer can be improved. In some embodiments, a substantially vertical sidewall is obtained. Specifically, an undercut of the absorber layer 25 below the hard mask layer 30, which would otherwise be formed during the over-etching step of the etching process, can be avoided.

[0049] In other embodiments, the additional element is provided in the mask blank as a layer 22 disposed between the cap layer 20 and the absorber layer 25, such as Figures 5A-5D As shown. Figure 5A As shown, an intermediate layer 22 is formed between the cap layer 20 and the absorber layer 25 as a source of additional elements. In some embodiments, the intermediate layer 22 is made of one of Si, B, Ge, Al, As, Sb, Te, Se and / or Bi (non-compound), or an alloy or compound thereof. In some embodiments, the thickness of the intermediate layer 22 is in the range from about 1 nm to about 10 nm, and in other embodiments, in the range from about 2 nm to about 5 nm. If the thickness is too small, the supply of additional elements used to form the protective layer is insufficient, and if the thickness is too large, the reflectivity and / or absorptivity of the EUV mask will be affected. In some embodiments, the intermediate layer is formed by CVD, PECVD, ALD, PVD (sputtering), or any other suitable method of forming a film. In some embodiments, the absorber layer 25 does not contain the elements of the intermediate layer 22.

[0050] like Figure 5B As shown, the etching of the absorber layer 25 reaches the intermediate layer 22. Then, during the over-etching step, the intermediate layer is etched to form Figure 5CThe protective layer 29 shown. Thus, an undercut or convex sidewall shape that would otherwise be formed during the over-etching step is suppressed. In some embodiments, the thickness of the protective layer 29 along the vertical direction is not uniform. In some embodiments, the thickness increases from the bottom to the top, such as Figure 5D In some embodiments, the intermediate layer 22 is formed within the absorbent layer 25 so that the intermediate layer 22 is disposed between the lower absorbent layer and the upper absorbent layer. In this case, the thickness of the lower absorbent layer is the same as or different (smaller / larger) from the thickness of the upper absorbent layer.

[0051] In some embodiments, a plurality of intermediate layers 23 are formed in the absorber layer 25, such as Fig. 6A As shown. In some embodiments, each intermediate layer 23 is made of one of Si, B, Ge, Al, As, Sb, Te, Se and / or Bi (non-compound), or an alloy thereof. In some embodiments, 2 to 10 layers made of additional elements as described above are within the absorber layer. In some embodiments, all intermediate layers 23 are made of the same material, while in other embodiments, at least one intermediate layer 23 is made of a different material than the remaining layers. In some embodiments, a layer is formed at the bottom of the absorber layer (similar to Figure 5A ) or a layer is formed on top of the absorber layer. In some embodiments, the thickness of each intermediate layer 23 is in a range from about 0.1 nm to about 1 nm, and in other embodiments, in a range from about 0.2 nm to about 0.5 nm. If the thickness is too small, the supply of additional elements used to form the protective layer is insufficient, and if the thickness is too large, the absorption capacity of the absorber layer 25 will be affected. In some embodiments, at least one intermediate layer 23 is a single layer or a double layer of the additional element. In some embodiments, the thicknesses of the intermediate layers 23 are the same as each other, and in other embodiments, at least one intermediate layer 23 has a different thickness from the remaining layers. In some embodiments, the intermediate layers 23 are arranged at equal intervals along the vertical direction. In other embodiments, the spacing of the intermediate layers 23 varies.

[0052] In some embodiments, the intermediate layer 22 or the intermediate layer 23 is formed by sputtering using a sputtering target made of an additional element (e.g., Si). The sputtering target may be disposed next to another sputtering target (e.g., a target for an absorber layer). By switching the target, a double-layer or multi-layer structure of the intermediate layer and the absorber layer may be formed. The switching may include switching an ion beam or an electron beam of the sputtering process to the target.

[0053] In some embodiments, the protective layer 29 remains on the finished photomask. In other embodiments, after patterning the absorber layer 25, the protective layer 29 is removed by, for example, wet and / or dry etching, and thus no protective layer remains on the finished photomask.

[0054] Fig. 7A 1 shows a cross-sectional view of a completed EUV photomask according to an embodiment of the present disclosure. Fig. 7A The EUV photomask with circuit pattern 42 shown includes substrate 10, multilayer Mo / Si stack 15 of multiple alternating layers of silicon and molybdenum, cap layer 20, and patterned absorber layer 25. In addition, black edge pattern 57 is formed in absorber layer 25, cap layer 20, and multilayer stack 15, and back conductive layer 45 is formed on the back side of substrate 10. In some embodiments, patterned absorber layer 25 includes Cr-based material, Pt-based material, Ir-based material, or Co-based material. In some embodiments, absorber layer 25 also includes one or more of Si, B, Ge, Al, As, Sb, Te, Se, and / or Bi. In some embodiments, protective layer 29 (e.g., oxide of one or more of Si, B, Ge, Al, As, Sb, Te, Se, and / or Bi) is formed on the sidewalls of patterned absorber layer 25. In some embodiments, the protective layer is formed on the sidewalls of cap layer and / or multilayer stack 15 with black edge pattern 57. In some embodiments, no protective layer remains on the completed photomask.

[0055] Figure 7B 1 shows a cross-sectional view of a completed EUV photomask according to an embodiment of the present disclosure. Figure 7B The EUV photomask with the circuit pattern 42 shown includes a substrate 10, a multilayer Mo / Si stack 15 of a plurality of alternating layers of silicon and molybdenum, a cap layer 20, a patterned intermediate layer 22, and a patterned absorber layer 25. In addition, a black edge pattern 57 is formed in the absorber layer 25, the intermediate layer 22, the cap layer 20, and the multilayer stack 15, and a back conductive layer 45 is formed on the back side of the substrate 10.

[0056] In some embodiments, the patterned absorber layer 25 includes a Cr-based material, a Pt-based material, an Ir-based material, or a Co-based material. In some embodiments, the intermediate layer 22 includes one or more of Si, B, Ge, Al, As, Sb, Te, Se, and / or Bi, or an alloy thereof. In some embodiments, a protective layer 29 (e.g., an oxide of one or more of Si, B, Ge, Al, As, Sb, Te, Se, and / or Bi) is formed on the sidewalls of the patterned absorber layer 25. In some embodiments, the protective layer is formed on the sidewalls of the cap layer and / or the multilayer stack 15 in a black edge pattern 57. In some embodiments, no protective layer remains on the completed photomask.

[0057] Fig. 8A A process of manufacturing a semiconductor device is shown, and Figure 8B , Figure 8C , Fig.8D and Fig. 8E Sequential manufacturing operations of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure are shown. A semiconductor substrate or other suitable substrate is provided, which is to be patterned to form an integrated circuit thereon. In some embodiments, the semiconductor substrate includes silicon. Alternatively or additionally, the semiconductor substrate includes germanium, silicon germanium, or other suitable semiconductor materials, such as III-V semiconductor materials. Fig. 8A In S801, a target layer to be patterned is formed on a semiconductor substrate. In some embodiments, the target layer is a semiconductor substrate. In some embodiments, the target layer includes a conductive layer such as a metallization layer or a polysilicon layer, a dielectric layer such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, SiCN, hafnium oxide, or aluminum oxide, or a semiconductor layer such as an epitaxially formed semiconductor layer. In some embodiments, the target layer is formed on an underlying structure such as an isolation structure, a transistor, or a wiring. Fig. 8A At S802, a photoresist layer is formed on the target layer, such as Figure 8B As shown. In the subsequent photolithography exposure process, the photoresist layer is sensitive to radiation from the exposure source. In this embodiment, the photoresist layer is sensitive to EUV light used in the photolithography exposure process. The photoresist layer can be formed on the target layer by spin coating or other suitable techniques. The coated photoresist layer can be further baked to drive out the solvent in the photoresist layer. Fig. 8A At S803, the photoresist layer is patterned using the EUV reflective mask as described above, such as Figure 8B As shown. Patterning the photoresist layer includes performing a photolithography exposure process using an EUV exposure system using an EUV mask. In the exposure process, the integrated circuit (IC) design pattern defined on the EUV mask is imaged to the photoresist layer to form a latent pattern thereon. Patterning the photoresist layer also includes developing the exposed photoresist layer to form a patterned photoresist layer with one or more openings. In an embodiment where the photoresist layer is a positive photoresist layer, the exposed portion of the photoresist layer is removed in the development process. Patterning the photoresist layer may also include other process steps, for example, various baking steps at different stages. For example, a post-exposure baking (PEB) process may be implemented after the photolithography exposure process and before the development process.

[0058] exist Fig. 8A At S804, the target layer is patterned using the patterned photoresist layer as an etching mask, such as Fig.8DIn some embodiments, patterning the target layer includes applying an etching process to the target layer using the patterned photoresist layer as an etching mask. Portions of the target layer exposed within the openings of the patterned photoresist layer are etched, while the remaining portions are protected from being etched. In addition, the patterned photoresist layer can be removed by wet stripping or plasma ashing, such as Fig. 8E shown.

[0059] In the present disclosure, one or more additional elements are included in or near the absorber layer, which can form a protective layer during etching of the absorber layer to control the profile of the patterned absorber layer. Undercutting (undercutting) under the hard mask layer can also be suppressed or prevented. The additional elements are effective for the absorber layer, which generally has a low etching rate. Vertical sidewalls of the patterned absorber layer can be obtained, which in turn suppresses the three-dimensional effect in EUV lithography.

[0060] It should be understood that not all advantages are necessarily discussed herein, that no particular advantage is required of all embodiments or examples, and that other embodiments or examples may provide different advantages.

[0061] According to one aspect of the present application, a reflective mask includes: a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, and an absorber layer disposed on the cap layer. The absorber layer includes a base material made of one or more of a Cr-based material, an Ir-based material, a Pt-based material, or a Co-based material, and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se, and Bi. In one or more of the foregoing and following embodiments, the one or more additional elements are not included in the base material. In one or more of the foregoing and following embodiments, the concentration of the one or more additional elements is in the range from 0.5 atomic % to 30 atomic %. In one or more of the foregoing and following embodiments, the concentration of the one or more additional elements in the absorber layer along the vertical direction is non-uniform. In one or more of the foregoing and following embodiments, the base material of the absorber layer is made of an Ir-based material, a Pt-based material, or a Co-based material. In one or more of the foregoing and following embodiments, the absorber layer is patterned, and the reflective mask also includes a protective layer disposed on the sidewalls of the patterned absorber layer. In one or more of the foregoing and following embodiments, the protective layer includes an oxide of the one or more additional elements.

[0062] According to another aspect of the present disclosure, a reflective mask includes: a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, an intermediate layer disposed on the cap layer, and an absorber layer disposed on the intermediate layer. The intermediate layer is a layer of one or more metalloid elements. In one or more of the foregoing and following embodiments, the absorber layer includes one or more of a Cr-based material, an Ir-based material, a Pt-based material, or a Co-based material. In one or more of the foregoing and following embodiments, the thickness of the intermediate layer is in the range from 1 nm to 10 nm. In one or more of the foregoing and following embodiments, the absorber layer is patterned, and the reflective mask also includes a protective layer disposed on the sidewalls of the patterned absorber layer. In one or more of the foregoing and following embodiments, the protective layer includes a compound of the one or more metalloid elements. In one or more of the foregoing and following embodiments, the protective layer includes silicon oxide or boron oxide. In one or more of the foregoing and following embodiments, the absorber layer does not contain elements of the intermediate layer.

[0063] According to another aspect of the present disclosure, a reflective mask includes: a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, and an absorber layer disposed on the cap layer. The absorber layer includes one or more additional layers made of at least one selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se, and Bi. In one or more of the foregoing and following embodiments, the absorber layer includes one or more of a Cr-based material, an Ir-based material, a Pt-based material, or a Co-based material. In one or more of the foregoing and following embodiments, two or more additional layers are provided, at least one of which is disposed at the bottom of the absorber layer or at the top of the absorber layer. In one or more of the foregoing and following embodiments, the thickness of each of the one or more additional layers is in the range of from 0.1 nm to 1 nm. In one or more of the foregoing and following embodiments, the absorber layer is patterned, and the reflective mask further includes a protective layer disposed on the sidewalls of the patterned absorber layer. In one or more of the foregoing and following embodiments, the protective layer includes a compound selected from at least one of the group consisting of Si, B, Ge, Al, As, Sb, Te, Se, and Bi.

[0064] According to another aspect of the present disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed on a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an absorber layer on the cap layer, and a hard mask layer. The photoresist layer is patterned, the hard mask layer is patterned by using the patterned photoresist layer, the absorber layer is patterned by using the patterned hard mask layer, and the hard mask layer is removed. The absorber layer includes a base material and further contains one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi, which are not included in the base material. In one or more of the foregoing and following embodiments, the base material is made of one or more of a Cr-based material, an Ir-based material, a Pt-based material or a Co-based material. In one or more of the foregoing and following embodiments, during patterning of the absorber layer, a protective layer is formed on the etched sidewalls of the absorber layer to inhibit lateral etching of the absorber layer. In one or more of the foregoing and following embodiments, the protective layer comprises a compound of the one or more additional elements. In one or more of the foregoing and following embodiments, the protective layer comprises an oxide of the one or more additional elements. In one or more of the foregoing and following embodiments, the absorber layer is patterned by plasma dry etching using an oxygen-containing gas. In one or more of the foregoing and following embodiments, the plasma dry etching also uses a chlorine-containing gas.

[0065] According to another aspect of the present disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed on a mask blank. The mask blank includes: a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, and a hard mask layer. The photoresist layer is patterned, the hard mask layer is patterned by using the patterned photoresist layer, the absorber layer is patterned by using the patterned hard mask layer, and the hard mask layer is removed. The intermediate layer includes a layer of one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi. In one or more of the foregoing and following embodiments, the base material is made of one or more of a Cr-based material, an Ir-based material, a Pt-based material or a Co-based material. In one or more of the foregoing and following embodiments, the one or more additional elements are not constituent elements of the absorber layer. In one or more of the foregoing and following embodiments, during the over-etching step of patterning the absorber layer, a protective layer is formed on the etched sidewalls of the absorber layer to inhibit lateral etching of the absorber layer. In one or more of the foregoing and following embodiments, the protective layer comprises an oxide of the one or more additional elements. In one or more of the foregoing and following embodiments, the absorber layer is patterned by plasma dry etching using an oxygen-containing gas. In one or more of the foregoing and following embodiments, the plasma dry etching also uses a chlorine-containing gas.

[0066] According to another aspect of the present disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed on a mask blank. The mask blank includes: a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an absorber layer on the cap layer, and a hard mask layer. The photoresist layer is patterned, the hard mask layer is patterned by using the patterned photoresist layer, the absorber layer is patterned by using the patterned hard mask layer, and the hard mask layer is removed. During the patterning of the absorber layer, a protective layer is formed on the etched sidewalls of the absorber layer to inhibit lateral etching of the absorber layer. In one or more of the foregoing and following embodiments, the absorber layer includes one or more of a Cr-based material, an Ir-based material, a Pt-based material, or a Co-based material. In one or more of the foregoing and following embodiments, the protective layer includes a compound of one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se, and Bi. In one or more of the foregoing and following embodiments, the one or more additional elements are supplied from the absorber layer. In one or more of the foregoing and following embodiments, the one or more additional elements are supplied from an intermediate layer disposed between the cap layer and the absorber layer.In one or more of the foregoing and following embodiments, the absorber layer is patterned by plasma dry etching using an oxygen-containing gas.

[0067] The foregoing summarizes the features of several embodiments or examples so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments or examples introduced herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0068] Example 1 is a reflective mask comprising: a substrate; a reflective multilayer disposed on the substrate; a cap layer disposed on the reflective multilayer; and an absorber layer disposed on the cap layer, wherein the absorber layer comprises a base material made of one or more of a Cr-based material, an Ir-based material, a Pt-based material or a Co-based material, and further comprises one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

[0069] Example 2 is the reflective mask of Example 1, wherein the one or more additional elements are not included in the base material.

[0070] Example 3 is the reflective mask of Example 1, wherein a concentration of the one or more additional elements is in a range from 5 atomic % to 30 atomic %.

[0071] Example 4 is the reflective mask of Example 1, wherein a concentration of the one or more additional elements in the absorber layer along a vertical direction is non-uniform.

[0072] Example 5 is the reflective mask of Example 1, wherein the base material of the absorber layer is made of an Ir-based material, a Pt-based material, or a Co-based material.

[0073] Example 6 is the reflective mask of Example 1, wherein: the absorber layer is patterned, and the reflective mask further comprises a protective layer disposed on a sidewall of the patterned absorber layer.

[0074] Example 7 is the reflective mask of Example 6, wherein the protective layer includes an oxide of the one or more additional elements.

[0075] Example 8 is a reflective mask comprising: a substrate; a reflective multilayer disposed on the substrate; a cap layer disposed on the reflective multilayer; an intermediate layer disposed on the cap layer; and an absorber layer disposed on the intermediate layer, wherein the intermediate layer is a layer comprising one or more metalloid elements.

[0076] Example 9 is the reflective mask of Example 8, wherein the absorber layer includes one or more of a Cr-based material, an Ir-based material, a Pt-based material, or a Co-based material.

[0077] Example 10 is the reflective mask of Example 8, wherein the thickness of the intermediate layer is in a range from 1 nm to 10 nm.

[0078] Example 11 is the reflective mask of Example 8, wherein: the absorber layer is patterned, and the reflective mask further comprises a protective layer disposed on a sidewall of the patterned absorber layer.

[0079] Example 12 is the reflective mask of Example 11, wherein the protective layer includes a compound of the one or more metalloid elements.

[0080] Example 13 is the reflective mask of Example 11, wherein the protective layer comprises silicon oxide or boron oxide.

[0081] Example 14 is the reflective mask of Example 8, wherein the absorber layer does not contain elements of the intermediate layer.

[0082] Example 15 is a method for manufacturing a reflective mask, the method comprising: forming a photoresist layer on a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an absorber layer on the cap layer, and a hard mask layer; patterning the photoresist layer; patterning the hard mask layer by using the patterned photoresist layer as a mask; patterning the absorber layer by using the patterned hard mask layer as a mask; and removing the hard mask layer, wherein, during patterning the absorber layer, a protective layer is formed on the etched sidewalls of the absorber layer, wherein the protective layer inhibits lateral etching of the absorber layer.

[0083] Example 16 is the method of Example 15, wherein the absorber layer includes one or more of a Cr-based material, an Ir-based material, a Pt-based material, or a Co-based material.

[0084] Example 17 is the method of Example 16, wherein the protective layer includes a compound of one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

[0085] Example 18 is the method of Example 17, wherein the one or more additional elements are supplied from the absorber layer.

[0086] Example 19 is the method of Example 17, wherein the one or more additional elements are supplied from an intermediate layer disposed between the cap layer and the absorber layer.

[0087] Example 20 is the method of Example 17, wherein the absorber layer is patterned by plasma dry etching using an oxygen-containing gas.

Claims

1. A reflective mask, comprising: substrate; a reflective multilayer disposed on the substrate; A cap layer, disposed on the reflective multilayer; as well as an absorbent layer, disposed on the cap layer, wherein the absorber layer comprises a base material layer made of one or more of an Ir-based material, a Pt-based material or a Co-based material, and the base material layer further comprises one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

2. The reflective mask according to claim 1, wherein: The concentration of the one or more additional elements ranges from 5 atomic % to 30 atomic %.

3. The reflective mask according to claim 1, wherein: The concentration of the one or more additional elements in the absorber layer along the vertical direction is non-uniform.

4. The reflective mask according to claim 1, wherein: The base material layer of the absorber layer is made of one selected from the group consisting of: IrPt, IrAl, IrRu, IrB, IrN, IrSi, IrTi, PtAl, PtRu, PtB, PtSi, PtN, PtTi, CoO, CoB, CoBN, CoN and CoSi.

5. The reflective mask according to claim 1, wherein: The absorber layer is patterned, and The reflective mask also includes a protection layer disposed on sidewalls of the patterned absorber layer.

6. The reflective mask according to claim 5, wherein: The protective layer includes an oxide of the one or more additional elements.

7. A reflective mask comprising: substrate; a reflective multilayer disposed on the substrate; A cap layer, disposed on the reflective multilayer; An intermediate layer, disposed on the cap layer; as well as an absorbent layer disposed on the intermediate layer, Wherein, the intermediate layer is a layer comprising one or more metalloid elements, wherein the absorber layer comprises a base material layer made of one or more of an Ir-based material, a Pt-based material or a Co-based material, and the base material layer further comprises one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

8. The reflective mask according to claim 7, wherein: The one or more metalloid elements include one or more of Si, Ge, Al, As, Se, and Bi.

9. The reflective mask according to claim 7, wherein: The thickness of the intermediate layer is in the range from 1 nm to 10 nm.

10. The reflective mask according to claim 7, wherein: The absorber layer is patterned, and The reflective mask also includes a protection layer disposed on sidewalls of the patterned absorber layer.

11. The reflective mask according to claim 10, wherein: The protective layer includes a compound of the one or more metalloid elements.

12. The reflective mask according to claim 10, wherein: The protective layer includes silicon oxide or boron oxide.

13. The reflective mask according to claim 7, wherein: The absorber layer does not contain elements of the intermediate layer.

14. A method for manufacturing a reflective mask, the method comprising: forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an absorber layer on the cap layer, and a hard mask layer; patterning the photoresist layer; patterning the hard mask layer by using the patterned photoresist layer as a mask; patterning the absorber layer by using the patterned hard mask layer as a mask; as well as removing the hard mask layer, wherein during patterning of the absorber layer, a protective layer is formed on the etched sidewalls of the absorber layer, wherein the protective layer inhibits lateral etching of the absorber layer, wherein the absorber layer comprises a base material layer made of one or more of an Ir-based material, a Pt-based material or a Co-based material, and the base material layer further comprises one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

15. The method according to claim 14, wherein: The protective layer includes a compound of one or more additional elements selected from the group consisting of Si, B, Ge, Al, As, Sb, Te, Se and Bi.

16. The method according to claim 15, wherein: The one or more additional elements are supplied from the absorber layer.

17. The method according to claim 15, wherein: The one or more additional elements are supplied from an intermediate layer arranged between the cap layer and the absorber layer.

18. The method according to claim 15, wherein: The absorber layer is patterned by plasma dry etching using an oxygen-containing gas.

19. The method according to claim 15, wherein: The protective layer includes oxides of one or more additional elements selected from the group consisting of Si, Ge, Al, As, Se, and Bi.

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