System-in-Package (SiP) Chip and Electronic Shelf Label

Abstract

The present invention provides a system-in-package (SiP) chip and an electronic shelf label. The system-in-package SiP chip includes: an SoC chip; the SoC chip includes: a microcontroller and a radio frequency transceiver; a memory connected to the SoC chip; a near field communication (NFC) circuit connected to the SoC chip; an electronic paper display (EPD) driving circuit, with the first end connected to the SoC chip and the second end connected to the electronic paper display; an LED lamp driving interface, with the first end connected to the SoC chip and the second end connected to an external LED lamp; a sensor driving interface, with the first end of the sensor driving interface connected to the SoC chip and the second end of the sensor driving interface connected to a relevant external sensor of the electronic shelf label. The above technical solution enables the electronic shelf label to have high integration, small occupied area of components, be conducive to realizing miniaturization of the whole machine design, and have high system reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic shelf labels, and particularly to a system-in-package SiP chip and an electronic shelf label. Background Art

[0002] An ESL (Electronic Shelf Label) is a wireless communication device powered by a button battery and is used to replace traditional paper price tags to display product information. The electronic shelf label uses an electronic paper display screen, which has the characteristics of clear display and low power consumption, supports user-defined display content, and realizes one-key change.

[0003] A complete set of electronic shelf label systems includes multiple electronic shelf labels, an access base station, a server and a control system, and intelligent handheld terminal devices. First, the electronic shelf label is bound to the goods on the shelf one by one through the handheld terminal device. Price data is transmitted to the server through Ethernet, and after being scheduled by the server, the data is sent to the access base station, and the access base station then transmits the data to the electronic shelf label through wireless communication. The electronic shelf label system supports batch update mode and point-to-point update mode.

[0004] As Figure 1 and Figure 2 shown, existing electronic shelf labels generally include: a microcontroller (MCU), a radio frequency transceiver (Transceiver), a memory (FLASH), peripheral circuits, an electronic paper display screen (EPD), an indicator light, and a battery. Among them, the peripheral circuits mainly include: a screen driving circuit, an indicator light driving circuit, an NFC circuit, a sensor circuit, etc. The microcontroller controls the radio frequency transceiver to realize the transceiver of radio frequency signals and complete uplink and downlink wireless communication; the memory stores binary codes and price data information, etc. The microcontroller and the radio frequency transceiver can also be replaced by an SoC chip integrating the functions of both. However, this solution has low integration, large occupied area of components, is not conducive to the miniaturization of the whole machine design, and at the same time, more components reduce the system reliability.

[0005] In view of the above problems, no effective solution has been proposed yet. Summary of the Invention

[0006] Embodiments of the present invention provide a system-in-package SiP chip, which enables the electronic shelf label to have high integration, small occupied area of components, is conducive to realizing the miniaturization of the whole machine design and high system reliability. The SiP chip includes:

[0007] Chip-level system-on-chip (SoC) chip; the SoC chip includes: a microcontroller for controlling the operation of each component in the electronic shelf label; a radio frequency transceiver connected to the microcontroller for receiving instructions sent by an external control center or uploading information related to the electronic shelf label to the external control center according to the control of the microcontroller;

[0008] A memory connected to the SoC chip for storing information related to the electronic shelf label;

[0009] A near field communication (NFC) circuit connected to the SoC chip for performing wireless communication with a handheld terminal device according to the control of the SoC chip to complete the read and write operations of information related to the electronic shelf label;

[0010] An electronic paper display (EPD) driving circuit, with its first end connected to the SoC chip and its second end connected to the EPD, for driving the EPD to work according to the control of the SoC chip;

[0011] An LED lamp driving interface, with its first end connected to the SoC chip and its second end connected to an external LED lamp, for driving the external LED lamp to work according to the control of the SoC chip;

[0012] A sensor driving interface, with its first end connected to the SoC chip and its second end connected to a relevant external sensor of the electronic shelf label, for configuring the external sensor according to the configuration command of the SoC chip or transmitting the sensed information to the SoC chip.

[0013] An embodiment of the present invention also provides an electronic shelf label to provide an electronic shelf label with high integration, small occupied area of components, conducive to realizing miniaturization of the whole machine design and high system reliability. The electronic shelf label includes:

[0014] The system-in-package (SiP) chip as described above;

[0015] An LED lamp connected to the LED lamp driving interface; the LED lamp is the external LED lamp;

[0016] A sensor connected to the sensor driving interface; the sensor is the relevant external sensor.

[0017] Compared with the solution of the existing electronic shelf label which adopts a discrete device design, has problems such as low integration, complex circuit design, large occupied area of components, inability to achieve miniaturized design of the whole machine, and low system reliability, the technical solution provided in the embodiment of the present invention integrates the SoC chip, the electronic paper display EPD drive circuit, the near field communication NFC circuit, and the memory into a system-in-package SiP chip. Among them, the SoC chip integrates a microcontroller and a radio frequency transceiver to control the memory, the NFC circuit, and the EPD drive circuit. At the same time, an LED lamp drive interface is provided to control the external LED lamp, and a sensor drive interface is provided to configure the external sensor and realize data interaction, effectively improving the integration, reducing the occupied area of components by 90%, facilitating the realization of miniaturized design of the whole machine and improving the system reliability. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 is a schematic structural diagram of an electronic shelf label in the prior art;

[0020] Figure 2 is a schematic layout diagram of an electronic shelf label in the prior art;

[0021] Figure 3 is a schematic structural diagram of a system-in-package SiP chip in the embodiment of the present invention;

[0022] Figure 4 is a schematic connection structure diagram of the SoC chip and the memory in the embodiment of the present invention;

[0023] Figure 5 is a schematic connection structure diagram of the SoC chip and the NFC circuit in the embodiment of the present invention;

[0024] Figure 6A is a schematic structural diagram of the EPD drive circuit in the embodiment of the present invention;

[0025] Figure 6B is a schematic connection relationship diagram of the Sip chip and three external devices in the embodiment of the present invention;

[0026] Figure 7 is a schematic layout diagram of a system-in-package SiP chip in the embodiment of the present invention;

[0027] Figure 8It is a schematic structural diagram of an electronic shelf label in an embodiment of the present invention;

[0028] Figure 9 It is a schematic layout diagram of an electronic shelf label in an embodiment of the present invention. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0030] Before introducing the embodiments of the present invention, the nouns and full names related to the embodiments of the present invention will be introduced first.

[0031] 1. ESL: Electronic Shelf Label, electronic shelf label.

[0032] 2. MCU: Micro Controller Unit, microcontroller.

[0033] 3. RF: Radio Frequency, radio frequency.

[0034] 4. EPD: Electronic Paper Displays, electronic paper display screen.

[0035] 5. SiP: System in Package, system-level packaging. System-level packaging integrates multiple functional chips including processors, memories, etc. in one package to achieve a basically complete function.

[0036] 6. SoC: System on Chip, system-on-chip.

[0037] 7. PCB: Printed Circuit Board, printed circuit board.

[0038] 8. NFC: Near Field Communication, near field communication.

[0039] 9. SPI: Serial Peripheral Interface, serial peripheral interface.

[0040] 10. IIC: Inter-Integrated Circuit, integrated circuit bus.

[0041] The inventor found that there are technical problems with existing electronic shelf labels: adopting a discrete device design solution, there are problems such as complex circuit design, low integration, large PCB footprint, which is not conducive to the miniaturization of the overall machine design. At the same time, a large number of components result in low system reliability.

[0042] Since the inventor discovered these technical problems, a system-in-package (SiP) chip and an electronic shelf label solution were proposed. The system-in-package SiP chip provided by this solution integrates a radio frequency (RF) system-on-chip (SoC) die, a near field communication (NFC) die, a flash die, and an electrophoretic display (EPD) screen driving circuit in one package. Among them, the SoC chip integrates the functions of a microcontroller unit (MCU) and an RF transceiver, controls the peripheral flash and NFC die, and at the same time provides LED lamp and sensor driving interfaces, effectively improving the integration. The area occupied by the peripheral circuit is reduced by 90%, which is conducive to realizing the miniaturization of the overall machine design and improving the system reliability. At the same time, this solution is a high-integration multi-wafer system-in-package device, which solves problems such as low integration, complex design, and low reliability. Through the SiP chip, RF communication, NFC communication, screen driving, LED, and other peripheral device driving can be realized.

[0043] The system-in-package SiP chip and the electronic shelf label solution will be introduced in detail below.

[0044] Figure 3 It is a schematic structural diagram of the system-in-package SiP chip in an embodiment of the present invention. As Figure 3 shown, the system-in-package SiP chip includes:

[0045] A chip-level system SoC chip; the SoC chip includes: a microcontroller for controlling the operation of each component in the electronic shelf label; an RF transceiver connected to the microcontroller for receiving instructions sent by an external control center or uploading relevant information of the electronic shelf label to the external control center according to the control of the microcontroller;

[0046] A memory connected to the SoC chip for storing relevant information of the electronic shelf label;

[0047] A near field communication (NFC) circuit connected to the SoC chip for performing wireless communication with a handheld terminal device according to the control of the SoC chip to complete the read and write operations of relevant information of the electronic shelf label;

[0048] An electrophoretic display (EPD) screen driving circuit, with the first end connected to the SoC chip and the second end connected to the EPD, for driving the EPD to work according to the control of the SoC chip;

[0049] The LED lamp driving interface has its first end connected to the SoC chip and its second end connected to an external LED lamp, and is used to drive the external LED lamp to work according to the control of the SoC chip;

[0050] The sensor driving interface has its first end connected to the SoC chip and its second end connected to a relevant external sensor of the electronic shelf label, and is used to configure the external sensor according to the configuration command of the SoC chip or transmit the sensed information to the SoC chip.

[0051] In specific implementation, the meaning of the above "external" is relative to the SiP chip. For example, the external LED lamp refers to the LED lamp outside the SiP chip, and the external sensor refers to the sensor outside the SiP chip.

[0052] Next, in combination with the attached Figures 2 to 7 , the detailed structure of the SiP chip provided by the present invention will be introduced.

[0053] In one embodiment, the SoC chip is connected to the memory through the Serial Peripheral Interface (SPI).

[0054] In specific implementation, the memory can be a FLASH memory. Binary codes, product configuration information, data displayed on the screen, etc. are stored in the FLASH. As Figure 4 shown, the SoC can be connected to the FLASH through the SPI (Serial Peripheral Interface) interface, send control commands through the SPI interface, and complete data reading and writing. The SoC chip is connected to the memory through the SPI to ensure the data reading and writing efficiency, and thus ensure the working efficiency of the electronic shelf label.

[0055] In Figure 4 , CLK: Connect to the EPD clock signal, CS: Connect to the EPD chip select signal, MOSI is the master output and slave input, and MISO is the master input and slave output.

[0056] In one embodiment, the SoC chip is connected to the NFC circuit through the Serial Peripheral Interface (SPI) or the Inter-Integrated Circuit (IIC) interface.

[0057] In specific implementation, as Figure 5As shown, the SoC is connected to the NFC through an SPI or IIC interface (Inter-Integrated Circuit), to complete the control of the NFC chip (circuit) and data reading and writing. Through the NFC interface, external devices (such as smart handheld devices) can transmit control commands (such as commands to check or modify the price of the goods represented by the electronic shelf label) or data content to be displayed (such as product introduction information, etc.).

[0058] In Figure 5 CS: Connect the chip select signal of the EPD, SDA: Connect the data signal of the EPD, INT is an input, and SCK is the clock signal.

[0059] In one embodiment, the number of the LED lamp driving interfaces is three.

[0060] In specific implementation, the SiP chip provides three LED lamp driving interfaces to control the lighting and extinguishing of the externally connected LED lamps. The number of the LED lamp driving interfaces is three, which is flexible and convenient.

[0061] In one embodiment, the SoC chip is connected to the relevant externally connected sensors through the IIC interface of the integrated circuit bus.

[0062] In specific implementation, the SiP chip provides one IIC interface, which can be externally connected to sensors to complete configuration (such as configuring when to report sensor sensing data, etc.) and data interaction (such as transmitting the sensed environmental temperature information to the SiP chip or sending control commands for reporting sensing data, etc.).

[0063] In one embodiment, the EPD driving circuit includes: an EPD boost circuit, a diode, and a capacitor.

[0064] In specific implementation, as Figure 6A shown, the screen driving circuit (EPD driving circuit) includes a MOS transistor EPD boost circuit, a diode, and a capacitor, so that only three devices are required on the periphery of the SiP to drive the EPD screen. The connection relationship between the three peripheral devices and the SiP is as Figure 6B shown, Figure 6B which is represented as resistor R10, inductor L10, and capacitor C10 in

[0065] In Figure 6A the Chinese meanings of each pin are shown in Table 1 below:

[0066]

[0067] Table 1

[0068] In one embodiment, the EPD driving circuit includes: an EPD boost circuit; the EPD boost circuit includes: a first transistor Q1, a first diode D1, a second diode D2, a third diode D3, an eighth capacitor C8, and a ninth capacitor C9; where:

[0069] The first transistor Q1, the source of the first transistor Q1 is connected to the RESE interface of the EPD, and an externally connected sampling resistor R10 is connected to the ground; the drain of the first transistor Q1 is connected to the PreVGLCAP interface of the EPD through an external capacitor C10, and is connected to the VDD interface of the EPD through an external power inductor L10; the gate of the first transistor Q1 is connected to the GDR interface of the EPD;

[0070] The first diode D1, the positive electrode of the first diode D1 is connected to the drain of the first transistor Q1, and the negative electrode of the first diode D1 is connected to the PreVGH interface of the EPD;

[0071] The second diode D2, the positive electrode of the second diode D2 is connected to the PreVGL interface of the EPD, and the negative electrode of the second diode D2 is connected to the PreVGLCAP interface of the EPD;

[0072] The positive electrode of the third diode D3 is connected to the negative electrode of the second diode D2, and the negative electrode of the third diode D3 is connected to the first end of the ninth capacitor C9;

[0073] The first end of the eighth capacitor C8 is grounded, and the second end is connected to the negative electrode of the first diode D1;

[0074] The first end of the ninth capacitor C9 is grounded, and the second end of the ninth capacitor is connected to the positive electrode of the second diode D2.

[0075] During specific implementation, the source of the first transistor Q1 is connected to the RESE interface of the EPD, and an externally connected sampling resistor R10 is connected to the ground; the drain of the first transistor Q1 is connected to PreVGLCAP through an external capacitor C10, and is connected to VDD_EPD (the VDD interface of the EPD) through an external power inductor L10, and is connected to the positive electrode of the first diode D1; the gate of the first transistor Q1 is connected to the GDR interface of the EPD. The negative electrode of D1 is connected to the EPD interface: PreVGH; the first end of C8 is grounded, and the second end is connected to the negative electrode of D1.

[0076] During specific implementation, the positive electrode of the second diode D2 is connected to the EPD interface PreVGL, and the negative electrode of the second diode D2 is connected to PreVGLCAP; the positive electrode of the third diode D3 is connected to the negative electrode of the second diode D2, and the negative electrode of the third diode D3 is connected to the first end of the ninth capacitor C9; the first end of the ninth capacitor C9 is grounded, and the second end of the ninth capacitor is connected to the positive electrode of the second diode D2.

[0077] In specific implementation, Q1, D1, D2, D3, L10, C8, C9, C10 and R10 together form a boost circuit. When GDR is at a high level, the inductor L10 stores energy, C8 maintains PreVGH at a high level, while C9 is charged and C10 is discharged, and PreVGL provides a negative level. When GDR is at a low level, the inductor L10 releases energy and simultaneously charges C8 and C10, PreVGH maintains the output at a high level, and C9 remains at a low level. These two states occur alternately, and by sensing the voltage at RESE, the change frequency of GDR is controlled to control the output voltages of PreVGH and PreVGL.

[0078] In specific implementation, the structural design of the boost circuit in the EPD driving circuit within the above-mentioned SIP chip enables only three devices to be required on the periphery of the SiP to drive the EPD screen, further improving the integration level, further reducing the occupied area of components, facilitating the realization of the miniaturization of the whole machine design and improving the system reliability.

[0079] In specific implementation, in Figure 6A , the first terminal of the third capacitor C3 is grounded, and the second terminal is connected to the GND of the EPD; the first terminal of the fourth capacitor C4 is grounded, and the second terminal is connected to the VPP of the EPD; the first terminal of the fifth capacitor C5 is grounded, and the second terminal is connected to the VSL of the EPD; the first terminal of the sixth capacitor C6 is grounded, and the second terminal is connected to the VCOM of the EPD. C3, C4, C5, and C6 act as energy storage capacitors to store charges.

[0080] In specific implementation, in Figure 6A , the first terminal of R1 is grounded, and the second terminal of R1 is connected to the GDR of the EPD; the first terminal of C1 is connected to the first terminal of R1, and the second terminal is connected to the VGH of the EPD.

[0081] In specific implementation, in Figure 6A , C2 and C7 function as energy storage capacitors and filter capacitors.

[0082] In one embodiment, the core components of the EPD driving circuit, the first diode D1, the second diode D2, the third diode D3, the eighth capacitor C8 and the ninth capacitor C9 are arranged away from the SoC chip and the NFC circuit.

[0083] In specific implementation, as Figure 7 shown, the core devices D1, D2, D3, C8, C9 of the screen driving circuit are away from the SoC and the NFC radio frequency circuit, avoiding affecting the flow of the encapsulation material, ensuring the quality of the SiP chip, and thus ensuring the service life of the electronic shelf label.

[0084] In one embodiment, the eighth capacitor C8 is disposed on one side along the length direction of the SiP chip, and the ninth capacitor C9 is disposed on the other side along the length direction of the SiP chip.

[0085] When implementing it, Figure 7 As shown, C8 and C9 are arranged on the left and right sides to avoid affecting the flow of the plastic packaging material, further ensuring the quality of the SiP chip, and further ensuring the service life of the electronic shelf label.

[0086] In one embodiment, the SoC chip and the memory are arranged in a stacked manner.

[0087] When implementing it, Figure 7 As shown, when SiP is implemented, SoC and FLASH are stacked to further reduce the area occupied.

[0088] In one embodiment, Figure 3 As shown, the above-mentioned system-level package SiP chip may also include: a power supply interface connected to an external power supply for supplying power to the SiP chip.

[0089] During specific implementation, the setting of the power interface facilitates the use of electronic shelf labels.

[0090] Based on the same inventive concept, an electronic shelf label is also provided in the embodiment of the present invention, as described in the following embodiment. Since the principle of solving the problem by the electronic shelf label is similar to that of the system-level package SiP chip, the implementation of the electronic shelf label can refer to the implementation of the system-level package SiP chip, and the repeated parts will not be repeated.

[0091] Figure 8 is a schematic diagram of the structure of an electronic shelf label in an embodiment of the present invention. Figure 8 As shown, the electronic shelf label includes:

[0092] The system-in-package SiP chip as described above;

[0093] An LED lamp connected to the LED lamp driving interface; the LED lamp is the external LED lamp;

[0094] A sensor is connected to the sensor driving interface; the sensor is the related external sensor.

[0095] In specific implementation, the SiP chip provided by the embodiment of the present invention is used, and the circuit design of the electronic shelf label is shown in FIG. Figure 9 As shown, the area occupied by components is saved by about 90%, and the integration is high, which is conducive to the miniaturization of the whole machine design and high system reliability.

[0096] In one embodiment, the above-mentioned electronic shelf label may further include: a battery, connected to the system-in-package SiP chip, the LED lamp and the sensor, and powering the system-in-package SiP chip, the LED lamp and the sensor.

[0097] Specifically, the setting of the battery facilitates the use of the electronic shelf label.

[0098] In one embodiment, the number of the LED lamps is three.

[0099] Specifically, the LED lamps can represent different prompt messages, such as indicating the working state, alarm prompt, and so on.

[0100] The beneficial technical effects of the technical solution provided by the embodiment of the present invention are:

[0101] The integration degree is effectively improved, the occupied area of the components is reduced by 90%, which is beneficial to realizing the miniaturization of the whole machine design and improving the system reliability.

[0102] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various changes and modifications can be made to the embodiments of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A system-in-package SiP chip, characterized in that, Comprising: A chip-level system-on-chip (SoC) chip; The SoC chip includes: a microcontroller for controlling the operation of various components in the electronic shelf label; a radio frequency transceiver connected to the microcontroller for receiving instructions sent by an external control center or uploading relevant information of the electronic shelf label to the external control center according to the control of the microcontroller; A memory connected to the SoC chip for storing relevant information of the electronic shelf label; A near-field communication (NFC) circuit connected to the SoC chip for performing wireless communication with a handheld terminal device according to the control of the SoC chip to complete the read and write operations of relevant information of the electronic shelf label; An electronic paper display (EPD) driving circuit, with the first end connected to the SoC chip and the second end connected to the EPD, for driving the EPD to work according to the control of the SoC chip; An LED lamp driving interface, with the first end connected to the SoC chip and the second end connected to an external LED lamp, for driving the external LED lamp to work according to the control of the SoC chip; A sensor driving interface, with the first end of the sensor driving interface connected to the SoC chip and the second end of the sensor driving interface connected to a relevant external sensor of the electronic shelf label, for configuring the external sensor according to the configuration command of the SoC chip or transmitting the sensed information to the SoC chip.

2. The system-in-package SiP chip according to claim 1, characterized in that, The SoC chip is connected to the memory through a serial peripheral interface (SPI).

3. The system-in-package SiP chip according to claim 1, characterized in that The SoC chip is connected to the NFC circuit through a serial peripheral interface (SPI) or an inter-integrated circuit (IIC) interface.

4. The system-in-package SiP chip according to claim 1, wherein The number of the LED lamp driving interfaces is 3.

5. The system-in-package SiP chip according to claim 1, characterized in that, The SoC chip is connected to the relevant external sensor through an inter-integrated circuit (IIC) interface.

6. The system-in-package SiP chip according to claim 1, characterized in that, The SoC chip and the memory are arranged in a stacked manner.

7. The system-in-package SiP chip according to claim 1, characterized in that, The EPD driving circuit includes: an EPD boost circuit; the EPD boost circuit includes: a first transistor (Q1), a first diode (D1), a second diode (D2), a third diode (D3), an eighth capacitor (C8), and a ninth capacitor (C9); wherein: A first transistor (Q1), the source of the first transistor (Q1) is connected to the RESE interface of the EPD and an external ground sampling resistor (R10) is connected; the drain of the first transistor (Q1) is connected to the PreVGLCAP interface of the EPD through an external capacitor (C10) and connected to the VDD interface of the EPD through an external power inductor (L10); the gate of the first transistor (Q1) is connected to the GDR interface of the EPD; A first diode (D1), the positive electrode of the first diode (D1) is connected to the drain of the first transistor (Q1), and the negative electrode of the first diode (D1) is connected to the PreVGH interface of the EPD; A second diode (D2), the positive electrode of the second diode (D2) is connected to the PreVGL interface of the EPD, and the negative electrode of the second diode (D2) is connected to the PreVGLCAP interface of the EPD; The positive electrode of the third diode (D3) is connected to the negative electrode of the second diode (D2), and the negative electrode of the third diode (D3) is connected to the first end of the ninth capacitor (C9); The first terminal of the eighth capacitor (C8) is grounded, and the second terminal is connected to the negative electrode of the first diode (D1); The first terminal of the ninth capacitor (C9) is grounded, and the second terminal of the ninth capacitor is connected to the positive electrode of the second diode (D2).

8. The system-in-package SiP chip according to claim 7, characterized in that, The first transistor (Q1), the first diode (D1), the second diode (D2), the third diode (D3), the eighth capacitor (C8) and the ninth capacitor (C9) are arranged away from the SoC chip and the NFC circuit.

9. The system-in-package SiP chip according to claim 8, wherein, The eighth capacitor (C8) is arranged on one side along the length direction of the SiP chip, and the ninth capacitor (C9) is arranged on the other side along the length direction of the SiP chip.

10. The system-in-package SiP chip according to claim 1, wherein, It further includes: A power interface, connected to an external power supply for supplying power to the SiP chip.

11. An electronic shelf label, characterized in that, It includes: A system-in-package SiP chip according to any one of claims 1 to 10; An LED lamp, connected to the LED lamp driving interface; The LED lamp is the external LED lamp; A sensor, connected to the sensor driving interface; the sensor is the relevant external sensor.

12. The electronic shelf label according to claim 11, wherein It further includes: A battery, connected to the system-in-package SiP chip, the LED lamp and the sensor for supplying power to the system-in-package SiP chip, the LED lamp and the sensor.

13. The electronic shelf label according to claim 11, wherein, The number of the LED lamps is 3.

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