Semiconductor device and method for forming the same

Abstract

An embodiment of the present invention provides a semiconductor device and a method for forming the same. The semiconductor device includes a capacitor and a resistor. The capacitor includes: a first plate; a capacitor dielectric layer disposed above the first plate; and a second plate disposed above the capacitor dielectric layer. The resistor includes a thin film. The thin film of the resistor and the first plate of the capacitor are formed of the same conductive material and are defined in a single patterning process.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same. Background Art

[0002] Capacitors and resistors are standard components in many semiconductor integrated circuits. For example, capacitors can be used in various radio frequency (RF) circuits (such as oscillators, phase shift networks, filters, converters, etc.) in dynamic random access memory (DRAM) units, and can be used as decoupling capacitors in high-power microprocessor units (MPUs); and resistors are often used together with capacitors to control the corresponding resistance of at least one of the other electronic components of the circuits mentioned above. Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor device, which includes a resistor and a capacitor. The resistor includes a thin film. The capacitor includes a first plate, a capacitor dielectric layer disposed above the first plate, and a second plate disposed above the capacitor dielectric layer. The thin film of the resistor and the first plate of the capacitor include the same conductive material and are defined in a single patterning process.

[0004] An embodiment of the present invention provides a method for forming a semiconductor device, which includes: forming a first dielectric layer above a plurality of interconnect structures; depositing a conductive material above the first dielectric layer; depositing a dielectric material above the conductive material; etching the conductive material and the dielectric material to simultaneously define a thin film of a resistor, a bottom plate of a capacitor, and a capacitor dielectric layer of the capacitor; and forming a top plate of a capacitor above the capacitor dielectric layer.

[0005] An embodiment of the present invention provides a semiconductor device, comprising: a first plate, a film, a capacitor dielectric layer, and a second plate. The first plate comprises a first conductive material. The film also comprises the first conductive material, and the film is substantially coplanar with the first plate. The capacitor dielectric layer comprises a dielectric material and is disposed above the first plate. The second plate comprises a second conductive material and is disposed above the capacitor dielectric layer. The film constitutes at least a portion of a resistor, and the first plate, the capacitor dielectric layer, and the second plate constitute at least a portion of a capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that the various features are not necessarily drawn to scale. In fact, the size and geometry of the various features may be arbitrarily increased or reduced for the sake of clarity of illustration.

[0007] Figure 1A and Figure 1B A flowchart is shown of an exemplary method for forming a semiconductor device in accordance with some embodiments.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Fig.2I , Figure 2J , Figure 2K , Figure 2L as well as Figure 2M According to some embodiments, Figure 1A and Figure 1B 1 is a cross-sectional view of an exemplary semiconductor device during various fabrication stages performed by a method of manufacturing a semiconductor device. DETAILED DESCRIPTION

[0009] The following disclosure describes various exemplary embodiments for implementing the different features of the subject matter. The specific examples of components and arrangements described below are for simplifying the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature may not be in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0011] In general, the capacitor is implemented as a metal-insulator-metal (MIM) structure (hereinafter referred to as a "MIM capacitor"), which includes two metal plates and an insulator sandwiched between the two metal plates that acts as a capacitor dielectric layer. The resistor is implemented as a metal film resistor. The metal film can be characterized as having a low temperature coefficient of resistance (temperature coefficient of resistivity, TCR) (hereinafter referred to as a "low TCR metal resistor"). There are various reasons for implementing the capacitor and the resistor as a MIM capacitor and a low TCR metal resistor, respectively, rather than other capacitor and resistor structures (or materials). For example, compared with a metal oxide semiconductor (metal-oxide-semiconductor, MOS) capacitor consisting of a semiconductor electrode and a metal plate, a MIM capacitor can provide a larger capacitance than the capacitance of a MOS capacitor in the case of the same area (the larger capacitance is usually required in various circuits). Moreover, although other thin film resistors that are not made of metal (e.g., made of polysilicon) may also have low TCRs, such non-metallic thin film resistors typically have tighter (i.e., narrower) sheet resistance tolerances when compared to metal thin film resistors, which can adversely limit the use of such resistors.

[0012] Conventionally, when making MIM capacitors compatible with complementary metal-oxide-semiconductor (CMOS) technology, two or more patterning processes (e.g., photolithography processes, sometimes referred to as "masks") are required. For example, a first mask is used to make (e.g., define) a metal film of a low TCR metal resistor, followed by a second mask for etching additional layers (e.g., anti-reflective coating (ARC) and landing pad layer) formed on the metal film. As a result, manufacturing costs / resources / time may be increased. Therefore, conventional MIM capacitors and low TCR metal resistors and methods for forming such capacitors and resistors are not entirely satisfactory.

[0013] The present disclosure provides various embodiments of a semiconductor device, the semiconductor device comprising at least one capacitor and at least one thin film resistor that can be manufactured by a single patterning process. In some embodiments, the capacitor can be a metal-insulator-metal (MIM) capacitor, and the thin film resistor can be a metal resistor with a low temperature coefficient of resistivity (TCR). In some embodiments, one of the metal plates of the MIM capacitor (e.g., the bottom metal plate) and the metal film of the low TCR metal resistor are defined simultaneously during a single patterning process. For example, the bottom metal plate of the MIM capacitor and the metal film of the low TCR metal resistor are formed by patterning (e.g., etching) the same metal material using corresponding different patterns contained in the same mask during a common patterning process. Thus, the above-mentioned problems can be advantageously avoided when making a semiconductor device comprising a MIM capacitor and a low TCR metal resistor.

[0014] Figure 1A and Figure 1B 1 and 2 collectively show a flow chart of a method 100 of forming a semiconductor device including at least one MIM capacitor and a low TCR metal resistor according to one or more embodiments of the present disclosure. It should be noted that the method 100 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 100 may be used in the present invention. Figure 1A to Figure 1B Additional operations are provided before, during, and after the method 100, and it should be understood that some other operations may only be briefly described herein. In some embodiments, the operations of the method 100 may be the same as those described in Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F , Figure 2G , Figure 2H , Fig.2I , Figure 2J , Figure 2K , Figure 2L as well as Figure 2M , which will be discussed in further detail below.

[0015] In summary, the method 100 begins with operation 102 of providing a substrate. The method 100 proceeds to operation 104 of forming a plurality of first interconnect structures. The method 100 proceeds to operation 106 of forming a first dielectric layer. The method 100 proceeds to operation 108 of depositing a silicon (Si) rich dielectric material. The method 100 proceeds to operation 110 of forming a plurality of first vias. The method 100 proceeds to operation 112 of depositing a conductive material. The method 100 proceeds to operation 114 of depositing an anti-reflective coating material. The method 100 proceeds to operation 116 of simultaneously forming a bottom plate of a capacitor and a capacitor dielectric layer and a thin film of a resistor. The method 100 proceeds to operation 118 of forming a plurality of second interconnect structures. The method 100 proceeds to operation 120 of again depositing a Si rich dielectric material. The method 100 proceeds to operation 122 of forming a second dielectric layer. The method 100 proceeds to operation 124 of forming a plurality of second vias. The method 100 continues with operation 126 of forming a plurality of third interconnect structures. The method 100 continues with operation 128 of forming a third dielectric layer.

[0016] As mentioned above, Figures 2A to 2M The cross-sectional view shows Figure 1A and Figure 1B The semiconductor device 200 (including at least one capacitor and at least one resistor) is a portion of a semiconductor device 200 (including at least one capacitor and at least one resistor) in various manufacturing stages of the method 100. The semiconductor device 200 may be included in a microprocessor, a memory cell and / or other integrated circuits (ICs). In addition, for a better understanding of the concepts of the present disclosure, the following are simplified. Figures 2A to 2M Although the figure shows a semiconductor device 200, it should be understood that the IC may include a plurality of other devices (such as inductors, fuses, transistors, coils, etc.), for the purpose of clarity of description, Figures 2A to 2M The other devices are not shown.

[0017] Corresponds to Figure 1A Operation 102, Figure 2A 2 is a cross-sectional view of a semiconductor device 200 including a substrate 202 at one of various manufacturing stages. The substrate 202 may be an inter-layer dielectric (ILD) layer disposed at the bottom layer. Accordingly, there may be one or more device features (e.g., gates, drains, sources of transistors) and / or conductive features (e.g., conductive plugs) disposed below or overlying the substrate 202, which are not depicted for the purpose of clarity. In some embodiments, the layers disposed above the substrate 202 may be collectively referred to as back-end-of-line (BEOL) layers.

[0018] The substrate 202 includes a material that is at least one of the following materials: silicon oxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low-k dielectric material may include fluorinated silica glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), Black (Applied Materials of Santa Clara, Calif.), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, bis-benzocyclobutenes (BCB), SiLK (Dow Chemical, Midland, Mich.), polyimide, and / or other low-k dielectric materials developed in the future.

[0019] Corresponds to Figure 1A Operation 104, Figure 2B 2 is a cross-sectional view of a semiconductor device 200 including a plurality of first interconnect structures 204 in one of various manufacturing stages. For example, the first interconnect structure 204 includes a first interconnect structure 204a, a first interconnect structure 204b, a first interconnect structure 204c, and a first interconnect structure 204d. Figure 2B In the illustrated embodiment of FIG. 1 (and the following figures), four first interconnect structures 204 are depicted, but it should be understood that any number of first interconnect structures 204 may be formed on the substrate 202 while still falling within the scope of the present disclosure. In some embodiments, the first interconnect structures 204a-204d formed on the substrate 202 may be laterally spaced apart from each other. In this manner, after a dielectric material is formed over the first interconnect structures 204a-204d (which will be discussed below), each of the first interconnect structures 204a-204d may be used as a conductive contact or pad for a device component, respectively.

[0020] exist Figure 2BIn the illustrated embodiment, the first interconnect structures 204 a to 204 d may be formed by performing at least one or more of the following processes: depositing a metal material (e.g., Cu, Al, or a combination thereof) over the substrate 202 using chemical vapor deposition (CVD), physical vapor deposition (PVD), an electron-gun (E-gun), and / or other suitable techniques; forming a mask layer (e.g., one or more photoresist layers, hard mask layers, etc.) having a pattern over the metal material, the pattern defining respective desired locations of the first interconnect structures 204 a to 204 d; etching the metal material using the pattern; removing the mask layer; and cleaning residues. In some other embodiments, the first interconnect structure 204a to the first interconnect structure 204d may be formed by performing at least one or more of the following processes: depositing a dielectric layer (e.g., at least a portion of an inter-metal dielectric (IMD) layer) over the substrate 202; forming a mask layer (e.g., one or more photoresist layers, hard mask layers, etc.) having a pattern over the dielectric layer, the pattern defining the respective desired positions of the first interconnect structure 204a to the first interconnect structure 204d; etching the dielectric layer using the pattern to form a recess (e.g., a trench) extending at least partially through the dielectric layer; depositing a metal material (e.g., Cu, Al, or a combination thereof) over the dielectric layer to fill the recess; performing a polishing process (e.g., a chemical-mechanical polishing (CMP) process) on the deposited metal material to form the first interconnect structure 204a to the first interconnect structure 204d embedded in the dielectric layer; and cleaning residues. Forming the embedded first interconnect structures 204 a to 204 d in the dielectric layer may sometimes be referred to as a damascene process.

[0021] Corresponds to Figure 1A Operation 106, Figure 2C 2 is a cross-sectional view of a semiconductor device 200 including a first dielectric layer 206 during one of various manufacturing stages. The first dielectric layer 206, which may be an IMD layer, overlies first to second interconnect structures 204a to 204d. In examples where the first to second interconnect structures 204a to 204d are formed as the bottommost interconnect structure of the BEOL layer, the first interconnect structure 204 may sometimes be referred to as metal 1s (M1s), and the first dielectric layer 206 including the M1s may sometimes be referred to as an IMD1 layer. Figure 2CIn the illustrated embodiment of the present invention, the first interconnect structures 204a to 204d are formed before forming such an IMD1 layer. It should be understood that the first interconnect structures 204a to 204d may be formed after forming the IMD1 layer, for example, by the damascene process described above, while still falling within the scope of the present disclosure.

[0022] The first dielectric layer 206 includes a material that is at least one of the following materials: silicon oxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low-k dielectric material may include fluorosilicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), Black (Applied Materials, Inc., Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK (The Dow Chemical Company, Midland, Michigan), polyimide, and / or other low-k dielectric materials or ultra-low-k dielectric materials to be developed in the future. The first dielectric layer 206 may be formed by depositing one or more of the dielectric materials listed above over the first interconnect structures 204a to 204d using one of the following deposition techniques: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, and / or other suitable dielectric material deposition techniques.

[0023] Corresponds to Figure 1A Operation 108, Figure 2D 2 is a cross-sectional view of a semiconductor device 200 including a Si-rich dielectric material 208 during one of various manufacturing stages. In some embodiments, the Si-rich dielectric material 208 may be a Si-rich oxide material. Forming such a Si-rich dielectric material 208 over the first dielectric layer 206 may help prevent undesirable atoms from diffusing into device components to be formed over the Si-rich dielectric material 208. The Si-rich dielectric material 208 may include an oxide layer having a plurality of silicon nanocrystals therein. The Si-rich dielectric material 208 may be formed using silane (SiH4) gas and nitrogen oxide (N2O) gas via a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a silicon implantation process.

[0024] Corresponds to Figure 1A Operation 110, Figure 2E 2 is a cross-sectional view of a semiconductor device 200 including a plurality of first vias 210 in one of various manufacturing stages. For example, the first vias include vias 210a, 210b, 210c, and 210d. The term "via" generally refers to a vertical interconnect structure that extends through one or more dielectric layers (e.g., IMD layers) to electrically connect device components disposed along the top and bottom boundaries of the one or more dielectric layers. For example, via 210a extending through the first dielectric layer 206 and the Si-rich dielectric material 208 may electrically connect the first interconnect structure 204a to another device component (which will be illustrated below); via 210b extending through the first dielectric layer 206 and the Si-rich dielectric material 208 may electrically connect the first interconnect structure 204b to another device component (which will be illustrated below); via 210c extending through the first dielectric layer 206 and the Si-rich dielectric material 208 may electrically connect the first interconnect structure 204c to another device component (which will be illustrated below); and via 210d extending through the first dielectric layer 206 and the Si-rich dielectric material 208 may electrically connect the first interconnect structure 204d to another device component (which will be illustrated below).

[0025] The through holes 210a to 210d may be formed by performing at least one or more of the following processes: forming a dielectric layer 208 ( Figure 2D A mask layer having a pattern (e.g., one or more photoresist layers, hard mask layers, etc.) is formed over the Si-rich dielectric material 208 (as shown in FIG. 1 ), the pattern defining the respective desired locations of the through-holes 210 a to 210 d; the Si-rich dielectric material 208 and the first dielectric layer 206 are etched using the pattern to form a recess (e.g., a via hole) exposing the respective top boundaries of the first interconnect structure 204 a to the first interconnect structure 204 d; a metal material (e.g., Cu, Al, or a combination thereof) is deposited to fill the recess; a polishing process (e.g., a chemical mechanical polishing (CMP) process) is performed on the deposited metal material to form the through-holes 210 a to 210 d extending through the Si-rich dielectric material 208 and the first dielectric layer 206; and residues are cleaned.

[0026] Corresponds to Figure 1A Operation 112 and operation 114, Figure 2F2 is a cross-sectional view of a semiconductor device 200 including a conductive material 212 and an anti-reflective coating (ARC) material 214 in one of the various manufacturing stages. As will be discussed below, the conductive material 212 can be used to define a thin film of a resistor (e.g., a low TCR metal resistor) and a bottom plate of a capacitor (MIM capacitor). In some embodiments, the conductive material 212 is in direct contact with the vias 210a to 210d. Some vias can serve as an inner wiring structure of the resistor. Compared to existing resistors that typically include a landing pad layer (e.g., a TiN layer) between the via and the resistor, the contact resistance of the resistor can be advantageously reduced because the via of the present disclosure is in direct contact with the resistor.

[0027] The conductive material 212 and the anti-reflective coating material 214 may be sequentially formed over the Si-rich dielectric material 208. In some embodiments, the conductive material 212 may include a metal material selected from at least one of the following materials: Ta, TaN, Ti, TiN, W, WN, NiCr, or SiCr. The conductive material 212 may be formed by depositing one or more of the metal materials listed above over the Si-rich dielectric material 208 using chemical vapor deposition (CVD), physical vapor deposition (PVD), an electron gun (E-gun), and / or other suitable techniques. In some embodiments, the ARC material 214 may include a dielectric material selected from at least one of the following materials: SiO2, La2O3, ZrO3, Ba-Sr-Ti-O, or Si3N4. The ARC material 214 may be formed by depositing one or more of the dielectric materials listed above over the conductive material 212 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, and / or other suitable dielectric material deposition techniques. In some embodiments, the conductive material 212 may have a thickness in a range of about 40 angstroms to about 50 angstroms, and the ARC material 214 may have a thickness in a range of about 40 angstroms to about 50 angstroms.

[0028] Corresponds to Figure 1A Operation 116, Figure 2G2 is a cross-sectional view of a semiconductor device 200 including a first plate 218, a first dielectric segment 220, a thin film 222, and a second dielectric segment 224 in one of various manufacturing stages. In some embodiments, the first plate 218, the first dielectric segment 220, the thin film 222, and the second dielectric segment 224 can be formed simultaneously by performing a single patterning process 215 on the conductive material 212 and the ARC material 214, which will be discussed below. As a result, the first plate 218 and the thin film 222 can be coplanar with each other; and the first dielectric segment 220 and the second dielectric segment 224 can be coplanar with each other. The term "coplanar" refers to the alignment of the corresponding top or bottom boundaries of two objects along a virtual boundary or a physical boundary. For example, the first plate 218 and the thin film 222 are coplanar with each other because the bottom boundary of the first plate 218 and the bottom boundary of the thin film 222 are aligned along the middle boundary 209 of the Si-rich dielectric material 208.

[0029] The patterning process 215 may include at least one or more of the following processes: Figure 2F 214 (shown in FIG. 215 ), the pattern defining the respective desired locations of the first plate 218 and the thin film 222; etching the ARC material 214 and the conductive material 212 using the pattern to simultaneously form the first plate 218, the first dielectric segment 220, the thin film 222, and the second dielectric segment 224; and cleaning the residue. In some other embodiments, the pattern may be used to form the first dielectric segment 220 and the second dielectric segment 224 by etching the ARC material 214 at a first etch rate. In response to forming the first dielectric segment 220 and the second dielectric segment 224 over the conductive material 212, the same pattern may be used to form the first plate 218 and the thin film 222 by etching the conductive material 212 at a second etch rate.

[0030] In some embodiments, after forming the thin film 222, the low TCR metal resistor 225R may be formed to have a second dielectric segment 224 as a resistor dielectric layer, the second dielectric segment 224 being formed above the low TCR metal resistor 225R. In addition, while forming the first plate 218 and the first dielectric segment 220, a portion of the MIM capacitor 225C may be formed. For example, the first plate 218 may be used as a bottom plate or bottom electrode of the MIM capacitor 225C, and the first dielectric segment 220 may be used as a capacitor dielectric layer of the MIM capacitor 225C. Therefore, the first plate 218, the first dielectric segment 220, and the second dielectric segment 224 are referred to herein as "bottom plate 218", "capacitor dielectric layer 220", and "resistor dielectric layer 224", respectively. In some embodiments, the bottom plate 218 and the thin film 222 may inherit a thickness substantially similar to the thickness of the conductive material 212, which is in the range of about 40 angstroms to about 50 angstroms; and the capacitor dielectric layer 220 and the resistor dielectric layer 224 may inherit a thickness substantially similar to the thickness of the ARC material 214, which is in the range of about 100 angstroms to about 300 angstroms. In some embodiments, the ratio of the thickness of the bottom plate 218 and the thin film 222 to the thickness of the capacitor dielectric layer 220 and the resistor dielectric layer 224 may be in the range of about 0.2 to about 0.25, which is because it may be desirable to maintain the thickness of the thin film 222 of the low TCR metal resistor 225R, which also defines a substantially smaller thickness of the bottom plate 218 of the MIM capacitor 225C. This is because when the thickness of the thin film 222 is too large, the resistance of the low TCR metal resistor 225R may become too small, which is generally undesirable in the application of the low TCR metal resistor.

[0031] Corresponds to Figure 1A Operation 118, Figure 2H2 is a cross-sectional view of a semiconductor device 200 including a plurality of second interconnect structures 226 at one of various manufacturing stages. For example, the second interconnect structures 226 include interconnect structures 226a and interconnect structures 226b. In some embodiments, at least one of the second interconnect structures 226, such as, for example, the second interconnect structure 226b, is formed over the capacitor dielectric layer 220. The second interconnect structure 226b may have a width (W1) that is smaller than a width (W2) of the bottom plate 218 and the capacitor dielectric layer 220. In some embodiments, the ratio of the width W2 to the width W1 may be in the range of 1.2 to 1.8. This is because in some embodiments, when forming the second interconnect structure 226b, it is desirable to laterally offset the second interconnect structure 226b from the through hole 210b to ensure smoothness of the bottom plate 218 and the capacitor dielectric layer 220. Making the bottom plate 218 and the capacitor dielectric layer 220 wider than the second interconnect structure 226b may facilitate this lateral offset between the second interconnect structure 226b and the via 210b.

[0032] For example, the width W1 of the second interconnect structure 226b may be in the range of about 3 microns to about 6 microns, and the width W2 of the bottom plate 218 and the capacitor dielectric layer 220 may be in the range of about 800 microns to about 1200 microns. At least one of the second interconnect structures 226, such as, for example, the second interconnect structure 226a, is formed to electrically connect the via 210a. Although Figure 2H In the illustrated embodiment of FIG. 1 (and the following figures), two second interconnect structures 226 are depicted, but it should be understood that any number of second interconnect structures 226 may be formed while still falling within the scope of the present disclosure. In some embodiments, the second interconnect structures 226a-226b may be laterally spaced apart from each other. In this manner, after a dielectric material is formed over the second interconnect structures 226a-226b (which will be discussed below), each of the second interconnect structures 226a-226b may be used as a conductive contact, plate, or pad of a device component, respectively.

[0033] exist Figure 2HIn the illustrated embodiment, the second interconnect structures 226a to 226b may be formed by performing at least one or more of the following processes: depositing a metal material (e.g., Cu, Al, or a combination thereof) over the Si-rich dielectric material 208 using chemical vapor deposition (CVD), physical vapor deposition (PVD), an electron gun (E-gun), and / or other suitable techniques; forming a mask layer (e.g., one or more photoresist layers, hard mask layers, etc.) having a pattern over the metal material, the pattern defining the respective desired locations of the second interconnect structures 226a to 226b; etching the metal material using the pattern; removing the mask layer; and cleaning the residue. In some other embodiments, the second interconnect structures 226a to 226b may be formed by the damascene process described above.

[0034] In some embodiments, the second interconnect structure 226b can be used as a top plate or top electrode of the MIM capacitor 225C, referred to herein as “top electrode 226b.” Thus, in response to forming the top electrode 226b, the formation of the MIM capacitor 225C can be completed.

[0035] Corresponds to Figure 1A Operation 120, Fig.2I 2 is a cross-sectional view of a semiconductor device 200 including another Si-rich dielectric material 230 at one of various manufacturing stages. In some embodiments, the Si-rich dielectric material 230 may be formed of a dielectric material substantially similar to the Si-rich dielectric material 208. As depicted, the Si-rich dielectric material 230 may be formed overlying the second interconnect structure 226a, the low TCR metal resistor 225R, and the MIM capacitor 225C. Thus, after forming the Si-rich dielectric material 230, the low TCR metal resistor 225R and the MIM capacitor 225C may be at least partially encapsulated by a continuous Si-rich dielectric layer consisting of the Si-rich dielectric material 208 and the Si-rich dielectric material 230.

[0036] Corresponds to Figure 1B Operation 122, Figure 2Jis a cross-sectional view of a semiconductor device 200 including a second dielectric layer 232 at one of various manufacturing stages. The second dielectric layer 232 (which may be an IMD layer) overlies a Si-rich dielectric material 230. In instances where the first dielectric layer 206 is formed as an IMD1 layer, the second interconnect structure 226 may sometimes be referred to as metal 2s (M2s), and the second dielectric layer 232 including the M2s may sometimes be referred to as an IMD2 layer. Although the low TCR metal resistor 225R and the MIM capacitor 225C are formed between an IMD1 layer (e.g., the first dielectric layer 206) and an IMD2 layer (e.g., the second dielectric layer 232), it should be understood that embodiments of the methods disclosed herein may enable the low TCR metal resistors and MIM capacitors to be formed between any subsequent IMD layers. Figure 2J In the illustrated embodiment of the present invention, the second interconnect structures 204a to 204d are formed before forming such an IMD2 layer. It should be understood that the second interconnect structures 226a to 226b may be formed after forming the IMD2 layer, for example, by the damascene process described above, while still falling within the scope of the present disclosure.

[0037] The second dielectric layer 232 includes a material that is at least one of the following materials: silicon oxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low-k dielectric material may include fluorosilicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), Black (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK (Dow Chemical Company, Midland, Michigan), polyimide, and / or other low-k dielectric materials or ultra-low-k dielectric materials to be developed in the future. One or more of the dielectric materials listed above may be deposited over the Si-rich dielectric material 230 using one of the following deposition techniques to form the second dielectric layer 232: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, and / or other suitable dielectric material deposition techniques. In some embodiments, the second dielectric layer 232 may have a thickness that is greater than about 10 times the thickness of the conductive material 212 (thin film 222). For example, the thickness of the second dielectric layer 232 may be in the range of about 4000 angstroms to about 6000 angstroms. Each of the other dielectric layers (IMD layers) of the semiconductor device 200 may have a thickness substantially similar to the thickness of the second dielectric layer 232.

[0038] Corresponds to Figure 1B Operation 124, Figure 2K2 is a cross-sectional view of a semiconductor device 200 including a plurality of second vias 234 in one of the various manufacturing stages. For example, the second vias include vias 234a and 234b. The via 234a extending through the second dielectric layer 232 and the Si-rich dielectric material 230 can electrically connect the second interconnect structure 226a to another device component (which will be described below); and the via 234b extending through the second dielectric layer 232 and the Si-rich dielectric material 230 can electrically connect the second interconnect structure (top plate) 226b to another device component (which will be described below).

[0039] The through holes 234a to 234b may be formed by performing at least one or more of the following processes: Figure 2J A mask layer having a pattern (e.g., one or more photoresist layers, hard mask layers, etc.) is formed over the second dielectric layer 232 (as shown in FIG. 1 ), the pattern defining the corresponding desired positions of the through-holes 234a to the through-holes 234b; the second dielectric layer 232 and the Si-rich dielectric material 230 are etched using the pattern to form grooves (e.g., vias) exposing the corresponding top boundaries of the second interconnect structure 226a to the second interconnect structure 226b; a metal material (e.g., Cu, Al, or a combination thereof) is deposited to fill the grooves; a polishing process (e.g., a chemical mechanical polishing (CMP) process) is performed on the deposited metal material to form through-holes 234a to the through-holes 234b extending through the Si-rich dielectric material 230 and the second dielectric layer 232; and residues are cleaned.

[0040] Corresponds to Figure 1B Operation 126, Figure 2L FIG. 2 is a cross-sectional view of a semiconductor device 200 including a plurality of third interconnect structures 236 in one of the various manufacturing stages. For example, the third interconnect structures include interconnect structures 236a and 236b. Figure 2L In the illustrated embodiment of FIG. 1 (and the following figures), two third interconnect structures 236 are depicted, but it should be understood that any number of third interconnect structures 236 may be formed on the second dielectric layer 232 while still falling within the scope of the present disclosure. In some embodiments, the third interconnect structures 236a-236b formed on the second dielectric layer 232 may be laterally spaced apart from each other. In this manner, after a dielectric material is formed over the third interconnect structures 236a-236b (which will be discussed below), each of the third interconnect structures 236a-236b may be used as a conductive contact or pad for a device component, respectively.

[0041] exist Figure 2LIn the illustrated embodiment, the third interconnect structures 236a to 236b can be formed by performing at least one or more of the following processes: depositing a metal material (e.g., Cu, Al, or a combination thereof) over the second dielectric layer 232 using chemical vapor deposition (CVD), physical vapor deposition (PVD), an electron gun (E-gun), and / or other suitable techniques; forming a mask layer (e.g., one or more photoresist layers, hard mask layers, etc.) having a pattern over the metal material, the pattern defining the respective desired locations of the third interconnect structures 236a to 236b; etching the metal material using the pattern; removing the mask layer; and cleaning the residue. In some other embodiments, the third interconnect structures 236a to 236b can be formed by performing the damascene process described above.

[0042] Corresponds to Figure 1B Operation 128, Figure 2M 2 is a cross-sectional view of a semiconductor device 200 including a third dielectric layer 238 during one of various manufacturing stages. The third dielectric layer 238 (which may be an IMD layer) overlies the third interconnect structure 236a to the third interconnect structure 236b. In the example where the second dielectric layer 232 is formed as an IMD2 layer, the third interconnect structure 236 may sometimes be referred to as metal 3s (M3s), and the third dielectric layer 238 including the M3s may sometimes be referred to as an IMD3 layer. Figure 2M In the illustrated embodiment of the present invention, the third interconnect structures 236a to 236b are formed before forming such an IMD3 layer. It should be understood that the third interconnect structures 236a to 236b may be formed after forming the IMD3 layer, for example, by the damascene process described above, while still falling within the scope of the present disclosure.

[0043] The third dielectric layer 238 includes a material that is at least one of the following materials: silicon oxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low-k dielectric material may include fluorosilicate glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO x C y ), Black (Applied Materials, Inc., Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), SiLK (The Dow Chemical Company, Midland, Michigan), polyimide, and / or other low-k dielectric materials or ultra-low-k dielectric materials to be developed in the future. The third dielectric layer 238 may be formed by depositing one or more of the dielectric materials listed above over the third interconnect structures 236a to 236b using one of the following deposition techniques: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, and / or other suitable dielectric material deposition techniques.

[0044] The foregoing summarizes the features of several embodiments so that those of ordinary skill in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and those skilled in the art may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0045] In an embodiment, a semiconductor device includes a capacitor and a resistor. The capacitor includes: a first plate; a capacitor dielectric layer disposed above the first plate; and a second plate disposed above the capacitor dielectric layer. The resistor includes a thin film. The thin film of the resistor and the first plate of the capacitor include the same conductive material. The thin film of the resistor and the first plate of the capacitor are defined by a single patterning process.

[0046] In the above-mentioned semiconductor device, it also includes: a first vertical interconnect structure, which at least partially extends through a first dielectric layer arranged below the first plate and the film and electrically connects the first plate to a first interconnect structure among multiple interconnect structures embedded in the first dielectric layer; and a second vertical interconnect structure, which at least partially extends through a second dielectric layer arranged above the capacitor and electrically connects the second plate to a third interconnect structure embedded in a third dielectric layer, and the third dielectric layer is arranged above the second dielectric layer.

[0047] In the above-mentioned semiconductor device, it also includes a second internal wiring structure embedded in the second dielectric layer, wherein the second internal wiring structure, the capacitor and the resistor are laterally spaced apart from each other in a fourth dielectric layer, and the fourth dielectric layer is arranged between the first dielectric layer and the second dielectric layer.

[0048] In the above semiconductor device, the second interconnect structure, the capacitor and the resistor are at least partially wrapped by the fourth dielectric layer.

[0049] In the above-mentioned semiconductor device, it also includes: a third vertical interconnect structure, which at least partially extends through the first dielectric layer and electrically connects the first end of the film to the second interconnect structure among the multiple interconnect structures embedded in the first dielectric layer; and a fourth vertical interconnect structure, which at least partially extends through the first dielectric layer and electrically connects the second end of the film to the third interconnect structure among the multiple interconnect structures embedded in the first dielectric layer.

[0050] In the above semiconductor device, the third vertical interconnect structure and the fourth vertical interconnect structure are in direct contact with the film.

[0051] In the above semiconductor device, the resistor further comprises a resistor dielectric layer disposed above the thin film, wherein the resistor dielectric layer and the capacitor dielectric layer comprise the same dielectric material and are formed in the single patterning process.

[0052] In the above semiconductor device, the dielectric material includes an anti-reflective coating (ARC) material.

[0053] In the above semiconductor device, the conductive material includes at least one material selected from the group consisting of the following materials: tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, nickel chromium and silicon chromium.

[0054] In another embodiment, a method for forming a semiconductor device includes: forming a first dielectric layer over a plurality of interconnect structures. The method includes: depositing a conductive material over the first dielectric layer. The method includes: depositing a dielectric material over a first metal material. The method includes: etching the conductive material and the dielectric material to simultaneously define a film of a resistor, a bottom plate of a capacitor, and a capacitor dielectric layer of the capacitor. The method includes: forming a top plate of the capacitor over the capacitor dielectric layer.

[0055] The above-mentioned method for forming a semiconductor device also includes: before depositing the conductive material, forming a first vertical interconnect structure, a third vertical interconnect structure and a fourth vertical interconnect structure, each of the first vertical interconnect structure, the third vertical interconnect structure and the fourth vertical interconnect structure at least partially extending through the first dielectric layer.

[0056] In the above-mentioned method for forming a semiconductor device, wherein: the first vertical interconnect structure is configured to electrically connect the bottom plate of the capacitor to a first interconnect structure among the multiple interconnect structures; the third vertical interconnect structure is configured to electrically connect the first end of the thin film of the resistor to a second interconnect structure among the multiple interconnect structures; and the fourth vertical interconnect structure is configured to electrically connect the second end of the thin film of the resistor to a third interconnect structure among the multiple interconnect structures.

[0057] In the above method for forming a semiconductor device, it also includes: after forming the top plate of the capacitor, forming a second dielectric layer above the capacitor and the resistor; and forming a second vertical interconnect structure extending at least partially through the second dielectric layer.

[0058] In the above method for forming a semiconductor device, the second vertical interconnect structure is configured to electrically connect the top plate of the capacitor to a third interconnect structure embedded in a third dielectric layer, the third dielectric layer being disposed above the second dielectric layer.

[0059] In the above method for forming a semiconductor device, the dielectric material comprises an anti-reflective coating (ARC) material.

[0060] In the above method for forming a semiconductor device, the conductive material includes at least one material selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, nickel chromium, and silicon chromium.

[0061] In yet another embodiment, a semiconductor device includes a first plate, the first plate including a conductive material. The semiconductor device includes a thin film substantially coplanar with the first plate, the thin film also including a conductive material. The semiconductor device includes a capacitor dielectric layer disposed above the first plate, the capacitor dielectric layer including a dielectric material. The semiconductor device includes a second plate disposed above the capacitor dielectric layer, the second plate including a conductive material. The thin film constitutes at least a portion of a resistor, and the first plate, the capacitor dielectric layer, and the second plate constitute at least a portion of a capacitor.

[0062] In the above semiconductor device, the dielectric material comprises an anti-reflective coating (ARC) material.

[0063] In the above semiconductor device, the first conductive material includes at least one material selected from the group consisting of the following materials: tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, nickel chromium, and silicon chromium.

[0064] In the above-mentioned semiconductor device, it also includes: a first vertical interconnect structure, which at least partially extends through a first dielectric layer arranged below the first plate and the film and electrically connects the first plate to a first interconnect structure among the multiple interconnect structures embedded in the first dielectric layer; a second vertical interconnect structure, which at least partially extends through a second dielectric layer arranged above the capacitor and electrically connects the second plate to a third interconnect structure embedded in a third dielectric layer, and the third dielectric layer is arranged above the second dielectric layer; a third vertical interconnect structure, which at least partially extends through the first dielectric layer, and the third vertical interconnect structure electrically connects the first end of the film to the second interconnect structure among the multiple interconnect structures embedded in the first dielectric layer; and a fourth vertical interconnect structure, which at least partially extends through the first dielectric layer, and the fourth vertical interconnect structure electrically connects the second end of the film to the third interconnect structure among the multiple interconnect structures embedded in the first dielectric layer.

Claims

1. A semiconductor device, comprising: a resistor disposed over the substrate and comprising a thin film overlying a resistor dielectric layer; A capacitor disposed above the substrate and comprising: First board; a capacitor dielectric layer disposed over the first plate; and a second plate disposed above the capacitor dielectric layer; a first Si-rich dielectric material having a plurality of silicon nanocrystals and disposed below the membrane and the first plate; and a second Si-rich dielectric material having a plurality of silicon nanocrystals and disposed over the membrane and the second plate; wherein the film of the resistor and the first plate of the capacitor comprise the same conductive material and are defined in a single patterning process, wherein the first plate and the capacitor dielectric layer have a first width, and the second plate has a second width, the first width being greater than the second width, The film and the first plate each have a first thickness, and the resistor dielectric layer and the capacitor dielectric layer each have a second thickness, and a ratio of the first thickness to the second thickness is between 0.2 and 0.

25.

2. The semiconductor device according to claim 1, further comprising: a first vertical interconnect structure extending at least partially through a first dielectric layer disposed below the first plate and the film and electrically connecting the first plate to a first interconnect structure of a plurality of interconnect structures embedded in the first dielectric layer; as well as A second vertical interconnect structure extends at least partially through a second dielectric layer disposed over the capacitor and electrically connects the second plate to a third interconnect structure embedded in a third dielectric layer disposed over the second dielectric layer.

3. The semiconductor device of claim 2 , further comprising a second interconnect structure partially embedded in the second dielectric layer, wherein the second interconnect structure, the capacitor, and the resistor are laterally spaced apart from each other in the second Si-rich dielectric material, and the second Si-rich dielectric material is disposed between the first dielectric layer and the second dielectric layer. 4 . The semiconductor device of claim 3 , wherein the second interconnect structure, the capacitor, and the resistor are at least partially encapsulated by the second Si-rich dielectric material.

5. The semiconductor device according to claim 2, further comprising: a third vertical interconnect structure extending at least partially through the first dielectric layer and electrically connecting the first end of the film to a second interconnect structure of the plurality of interconnect structures embedded in the first dielectric layer; as well as A fourth vertical interconnect structure extends at least partially through the first dielectric layer and electrically connects the second end of the film to a third interconnect structure of the plurality of interconnect structures embedded in the first dielectric layer. 6 . The semiconductor device according to claim 5 , wherein the third vertical interconnect structure and the fourth vertical interconnect structure are in direct contact with the thin film. 7 . The semiconductor device of claim 1 , wherein the resistor dielectric layer and the capacitor dielectric layer comprise the same dielectric material and are formed in the single patterning process.

8. The semiconductor device of claim 7, wherein the dielectric material comprises an anti-reflective coating material.

9. The semiconductor device according to claim 1, wherein the conductive material comprises at least one material selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, nickel chromium, and silicon chromium.

10. A method for forming a semiconductor device, comprising: forming a first Si-rich dielectric layer over the plurality of interconnect structures; depositing a conductive material over the first Si-rich dielectric layer; depositing a dielectric material over the conductive material; etching the conductive material and the dielectric material to simultaneously define a thin film of a resistor, a bottom plate of a capacitor, a resistor dielectric layer of the resistor over the thin film, and a capacitor dielectric layer of the capacitor over the bottom plate; forming a top plate of the capacitor over the capacitor dielectric layer, wherein the film and the bottom plate each have a first thickness, and the resistor dielectric layer and the capacitor dielectric layer each have a second thickness, and a ratio of the first thickness to the second thickness is between 0.2 and 0.25; as well as A second Si-rich dielectric layer is formed over the capacitor and the resistor, wherein the second Si-rich dielectric material has a plurality of silicon nanocrystals, and the capacitor and the resistor are partially surrounded by the first Si-rich dielectric material and the second Si-rich dielectric material.

11. The method for forming a semiconductor device according to claim 10, further comprising: Prior to depositing the conductive material, a first vertical interconnect structure, a third vertical interconnect structure, and a fourth vertical interconnect structure are formed, each of the first vertical interconnect structure, the third vertical interconnect structure, and the fourth vertical interconnect structure extending at least partially through the first Si-rich dielectric layer.

12. The method for forming a semiconductor device according to claim 11, wherein: The first vertical interconnect structure is configured to electrically connect the bottom plate of the capacitor to a first interconnect structure of the plurality of interconnect structures; The third vertical interconnect structure is configured to electrically connect the first end of the thin film of the resistor to a second interconnect structure of the plurality of interconnect structures; as well as The fourth vertical interconnect structure is configured to electrically connect the second end of the thin film of the resistor to a third interconnect structure of the plurality of interconnect structures.

13. The method for forming a semiconductor device according to claim 10, further comprising: forming a second dielectric layer over the capacitor and the resistor after forming the top plate of the capacitor; as well as A second vertical interconnect structure is formed extending at least partially through the second dielectric layer.

14. The method for forming a semiconductor device according to claim 13, wherein the second vertical interconnect structure is configured to electrically connect the top plate of the capacitor to a third interconnect structure embedded in a third dielectric layer, the third dielectric layer being disposed above the second dielectric layer.

15. The method for forming a semiconductor device according to claim 10, wherein the dielectric material comprises an anti-reflective coating material.

16. The method for forming a semiconductor device according to claim 10, wherein the conductive material comprises at least one material selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, nickel chromium, and silicon chromium.

17. A semiconductor device comprising: a first plate disposed over the substrate and comprising a first conductive material; a thin film, also disposed over the substrate and comprising the first conductive material, the thin film being coplanar with the first plate, a resistor dielectric layer overlying the thin film; a capacitor dielectric layer comprising a dielectric material and disposed over the first plate; a second plate comprising a second conductive material and disposed over the capacitor dielectric layer; a first Si-rich dielectric material having a plurality of silicon nanocrystals and disposed below the membrane and the first plate; as well as a second Si-rich dielectric material having a plurality of silicon nanocrystals and disposed over the membrane and the second plate; wherein the film forms at least a portion of a resistor and the first plate, the capacitor dielectric layer and the second plate form at least a portion of a capacitor, wherein the first plate and the capacitor dielectric layer have a first width, and the second plate has a second width, the first width being greater than the second width, The film and the first plate each have a first thickness, and the resistor dielectric layer and the capacitor dielectric layer each have a second thickness, and a ratio of the first thickness to the second thickness is between 0.2 and 0.

25.

18. The semiconductor device of claim 17, wherein the dielectric material comprises an anti-reflective coating material.

19. The semiconductor device of claim 17, wherein the first conductive material comprises at least one material selected from the group consisting of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, nickel chromium, and silicon chromium.

20. The semiconductor device according to claim 17, further comprising: a first vertical interconnect structure extending at least partially through a first dielectric layer disposed below the first plate and the film and electrically connecting the first plate to a first interconnect structure of a plurality of interconnect structures embedded in the first dielectric layer; a second vertical interconnect structure extending at least partially through a second dielectric layer disposed over the capacitor and electrically connecting the second plate to a third interconnect structure embedded in a third dielectric layer disposed over the second dielectric layer; a third vertical interconnect structure extending at least partially through the first dielectric layer, the third vertical interconnect structure electrically connecting the first end of the thin film to a second interconnect structure of the plurality of interconnect structures embedded in the first dielectric layer; as well as A fourth vertical interconnect structure at least partially extends through the first dielectric layer, the fourth vertical interconnect structure electrically connecting the second end of the film to a third interconnect structure of the plurality of interconnect structures embedded in the first dielectric layer.

Images