Semiconductor device and method for manufacturing the same

Abstract

Embodiments of the present application disclose a semiconductor device with an isolation structure and a method for manufacturing the same. The semiconductor device includes a first fin structure and a second fin structure disposed on a substrate, and a first pair of gate structures and a second pair of gate structures disposed on the first fin structure and the second fin structure. The first end surface of the first pair of gate structures faces the second end surface of the second pair of gate structures. The first end surface and the second end surface of the first pair of gate structures and the second pair of gate structures are in physical contact with the first sidewall and the second sidewall of the isolation structure, respectively. The semiconductor device also includes an isolation structure interposed between the first pair of gate structures and the second pair of gate structures. The aspect ratio of the isolation structure is less than the combined aspect ratio of the first pair of gate structures.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs continues to grow. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices (such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs, fin field effect transistors (finFETs), and interconnect structures for semiconductor devices). This scaling down increases the complexity of semiconductor manufacturing processes. Summary of the invention

[0003] In some embodiments, a semiconductor device includes: a substrate; a first fin structure and a second fin structure, disposed on the substrate; a first pair of gate structures, disposed on the first fin structure; and a second pair of gate structures, disposed on the second fin structure. A first end surface of the first pair of gate structures faces a second end surface of the second pair of gate structures. The first end surface of the first pair of gate structures is in physical contact with a first sidewall of the isolation structure, and the second end surface of the second pair of gate structures is in physical contact with a second sidewall of the isolation structure. The semiconductor device further includes: an isolation structure, interposed between the first pair of gate structures and the second pair of gate structures. The aspect ratio of the isolation structure is less than the combined aspect ratio of the first pair of gate structures.

[0004] In some embodiments, a semiconductor device includes: a substrate; a first fin structure and a second fin structure, disposed on the substrate. The first fin structure and the second fin structure include a first epitaxial region and a second epitaxial region, respectively. The semiconductor device also includes: a first pair of gate structures, disposed on the first fin structure; and a second pair of gate structures, disposed on the second fin structure. The first end surface of the first pair of gate structures faces the second end surface of the second pair of gate structures. The first epitaxial region intervenes between the first side walls of the first pair of gate structures, and the second epitaxial region intervenes between the second side walls of the second pair of gate structures. The semiconductor device also includes: an isolation structure, interposed between the first end surface of the first pair of gate structures and the second end surface of the second pair of gate structures, and between the first fin structure and the second fin structure; and a contact structure, disposed on the first epitaxial region, the second epitaxial region and the isolation structure. The aspect ratio of the isolation structure is less than the combined aspect ratio of the first pair of gate structures.

[0005] In some embodiments, a method includes: forming a first gate structure and a second gate structure on a first fin structure and a second fin structure disposed on a substrate; forming an isolation trench across the first gate structure and the second gate structure; and forming an isolation structure located within the isolation trench. The isolation trench divides the first gate structure into a first pair of gate structures that are electrically isolated from each other, and divides the second gate structure into a second pair of gate structures that are electrically isolated from each other. Forming the isolation trench includes: forming a first trench portion extending to a first distance in the substrate, and forming a second trench portion extending to a second distance in the substrate. The second distance is shorter than the first distance. And forming an isolation structure located within the isolation trench.

[0006] Embodiments of the present application provide an isolation structure for a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read with the accompanying figures.

[0008] Figure 1A shows an isometric view of a semiconductor device having an isolation structure according to some embodiments;

[0009] Figure 1B-Figure 1E A top view and a cross-sectional view of a semiconductor device having an isolation structure according to some embodiments are shown;

[0010] Figure 1F-1I A top view and a cross-sectional view of a semiconductor device having an isolation structure according to some embodiments are shown;

[0011] Figures 1J-1M A top view and a cross-sectional view of a semiconductor device having an isolation structure according to some embodiments are shown;

[0012] Figure 2 is a flow chart of a method for manufacturing a semiconductor device having an isolation structure according to some embodiments;

[0013] Figures 3A-10D Cross-sectional views of a semiconductor device having an isolation structure at various stages of its manufacturing process according to some embodiments are shown.

[0014] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0016] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "exemplary," etc., indicate that the described embodiments may include specific components, structures, or characteristics, but not every embodiment necessarily includes specific components, structures, or characteristics. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when specific components, structures, or characteristics are described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such components, structures, or characteristics in conjunction with other embodiments.

[0018] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, and thus the phraseology or terminology of this specification will be interpreted by those skilled in the relevant (some) field(s) based on the teachings herein.

[0019] As used herein, the term "etch selectivity" refers to the ratio of etching rates of two different materials under the same etching conditions.

[0020] As used herein, the term “high-k” refers to a high dielectric constant. In the field of semiconductor device structure and manufacturing process, high-k refers to a dielectric constant greater than the dielectric constant of SiO2 (eg, greater than 3.9).

[0021] As used herein, the term “low-k” refers to a low dielectric constant. In the field of semiconductor device structure and manufacturing process, low-k refers to a dielectric constant that is less than the dielectric constant of SiO2 (eg, less than 3.9).

[0022] As used herein, the term "p-type" is defined as structures, layers, and / or regions that are doped with a p-type dopant, such as boron.

[0023] As used herein, the term "n-type" is defined as structures, layers, and / or regions that are doped with an n-type dopant, such as phosphorus.

[0024] As used herein, the term "conductive" refers to electrically conductive structures, layers, and / or regions.

[0025] As used herein, the term “gate pitch” refers to the sum of the distance between adjacent gate structures and the gate length of one of the adjacent gate structures.

[0026] In some embodiments, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. It should be understood that the terms "approximately" and "substantially" may refer to a percentage of a value of a given quantity as interpreted by a person skilled in the relevant (some) art(s) in accordance with the teachings herein.

[0027] The fin structures disclosed herein can be patterned by any suitable method. For example, the fin structure can be patterned using one or more lithography processes including a double patterning process or a multiple patterning process. Typically, the double patterning process or the multiple patterning process combines lithography and self-alignment processes, allowing the creation of patterns with smaller pitches, for example, than can be obtained using a single direct lithography process. For example, in some embodiments, a sacrificial layer is formed above a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure.

[0028] The gate structure in a finFET can extend over two or more finFETs. For example, the gate structure can be formed as a long gate structure that extends across the active area (e.g., the fin area) of the finFET. Once the gate structure is formed, the patterning process can "cut" one or more long gate structures into shorter parts according to the desired structure. In other words, the patterning process can remove redundant gate portions of one or more long gate structures to form one or more isolation trenches (also called "metal cuts") between the finFETs and separate the long gate structures into shorter parts. This process is called a cut metal gate (CMG) process. Subsequently, the isolation trenches formed between the separated portions of the long gate structure can be filled with a dielectric material to form an isolation structure. The isolation structure can electrically isolate the spaced-apart gate structure portions.

[0029] As the dimensions in semiconductor technology shrink, the aspect ratio of the gate structure increases, resulting in an increase in the complexity of the CMG process. For example, the high aspect ratio of the gate structure makes it challenging to remove redundant gate portions from the bottom and / or corners of the isolation trench. The presence of any residual gate portion in the isolation trench will prevent the subsequently formed isolation structure from electrically isolating the separated gate structure portions.

[0030] The present invention provides an exemplary isolation structure in a semiconductor device for improving the control of a device manufacturing process, and an exemplary method for manufacturing the same. In some embodiments, the isolation structure can be formed by dielectric filling of an isolation trench having an aspect ratio less than the aspect ratio of one or more gate structures and / or a horizontal dimension (e.g., along the X-axis and / or Y-axis) greater than the gate spacing of the gate structure. Such an isolation trench can be formed by removing two or more redundant gate portions from adjacent gate structures and by removing a dielectric layer (e.g., a gate spacer, an etch stop layer, and an interlayer dielectric (ILD) layer) located between adjacent gate structures. The smaller aspect ratio of the isolation trench helps to effectively remove redundant gate portions from difficult-to-etch locations (e.g., corners and / or bottoms of the isolation trenches) using a simplified etching process in terms of the number of operations required, which in turn reduces device manufacturing costs. Such an isolation trench also helps to effectively fill difficult-to-fill locations, such as corners and / or bottoms of the isolation trenches, at a faster deposition rate, which in turn reduces overall process time and device manufacturing costs. Therefore, when the isolation structure has a smaller aspect ratio than the gate structure, it can be formed to have better control of the CMG process, compared to when the isolation structure and the gate structure have similar aspect ratios and / or horizontal dimensions.

[0031] By cutting multiple long gate structures simultaneously using a single isolation structure, the control of the device manufacturing process can be further improved. The process of cutting multiple long gate structures simultaneously using a single isolation structure can eliminate the variability associated with the CMG process and the complexity associated with the CMG process associated with cutting a single gate structure with a smaller isolation structure (e.g., a length along the X-axis that is less than the gate pitch). Reducing the process-related variability and process-related complexity of finFETs across semiconductor devices can reduce performance variability and device manufacturing costs across finFETs.

[0032] In addition, the isolation structure can extend into the substrate and provide electrical isolation between the p-well region and the n-well region under the finFET. Moreover, the isolation structure can be used as an etch stop layer during the formation of the S / D contact structure to control the height of the S / D contact structure. If the height is greater than about 20nm, the S / D contact structure may form a parasitic capacitor with the adjacent gate structure, which in turn produces undesirable parasitic capacitance in the finFET. The parasitic capacitance can adversely affect device performance, such as adversely affecting the threshold voltage of the finFET. Therefore, by using an isolation structure, the control of the finFET manufacturing process can be further improved.

[0033] According to some embodiments, reference Figure 1A-1M A semiconductor device 100 having finFETs 101 - 102 is depicted. Figure 1A FIG. 1 shows an isometric view of a semiconductor device 100 according to some embodiments. The semiconductor device 100 may have a configuration according to various embodiments such as Figure 1B-1M The different top and cross-sectional views shown. Although reference Figure 1A-1M Two finFETs are discussed, but semiconductor device 100 may have any number of finFETs. FinFETs 101-102 may be n-type, p-type, or a combination thereof. Discussions of elements of finFETs 101-102 having the same annotation apply to each other unless otherwise noted.

[0034] refer to Figure 1A , finFETs 101-102 may be formed on a substrate 106. Substrate 106 may be a semiconductor material, such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, and combinations thereof. In addition, substrate 106 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic). In some embodiments, when finFETs 101-102 have different conductivity types, substrate 106 may include an n-well region and a p-well region (not shown). For example, a p-type finFET 101 may be formed on an n-well region of substrate 106, and an n-type finFET 102 may be formed on a p-well region of substrate 106.

[0035] FinFET 101 may include a fin structure 107 extending along an X-axis, and gate structures 112B-112C extending along a Y-axis disposed on the fin structure 107. Similarly, finFET 102 may include a fin structure 109 extending along an X-axis, and gate structures 112D-112E extending along a Y-axis disposed on the fin structure 108. In some embodiments, in addition to independently controlled gate structures 112B-112E, finFETs 101-102 may also include common gate structures 112A and 112F disposed on both fin structures 107-108. Fin structures 107-108 may be electrically isolated from each other by dielectric structures such as an etch stop layer (ESL) 116, an interlayer dielectric (ILD) layer 118, and a shallow trench isolation (STI) region 120. ESL 116, ILD layer 118, and STI region 120 may include dielectric materials such as silicon oxide, silicon nitride, silicon germanium oxide, and combinations thereof. The gate structures 112A-112F may be electrically isolated from each other by gate spacers 114, ESL 116, and ILD layer 118. The gate spacers 114 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k materials, and combinations thereof.

[0036] In some embodiments, in addition to the gate spacers 114, the ESL 116, and the ILD layer 118, the gate structures 112B-112C can be electrically isolated from the gate structures 112D-112E by the isolation structure 104 to provide an independently controlled gate structure for each FET 101-102. The isolation structure 104 can be formed in a CMG process (described in further detail below) to cut the long gate structure formed on the fin structure 107-108 (e.g., along the Y axis) into shorter gate structures, such as the gate structures 112B-112E. This practice of forming the shorter gate structures can provide better control of the finFET manufacturing process compared to other finFET manufacturing methods that form the shorter gate structures at one time. Forming the shorter gate structures from the same original gate structure can eliminate process-related variability (e.g., during patterning, layer deposition, planarization, etc.) associated with forming multiple shorter gate structures of similar gate structures 112B-112E.

[0037] By using the isolation structure 104 to simultaneously cut multiple long gate structures, the control of the finFET manufacturing process can be further improved. Figure 1AAs shown, an isolation structure 104 having a length along the X-axis that is greater than the gate pitch can simultaneously cut two long gate structures into four shorter gate structures 112B-112E. Although the isolation structure 104 is shown as cutting two long gate structures, the isolation structure 104 can be extended along the X-axis to cut more than two gate structures (e.g., cut gate structures 112A and / or 112F) into shorter gate structures of finFETs 101-102. The process of simultaneously cutting multiple long gate structures with an isolation structure can eliminate the variability associated with the CMG process and the complexity associated with the CMG process related to cutting a single gate structure with a smaller isolation structure (e.g., a length along the X-axis that is less than the gate pitch). Reducing the process-related variability and process-related complexity across finFETs 101-102 can reduce the performance variability and device manufacturing cost across finFETs 101-102. Although one isolation structure 104 is discussed, the semiconductor device 100 can have any number of isolation structures.

[0038] Figure 1B A top view of the semiconductor device 100 is shown without the ILD layer 118 and the ESL 116 on the fin structures 107 - 108 , so that the fin structures 107 - 108 are visible. Figure 1C-1E Shown along Figure 1B Cross-sectional views along lines AA, BB, and CC.

[0039] refer to Figure 1A-1E , the fin structures 107-108 may include fin regions 107A-108A and epitaxial regions 107B-108B disposed on the respective fin regions 107A-108A. Portions of the fin regions 107A-108A under the epitaxial regions 107B-108B may be recessed within the STI region 120 compared to portions of the fin regions 107A-108A under the gate structures 112A-112F. The fin regions 107A-108A may include a material similar to the substrate 106 and may be formed by patterning and etching the substrate 106. In some embodiments, the fin regions 107A-108A may include a semiconductor material different from the substrate 106 and may be formed by patterning and etching an epitaxial layer grown on the substrate 106. In some embodiments, the fin regions 107A-108A may have a semiconductor material having a crystalline microstructure (e.g., an amorphous or non-polycrystalline microstructure).

[0040] Epitaxial regions 107B-108B are formed on portions of respective fin regions 107A-108A not covered by gate structures 112A-112F. Epitaxial regions 107B-108B may be source / drain (S / D) regions of respective finFETs 101-102 and may include epitaxially grown semiconductor materials that are similar to or different from each other. In some embodiments, the epitaxially grown semiconductor material may include the same material as or different from that of substrate 106. Depending on the conductivity type of finFETs 101-102, epitaxial regions 107B-108B may include (i) boron (B) doped SiGe, B doped Ge, or B doped germanium tin (GeSn) for p-type finFETs 101-102; and (ii) carbon doped Si (Si:C), phosphorus doped Si (Si:P), or arsenic doped Si (Si:As) for n-type finFETs 101-102. Additionally, the epitaxial regions 107B- 108B may include multiple layers (eg, two layers, three layers, or multiple layers) having different dopant concentrations and / or different material compositions.

[0041] The gate structures 112A-112F are isolated from the epitaxial regions 107B-108B by gate spacers 114. The gate structures 112A-112F may be multi-layer structures. For simplicity, the different layers of the gate structures 112A-112F are not shown. Each of the gate structures 112A-112F may include an interface oxide (IO) layer, a high-k gate dielectric layer on the IO layer, a work function metal (WFM) layer on the high-k dielectric layer, and a gate metal filling layer on the WFM layer. The IO layer may include silicon oxide (SiO2), silicon germanium oxide (SiGeO x ), or germanium oxide (GeO x ). The high-k gate dielectric layer may include a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). The WFM layer may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), and combinations thereof. The gate metal fill layer may include a suitable conductive material, such as tungsten (W), titanium, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0042] refer to Figure 1B-Figure 1E, the isolation structure 104 may be formed to have an aspect ratio that is less than the aspect ratio of each gate structure 112A-112F, or less than the combined aspect ratio of two or more gate structures 112A-112F, to improve control of the CMG process as discussed above. To achieve a smaller aspect ratio, the isolation structure 104 may be formed to have a length L1 along the X-axis that is at least equal to or greater than the gate pitch of the gate structures 112A-112F (e.g., Figure 1B GP shown), and the height H1 (or H2) along the Z axis is greater than the gate height (eg, Figure 1C In addition, the width W1 of the isolation structure 104 along the Y axis may be smaller than the fin pitch (eg, Figure 1B The gate pitch is defined as the distance between adjacent gate structures along the X-axis divided by the gate length of one of the adjacent gate structures (e.g. Figure 1B The fin pitch is defined as the sum of the distance along the Y axis between adjacent fin structures and the fin width along the Y axis of one of the adjacent fin structures. The aspect ratio of the isolation structure 104 is defined as the ratio of its length L1 to its height H1 or H2. The aspect ratio of each gate structure 112A-112F is defined as the ratio of its gate length GL to its gate height GH.

[0043] The isolation portions 104A-104B of the isolation structure 104 may have different heights at different regions of the semiconductor device 100 (eg, Figure 1C 1-H2). In some embodiments, isolation portion 104A between gate structures 112B and 112D and between gate structures 112C and 112E extends into substrate 106, while isolation portion 104B extends into STI region 120 and does not extend into substrate 106, as shown in FIG. Figure 1C-1E 104B. In some embodiments, the isolation portions 104A-104B may extend into the substrate 106 (not shown), but the isolation portions 104A may extend deeper into the substrate 106 than the isolation portions 104B. The different heights H1-H2 of the respective isolation portions 104A-104B are a result of an etching process used in the formation of the isolation structure 104 described in further detail below. The horizontal dimension of the isolation portion 104A along the X-axis in the substrate 106 may correspond to the gate length of the gate structures 112B-112E. The horizontal dimension of the isolation portion 104B along the X-axis in the STI region 120 may correspond to the distance between the gate structures 112B-112C or 112D-112E.

[0044] In some embodiments, the height H1 may be greater than the height H2 by about 65 nm to about 250 nm. The isolation portion 104A may extend to a distance D1 in the substrate 106 that is about 5 nm to about 250 nm below the STI surface 120 b. The bottom surface of the isolation portion 104B may be (i) a distance D2 that is about 10 nm to about 60 nm above the STI surface 120 b, (ii) a distance (not shown) that is about 10 nm below the STI surface 120 b, or (iii) at the STI surface 120 b. The isolation structure 104 may have a length L1 in a range of about 80 nm to about 140 nm. These ranges of dimensions of the isolation structure 104 provide an aspect ratio for effectively removing redundant gate portions before a dielectric fill process is used to form the isolation structure 104, which will be described in detail below. If the length L1 is shorter than 80 nm, the distance D1 is shorter than 5 nm, and / or the distance D2 is greater than 60 nm above the STI surface 120 b, the aspect ratio of the isolation structure 104 may not be sufficient to effectively remove redundant gates. On the other hand, if length L1 is greater than 140 nm, distance D1 is greater than 250 nm, and / or distance D2 is greater than 10 nm below STI surface 120 b, process time (eg, etching and dielectric filling time) for forming isolation structure 104 increases, which increases device manufacturing cost.

[0045] Additionally, when a p-well region and an n-well region are formed in portions of substrate 106 beneath finfets 101 and 102, respectively, an area of ​​isolation portion 104A extending to a distance D1 in substrate 106 may provide electrical isolation between the p-well region and the n-well region (e.g., Figure 1D Therefore, if the distance D1 is shorter than 5 nm, leakage may exist between the p-well region and the n-well region. Figure 1D P-well and n-well regions are shown in finFETs 101 and 102 , respectively, but finFETs 101 - 102 may both have n-well or p-well regions (not shown), or may not have any well regions.

[0046] In some embodiments, the side and bottom surfaces of the isolation structure 104 may have Figure 1C-1E The dashed outline in the figure is not Figure 1C-1E The straight solid line shown in . Figure 1C-1E The tapered sides and / or curved bottom shown in dashed lines in FIG. 1 may be attributed to an etching process used in the formation of isolation structure 104 described in further detail below. In some embodiments, isolation structure 104 may include one or more dielectric materials, such as silicon nitride, silicon oxide, silicon oxycarbide, and combinations thereof.

[0047] Figure 1F A top view of the semiconductor device 100 is shown when the S / D contact structure 122 is present. Figure 1G-1I Shown along Figure 1F Unless otherwise stated, the Figure 1B-Figure 1I Discussions of elements with the same annotation apply to each other.

[0048] In some embodiments, S / D contact structures 122 may be formed across fin structures 107-108 to electrically connect epitaxial regions 107B-108B to finFETs 101-102 and / or other elements of an integrated circuit (not shown). S / D contact structures 122 may include conductive materials such as ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), tungsten (W), cobalt (Co), and copper (Cu).

[0049] In some embodiments, the portion of the S / D contact structure 122 located on the isolation structure may have a height H3 along the Z-axis, and the portion of the S / D contact structure 122 located on the epitaxial regions 107B-108B may have a height H4 along the Z-axis, wherein the height H3 is greater than the height H4, or the height H3 is substantially equal to the height H4. In some embodiments, the height H3-H4 may be in a range of about 5 nm to about 20 nm. If the height H3-H4 is less than 5 nm, the conductive material in the S / D contact structure 122 may be too thin to provide the S / D contact structure 122 with sufficient conductivity. On the other hand, if the height H3 is greater than 20 nm, the S / D contact structure 122 may form a parasitic capacitor with the gate structures 112B-112F, which in turn may generate undesirable parasitic capacitance in the finFETs 101-102. The parasitic capacitance may adversely affect device performance, such as adversely affecting the threshold voltage of the finFETs 101-102.

[0050] To control the height H3 of the S / D contact structure 122, the isolation structure 104 may be used as an etch stop layer during the formation of the S / D contact structure 122, which will be discussed in further detail below. As an etch stop layer, the isolation structure 104 may prevent over-etching of the ILD layer 118 between the fin structures 107-108 when the contact opening is formed before the contact opening is filled with a conductive material to form the S / D contact structure 122. Therefore, by using the isolation structure 104, the control of the finFET manufacturing process may be further improved.

[0051] Figure 1J A top view of the semiconductor device 100 is shown when the S / D contact structures 122 and 122 * are present. Figure 1L-1M Shown along Figure 1J Unless otherwise stated, the Figure 1B-1MThe discussion of elements with the same annotation in FIG. 1 applies to each other. Unless otherwise stated, the discussion of S / D contact structures 122 and 122* applies to each other. Unless otherwise stated, the discussion of S / D contact structures 122 and 122* in FIG. 1 applies to each other. Figure 1A-1I The discussion of the isolation structure 104 is applicable to Figure 1J-1M Discussion of isolation structure 104**.

[0052] The isolation structure 104** can be formed by extending the isolation structure 104 along the X-axis by the isolation portion 104C, such as Figure 1K As shown. The isolation portion 104C is formed by removing portions of the ESL 116, the ILD layer 118, and the STI 120 between the isolation structure 104 and the gate structures 112A and 112F. Similar to the isolation portion 104B, the isolation portion 104C can be used as an etch stop layer for process control in the formation of the S / D contact structure 122*.

[0053] Figure 2 is a flow chart of an exemplary method 200 for manufacturing a semiconductor device 100 according to some embodiments. For illustrative purposes, reference will be made to Figures 3A-10D and Figure 7E-7J To describe Figure 2 The operation shown. Figure 3A-10A is a top view of various stages in the fabrication of a semiconductor device 100 according to some embodiments. Figure 3B-Figure 10B , Figure 3C-Figure 10C ,and Figure 3D-Figure 10D According to some embodiments, the various stages of manufacturing the semiconductor device 100 are as follows Figures 3A-10A 200. The method 200 is a cross-sectional view of each line DD, EE, and FF. Depending on the specific application, the operations may be performed in a different order, or not performed. It should be noted that the method 200 may not produce a complete semiconductor device 100. Therefore, it should be understood that additional processes may be provided before, during, and after the method 200, and some other processes may only be briefly described herein. Figure 1A-1M Elements in the same annotation Figures 3A-10D and Figure 7E-7J The elements in .

[0054] In operation 205, a fin structure and a gate structure of a finFET are formed. Figure 3A-3DAs shown, fin structures 107-108 having fin regions 107A-108A and epitaxial regions 107B-108B may be formed on substrate 106, and gate structures 112A, 112BD, 112CE, and 112F may be formed on fin regions 107A-108A. Gate structures 112BD-112CE will be cut into gate structures 112B-112E and isolation structure 104 in subsequent processes. The formation of the fin structures 107-108 may include the following sequential operations: (i) patterning the substrate 106 to form the fin regions 107A-108A, (ii) forming a polysilicon gate structure (not shown) on a portion of the fin regions 107A-108B, which polysilicon gate structure will have gate structures 112BD, 112CE, 112A, and 112F formed in a subsequent process, (iii) etching back the portions of the fin regions 107A-108A not covered by the polysilicon gate structure, (iv) forming epitaxial regions 107B-108B on the etched back fin regions 107A-108A, and (v) replacing the polysilicon gate structure with the gate structures 112A, 112BD, 112CE, and 112F.

[0055] refer to Figure 2 In operation 210, an isolation trench is formed across at least two gate structures. Fig.6D As described, an isolation trench 604 may be formed across the gate structures 112BD and 112CE. The formation of the isolation trench 604 may include the following sequential operations: (i) patterning the Figures 3A-3D The method further comprises: (i) forming an opening 424* on the mask layer 424 of the structure of FIG. 1 , and (ii) etching the redundant gate portion 112* and the redundant dielectric portion of the gate structures 112BD-112CE through the opening 424*. The redundant dielectric portion includes portions of the gate spacers 114 and the ESL 116 located on the sidewalls of the redundant gate portion 112*, and portions of the ILD layer 118 located between the redundant gate portions 112*.

[0056] In some embodiments, mask layer 424 is a photoresist material that is spin-coated on Figure 3A-3D The structure is then patterned to form an opening 424*. In some embodiments, the mask layer 424 is a silicon nitride layer, or can be used as an etching mask and prevent Figures 3A-3DThe masking area of ​​the structure is etched with any other suitable material. The opening 424* exposes the redundant gate portion 112* and the redundant dielectric portion that is removed in a subsequent process to form the isolation trench 604. In some embodiments, the opening 424* can be further extended along the X-axis to expose the portion of the ILD layer 118 between the redundant gate portion 112* and the gate structures 112A and 112B to form a longer isolation trench 604, and thus form a similar isolation structure 104** (see above). Figure 1K discussed).

[0057] The etching process for removing the exposed structure through the opening 424* may include a cycle process, wherein each cycle includes two etching operations. The first etching operation may include a dry etching process using a first etchant having a higher etching selectivity for the material of the ILD layer 118 (e.g., SiO2) than for the metal material of the redundant gate portion 112*. The first etchant may include a hydrogen fluoride (HF)-based gas or a carbon fluoride (C x F y The second etching operation may include a dry etching process using a second etchant having a higher etching selectivity for the material of the redundant gate portion 112* than for the material of the ILD layer 118. The second etchant may include a chlorine-based gas.

[0058] The first cycle of the etching process may start with the first etching operation or the second etching operation. In some embodiments, the first cycle may be performed by performing the first etching operation to form Figure 4B-4D The first etching operation may be followed by an etching operation at the opening 424* of the substrate, wherein the exposed redundant dielectric portion is etched deeper than the redundant gate portion 112*. Figure 4A-4D A second etching operation is performed on the structure to form Figure 5A-5D The opening 525 is formed by etching the redundant gate portion 112* deeper than the redundant dielectric portion. The etching process cycle is repeated until the STI region 120 and the substrate 106 below the etched redundant gate portion 112* and the redundant dielectric portion are etched to form the isolation trench 104*. Figure 6A-6D The isolation trench 104* cuts the two gate structures 112BD-112CE into four gate structures 112B-112F, as shown in FIG. Fig. 6A shown.

[0059] The trench portions 104A*-104B* of the isolation trench 104* have different heights H1-H2. Figure 6B-6DAs shown, the trench portion 104A* corresponding to the etched redundant gate portion 112* extends into the substrate 106, while the trench portion 104B* corresponding to the etched redundant dielectric portion extends into the STI region 120 but does not extend into the substrate 106. In some embodiments, the trench portions 104A*-104B* may both extend into the substrate 106 (not shown), but the trench portion 104A* may extend deeper into the substrate 106 than the trench portion 104B*. The different heights H1-H2 of the respective trench portions 104A*-104B* may be attributed to the different etching rates of the materials of the ILD layer 118 and the redundant gate portion 112*. The metal material of the redundant gate portion 112* has a higher etching rate than the material of the ILD layer 118, and therefore, the trench portion 104A* may be etched deeper into the substrate 106 than the trench portion 104B*. The horizontal dimension along the X-axis of trench portion 104A* in substrate 106 may correspond to the gate length of gate structures 112BD-112CE, while the horizontal dimension along the X-axis of trench portion 104B* in STI region 120 may correspond to the distance between gate structures 112BD-112CE.

[0060] In some embodiments, the height H1 may be greater than the height H2 by about 65 nm to about 250 nm. The trench portion 104A* may extend below the STI surface 120 b to a distance D1 of about 5 nm to about 250 nm in the substrate 106. The width of the trench portion 104A* along the X-axis depends on the gate length of the redundant gate portion 112*. In some embodiments, the width may be greater or less than the gate length by about 10 nm to about 40 nm, or may be about 15 nm. The bottom surface of the trench portion 104B* may be (i) located above the STI surface 120 b by a distance D2 of about 10 nm to about 60 nm, (ii) located below the STI surface 120 b by a distance of about 10 nm (not shown), or (iii) at the STI surface 120 b. The isolation trench 104* may have a length L1 in the range of about 80 nm to about 140 nm.

[0061] These size ranges of the isolation trench 104* provide an aspect ratio for effectively removing the redundant gate portion 112* without leaving any gate material residue in the isolation trench 104*. If the length L1 is less than about 80 nm, the distance D1 is shorter than about 5 nm, and / or the distance D2 is greater than about 60 nm above the STI surface 120b, the aspect ratio of the isolation trench 104* may not be sufficient to effectively remove the redundant gate portion 112*. On the other hand, if the length L1 is greater than about 140 nm, the distance D1 is greater than about 250 nm, and / or the distance D2 is greater than about 10 nm below the STI surface 120b, the etching process time increases, which increases the device manufacturing cost.

[0062] In some embodiments, the side and bottom surfaces of the isolation trench 104* may have a Figure 6B-6D The dashed outline in the figure is not Figure 6B-6D The straight solid line shown in . Figure 6B-6D The tapered sides and / or the curved bottom shown with dashed lines in FIG. 5 may be attributed to the etching process.

[0063] refer to Figure 2 In operation 215, the isolation trench is filled with a dielectric material to form an isolation structure. Figure 7A-7D As shown, the isolation trench 104* may be filled with a dielectric material to form the isolation structure 104. In some embodiments, the dielectric filling of the isolation trench 104* may include depositing the dielectric material into the isolation trench 104* from the bottom up, and then using a chemical mechanical polishing (CMP) process to make the isolation structure 104, the ILD layer 118, and the top surfaces of the gate structures 112A and 112F substantially coplanar, as shown in FIG. Figure 7B-7D In some embodiments, the dielectric filling process may include an ALD process that deposits the dielectric material substantially conformally ( Figure 7E-7G ) into the isolation trench 104* until the dielectric material fills the isolation trench 104* to form Figure 7A-7D The ALD process may be followed by a CMP process to substantially coplanarize the isolation structure 104, the ILD layer 118, and the top surfaces of the gate structures 112A and 112F. Figure 7B-7D In some embodiments, a double layer 105A-105B of two different dielectric materials may be substantially conformally deposited into the isolation trench 104* to form the isolation structure 104, as shown in FIG. Figure 7H-7J shown.

[0064] refer to Figure 2 In operation 220, an S / D contact structure is formed across the fin structure and the isolation structure. For example, the S / D contact structure 122 may be formed across the fin structure 107-108 and the isolation structure 104, as shown in FIG. Figures 8A-10D The formation of the S / D contact structure 122 may include the following sequential operations: (i) patterning the Figure 7A-7D The mask layer 826 is formed on the structure to form an opening 826*, such as Figure 8A-B and Fig.8D As shown, (ii) a first etching process is performed to etch back the portion of the isolation structure 104 exposed by the opening 826* to form a cavity 828 in the isolation structure 104 ( Figure 8B and 8D(iii) performing a second etching process to etch the portions of the ILD layer 118 and the ESL 116 exposed through the opening 826* to form S / D contact openings 122*, as shown in FIG. Figure 9A-9B and Fig.9D As shown, and (iv) filling the S / D contact opening 122* with a conductive material to form an S / D contact structure 122, as shown Figures 10A-10D shown.

[0065] In some embodiments, mask layer 826 is a photoresist material that is spin-coated on Figure 7A-7D The structure is then patterned to form openings 826*. In some embodiments, mask layer 424 is a silicon nitride layer, or can be used as an etching mask and prevent Figure 7A-7D The masked areas of the structure are etched of any other suitable material.

[0066] The first etching process may include a dry etching process using a first etchant having a higher etching selectivity for the dielectric material (eg, SiN) of the isolation structure 104 than for the material (eg, SiO2) of the ILD layer 118. The first etchant may include a carbon fluoride-based (C x H y F z ) gas. The second etching process may include a dry etching process using a second etchant, which has a higher etching selectivity for the material of the ILD layer 118 than for the material of the isolation structure 104. The second etchant may include a carbon fluoride (C x F y ) gas. In some embodiments, filling the S / D contact opening 122* may include depositing a conductive material from the bottom up into the S / D contact opening 122*, and then using a CMP process to substantially coplanarize the top surfaces of the S / D contact structure 122, the ILD layer 118, and the isolation structure 104, such as Fig. 10B and Fig. 10D shown.

[0067] The present invention provides an exemplary isolation structure (e.g., isolation structure 104) between finFETs (e.g., finFETs 101-102) for improving control of a device manufacturing process, and an exemplary method for manufacturing the same. In some embodiments, the isolation structure can be formed by dielectric filling of an isolation trench (e.g., isolation trench 104*) having an aspect ratio that is smaller than the aspect ratio of a gate structure and / or a horizontal dimension (e.g., along the X-axis and / or Y-axis) that is larger than the gate pitch of the gate structure. Such an isolation trench can be formed by removing two or more redundant gate portions (e.g., redundant gate portion 112*) from adjacent gate structures, and by removing redundant dielectric layers between the redundant gate portions. The smaller aspect ratio of the isolation trench helps to effectively remove the redundant gate portions from difficult-to-etch locations (e.g., corners and / or bottoms of the isolation trenches) through a simplified etching process in terms of the number of operations required, which in turn reduces device manufacturing costs. Therefore, when the isolation structure has a smaller aspect ratio than the gate structure, it can be formed to have better control of the CMG process compared to when the isolation structure and the gate structure have similar aspect ratios and / or horizontal dimensions.

[0068] By simultaneously cutting multiple long gate structures (e.g., gate structures 112BD-112CE) using a single isolation structure, control of the device manufacturing process can be further improved. The process of simultaneously cutting multiple long gate structures with an isolation structure can eliminate the variability associated with the CMG process and the complexity associated with the CMG process associated with cutting a single gate structure with a smaller isolation structure (e.g., a length along the X-axis that is less than the gate pitch). Reducing the process-related variability and process-related complexity across finFETs (e.g., finFETs 101-102) can reduce performance variability and device manufacturing costs across finFETs.

[0069] In addition, the isolation structure can extend into the substrate 106 and provide electrical isolation between the p-well region and the n-well region under the finFET. Moreover, the isolation structure can be used as an etch stop layer during the formation of the S / D contact structure (e.g., S / D contact structure 122) to control the height of the S / D contact structure and prevent the formation of undesirable parasitic capacitors with adjacent gate structures. Therefore, by using the isolation structure, the control of the finFET manufacturing process can be further improved.

[0070] In some embodiments, a semiconductor device includes: a substrate; a first fin structure and a second fin structure disposed on the substrate; a first pair of gate structures disposed on the first fin structure; and a second pair of gate structures disposed on the second fin structure. A first end surface of the first pair of gate structures faces a second end surface of the second pair of gate structures. The first end surface of the first pair of gate structures is in physical contact with a first sidewall of an isolation structure, and the second end surface of the second pair of gate structures is in physical contact with a second sidewall of the isolation structure. The semiconductor device further includes: an isolation structure interposed between the first pair of gate structures and the second pair of gate structures. The aspect ratio of the isolation structure is less than the combined aspect ratio of the first pair of gate structures. In some embodiments, the isolation structure includes: a first isolation portion extending into the substrate; and a second isolation portion spaced apart from the substrate and extending to a shallow trench isolation region disposed on the substrate. In some embodiments, the isolation structure includes: a first isolation portion extending into the substrate for a first distance; and a second isolation portion extending into the substrate for a second distance, wherein the second distance is shorter than the first distance. In some embodiments, the isolation structure includes: a first isolation portion extending below a top surface of the substrate; and a second isolation portion having a bottom surface disposed on the top surface of the substrate. In some embodiments, the isolation structure includes: a first isolation portion having a first vertical dimension; and a second isolation portion having a second vertical dimension less than the first vertical dimension. In some embodiments, the isolation structure includes: a first isolation portion extending into the substrate and having a horizontal dimension substantially equal to a gate length associated with the first pair of gate structures; and a second isolation portion extending into a shallow trench isolation region on the substrate and having a horizontal dimension substantially equal to a distance between gate structures of the first pair of gate structures. In some embodiments, the isolation structure has a horizontal dimension greater than the gate spacing of the first pair of gate structures. In some embodiments, it also includes: a p-type well region and an n-type well region located in the substrate, wherein the isolation structure is configured to electrically isolate the p-type well region and the n-type well region from each other.

[0071] In some embodiments, a semiconductor device includes: a substrate; a first fin structure and a second fin structure, disposed on the substrate. The first fin structure and the second fin structure include a first epitaxial region and a second epitaxial region, respectively. The semiconductor device also includes: a first pair of gate structures, disposed on the first fin structure; and a second pair of gate structures, disposed on the second fin structure. The first end surface of the first pair of gate structures faces the second end surface of the second pair of gate structures. The first epitaxial region intervenes between the first sidewalls of the first pair of gate structures, and the second epitaxial region intervenes between the second sidewalls of the second pair of gate structures. The semiconductor device also includes: an isolation structure, interposed between the first end surface of the first pair of gate structures and the second end surface of the second pair of gate structures, and between the first fin structure and the second fin structure; and a contact structure, disposed on the first epitaxial region, the second epitaxial region and the isolation structure. The aspect ratio of the isolation structure is less than the combined aspect ratio of the first pair of gate structures. In some embodiments, a portion of the contact structure is embedded in the isolation structure. In some embodiments, a first portion of the contact structure on the isolation structure has a larger vertical dimension than a second portion of the contact structure on the first epitaxial region. In some embodiments, the isolation structure includes: a first isolation portion having a first vertical dimension; and a second isolation portion having a second vertical dimension less than the first vertical dimension. In some embodiments, the isolation structure includes: the first isolation portion extending into the substrate a first distance; and the second isolation portion extending into the substrate a second distance, wherein the second distance is shorter than the first distance. In some embodiments, the isolation structure includes a nitride material.

[0072] In some embodiments, a method includes: forming a first gate structure and a second gate structure on a first fin structure and a second fin structure disposed on a substrate; forming an isolation trench across the first gate structure and the second gate structure; and forming an isolation structure located within the isolation trench. The isolation trench divides the first gate structure into a first pair of gate structures electrically isolated from each other, and divides the second gate structure into a second pair of gate structures electrically isolated from each other. Forming the isolation trench includes: forming a first trench portion extending to a first distance in the substrate, and forming a second trench portion extending to a second distance in the substrate. The second distance is shorter than the first distance. And forming the isolation structure located within the isolation trench. In some embodiments, forming the isolation trench includes: etching the first gate portion and the second gate portion of the first gate structure and the second gate structure, respectively, at a first etching rate; and etching a dielectric layer located between the first gate portion and the second gate portion at a second etching rate that is slower than the first etching rate. In some embodiments, forming the isolation trench includes: etching the first gate portion and the second gate portion of the first gate structure and the second gate structure, respectively, with a fluorine-based etchant gas; and etching the dielectric layer located between the first gate portion and the second gate portion with a chlorine-based etchant gas. In some embodiments, forming the isolation trench comprises a periodic etching process, wherein each period of the periodic etching process comprises: performing a first etching process on a first gate portion and a second gate portion of a first gate structure and a second gate structure, respectively, with a fluorine-based etchant gas at a first etching rate; and performing a second etching process on a dielectric layer between the first gate portion and the second gate portion with a chlorine-based etchant gas at a second etching rate slower than the first etching rate. In some embodiments, forming the isolation structure comprises depositing a dielectric material in the isolation trench. In some embodiments, it also comprises: forming a contact structure located on the isolation structure and the first fin structure and the second fin structure, wherein a portion of the contact structure is embedded in the isolation structure.

[0073] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: substrate; A first fin structure and a second fin structure are disposed on the substrate; a first pair of gate structures, disposed on the first fin structure; A second pair of gate structures, disposed on the second fin structure, wherein a first end surface of the first pair of gate structures faces a second end surface of the second pair of gate structures; and an isolation structure interposed between the first pair of gate structures and the second pair of gate structures; wherein the first end surface of the first pair of gate structures is in physical contact with the first side wall of the isolation structure, the second end surface of the second pair of gate structures is in physical contact with the second side wall of the isolation structure, and The aspect ratio of the isolation structure is smaller than the combined aspect ratio of the first pair of gate structures.

2. The semiconductor device according to claim 1, wherein The isolation structure comprises: a first isolation portion extending into the substrate; and The second isolation portion is spaced apart from the substrate and extends to a shallow trench isolation region disposed on the substrate.

3. The semiconductor device according to claim 1, wherein: The isolation structure comprises: a first isolation portion extending a first distance into the substrate; and A second isolation portion extends into the substrate a second distance, wherein the second distance is shorter than the first distance.

4. The semiconductor device according to claim 1, wherein The isolation structure comprises: a first isolation portion extending below a top surface of the substrate; and A second isolation portion has a bottom surface disposed on the top surface of the substrate.

5. The semiconductor device according to claim 1, wherein The isolation structure comprises: a first isolation portion having a first vertical dimension; and A second isolation portion has a second vertical dimension that is smaller than the first vertical dimension.

6. The semiconductor device according to claim 1, wherein: The isolation structure comprises: a first isolation portion extending into the substrate and having a horizontal dimension substantially equal to a gate length associated with the first pair of gate structures; and A second isolation portion extends into the shallow trench isolation region on the substrate and has a horizontal dimension substantially equal to a distance between the gate structures of the first pair of gate structures.

7. The semiconductor device according to claim 1, wherein The isolation structure has a horizontal dimension greater than a gate pitch of the first pair of gate structures.

8. The semiconductor device according to claim 1, further comprising: A p-type well region and an n-type well region are located in the substrate, wherein the isolation structure is configured to electrically isolate the p-type well region and the n-type well region from each other.

9. A semiconductor device comprising: substrate; A first fin structure and a second fin structure are disposed on the substrate, wherein the first fin structure and the second fin structure include a first epitaxial region and a second epitaxial region, respectively; A first pair of gate structures, disposed on the first fin structure, wherein the first epitaxial region is interposed between first sidewalls of the first pair of gate structures; a second pair of gate structures disposed on the second fin structure, wherein a first end surface of the first pair of gate structures faces a second end surface of the second pair of gate structures, and wherein the second epitaxial region is interposed between second side walls of the second pair of gate structures; an isolation structure interposed between the first end surface of the first pair of gate structures and the second end surface of the second pair of gate structures, and between the first fin structure and the second fin structure, wherein the aspect ratio of the isolation structure is smaller than the combined aspect ratio of the first pair of gate structures; and A contact structure is disposed on the first epitaxial region, the second epitaxial region and the isolation structure.

10. The semiconductor device according to claim 9, wherein A portion of the contact structure is embedded in the isolation structure.

11. The semiconductor device according to claim 9, wherein: A first portion of the contact structure on the isolation structure has a larger vertical dimension than a second portion of the contact structure on the first epitaxial region.

12. The semiconductor device according to claim 9, wherein The isolation structure comprises: a first isolation portion having a first vertical dimension; and A second isolation portion has a second vertical dimension that is smaller than the first vertical dimension.

13. The semiconductor device according to claim 9, wherein: The isolation structure comprises: a first isolation portion extending a first distance into the substrate; and A second isolation portion extends into the substrate a second distance, wherein the second distance is shorter than the first distance.

14. The semiconductor device according to claim 9, wherein: The isolation structure includes a nitride material.

15. A method of forming a semiconductor device, comprising: forming a first gate structure and a second gate structure on the first fin structure and the second fin structure disposed on the substrate; forming an isolation trench spanning the first gate structure and the second gate structure, The isolation trench divides the first gate structure into a first pair of gate structures electrically isolated from each other, and divides the second gate structure into a second pair of gate structures electrically isolated from each other, and wherein forming the isolation trench comprises: forming a first trench portion extending to a first distance in the substrate, and forming a second trench portion extending to a second distance in the substrate, wherein the second distance is shorter than the first distance; and forming an isolation structure within the isolation trench; The aspect ratio of the isolation structure is smaller than the combined aspect ratio of the first pair of gate structures.

16. The method according to claim 15, wherein: The forming of the isolation trench comprises: etching first and second gate portions of the first and second gate structures, respectively, at a first etch rate; and A dielectric layer between the first gate portion and the second gate portion is etched at a second etch rate that is slower than the first etch rate.

17. The method according to claim 15, wherein: The forming of the isolation trench comprises: etching first and second gate portions of the first and second gate structures, respectively, with a fluorine-based etchant gas; and The dielectric layer between the first gate portion and the second gate portion is etched using a chlorine-based etchant gas.

18. The method according to claim 15, wherein: The forming of the isolation trench comprises a periodic etching process, wherein each period of the periodic etching process comprises: performing a first etching process on the first gate portion and the second gate portion of the first gate structure and the second gate structure, respectively, at a first etching rate using a fluorine-based etchant gas; and A second etching process is performed on the dielectric layer between the first gate portion and the second gate portion using a chlorine-based etchant gas at a second etching rate slower than the first etching rate.

19. The method according to claim 15, wherein: The forming of the isolation structure includes depositing a dielectric material within the isolation trench.

20. The method of claim 15, further comprising: A contact structure is formed on the isolation structure and the first and second fin structures, wherein a portion of the contact structure is embedded in the isolation structure.

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