Differential Clock Duty Cycle Correction Using Hybrid Current Injector and Gradient Digital-to-Analog Converter

Abstract

The present invention relates to differential clock duty cycle correction by means of a hybrid current injector and a gradient digital-to-analog converter. An embodiment of the present disclosure provides a differential clock duty cycle correction (DCC) circuit, comprising: a hybrid current injector, which includes a current source for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node, and the correction current is subtracted from a clock signal of an opposite polarity at a second correction node, and wherein a plurality of current sources in the hybrid current injector are controlled by a first portion of an n-bit DAC code to generate the correction current; and a current DAC, which is used to receive a different second portion of the n-bit DAC code and to output a corresponding reference current to the current source in the hybrid current injector, wherein the current source generates the correction current in response to the reference current output by the current DAC for the second portion of the n-bit DAC code.

Description

Technical Field

[0001] The present disclosure relates to clock signals, and more particularly to a differential clock duty cycle correction circuit having a hybrid current injector and a gradient current digital-to-analog converter (DAC). Background Art

[0002] Clock signals are commonly used in all electronic devices and integrated circuits that have the ability to store information (memory). Clock signals can be generated by various types of oscillators and supporting circuits. Clock signals continuously switch between two levels (e.g., logic high and logic low). The duty cycle of the clock signal is determined by the duration of the logic high level and the duration of the logic low level.

[0003] The duty cycle of a clock signal is usually expressed as a percentage. For example, a clock signal with a pattern of 80% high and 20% low has a duty cycle of 80%. In some applications, a clock signal with a duty cycle of 50% may be required. For example, a circuit that relies on both clock edges may not work properly if the clock signal deviates significantly from a 50% duty cycle. For such circuits, a duty cycle correction (DCC) control loop is often employed to compensate for duty cycle distortion (DCD) caused by variations in the manufacturing process, operating temperature, supply voltage, and noise. Summary of the invention

[0004] A first aspect of the present disclosure relates to a differential clock duty cycle correction (DCC) circuit, comprising: a hybrid current injector, which includes a current source for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein a plurality of the current sources in the hybrid current injector are controlled by a first portion of an n-bit DAC code to generate the correction current; and a current DAC, which is used to receive a different second portion of the n-bit DAC code and to output a corresponding reference current to the current sources in the hybrid current injector, wherein the current sources generate the correction current in response to the reference current output by the current DAC for the second portion of the n-bit DAC code.

[0005] A second aspect of the present disclosure includes a method for differential clock duty cycle correction (DCC), comprising: generating an n-bit digital-to-analog converter (DAC) code corresponding to a duty cycle correction, the DAC code having a first part and a second part; receiving the second part of the DAC code at a current DAC, the current DAC generating a reference current in response to the second part of the DAC code; for a DAC code in the first part of the n-bit DAC code, controlling a current source in a hybrid current injector to generate a correction current; and for a DAC code in the second part of the n-bit DAC code, generating the correction current in the hybrid current injector based on the reference current.

[0006] A third aspect of the present disclosure provides a differential clock duty cycle correction (DCC) circuit, comprising: an n-bit digital-to-analog converter (DAC) code corresponding to a DCC correction, the n-bit DAC code comprising a first part and a second part, the first part comprising the first m bits of the n-bit DAC code, the second part comprising the m+1th to nth bits of the n-bit DAC code; a mixed current injector for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein the mixed current injector is controlled by a DAC code in the first part of the n-bit DAC code; and a tapered current DAC for receiving the second part of the n-bit DAC code and for outputting a corresponding reference current to the mixed current injector, wherein the mixed current injector generates the correction current in response to the reference current; wherein the tapered current DAC generates a constant reference current for the DAC code in the first part of the n-bit DAC code, and wherein the DCC circuit has a substantially linear DCC step transfer function.

[0007] The above and other features of the present disclosure will become apparent from the following more particular description of embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals represent like elements.

[0009] Figure 1 A conventional duty cycle correction (DCC) circuit with an analog controlled dynamic current source is shown.

[0010] Figure 2 A conventional DCC circuit with a digitally controlled dynamic current source is shown.

[0011] Figure 3A differential clock DCC circuit with a hybrid current injector and a gradient current digital-to-analog converter (DAC) according to an embodiment is shown.

[0012] Figure 4 A gradual current DAC according to an embodiment is shown.

[0013] Figure 5 A hybrid current injector with a gradual current DAC according to an embodiment is shown.

[0014] Figure 6 The duty cycle stepping and the Figure 1 The conventional DCC circuit and Figure 5 The relationship diagram of the DAC code of the DCC circuit is shown.

[0015] Figure 7 A flow chart of a process for differential clock duty cycle correction according to an embodiment is shown.

[0016] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, the same reference numerals represent the same elements between the drawings. DETAILED DESCRIPTION

[0017] In the following description, reference is made to the accompanying drawings which form a part thereof, and in which specific exemplary embodiments in which the present teachings may be practiced are shown by way of illustration. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Therefore, the following description is illustrative only.

[0018] Conventional duty cycle correction (DCC) circuits, such as Figure 1The DCC circuit shown typically has range and resolution specifications that may be conflicting requirements, especially when the DCC circuit does not have a linear DCC step transfer function (e.g., the DCC step size varies with the DAC current). Typically, the range is reduced until the maximum duty cycle step size reaches the minimum resolution specification. However, conventional DCC circuits that are specifically designed to have a linear transfer function typically require a larger area and more complex wiring to implement. This often results in additional parasitic capacitance that may limit the bandwidth or increase the power consumption of the clock circuit. In some embodiments, semiconductor devices in the DCC circuit may operate in undesirable regions (e.g., subthreshold regions) over multiple portions of the dynamic range. In the subthreshold operating region, mismatches between devices are amplified and the accuracy of transistor device models is typically reduced. This can result in severe nonlinear DCC step sizes, or in the worst case, unpredictable, uncorrectable DCD.

[0019] like Figure 1 As shown, a common type of differential DCC circuit 10 employs an analog controlled current injector 12. Since a fixed amount of charge is injected in a given clock cycle, the current injector 12 is also often referred to as a charge injector. The current injector is configured to add a fixed amount of correction current to a clock signal of a first polarity (e.g., CLKT_IN) and subtract the same amount of correction current from a clock signal of an opposite polarity (e.g., CLKC_IN). In the DCC circuit 10, the comparator 16 outputs a signal DCC_COMP_OUT corresponding to the difference between the duty cycles of the clock signals CLKT_IN and CLKC_IN at the measurement nodes 18 and 20. The signal DCC_COMP_OUT specifies the direction of the required duty cycle correction. The digital logic 22 increases / decreases the DAC code or adjusts the sign bit to an n-bit (e.g., 64-bit) current DAC 24. The DAC 24 converts the reference current I corresponding to the received DAC code to the reference current I ref Output to the current injector 12. In response, the current injector 12 adds a correction current to / from the clock signal CLKT_IN at the correction node 26 according to the received sign bit, and adds a current of the same amount but opposite sign to / from the clock signal CLKC_IN at the correction node 28. The current provided by the current injector 12 varies according to the compensated node voltage. When the feedback loop converges and the duty cycle distortion (DCD) is driven to a correction resolution of less than 1 bit, the current injector 12 has adjusted the rise / fall times at the correction nodes 26, 28, thereby offsetting the open-loop DCD at the measurement nodes 18, 20.

[0020] The current injector 12 generally includes a plurality of semiconductor devices (eg, transistors). As the DAC code of the n-bit DAC 24 increases from 0 to n (eg, n=64), the reference current I provided by the DAC 24 increases. ref The gate bias of the devices within the current injector 12 is gradually increased. The devices transition from subthreshold to saturation and approach triode operation. As the gate overdrive on the devices of the current injector 12 is gradually increased, the devices of the current injector 12 gradually provide more current, but the output voltage range in which the devices operate in the saturation region decreases. For example, for lower DAC codes provided to the DAC 24, the devices in the current injector 12 may operate in the subthreshold region, while for higher DAC codes, the devices in the current injector 12 may operate in the saturation region. When V gs <V t There is a weak reverse or subthreshold current. In this mode of operation, I ds With V gs Increases exponentially. Once V gs >V t , I ds It increases with the square of Vgs. The DAC code at which the current source switches to something other than subthreshold depends on the size of the device.

[0021] As the devices in the current injector 12 transition through these operating regions, the incremental increase in current decreases in a non-linear manner (e.g., the current step size decreases as the DAC code of the DAC 24 increases). This can cause the DCC step size to be severely non-linear, especially over a portion of the range where the current source operates in the sub-threshold region. Additionally, this can result in time delay steps at the correction nodes 26, 28 that may be up to 5 times larger for the lowest DAC code than for the highest DAC code. Furthermore, this can affect the range of the DCC circuit 10, which is limited by the maximum step size that occurs at the 0→1 / 1→0 DAC code transitions. Examples of non-linearities that can be experienced by differential DCC circuits, such as the differential DCC circuit 10, are given by Figure 6 The duty cycle step versus DAC code is indicated by the dashed line in the graph shown.

[0022] Figure 2 A conventional DCC circuit 40 with a digitally controlled dynamic current source is shown. Figure 1 Unlike the illustrated DCC circuit 10 which includes an analog controlled current injector 12, the DCC circuit 40 includes positive and negative current DACs connected directly to the correction nodes 26, 28. Figure 2 As shown, positive current DAC 42 and negative current DAC 44 are coupled to correction node 26 , while positive current DAC 46 and negative current DAC 48 are coupled to correction node 28 .

[0023] The comparator 16 outputs a signal DCC_COMP_OUT corresponding to the difference between the duty cycles of the clock signals CLKT_IN, CLKC_IN at the measurement nodes 18, 20. The signal DCC_COMP_OUT is provided to the digital logic 50, which increments / decrements the DAC code and correspondingly increments / decrements the sign bit of the decoder 52. The decoder 52 outputs a DAC code corresponding to the desired correction current to the positive and negative current DACs 42, 44 coupled to the correction node 26 and the positive and negative current DACs 46, 48 coupled to the correction node 28. In response, the positive and negative current DACs 42, 44, 46, 48 are configured to selectively add or subtract a fixed amount of correction current to the node 26, but to add or subtract the same amount of correction current of opposite polarity to the node 28. Adding / subtracting current at the nodes 26 and 28 will gradually distort the clock duty cycle, effectively canceling the open loop DCD measured at CLKT_OUT / CLKC_OUT.

[0024] Because all positive and negative current DACs in DCC circuit 40 have the same operating point independent of the DAC code, DCC circuit 40 has a more linear DAC code versus duty cycle correction transfer function than DCC circuit 10. However, this linearity is achieved at the expense of area (e.g., >4X), routing complexity (e.g., >4X), and parasitic capacitance (e.g., >5X) compared to DCC circuit 10.

[0025] Figure 3 and Figure 4 A differential DCC circuit 100 is shown according to an embodiment having a hybrid current injector 102 and a gradual current DAC 110 connected to correction nodes 106, 108. Unlike conventional DCC circuits 10, 40 described above, the DCC circuit 100 provides both analog and digital control of the current sources forming the hybrid current injector 102. Advantageously, the DCC circuit 100 provides a more linear DCC step transfer function, prevents subthreshold operation of all current source devices, and can be implemented in a smaller area with less wiring and lower parasitic capacitance than conventional DCC circuits.

[0026] In the DCC circuit 100, the mixed current injector 102 is configured to add / subtract a fixed amount of correction current to the clock signals CLKT_IN, CLKC_IN of the first polarity, and to add / subtract a correction current of the same amount but opposite sign to the clock signals CLKT_IN, CLKC_IN of the opposite polarity. In the DCC circuit 100, the comparator 112 outputs a signal DCC_COMP_OUT, which corresponds to the difference between the duty cycles of the differential clock signals CLKT_IN, CLKC_IN at the measurement nodes 114, 116. The signal DCC_COMP_OUT is provided to the digital logic 118, which increases / decreases the DAC code and adjusts the sign bit of the decoder 52 accordingly. The digital logic 118 outputs a DAC code to the decoder 122 (e.g., from a 6-bit binary to a hot decoder), which is typically an incremental change (e.g., ±1) of the previous DAC code or a change in the sign bit. In response, the decoder 122 outputs an n-bit hot DAC code (e.g., 64 bits).

[0027] According to an embodiment, the DAC code output by the decoder 122 is divided into several parts. For example, the n-bit DAC code output by the decoder 122 may include: a first part P1, which includes the first m least significant bits of the DAC code; and a second part P2, which includes the remaining bits of the DAC code (e.g., bits m+1 to n). For example, for a 64-bit DAC code (e.g., n=64), the first part P1 of the DAC code may include the first 16 least significant bits (e.g., bits 0:15), and the second part P2 of the DAC code may include the remaining 48 bits (e.g., bits 16:63). Figure 3 and Figure 4 As shown, the first part P1 (eg, bits 0:15) of the 64-bit DAC code is provided as a digital control input to the mixed current injector 102. The second part P2 (eg, bits 16:63) of the 64-bit DAC code is input to the gradient current DAC 110, which is configured to convert the reference current I ref The reference current is output as an analog control input to the mixed current injector 102. The reference current obtained from the gradual current DAC 110 is kept constant over the first part P1 of the n-bit DAC code.

[0028] According to an embodiment, the gradient current DAC 110 may be implemented as an n-bit (eg, 64-bit) thermally weighted current DAC. A non-limiting example of such a gradient current DAC 110 is Figure 4 As shown in the figure, each slice (branch) 124 of the gradient current DAC 110 is weighted as needed to compensate for any residual nonlinearity of the analog current source in the hybrid current injector 102. For example, Figure 4As shown, in the case where the DCC step size is larger at the lower DAC code and the DCC step size is smaller at the higher DAC code, the slice 124 of the gradual current DAC 110 corresponding to the lower DAC code can be assigned a lower weight (e.g., weight <1) than the slice 124 of the gradual current DAC 110 at the higher DAC code. This can effectively linearize the DCC step size (e.g., reduce it by up to 5X) across the dynamic range. In this way, maximum linearity in the DCC step transfer function can be achieved by adjusting the effective "weight" of each DAC slice 124.

[0029] like Figure 3 and 5 As shown, the second part P2 (eg, bits 16:63) of the 64-bit DAC code is input to the gradient current DAC 110, which is configured to convert the reference current I ref As an analog control input, the reference current I is output to the mixed current injector 102. For example, when the DAC code decreases from 63 to 16, the gradient current DAC 110 decreases the reference current I input to the mixed current injector 102 by a fixed amount. ref In response, and based on the received sign bit, the mixed current injector 102 is configured to add / subtract a fixed amount of correction current (eg, I ref ), and adds / subtracts correction currents of the same amount but opposite polarity to the clock signals CLKT_IN, CLKC_IN having opposite polarities. Since the gradual current DAC 110 is used, the DCC step size remains substantially linear as the DAC code decreases (eg, from 63 to 16).

[0030] Reference current I ref is provided to a catch diode 126 in the hybrid current injector 102 and sets its gate bias. The gate bias is applied to the transistor of the current source in the hybrid current injector 102 to provide the required amount of correction current. As the DAC code decreases (e.g., from 63 to 16), and the reference current I ref When the size of is correspondingly reduced by the gradual current DAC 110, the transistors in the mixed current injector 102 operate in the saturation region. At DAC codes below m+1, the reference current obtained from the gradual current DAC 110 remains constant, so the current density in the current source of the mixed current injector 102 also remains constant. The size of the current source in the mixed current injector 102 is determined to avoid subthreshold operation for all DAC codes with m+1 (e.g., 16) codes as the constraint.

[0031] While the use of the gradient current DAC 110 compensates for the inherent nonlinearity of the adjustable analog current source, the hybrid injector 102 is further configured to address the issue of DCC step size variation caused by devices operating in the subthreshold region (which may occur at low DAC codes). For example, according to an embodiment, Figure 5 As shown, the current sources in each hybrid current injector 102 can be divided into multiple groups of m current sources (slices) 128 connected in parallel, where each current source 128 is directly enabled / disabled by one of the m DAC codes in the first part P1 of the DAC code (bits 0:15). For example, for m DAC codes, all m current sources 128 are enabled; for m-1 DAC codes, m-1 current sources 128 are enabled, and so on. In this way, the magnitude of the correction current applied to the correction nodes 106, 108 can be increased / decreased as needed by selectively enabling / disabling one or more of the m current sources 128 according to the first part P1 of the DAC code output by the decoder 122. In other words, the first part P1 of the DAC code output by the decoder controls the effective "size" of the current source in the hybrid current injector 102. Advantageously, the reference current I output by the gradient current DAC 110 ref The current density of the current source of the hybrid current injector 102 is maintained at a constant level sufficient to ensure that the transistors of the current source in the hybrid current injector 102 do not operate in subthreshold, thereby improving the linearity of the DCC step transfer function at low DAC codes. An example of the linearity improvement provided by the differential DCC circuit 100 according to an embodiment of the present disclosure is shown by Figure 6 The duty cycle step versus DAC code graph shown is indicated by the solid line.

[0032] In summary, as described above, the first portion P1 of the DAC code (e.g., bits 0:15) can be used to directly control the m current sources 128 in the hybrid current injector 102, thereby preventing subthreshold operation of the current source devices and optimizing the linearity of the DCC step transfer function at low DAC codes. The second portion P2 of the DAC code (e.g., bits 16:63) can be used to control the reference current I output by the gradient current DAC 110. ref This optimizes the linearity of the DCC step transfer function at higher DAC codes.

[0033] Figure 7A flow chart of a process for differential clock duty cycle correction according to an embodiment is shown. In process A1, an n-bit digital-to-analog converter (DAC) code corresponding to the duty cycle correction is updated corresponding to the measured duty cycle correction. In process A2, for the DAC code in the first part P1 of the n-bit DAC code ("yes" at process A2), the DAC code is used in process A3 to directly control the current source in the hybrid current injector 102 to produce a change in the correction current. As described above, the reference current provided by the gradual current DAC 110 remains constant. For the DAC code in the second part P2 of the n-bit DAC code ("no" at process A2), the gradual current DAC 110 increases / decreases accordingly to generate a reference current in process A4, and in process A5, the hybrid current injector generates a correction current based only on the change in the reference current.

[0034] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are also intended to include plural forms, unless the context clearly states otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, integral bodies, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or the groups they constitute. "Optional" or "optionally" means that the event or situation described subsequently may or may not occur, and the description includes situations where the event occurs and situations where the event does not occur.

[0035] Approximate language used throughout the specification and claims may be used to modify any quantitative representation that may be permitted to vary without causing a change in the basic function to which it is related. Therefore, values ​​modified by one or more terms such as "about," "approximately," and "substantially" are not limited to the exact values ​​specified. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. In this article and throughout the specification and claims, range limitations may be combined and / or interchanged, such ranges are identified and include all subranges contained therein, unless the context or language indicates otherwise. "Approximate" applied to a particular value of a range applies to both values, and may indicate + / -10% of the value unless otherwise dependent on the precision of the instrument for measuring the value.

[0036] The corresponding structures, materials, actions, and equivalents of all means or step-plus-function elements in the following claims are intended to include any structure, material, or action that performs a function in conjunction with other claimed elements specifically claimed. The description of the present disclosure has been given for the purpose of illustration and description, but the description is not intended to be exhaustive or to limit the present disclosure to the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. The embodiments are selected and described in order to best explain the principles and practical applications of the present disclosure, and to enable other persons of ordinary skill in the art to understand the various embodiments of the present disclosure with various modifications suitable for the intended specific use.

Claims

1. A differential clock duty cycle correction DCC circuit, comprising: a hybrid current injector comprising current sources for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein a plurality of the current sources in the hybrid current injector are controlled by a first portion of an n-bit DAC code to generate the correction current; and a current DAC for receiving a different second portion of the n-bit DAC code and for outputting a corresponding reference current to the current source in the hybrid current injector, wherein the current source generates the correction current in response to the reference current output by the current DAC for the second portion of the n-bit DAC code.

2. The DCC circuit according to claim 1, wherein: The current DAC generates a reference current that is constant over the first portion of the n-bit DAC code.

3. The DCC circuit according to claim 1, wherein: The first portion of the n-bit DAC code includes the m least significant bits of the n-bit DAC code.

4. The DCC circuit according to claim 3, wherein: The second portion of the n-bit DAC code includes bits (m+1) to (n) of the n-bit DAC code.

5. The DCC circuit according to claim 1, wherein: The current source includes a plurality of semiconductor devices, and wherein none of the semiconductor devices operates in a subthreshold region.

6. The DCC circuit according to claim 1, wherein: The DCC circuit has a substantially linear DCC step transfer function.

7. The DCC circuit according to claim 6, wherein: The current DAC includes a gradual current DAC.

8. The DCC circuit according to claim 7, wherein: The gradient current DAC includes a plurality of slices, and wherein each slice of the plurality of slices is weighted to linearize the DCC step transfer function.

9. The DCC circuit according to claim 8, wherein: The weight of the slices of the gradually changing current DAC corresponding to the lower DAC code is less than the weight of the slices of the gradually changing current DAC corresponding to the higher DAC code.

10. The DCC circuit according to claim 1, wherein: The first portion of the n-bit DAC code directly enables or disables one or more of the current sources to generate the correction current.

11. The DCC circuit of claim 1 , further comprising: a comparator for comparing a duty cycle of a clock signal of a first polarity at a first measurement node with a duty cycle of a clock signal of an opposite polarity at a second measurement node, and for outputting a difference signal; digital logic for generating a correction code and a sign bit indicating the direction of the duty cycle correction; as well as A decoder is used for receiving the correction code and for outputting the n-bit DAC code.

12. A method for differential clock duty cycle correction (DCC), comprising: generating an n-bit DAC code corresponding to a duty cycle correction, the n-bit DAC code having a first portion and a second portion; receiving the second portion of the n-bit DAC code at a current DAC, the current DAC generating a reference current in response to the second portion of the n-bit DAC code; for a DAC code in said first portion of said n-bit DAC code, controlling a current source in a mixed current injector to generate a correction current; as well as For a DAC code in the second portion of the n-bit DAC code, the correction current is generated in the hybrid current injector based on the reference current.

13. The method according to claim 12, wherein: The current DAC generates a reference current that is constant over the first portion of the n-bit DAC code.

14. The method according to claim 12, wherein: The first portion of the n-bit DAC code includes the m least significant bits of the n-bit DAC code.

15. The method according to claim 14, wherein: The second portion of the n-bit DAC code includes bits (m+1) to (n) of the n-bit DAC code.

16. The method according to claim 12, wherein: The first portion of the n-bit DAC code directly controls the effective size of the current source in the hybrid current injector to produce the correction current.

17. The method according to claim 12, wherein: The current source includes a plurality of semiconductor devices, and the method further includes biasing the current source with the reference current when generating the correction current in response to a DAC code in the first portion of the n-bit DAC code, the bias preventing the semiconductor devices in the current source from operating in a subthreshold region.

18. The method according to claim 12, wherein: The current DAC comprises a gradual current DAC including a plurality of slices, the method further comprising weighting each of the plurality of slices to linearize a DCC step transfer function.

19. A differential clock duty cycle correction DCC circuit, comprising: An n-bit DAC code corresponding to DCC correction, the n-bit DAC code comprising a first part and a second part, the first part comprising first m bits of the n-bit DAC code, the second part comprising bits (m+1) to (n) of the n-bit DAC code; a mixed current injector for generating a correction current, wherein the correction current is added to a clock signal of a first polarity at a first correction node and subtracted from a clock signal of an opposite polarity at a second correction node, and wherein the mixed current injector is controlled by a DAC code in the first portion of the n-bit DAC code; and a gradual current DAC for receiving the second portion of the n-bit DAC code and for outputting a corresponding reference current to the hybrid current injector, wherein the hybrid current injector generates the correction current in response to the reference current; wherein the gradient current DAC generates a constant reference current for the DAC code in the first part of the n-bit DAC code, and Wherein, the DCC circuit has a substantially linear DCC step transfer function.

20. The DCC circuit of claim 19, wherein: The gradient current DAC includes a plurality of slices, and wherein each slice of the plurality of slices is weighted to partially linearize the DCC step transfer function.

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