Three-dimensional memory device comprising alternating stacks of source and drain layers and a vertical gate electrode

Abstract

The present invention provides a three-dimensional memory device, which includes an alternating stack of source layers and drain layers located above a substrate, a gate electrode vertically extending through each of the source layers and drain layers of the alternating stack, a memory film laterally surrounding a corresponding one of the gate electrodes, and a semiconductor channel laterally surrounding a corresponding one of the memory films and connected to a corresponding vertically adjacent pair of source layers and drain layers. A memory opening array can vertically extend through the alternating stack, and each of the gate electrodes is located within a corresponding one of the memory openings.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. patent application serial numbers 16 / 539,103 and 16 / 539,124, filed on August 13, 2019, and the entire contents of these applications are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and in particular to a three-dimensional memory device including alternating stacks of source and drain layers and a vertical gate electrode and a method for manufacturing the same. Background Art

[0004] A typical three-dimensional NAND memory device includes an alternating stack of word lines and insulating layers located above a substrate. A vertical semiconductor channel surrounded by memory films includes a charge storage layer located between a blocking dielectric layer and a tunneling dielectric layer and extends vertically through the alternating stack in a memory opening. The bit line is electrically connected to a drain region located at the top of the semiconductor channel, while a source line or interconnect is electrically connected to a source region located at the bottom portion of the vertical semiconductor channel. Summary of the invention

[0005] According to one aspect of the present disclosure, a three-dimensional memory device includes an alternating stack of source layers and drain layers located above a substrate, a gate electrode vertically extending through each of the alternating stack of source layers and drain layers, a memory film each laterally surrounding a corresponding one of the gate electrodes, and a semiconductor channel each laterally surrounding a corresponding one of the memory films and contacting a sidewall of a source layer in a pair of source layers and a drain layer in a pair of drain layers that are respectively vertically adjacent.

[0006] According to another aspect of the present disclosure, a method for forming a three-dimensional memory device includes: forming an alternating stack of doped semiconductor source layers and doped semiconductor drain layers above a substrate; forming a memory opening extending vertically through the alternating stack; forming a continuous semiconductor channel layer in each memory opening, wherein the semiconductor channel is formed on the sidewalls of one doped semiconductor source layer in a pair of doped semiconductor source layers and one doped semiconductor drain layer in a corresponding vertically adjacent pair of doped semiconductor drain layers; forming a memory film above the semiconductor channels; and forming gate electrodes above the memory films, wherein each of the gate electrodes extends vertically through each of the alternating stacks of doped semiconductor source layers and doped semiconductor drain layers.

[0007] According to one aspect of the present disclosure, a three-dimensional memory device includes an alternating stack of source layers and drain layers located above a substrate, an array of memory openings extending vertically through the alternating stack, gate electrodes each located in one memory opening in the array of memory openings and extending vertically through each of the source layers and drain layers in the alternating stack, a memory film each located in one memory opening in the array of memory openings and laterally surrounding a corresponding one of the gate electrodes, and a vertical stack of semiconductor channels laterally surrounding a corresponding one of the memory films, wherein each of the vertical semiconductor channels contacts a horizontal surface of a corresponding vertically adjacent pair of source layers and a drain layer.

[0008] According to another aspect of the present disclosure, a method for forming a three-dimensional memory device includes: forming an alternating stack of doped semiconductor source layers and doped semiconductor drain layers above a substrate; forming a memory opening extending vertically through the alternating stack; forming a memory film and a gate electrode in each memory opening, wherein the memory film and the gate electrode extend vertically through each of the alternating stack of doped semiconductor source layers and doped semiconductor drain layers; and forming a vertical stack of semiconductor channels on horizontal surfaces of one doped semiconductor source layer in a corresponding vertically adjacent pair of doped semiconductor source layers and one doped semiconductor drain layer in a corresponding vertically adjacent pair of doped semiconductor source layers before or after forming the memory film and the gate electrode, wherein each vertical stack of semiconductor channels laterally surrounds a corresponding memory film and a corresponding gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic vertical cross-sectional view of a first exemplary structure after forming multiple instances of a unit layer stack including a source sacrificial material layer, a doped semiconductor source layer, a channel-level insulating layer, a doped semiconductor drain layer, a drain sacrificial material layer and a transistor-interlevel insulating layer above a substrate according to the first embodiment of the present disclosure.

[0010] Figure 2 is a schematic vertical cross-sectional view of a first exemplary structure after forming a stepped surface according to the first embodiment of the present disclosure.

[0011] Figure 3A is a schematic vertical cross-sectional view of a first exemplary structure after forming a backward stepped dielectric material portion and a memory opening array according to the first embodiment of the present disclosure.

[0012] Figure 3B for Figure 3A A top-down view of the first exemplary structure. The vertical plane A-A' is Figure 3A The plane of the section.

[0013] Figure 4 is a schematic vertical cross-sectional view of a first exemplary structure after forming a memory opening filling structure according to the first embodiment of the present disclosure.

[0014] Figure 5 is a schematic vertical cross-sectional view of a first exemplary structure after forming a contact pad structure according to the first embodiment of the present disclosure.

[0015] Fig. 6A is a schematic vertical cross-sectional view of a first exemplary structure after forming backside trenches according to the first embodiment of the present disclosure.

[0016] Figure 6B for Fig. 6A A top-down view of the first exemplary structure. The vertical plane A-A' is Fig. 6A The plane of the section.

[0017] Figure 7 is a schematic vertical cross-sectional view of a first exemplary structure after forming source level backside recesses and drain level backside recesses according to the first embodiment of the present disclosure.

[0018] Figure 8 is a schematic vertical cross-sectional view of a first exemplary structure after forming a metal source layer, a metal drain layer, and a backside trench filling structure according to the first embodiment of the present disclosure.

[0019] Fig.9A is a schematic vertical cross-sectional view of a first exemplary structure after forming a contact via structure according to the first embodiment of the present disclosure. Fig. 9B for Fig.9A A top and partially transparent view of the first exemplary structure of FIG. The vertical plane A-A' is Fig.9A The plane of the section.

[0020] Fig.10 A schematic vertical cross-sectional view of a second exemplary structure after forming multiple instances of a unit layer stack including a source sacrificial material layer, a doped semiconductor source layer, an insulating layer, a doped semiconductor drain layer, a drain sacrificial material layer and an inter-transistor sacrificial material layer above a substrate according to a second embodiment of the present disclosure.

[0021] Fig.11 is a schematic vertical cross-sectional view of a second exemplary structure after forming a stepped surface according to the second embodiment of the present disclosure.

[0022] Fig. 12Ais a schematic vertical cross-sectional view of a second exemplary structure after forming a backward stepped dielectric material portion and a memory opening array according to a second embodiment of the present disclosure.

[0023] Fig. 12B for Fig. 12A A top-down view of the second exemplary structure of FIG. The vertical plane A-A' is Fig. 12A The plane of the section.

[0024] Fig.13 is a schematic vertical cross-sectional view of a second exemplary structure after forming a memory opening filling structure according to the second embodiment of the present disclosure.

[0025] Fig.14 is a schematic vertical cross-sectional view of a second exemplary structure after forming a contact pad structure according to the second embodiment of the present disclosure.

[0026] Fig.15A is a schematic vertical cross-sectional view of a second exemplary structure after forming backside trenches according to the second embodiment of the present disclosure.

[0027] Fig. 15B for Fig.15A A top-down view of the second exemplary structure of FIG. The vertical plane A-A' is Fig.15A The plane of the section.

[0028] Fig.16 is a schematic vertical cross-sectional view of a second exemplary structure after forming source level backside recesses and drain level backside recesses according to the second embodiment of the present disclosure.

[0029] Fig.17 is a schematic vertical cross-sectional view of a second exemplary structure after forming a metal source layer and a metal drain layer according to the second embodiment of the present disclosure.

[0030] Fig.18 is a vertical cross-sectional view of a second exemplary structure after forming inter-transistor backside grooves according to the second embodiment of the present disclosure.

[0031] Fig.19 is a vertical cross-sectional view of the second exemplary structure after dividing each continuous semiconductor channel layer into a group of discrete semiconductor channels vertically spaced apart from each other according to the second embodiment of the present disclosure.

[0032] Fig. 20 is a vertical cross-sectional view of a second exemplary structure after depositing a replacement insulating layer in the inter-transistor backside recess and forming a backside trench fill structure according to the second embodiment of the present disclosure.

[0033] Fig.21is a schematic vertical cross-sectional view of a second exemplary structure after forming a contact via structure according to the second embodiment of the present disclosure.

[0034] Fig. 22 A schematic vertical cross-sectional view of a third exemplary structure after multiple instances of a unit layer stack including a source sacrificial material layer, a doped semiconductor source layer, a channel-level insulating layer, a doped semiconductor drain layer, a drain sacrificial material layer and a transistor-interlevel insulating layer are formed above a substrate according to the third embodiment of the present disclosure.

[0035] Fig.23 is a schematic vertical cross-sectional view of a third exemplary structure after forming a stepped surface according to a third embodiment of the present disclosure.

[0036] Fig.24A is a schematic vertical cross-sectional view of a third exemplary structure after forming a backward stepped dielectric material portion and a memory opening array according to a third embodiment of the present disclosure.

[0037] Fig. 24B for Fig.24A A top-down view of the third exemplary structure of FIG. The vertical plane A-A' is Fig.24A The plane of the section.

[0038] Fig.25 is a schematic vertical cross-sectional view of a third exemplary structure after forming an annular cavity at each level of a trench-level insulating layer according to a third embodiment of the present disclosure.

[0039] Fig.26 is a schematic vertical cross-sectional view of a third exemplary structure after forming a vertical stack of discrete semiconductor channels according to a third embodiment of the present disclosure.

[0040] Fig. 27 is a schematic vertical cross-sectional view of a third exemplary structure after forming a memory opening filling structure according to a third embodiment of the present disclosure.

[0041] Fig.28 is a schematic vertical cross-sectional view of a third exemplary structure after forming a contact pad structure according to the third embodiment of the present disclosure.

[0042] Fig.29A is a schematic vertical cross-sectional view of a third exemplary structure after forming backside trenches according to a third embodiment of the present disclosure.

[0043] Fig.29B for Fig.29A A top-down view of the third exemplary structure of FIG. The vertical plane A-A' is Fig.29A The plane of the section.

[0044] Fig.30 is a schematic vertical cross-sectional view of a third exemplary structure after forming a source level backside recess and a drain level backside recess according to the third embodiment of the present disclosure.

[0045] Fig.31 is a schematic vertical cross-sectional view of a third exemplary structure after forming a metal source layer, a metal drain layer, and a backside trench filling structure according to the third embodiment of the present disclosure.

[0046] Fig.32 is a schematic vertical cross-sectional view of a third exemplary structure after forming a contact via structure according to the third embodiment of the present disclosure.

[0047] Fig.33 A schematic vertical cross-sectional view of a fourth exemplary structure after multiple instances of a unit layer stack including a source sacrificial material layer, a doped semiconductor source layer, a channel-level sacrificial material layer, a doped semiconductor drain layer, a drain sacrificial material layer and a transistor inter-level insulating layer are formed above a substrate according to the fourth embodiment of the present disclosure.

[0048] Fig.34 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a stepped surface according to a fourth embodiment of the present disclosure.

[0049] Fig.35A is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a backward stepped dielectric material portion and a memory opening array according to a fourth embodiment of the present disclosure.

[0050] Fig.35B for Fig.35A A top-down view of the fourth exemplary structure of FIG. The vertical plane A-A' is Fig.35A The plane of the section.

[0051] Fig.36 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a memory opening filling structure according to a fourth embodiment of the present disclosure.

[0052] Fig.37 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a contact pad structure according to a fourth embodiment of the present disclosure.

[0053] Fig.38A is a schematic vertical cross-sectional view of a fourth exemplary structure after forming backside trenches according to a fourth embodiment of the present disclosure.

[0054] Fig.38B for Fig.38A A top-down view of the fourth exemplary structure of FIG. The vertical plane A-A' is Fig.38A The plane of the section.

[0055] Fig.39 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming source level backside recesses and drain level backside recesses according to a fourth embodiment of the present disclosure.

[0056] Fig.40 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a metal source layer, a metal drain layer, and a backside trench filling structure according to a fourth embodiment of the present disclosure.

[0057] Fig.41 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a channel-level backside groove by removing a channel-level sacrificial material layer according to a fourth embodiment of the present disclosure.

[0058] Fig.42 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a semiconductor channel material layer according to the fourth embodiment of the present disclosure.

[0059] Fig.43 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a trench-level insulating layer and a backside trench-filling structure according to a fourth embodiment of the present disclosure.

[0060] Fig.44 is a schematic vertical cross-sectional view of a fourth exemplary structure after forming a contact via structure according to a fourth embodiment of the present disclosure.

[0061] Fig.45 According to the fourth embodiment of the present disclosure, Fig.34 Schematic vertical cross-sectional view of an alternative embodiment of the fourth exemplary structure in which the source sacrificial layer and the drain sacrificial layer are omitted at the processing steps corresponding to the processing steps.

[0062] Fig.46 According to the fourth embodiment of the present disclosure, Fig.37 Schematic vertical cross-sectional view of an alternative embodiment of a fourth exemplary structure at processing steps corresponding to processing steps of .

[0063] Fig.47 According to the fourth embodiment of the present disclosure, Fig.44 Schematic vertical cross-sectional view of an alternative embodiment of a fourth exemplary structure at processing steps corresponding to processing steps of .

[0064] Fig.48 is a circuit diagram of a three-dimensional memory device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0065] As discussed above, embodiments of the present disclosure relate to a three-dimensional memory device and a method for manufacturing the same, the three-dimensional memory device comprising an alternating stack of horizontal source lines, source layers, drain layers, and bit lines, and a vertical gate electrode surrounded by a memory film and a semiconductor channel extending through the alternating stack, various aspects of which are described below. The three-dimensional memory device of the embodiments of the present disclosure provides simpler electrical connections to the source lines, drain lines, and word lines. The semiconductor channel width can be increased in such devices, which provides a tighter threshold voltage distribution and allows the use of higher cell currents to achieve faster memory speeds. Some embodiments also provide electrical isolation between adjacent semiconductor channels.

[0066] The drawings are not drawn to scale. Multiple instances of elements may be repeated in the case of a single instance of an element shown therein, unless explicitly described or otherwise clearly indicated that there is no repetition of elements. Serial numbers such as "first", "second" and "third" are used only to identify similar elements, and different serial numbers may be used throughout the specification and claims of the present disclosure. The same reference numerals represent the same element or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. As used herein, a first element positioned "on" a second element may be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or "process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of the components.

[0067] As used herein, "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0068] As used herein, a first surface and a second surface are "vertically coincident" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends in a straight line along a direction that deviates from the vertical direction by an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along a vertical direction or a substantially vertical direction and may or may not include a curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0069] A monomeric three-dimensional memory array is a memory array in which multiple memory levels are formed on a single substrate such as a semiconductor wafer without a substrate in between. The term "monomeric" refers to the layers of each level of the array being deposited directly on the layers of each lower level of the array. In contrast, a two-dimensional array can be formed separately and then packaged together to form a non-monomeric memory device. For example, as described in U.S. Pat. No. 5,915,167, entitled "Three-dimensional Structure Memory", a non-monomeric stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory level before bonding, but since the memory level is initially formed above a separate substrate, such memory is not a true monomeric three-dimensional memory array. Various three-dimensional memory devices disclosed herein include monomeric three-dimensional NAND string memory devices and may be manufactured using various embodiments described herein.

[0070] refer to Figure 1, the figure shows a first exemplary structure according to the first embodiment of the present disclosure, which can be formed by forming a bottommost insulating layer 32B above a substrate 9, and forming multiple instances of a unit layer stack including an optional source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel-level insulating layer 32C (also referred to as a first insulating layer), a doped semiconductor drain layer 26, an optional drain sacrificial material layer 42D, and a transistor-interlevel insulating layer 32I (also referred to as a second insulating layer) above the bottommost insulating layer 32B. In an alternative configuration, one or both of the optional source sacrificial material layer 42S and / or the optional drain sacrificial material layer 42D can be omitted. As used herein, "unit layer stack" refers to a layer stack of multiple layers as a repeating unit in a structure of multiple instances of a repeating layer stack. A topmost insulating layer 32T can be formed instead of the transistor-interlevel insulating layer 32I as the topmost instance of the unit layer stack (42S, 24, 32C, 26, 42D, 32I). The total number of repetitions of the cell layer stack (42S, 24, 32C, 26, 42D, 32I) can be the same as the total number of levels of vertical field effect transistors to be formed subsequently, which in turn can be the same as the total number of levels of memory elements to be formed subsequently. As used herein, "level" refers to the volume of a device located between a horizontal plane including the top surface of an element of the device and a horizontal plane including the bottom surface of an element of the device.

[0071] Therefore, the channel-level insulating layer 32C is an insulating layer formed between a horizontal plane including a top surface of a semiconductor channel to be formed later and a horizontal plane including a bottom surface of a semiconductor channel to be formed later. The inter-transistor-level insulating layer 32I is an insulating layer formed between a horizontal plane including a top surface of an inter-transistor gap to be formed later and a horizontal plane including a bottom surface of an inter-transistor gap to be formed later. In many examples of unit layer stacking, the number of repetitions of the unit layer stacking may be in the range of 2 to 1024, such as 8 to 128 times, but a lesser or greater number of repetitions may also be used.

[0072] When the present disclosure is described using the following embodiment, i.e., a unit layer stack including an optional source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel-level insulating layer 32C, a doped semiconductor drain layer 26, an optional drain sacrificial material layer 42D, and an inter-transistor-level insulating layer 32I arranged from bottom to top, the present disclosure explicitly contemplates that the layer stack is arranged in a manner such that: Figure 1 An embodiment of the layer stack shown arranged top to bottom in reverse order. Generally, because the source and drain regions can be symmetrical in a field effect transistor, the location of the source element (42S, 24) can be swapped with the location of the drain element (42D, 26).

[0073] The channel-level insulating layer 32C, the inter-transistor insulating layer 32I, the bottommost insulating layer 32B, and the topmost insulating layer 32T are collectively referred to as insulating layers 32. Each insulating layer in the insulating layer 32 includes a corresponding insulating material, such as doped silicate glass, undoped silicate glass (e.g., silicon oxide), or organic silicate glass. The material composition of the channel-level insulating layer 32C may be the same as or different from the material composition of the inter-transistor insulating layer 32I. In one embodiment, each insulating layer in the insulating layer 32 has the same dielectric material composition as a whole. Alternatively, the channel-level insulating layer 32C may have a first dielectric material composition as a whole, and the inter-transistor insulating layer 32I may have a second dielectric material composition different from the first dielectric material composition. The thickness of each channel-level insulating layer 32C may be in the range of 5nm to 50nm, and the thickness of each inter-transistor insulating layer 32I may be in the range of 5nm to 50nm, but smaller and larger thicknesses may also be used.

[0074] The doped semiconductor source layer 24 and the doped semiconductor drain layer 26 include doped semiconductor materials, such as doped polysilicon or doped amorphous silicon that may be subsequently annealed to form doped polysilicon. The conductivity type of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26 is referred to herein as a first conductivity type, which may be p-type or n-type.

[0075] As used herein, "semiconductor material" refers to a material with an electrical conductivity of 1.0×10 -5 S / m to 1.0×10 5 As used herein, "semiconductor material" refers to a material having an electrical conductivity between 1.0×10 -5 S / m to 1.0 S / m and can produce electrical conductivity between 1.0 S / m and 1.0×10 5 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material with an electrical conductivity greater than 1.0×10 5 As used herein, "insulator material" or "dielectric material" refers to a material with an electrical conductivity of less than 1.0×10 -5 As used herein, "heavily doped semiconductor material" refers to a material doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state) (i.e., having a S / m greater than 1.0×10 5S / m) of a semiconductor material. A "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 5 S / m in the range of 1000 s / m. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Therefore, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. Doped semiconductor materials can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that includes at least one metal element. All conductivity measurements are performed under standard conditions.

[0076] The atomic concentration of the first conductivity type dopant in the doped semiconductor source layer 24 and the doped semiconductor drain layer 26 may be 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 The thickness of each doped semiconductor source layer 24 may be in the range of 5 nm to 50 nm, and the thickness of each doped semiconductor drain layer 26 may be in the range of 5 nm to 50 nm, but smaller and larger thicknesses may also be used.

[0077] The source sacrificial material layer 42S and the drain sacrificial material layer 42D are optional layers that may or may not exist. The source sacrificial material layer 42S and the drain sacrificial material layer 42D include materials that can be selectively removed relative to the materials of the insulating layer 32, the doped semiconductor source layer 24, and the doped semiconductor drain layer 26. For example, if the insulating layer 32 includes doped silicate glass, undoped silicate glass, or organic silicate glass, the source sacrificial material layer 42S and the drain sacrificial material layer 42D may include silicon nitride, undoped amorphous silicon, or a silicon-germanium alloy. The thickness of each source sacrificial material layer 42S may be in the range of 5nm to 50nm, and the thickness of each drain sacrificial material layer 42D may be in the range of 5nm to 50nm, but smaller and larger thicknesses may also be used.

[0078] Multiple examples of the unit layer stack may include a first alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 interleaved with a second alternating stack of channel-level insulating layers 32C and inter-transistor-level insulating layers 32I. In the case where the source sacrificial material layer 42S and the drain sacrificial material layer 42D are omitted, each doped semiconductor source layer 24 constitutes a source layer serving as a source region of a corresponding two-dimensional array of vertical field effect transistors, and the doped semiconductor drain layer 26 constitutes a drain layer serving as a drain region of a corresponding two-dimensional array of vertical field effect transistors. In the case where the source sacrificial material layer 42S and the drain sacrificial material layer 42D are included, each adjacent combination of the doped semiconductor source layer 24 and the metal source layer that subsequently replaces the source sacrificial material layer 42S constitutes a source layer serving as a source region of a corresponding two-dimensional array of vertical field effect transistors, and each adjacent combination of the doped semiconductor drain layer 26 and the metal drain layer that subsequently replaces the drain sacrificial material layer 42D constitutes a drain layer serving as a drain region of a corresponding two-dimensional array of vertical field effect transistors.

[0079] The insulating layer (32C, 32I) is formed between each vertically adjacent pair of doped semiconductor source layers 24 and doped semiconductor drain layers 26. The channel-level insulating layer 32C is formed between each vertically adjacent pair of doped semiconductor source layers 24 and doped semiconductor drain layers 26.

[0080] In one embodiment, each of the source-level sacrificial material layers 42S is formed below a corresponding one of the doped semiconductor source layers 24, and each of the drain-level sacrificial material layers 42D is formed above a corresponding one of the doped semiconductor drain layers 26. The first exemplary structure may include at least one memory array region 100, in which a three-dimensional array of memory elements will be subsequently formed, and stepped regions (200A, 200B), in which a stepped surface of multiple instances of a cell layer stack (42S, 24, 32C, 26, 42D, 32I) will be subsequently formed. The stepped regions may include a source-side stepped region 200A and a drain-side stepped region 200B.

[0081] refer to Figure 2, multiple instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I) may be patterned to form a stepped surface in the stepped region (200A, 200B). For example, a trimmable mask layer (not shown) may be formed above the first exemplary structure and may be patterned to cover each memory array region 100 and the proximal portion of the stepped region (200A, 200B) such that an edge of the trimmable mask layer is formed at a location where an outermost vertical step of the stepped surface will subsequently be formed. An anisotropic etching process may be performed to etch through a cell layer stack (42S, 24, 32C, 26, 42D, 32I) in an area not covered by the trimmable mask layer. The trimmable mask layer may be isotropically trimmed such that an edge of the trimmable mask layer is formed at a location where a second outermost vertical step of the stepped surface will subsequently be formed. An anisotropic etching process may be performed to etch through a unit layer stack (42S, 24, 32C, 26, 42D, 32I) in areas not covered by the trimmable mask layer. An isotropic trimming process and an anisotropic etching process for the trimmable mask layer may be repeatedly performed in each of the stepped regions (200A, 200B) to form a stepped surface.

[0082] In one embodiment, the stepped surfaces in a pair of stepped regions (200A, 200B) located on each side of the memory array region 100 may be vertically biased so that one type of surface is physically exposed in one of the stepped regions (200A, 200B) and another type of surface is physically exposed in the other of the stepped regions (200A, 200B). For example, the horizontal surface of the doped semiconductor source layer 24 may be physically exposed in the source-side stepped region 200A adjacent to one side of the memory array region 100, and the horizontal surface of the drain-level sacrificial material layer 42D may be physically exposed in the drain-side stepped region 200B adjacent to the opposite side of the memory array region 100. The vertical offset between the horizontal steps in each pair of stepped regions (200A, 200B) located on opposite sides of the same memory array region 100 may be the same as half the thickness of the cell layer stack (42S, 24, 32C, 26, 42D, 32I), such as the sum of the thickness of the optional source sacrificial material layer 42S, the doped semiconductor source layer 24, and the channel-level insulating layer 32C, or the sum of the thickness of the doped semiconductor drain layer 26, the optional drain sacrificial material layer 42D, and the transistor-level insulating layer 32I. In this case, an etching mask layer (not shown), such as a patterned photoresist layer, may cover the memory array region 100 and one of the stepped regions (e.g., 200A), and vertically recess the other stepped region (e.g., 200B) by half the thickness of the cell layer stack (42S, 24, 32C, 26, 42D, 32I).

[0083] A stepped cavity 69 having a stepped bottom surface may be formed in the stepped region (200A, 200B). When patterning the stepped surfaces on multiple instances of the unit layer stack (42S, 24, 32C, 26, 42D, 32I), the lateral extent of each type of layer in the multiple instances of the unit layer stack (42S, 24, 32C, 26, 42D, 32I) may decrease with the vertical distance from the substrate 9. Therefore, the doped semiconductor source layer 24 in the alternating stack of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26 has a different lateral extent that decreases with the vertical distance from the substrate 9. Similarly, the doped semiconductor drain layer 26 in the alternating stack of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26 has a different lateral extent that decreases with the vertical distance from the substrate 9. After forming the topmost vertical step, the trimmable mask layer may be removed.

[0084] refer to Figure 3A and Figure 3B , a backward stepped dielectric material portion 65 (i.e., an insulating filling material portion) may be formed therein by depositing a dielectric material in each stepped cavity 69. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from above the top surface of the topmost insulating layer 32T, for example, by chemical mechanical planarization (CMP). Each remaining portion of the deposited dielectric material that fills the stepped cavity constitutes a backward stepped dielectric material portion 65. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically according to the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the backward stepped dielectric material portion 65, the silicon oxide of the backward stepped dielectric material portion 65 may be doped with a dopant or may not be doped with a dopant, such as B, P, and / or F.

[0085] A photoresist material stack (not shown) including at least a photoresist layer may be formed over the topmost insulating layer 32T and the backward stepped dielectric material portion 65, and may be photolithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the stepped region (200A, 200B). The pattern in the photoresist material stack may be passed through the topmost insulating layer 32T or the backward stepped dielectric material portion 65, the multiple instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I), and the bottommost insulating layer 32B by at least one anisotropic etching using the patterned photoresist material stack as an etching mask. Portions of the multiple instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I) located in the memory array region 100 and below the first set of openings in the patterned photoresist material stack are etched to form memory openings 49. As used herein, "memory opening" refers to a structure in which a memory element such as a memory stack structure is subsequently formed. Memory opening 49 is formed through the entirety of the topmost insulating layer 32T and multiple instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I) in the memory array area 100. Multiple instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I) and portions of the back-stepped dielectric layer 65 located in the step region (200A, 200B) and below the second set of openings in the patterned photoresist material stack are etched to form Figure 3B Optional support opening 19 is shown.

[0086] The memory opening 49 extends through the entirety of the plurality of instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I). The chemistry of the anisotropic etching process used to etch the material through the plurality of instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I) may be alternated to optimize the etching of the corresponding material in the plurality of instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I). The anisotropic etching may be, for example, a series of reactive ion etchings. The sidewalls of the memory opening 49 may be substantially vertical, or may be tapered. The patterned photolithographic material stack may then be removed, for example, by ashing.

[0087] The memory openings 49 may extend from the top surface of the plurality of instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I) to at least a horizontal plane including the topmost surface of the substrate 9. Each of the memory openings 49 may include one sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate 9. A two-dimensional array of memory openings 49 may be formed in the memory array region 100 through the plurality of instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I). Thus, the two-dimensional array of memory openings 49 may be formed through the alternating stacking of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26. In one embodiment, the two-dimensional array of memory openings 49 may be formed as a cluster of a periodic two-dimensional array (such as a hexagonal array).

[0088] refer to Figure 4 , continuous material layers may be sequentially deposited in each memory opening in the memory opening 49 and each support opening in the support opening 19 (if present). These continuous material layers may include a continuous semiconductor channel layer, a continuous memory film, a continuous conductive material layer, and an optional dielectric filling material layer. Excess portions of the continuous material layer may be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T and the top surface of the backward stepped dielectric material portion by a planarization process. The planarization process may employ chemical mechanical planarization (CMP) and / or at least one recess etching process. Each portion of the continuous material layer remaining in the memory opening 49 constitutes a memory opening filling structure 58. Each portion of the continuous material layer remaining in the support opening 49 constitutes a pillar 20 (such as Figure 6B shown).

[0089] Each memory opening filling structure 58 includes a continuous semiconductor channel layer 60L, a memory film 54, a gate electrode 66, and an optional dielectric core 62. Each continuous semiconductor channel layer 60L is the remaining portion of the continuous semiconductor channel layer after the planarization process. Each memory film 54 is the remaining portion of the continuous memory film after the planarization process. Each gate electrode 66 is the remaining portion of the continuous conductive material layer after the planarization process. Each gate electrode 66 can be a control gate electrode of a NAND memory device. The gate electrode 66 can be electrically connected to an overlying word line to be formed in a subsequent step. Each dielectric core 62 is the remaining portion of the dielectric filling material layer.

[0090] The continuous semiconductor channel layer 60L comprises a doped semiconductor material having a second conductivity type, which is opposite to the first conductivity type. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa. The semiconductor material in the continuous semiconductor channel layer 60L may comprise silicon, a silicon-germanium alloy or a compound semiconductor material. The atomic concentration of the dopant of the second conductivity type in the continuous semiconductor channel layer 60L may be in the range of 1.0×10 14 / cm 3 to 3.0×10 17 / cm 3 but smaller and larger atomic concentrations may also be employed. The thickness of the continuous semiconductor channel layer 60L may be in the range of 1 nm to 30 nm, such as 3 nm to 10 nm, but smaller and larger thicknesses may also be employed.

[0091] The memory film 54 comprises at least one material layer capable of storing data bits in the form of trapped charges or polarization. In one embodiment, each memory film in the memory film comprises a layer stack which, from the outside to the inside, comprises a tunneling dielectric layer 542 in contact with the semiconductor channel layer 60L, a blocking dielectric layer 546 in contact with the gate electrode 66, and a charge storage layer 544 located between and in contact with both the tunneling dielectric layer 542 and the blocking dielectric layer 546. The tunneling dielectric layer 542 may comprise a tunneling dielectric material, such as a silicon oxide layer or an ONO stack (i.e., a stack of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer). The charge storage layer 544 may comprise a charge storage material, such as silicon nitride or charge storage nanoparticles embedded in a dielectric material. The blocking dielectric layer 546 may comprise a blocking dielectric material, such as silicon oxide and / or a dielectric metal oxide (such as aluminum oxide). In another embodiment, each memory film in the memory film 54 comprises a ferroelectric material layer (not shown) and at least one optional dielectric material layer (such as a silicon oxide layer) capable of contacting the continuous semiconductor channel layer 60L or the gate electrode 66. The ferroelectric material layer may comprise hafnium dioxide (HfO2) or hafnium zirconium oxide (Hf x Zr 1-x O2), where 0.01 < x < 0.99. The ferroelectric material layer may comprise suitable dopants (such as Al, Zr, Y, Gd, La, Sr and / or Si) to enhance ferroelectricity.

[0092] Each gate electrode 66 comprises a conductive material, such as a metal material. For example, each gate electrode 66 may comprise a layer stack including a metal nitride liner (e.g., a barrier layer) including a conductive metal nitride (such as TiN, TaN or WN) and a metal fill layer including a metal (such as W, Co, Mo, Ru, Cu or an alloy thereof).

[0093] Each optional dielectric core 62 includes a dielectric filler material, such as silicon oxide. In one embodiment, the dielectric core 62 may include a dielectric material having a higher etching rate in an etching process than the topmost insulating layer 32T. For example, the dielectric core 62 may include borosilicate glass, organosilicate glass, or phosphosilicate glass, and the topmost insulating layer 32T may include dense undoped silicate glass. In this case, the material of the dielectric core 62 may then be recessed relative to the material of the topmost insulating layer 32T.

[0094] Each portion of the continuous semiconductor channel layer 60L extending from the bottom surface of the doped semiconductor source layer 24 to the top surface of the doped semiconductor drain layer 26 constitutes a semiconductor channel. Each continuous semiconductor channel layer 60L includes a vertical stack of semiconductor channels. Each of these semiconductor channels is formed on the cylindrical sidewalls of a corresponding vertically adjacent pair of doped semiconductor source layers 24 and doped semiconductor drain layers 26. Each of these semiconductor channels is also formed on the cylindrical sidewalls of a corresponding channel-level insulating layer in the channel-level insulating layer 32C. In the first embodiment, each vertical stack of semiconductor channels is formed as a continuous semiconductor channel layer 60L, which extends through each doped semiconductor source layer 24 and each doped semiconductor drain layer 26 in the alternating stack of doped semiconductor source layers 24 and doped semiconductor drain regions 26. Each of these semiconductor channels is connected to a corresponding vertically adjacent pair of doped semiconductor source layers 24 and doped semiconductor drain layers 26. Each continuous semiconductor channel layer 60L extends through each doped semiconductor source layer 24 and each doped semiconductor drain layer 26 in the alternating stack of doped semiconductor source layers 24 and doped semiconductor drain layers 26 .

[0095] A memory film 54 is formed on each of the vertical stacks of semiconductor channels, and a gate electrode 66 is formed on each of the memory films 54. Each of the gate electrodes 66 vertically extends through each of the alternating stacks of doped semiconductor source layers 24 and doped semiconductor drain layers 26. Each gate electrode 66 extends through each doped semiconductor source layer 24 and each doped semiconductor drain layer 26 in the alternating stacks of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26.

[0096] Each continuous semiconductor channel layer 60L includes a hollow cylindrical portion and a bottom cover portion adjacent to the bottom outer edge of the cylindrical portion. Each memory film 54 includes a hollow cylindrical portion and a bottom cover portion adjacent to the bottom outer edge of the cylindrical portion. Each gate electrode 66 may include a hollow cylindrical portion and a bottom cover portion adjacent to the bottom outer edge of the cylindrical portion. The gate electrode 66 may be vertically spaced apart from the substrate 9 by a horizontal portion of the memory film 54. If the gate electrode 66 includes a hollow cylindrical portion, each of the gate electrodes 66 may laterally surround the corresponding dielectric core 62. Alternatively, if the gate electrode 66 includes a filled cylinder, the dielectric core 62 may be omitted. Although the above describes a cylinder and a cylindrical portion that fills the cylindrical memory opening 49, if the memory opening has a shape other than a cylinder (for example, if the memory opening 49 has a polygonal horizontal cross-sectional shape), other shapes that fill the memory opening 49 may be formed.

[0097] refer to Figure 5 , the top portion of the dielectric core 62 may be vertically recessed to form a cavity region. Conductive material (such as a metal material) may be deposited in these cavity regions. Excess portions of the conductive material may be removed from above the horizontal plane including the top surface of the topmost insulating layer 32T. Each remaining portion of the conductive material constitutes a contact pad structure 68.

[0098] In one embodiment, the contact pad structures 68 may include a metal nitride liner (TaN, TiN or WN) and a layer stack of a conductive fill material such as a metal material (such as W, Ru, Co or Mo), a doped semiconductor material and / or a metal silicide material. Each contact pad structure 68 contacts the top end of the corresponding gate electrode 66 and is laterally spaced apart from the corresponding continuous semiconductor channel layer 60L by the corresponding memory film 54. Alternatively, if the gate electrode 66 includes a filled cylinder, the contact pad structure 68 may be omitted.

[0099] refer to Fig. 6A and Figure 6B , a photoresist layer (not shown) may be applied over the topmost insulating layer 32T and photolithographically patterned to form openings in the region between the memory opening fill structures 58 and the clusters of pillars 20. For simplicity, the pillars 20 are not shown in subsequent figures. Anisotropic etching may be employed to cause the pattern in the photoresist layer to pass through the topmost insulating layer 32T and multiple instances of the cell layer stack (42S, 24, 32C, 26, 42D, 32I) to form backside trenches 79 that extend vertically from the top surface of the topmost insulating layer 32T to at least the top surface of the substrate 9 and extend laterally through the memory array region 100 and the step region (200A, 200B).

[0100] In one embodiment, the backside trenches 79 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The memory opening filling structures 58 may be arranged in rows extending along the first horizontal direction hd1.

[0101] Each backside trench 79 may have a uniform width that is constant along the longitudinal direction (ie, along the first horizontal direction hd1). Multiple rows of memory opening filling structures 58 may be located between adjacent pairs of backside trenches 79. The photoresist layer may be removed, for example, by ashing.

[0102] refer to Figure 7 , an etchant that selectively etches the material of the source sacrificial material layer 42S and the drain sacrificial material layer 42D relative to the material of the insulating layer 32, the doped semiconductor source layer 24, the doped semiconductor drain layer 26, the backward stepped dielectric material portion 65, and the continuous semiconductor channel layer 60L may be introduced into the backside trench 79, for example, by an etching process. The source-level backside recess 43S and the drain-level backside recess 43D are formed in the space from which the source sacrificial material layer 42S and the drain sacrificial material layer 42D are removed, respectively. In one embodiment, the source sacrificial material layer 42S and the drain sacrificial material layer 42D may include silicon nitride, and the material of the insulating layer 32 and the backward stepped dielectric material portion 65 may include silicon oxide.

[0103] The etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced in a vapor phase into the backside trench 79. For example, if the source sacrificial material layer 42S and the drain sacrificial material layer 42D include silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials.

[0104] Each back side groove (43S, 43D) can be a laterally extending cavity whose lateral dimension is greater than the vertical extent of the cavity. In other words, the lateral dimension of each back side groove (43S, 43D) can be greater than the height of the back side groove (43S, 43D). A plurality of source level back side grooves 43S and drain level back side grooves 43D can be formed in a space from which the material of the source sacrificial material layer 42S and the drain sacrificial material layer 42D is removed. The memory opening in which the memory opening filling structure 58 is formed is referred to herein as a front side opening or a front side cavity, in contrast to the source level back side groove 43S and the drain level back side groove 43D. Each of the plurality of source level back side grooves 43S and the drain level back side groove 43D can extend substantially parallel to the top surface of the substrate 9. In one embodiment, each back side groove (43S, 43D) can have the same height as a whole.

[0105] refer to Figure 8 , at least one metal material may be deposited in the source-level backside groove 43S and the drain-level backside groove 43D through the backside groove 79. The at least one metal material may include a metal nitride material (such as TaN, TiN or WN) forming a metal liner and a metal filling material (such as W, Co, Ru or Mo) filling the remaining space of the source-level backside groove 43S and the drain-level backside groove 43D that is not filled by the metal liner. The at least one metal material fills all the spaces of the source-level backside groove 43S and the drain-level backside groove 43D. The portion of the at least one metal material deposited on the outer edge portion of the backside groove 79 or above the topmost insulating layer 32T may be removed by an etching process, and the etching process may include an isotropic etching process and / or an anisotropic etching process. The remaining portion of the at least one metal material filling the source-level backside groove 43S constitutes a metal source layer (i.e., a conductive source line) 22. The remaining portion of the at least one metal material filling the drain level backside recess 43D constitutes a metal drain layer (i.e., a conductive bit line) 28. Each contiguous combination of the doped semiconductor source layer 24 and the metal source layer 22 constitutes a source layer (22, 24) that serves as a source region and a source line for a corresponding two-dimensional array of vertical field effect transistors. Each contiguous combination of the doped semiconductor drain layer 26 and the metal drain layer 28 constitutes a drain layer (26, 28) that serves as a drain region and a bit line for a corresponding two-dimensional array of vertical field effect transistors.

[0106] As discussed above, the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D are optional elements that can be omitted. In the presence of the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D, the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D are replaced with the metal source layer 22 and the metal drain layer 28 (i.e., the source line and the bit line), respectively. In this case, each of the source layers (22, 24) includes a vertical stack of a doped semiconductor source layer 24 and a metal source layer 22, and each of the drain layers (26, 28) includes a vertical stack of a doped semiconductor drain layer 26 and a metal drain layer 28. In the case of omitting the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D, each of the source layers consists of a doped semiconductor source layer 24, and each of the drain layers consists of a doped semiconductor drain layer 26. In this case, the doped semiconductor source layer 24 serves as both a source region and a source line, and the doped semiconductor drain layer 26 serves as both a drain region and a bit line. It should be understood that the processing steps for replacing the source level sacrificial material layer 42S and the drain level sacrificial material layer 42D with the metal source layer 22 and the metal drain layer 28, respectively, are omitted in all such embodiments.

[0107] The insulating layer (32C, 32I) is located between each vertically adjacent pair of source layers (22, 24) and drain layers (26, 28). In one embodiment, the insulating layer (32C, 32I) may have the same dielectric material composition throughout, which may be a composition of doped silicate glass, undoped silicate glass, or organic silicate glass. In another embodiment, the channel-level insulating layer 32C may have a different composition from the inter-transistor level insulating layer 32I. In one embodiment, each semiconductor channel contacts a cylindrical sidewall of a corresponding channel-level insulating layer 32C located between a corresponding vertically adjacent pair of source layers (22, 24) and drain layers (26, 28).

[0108] A dielectric material, such as silicon oxide, may be deposited in each backside trench to form a backside trench filling structure 76. The portion of the dielectric material deposited above the topmost insulating layer 32T may constitute a contact-level dielectric layer 80. Each backside trench filling structure 76 may extend vertically through multiple instances of a cell layer stack including a metal source layer 22, a doped semiconductor source layer 24, a channel-level insulating layer 32C, a doped semiconductor drain layer 26, a metal drain layer 28, and an inter-transistor-level insulating layer 32I.

[0109] refer to Fig.9A and Fig. 9B , contact via structures (88, 86) may be formed through the contact-level dielectric layer 80 and optionally through the rear stepped dielectric material portion 65. The contact via structures (88, 86) include word line contact via structures 88, each of which contacts a corresponding one of the contact pad structures 68 and is electrically connected to a corresponding gate electrode 66. In addition, the contact via structures (88, 86) include layer contact via structures 86 (e.g., 86S, 86D) that contact a corresponding one of the source layers (22, 24) and the drain layers (26, 28) within the corresponding stepped regions (200A, 200B). Specifically, each of these layer contact via structures (86S, 86D) can contact a horizontal surface of a corresponding one of the source layers (22, 24) or a corresponding one of the drain layers (26, 28) exposed in the stepped surface in the stepped region (200A, 200B). Then, a word line 98 is formed over the contact-level dielectric layer 80 (as well as over the gate electrode 66, the source layers (22, 24) and the drain layers (26, 28)) and is in electrical contact with the gate electrode 66 through the contact via structure 88 and the optional contact pad structure 68. Fig. 9B As shown, the word lines 98 are arranged in a two-dimensional array extending in a horizontal direction, which is perpendicular to the longitudinal direction of the backside trenches 79. Fig. 9B, the location of memory opening filling structure 58 is schematically represented as a transparent circle, and the location of backside trench 79 is schematically represented as a transparent line.

[0110] Each vertical stack of semiconductor channels is formed as part of a continuous semiconductor channel layer 60L and remains part of the continuous semiconductor channel layer after forming the contact via structures (86, 88), which extend through each source layer (22, 24) and each drain layer (26, 28) within the alternating stack of source layers (22, 24) and drain layers (26, 28). The layer contact via structures 86 include source layer contact via structures 86S and drain layer contact via structures 86D. Each source layer contact via structure 86S contacts a corresponding one of the source layers (22, 24). Each drain layer contact via structure 86D contacts a corresponding one of the drain layers (26, 28).

[0111] In one embodiment, the source layers (22, 24) in the alternating stack of source layers (22, 24) and drain layers (26, 28) have different lateral extents that decrease with the vertical distance from the substrate 9, and the drain layers (26, 28) in the alternating stack of source layers (22, 24) and drain layers (26, 28) have different lateral extents that decrease with the vertical distance from the substrate 9. The first backward stepped dielectric material portion 65 contacts the horizontal surface of the source layers (22, 24) in the alternating stack and laterally surrounds the source layer contact via structure 86S. The second backward stepped dielectric material portion 65 contacts the horizontal surface of the drain layers (26, 28) in the alternating stack and laterally surrounds the drain layer contact via structure 86D.

[0112] refer to Fig.10 , the inter-transistor insulating layer 32I can be replaced by a sacrificial material layer. Figure 1 The first exemplary structure of the second exemplary structure of the present disclosure leads to a second exemplary structure according to the second embodiment of the present disclosure, and these sacrificial material layers are referred to herein as inter-transistor level sacrificial material layers 142. Therefore, each instance of the unit layer stack within the multiple instances of the unit layer stack includes a source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel-level insulating layer 32C, a doped semiconductor drain layer 26, a drain sacrificial material layer 42D, and an inter-transistor level sacrificial material layer 142.

[0113] The source sacrificial material layer 42S and the drain sacrificial material layer 42D include sacrificial materials that can be selectively removed relative to the materials of the channel-level insulating layer 32C, the bottommost insulating layer 32, and the topmost insulating layer 32T, and relative to the materials of the inter-transistor level sacrificial material layer 142. For example, the channel-level insulating layer 32C, the bottommost insulating layer 32, and the topmost insulating layer 32T may include undoped silicate glass, doped silicate glass, or organic silicate glass; the inter-transistor level sacrificial material layer 142 may include materials such as dielectric metal oxides (e.g., aluminum oxide), silicon-germanium alloys with a germanium atomic concentration greater than 20%, polymer materials, or metal materials different from the metal source layer and the metal drain layer that will be used to subsequently replace the source sacrificial material layer 42S and the drain sacrificial material layer 42D; and the source sacrificial material layer 42S and the drain sacrificial material layer 42D may include silicon nitride. Each inter-transistor level sacrificial material layer 142 may have a thickness in the range of 5 nm to 50 nm, but smaller and larger thicknesses may also be used. In alternative configurations, one or both of the source sacrificial material layer 42S and / or the drain sacrificial material layer 42D may be omitted.

[0114] Multiple examples of unit layer stacking include alternating stacks of doped semiconductor source layers 24 and doped semiconductor drain layers 26. A channel-level insulating layer 32C may be disposed between each vertically adjacent pair of lower doped semiconductor source layers 24 and overlying doped semiconductor drain layers 26. An inter-transistor-level sacrificial material layer 142 is formed between vertically adjacent pairs of overlying doped semiconductor source layers 24 and lower doped semiconductor drain layers 26.

[0115] refer to Fig.11 , executable Figure 2 The processing steps are performed to form a stepped cavity 69 in the stepped region (200A, 200B). A stepped surface is formed in the stepped region (200A, 200B). The steps of the anisotropic etching process used to form the stepped surface can be modified to provide an etching chemistry that effectively etches the inter-transistor level sacrificial material layer 142.

[0116] refer to Fig. 12A and Fig. 12B , executable Figure 3A and Figure 3B The processing steps of the memory opening 49 are formed through each layer of the multiple instances of the cell layer stack. As discussed above, the cell layer stack of the second exemplary structure may include a source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel-level insulating layer 32C, a doped semiconductor drain layer 26, a drain sacrificial material layer 42D, and an inter-transistor sacrificial material layer 142. The steps of the anisotropic etching process for forming the memory opening 49 may be modified to provide an etching chemistry that effectively etches the inter-transistor level sacrificial material layer 142.

[0117] refer to Fig.13 , executable Figure 4 The processing steps are performed to form the memory opening filling structure 58. Each of the memory opening filling structures 58 of the second exemplary structure may have the same Figure 4 The memory opening filling structure 58 is the same as a set of elements.

[0118] refer to Fig.14 , executable Figure 5 The processing steps are as follows to form the contact pad structure 68. Each memory opening filling structure 58 may include a corresponding contact pad structure 68 that contacts a top end of a corresponding one of the gate electrodes 66.

[0119] refer to Fig.15A and Fig. 15B , executable Fig. 6A and Figure 6B The processing steps of the present invention are used to form the backside trenches 79 through multiple instances of the cell layer stack. The steps of the anisotropic etching process used to form the backside trenches 79 can be modified to provide an etching chemistry that effectively etches the inter-transistor level sacrificial material layer 142.

[0120] refer to Fig.16 , an etchant that selectively etches the material of the source sacrificial material layer 42S and the drain sacrificial material layer 42D relative to the material of the insulating layer 32, the inter-transistor level sacrificial material layer 142, the doped semiconductor source layer 24, the doped semiconductor drain layer 26, the backward stepped dielectric material portion 65, and the continuous semiconductor channel layer 60L may be introduced into the backside trench 79, for example, by an etching process. The source level backside recess 43S and the drain level backside recess 43D are respectively formed in the space from which the source sacrificial material layer 42S and the drain sacrificial material layer 42D are removed. In one embodiment, the source sacrificial material layer 42S and the drain sacrificial material layer 42D may include silicon nitride; the inter-transistor level sacrificial material layer 142 may include a material such as a dielectric metal oxide (e.g., aluminum oxide), a silicon-germanium alloy having a germanium atomic concentration greater than 20%, a polymer material, or a metal material different from the metal material of the metal source layer and the metal drain layer that will be used to subsequently replace the source sacrificial material layer 42S and the drain sacrificial material layer 42D; and the material of the channel-level insulating layer 32 and the backward stepped dielectric material portion 65 may include silicon oxide.

[0121] The etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced in a vapor phase into the backside trench 79. For example, if the source sacrificial material layer 42S and the drain sacrificial material layer 42D include silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials.

[0122] refer to Fig.17 , at least one metal material may be deposited in the source-level backside groove 43S and the drain-level backside groove 43D. The at least one metal material may include a metal nitride material (such as TaN, TiN or WN) forming a metal liner and a metal filling material (such as W, Co, Ru or Mo) filling the remaining space of the source-level backside groove 43S and the drain-level backside groove 43D that is not filled by the metal liner. The at least one metal material fills all the spaces of the source-level backside groove 43S and the drain-level backside groove 43D. The portion of the at least one metal material deposited on the outer edge portion of the backside trench 79 or above the topmost insulating layer 32T may be removed by an etching process, and the etching process may include an isotropic etching process and / or an anisotropic etching process. The remaining portion of the at least one metal material filling the source-level backside groove 43S constitutes the metal source layer 22. The remaining portion of the at least one metal material filling the drain-level backside groove 43D constitutes the metal drain layer 28. Each adjacent combination of the doped semiconductor source layer 24 and the metal source layer 22 constitutes a source layer (22, 24), which is used as a source region and source line of a corresponding two-dimensional array of vertical field effect transistors. Each adjacent combination of the doped semiconductor drain layer 26 and the metal drain layer 28 constitutes a drain layer (26, 28), which is used as a drain region and bit line of a corresponding two-dimensional array of vertical field effect transistors.

[0123] The source sacrificial material layer 42S and the drain-level sacrificial material layer 42D are optional elements that can be omitted. In the presence of the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D, the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D are replaced by the metal source layer 22 and the metal drain layer 28, respectively. In this case, each of the source layers (22, 24) includes a vertical stack of a doped semiconductor source layer 24 and a metal source layer 22, and each of the drain layers (26, 28) includes a vertical stack of a doped semiconductor drain layer 26 and a metal drain layer 28. In the case of omitting the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D, each of the source layers consists of a doped semiconductor source layer 24 or a doped semiconductor drain layer 26.

[0124] refer to Fig.18, the inter-transistor backside recess 143 may be formed by selectively removing the inter-transistor level sacrificial material layer 142 relative to the materials of the doped semiconductor source layer 24, the doped semiconductor drain layer 26, the channel-level insulating layer 32C, the metal source layer 22, and the metal drain layer 28. In one embodiment, the inter-transistor level sacrificial material layer 142 may include a material such as a dielectric metal oxide (e.g., aluminum oxide), a silicon-germanium alloy having a germanium atomic concentration greater than 20%, a polymer material, or a metal material different from the metal material of the metal source layer 22 and the metal drain layer 28, and the channel-level insulating layer 32C may include silicon oxide.

[0125] refer to Fig.19 , an isotropic etching process may be performed to remove the physically exposed portion of the continuous semiconductor channel layer 60L exposed in the inter-transistor backside recess 143. The removal of the physically exposed portion of the continuous semiconductor channel layer 60L may be selective to the material of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26. For example, the continuous semiconductor channel layer 60L may include amorphous silicon including an atomic concentration of 1.0×10 14 / cm 3 Up to 3.0×10 17 / cm 3 The dopant of the second conductivity type (e.g., p-type) is within a range of 5.0×10 19 / cm 3 Up to 2.0×10 21 / cm 3 In this case, the isotropic etching process for etching the physically exposed portion of the continuous semiconductor channel layer 60L may employ a wet etching process employing thermal trimethyl-2-hydroxyethylammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH). Alternatively, the physically exposed surface portions of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26 may be etched in parallel during the removal of the physically exposed portion of the continuous semiconductor channel layer 60L.

[0126] The portion of each continuous semiconductor channel layer 60L that is physically exposed to the inter-transistor stage backside recess 143 may be removed by an isotropic etching process. Thus, the isotropic etching process may separate each continuous semiconductor channel layer 60L into a group of discrete semiconductor channels 60 that are vertically spaced apart from each other. In other words, the remaining portion of each continuous semiconductor channel layer 60L includes a group of discrete semiconductor channels 60 that are not in direct contact with each other. Each of these discrete semiconductor channels 60 is in contact with a cylindrical vertical surface of a corresponding one of the source layers (22, 24) and a cylindrical vertical surface of a corresponding one of the drain layers (26, 28).

[0127] refer to Fig. 20 , a dielectric material may be deposited in the inter-transistor backside recess 143 by a conformal deposition process. Portions of the dielectric material filling the inter-transistor level backside recess 143 constitute alternative insulating layers, which are referred to herein as inter-transistor level insulating layers 176. Portions of the dielectric material filling the backside trench 79 constitute backside trench filling structures 76. Portions of the dielectric filling material covering the topmost insulating layer 32T constitute a contact-level dielectric layer 80. The dielectric materials of the inter-transistor level insulating layer 176, the backside trench filling structures 76, and the contact-level dielectric layer 80 may have the same material composition as a whole, and may include doped silicate glass, undoped silicate glass, or organic silicate glass.

[0128] The insulating layer (32C, 176) is disposed between each vertically adjacent pair of source layers (22, 24) and drain layers (26, 28). In one embodiment, the insulating layer (32C, 176) may have the same dielectric material composition throughout, which may be a composition of doped silicate glass, undoped silicate glass, or organic silicate glass. In another embodiment, the channel-level insulating layer 32C may have a composition different from that of the inter-transistor insulating layer 176. For example, the channel-level insulating layer 32C in contact with the sidewall of a corresponding one of the semiconductor channels 60 may have a first dielectric material composition, and the inter-transistor insulating layer 176 not in contact with the sidewall of the semiconductor channel 60 may have a second dielectric material composition different from the first dielectric material composition. In one embodiment, each semiconductor channel 60 is in contact with a cylindrical sidewall of a corresponding channel-level insulating layer 32C located between a corresponding vertically adjacent pair of source layers (22, 24) and drain layers (26, 28).

[0129] refer to Fig.21 , executable Fig.9AThe processing steps are to form contact via structures (88, 86) through the contact-level dielectric layer 80 and optionally through the rear stepped dielectric material portion 65. The contact via structures (88, 86) include word line contact via structures 88, each of which contacts a corresponding one of the contact pad structures 68 and is electrically connected to a corresponding gate electrode 66. In addition, the contact via structures (88, 86) include layer contact via structures 86 (e.g., 86S, 86D) that contact a corresponding one of the source layers (22, 24) and the drain layers (26, 28) within the corresponding stepped regions (200A, 200B). Specifically, each of these layer contact via structures (86S, 86D) can contact a horizontal surface of a corresponding one of the source layers (22, 24) or a corresponding one of the drain layers (26, 28) exposed in the stepped surface in the stepped region (200A, 200B). Then, a word line 98 is formed over the contact-level dielectric layer 80 (as well as over the gate electrode 66, the source layers (22, 24), and the drain layers (26, 28)), and is electrically contacted with the gate electrode 66 through the contact via structure 88 and the optional contact pad structure 68.

[0130] With reference to all the drawings of the first exemplary structure and the second exemplary structure of the first embodiment and the second embodiment, a three-dimensional memory device is provided, which includes: an alternating stack of source layers (24 and optionally 22) and drain layers (26 and optionally 28) located above a substrate 9; a gate electrode 66 vertically extending through each of the alternating stacks of source layers (24 and optionally 22) and drain layers (26 and optionally 28); a memory film 54 that each laterally surrounds a corresponding one of these gate electrodes 66; and a semiconductor channel (60 or a portion of layer 60L), each semiconductor channel laterally surrounding a corresponding one of these memory films 54 and contacting the sidewalls of a source layer (24 and optionally 22) in a pair of these source layers (24 and optionally 22) and a drain layer (26 and optionally 28) in a pair of these drain layers (26 and optionally 28) that are respectively vertically adjacent.

[0131] In one embodiment, word lines 98 are located above gate electrodes 66 and above the alternating stacks of source and drain layers, where the word lines are electrically connected to the gate electrodes. An array of memory openings 49, such as cylindrical memory openings, may extend vertically through the alternating stacks, and each of gate electrodes 66 is located within a corresponding one of memory openings 49. Each of the semiconductor channels may have a hollow cylindrical shape.

[0132] Each gate electrode 66 may extend through an alternating stack of at least four source layers ( 24 and optionally 22 ) and at least four drain layers ( 26 and optionally 28 ) located above the substrate 9 .

[0133] The insulating layer {(32C, 32I) or (32C, 176)} may be located between each vertically adjacent pair of first source layers (24 and optionally 22) and drain layers (26 and optionally 28). In one embodiment, the insulating layer {(32C, 32I) or (32C, 176)} has the same dielectric material composition as a whole. In another embodiment, the insulating layer {(32C, 32I) or (32C, 176)} includes a channel-level insulating layer 32C and an inter-transistor insulating layer 176, which are in contact with a corresponding one of the semiconductor channels (60 or portions of layer 60L) and have a first dielectric material composition, and the inter-transistor insulating layers are not in contact with any of the semiconductor channels (60 or portions of layer 60L) and have a second dielectric material composition different from the first dielectric material composition.

[0134] In one embodiment, the semiconductor channel includes respective portions of a continuous semiconductor channel layer 60L extending through each source layer ( 24 and optionally 22 ) and each drain layer ( 26 and optionally 28 ) within the alternating stack.

[0135] In another embodiment, each of the semiconductor channels comprises one channel 60 of a set of discrete semiconductor channels 60 that are vertically spaced apart from one another. In one embodiment, each of the discrete semiconductor channels 60 comprises an annular top surface that contacts a corresponding overlying inter-transistor insulating layer 176 and an annular bottom surface that contacts a corresponding underlying inter-transistor insulating layer 176.

[0136] In one embodiment, each of the semiconductor channels (parts of 60 or 60L) contacts a cylindrical sidewall of a corresponding channel-level insulating layer 32C located between a corresponding vertically adjacent pair of source layers (24 and optionally 22) and drain layers (26 and optionally 28).

[0137] In one embodiment, each of the source layers ( 24 , 22 ) includes a vertical stack of a doped semiconductor source layer 24 and a metal source line 22 ; and each of the drain layers ( 26 , 28 ) includes a vertical stack of a doped semiconductor drain layer 26 and a metal drain line 28 .

[0138] In one embodiment, each of the memory films 54 includes a nested layer stack including: a tunneling dielectric layer 542; a charge storage layer 544 in contact with the tunneling dielectric layer 542; and a blocking dielectric layer 546 in contact with the charge storage layer 544. In another embodiment, each of the memory films 54 includes and / or consists of a ferroelectric material layer.

[0139] In one embodiment, the three-dimensional memory device includes: a source layer contact via structure 86S and a drain layer contact via structure 86D, wherein the source layer contact via structures are in contact with a corresponding one of the source layers (24 and optionally 22), and the drain layer contact via structures are in contact with a corresponding one of the drain layers (26 and optionally 28).

[0140] In one embodiment, the source layers (24 and optionally 22) in the alternating stack have different lateral extents that decrease with the vertical distance from the substrate 9; the drain layers (26 and optionally 28) in the alternating stack have different lateral extents that decrease with the vertical distance from the substrate 9; the first backward stepped dielectric material portion 65 contacts the horizontal surface of the source layer (24 and optionally 22) in the alternating stack and laterally surrounds the source layer contact via structure 86S; and the second backward stepped dielectric material portion 65 contacts the horizontal surface of the drain layer (26 and optionally 28) in the alternating stack and laterally surrounds the drain layer contact via structure 86D.

[0141] In one embodiment, gate electrodes 66 are vertically spaced apart from substrate 9 by horizontal portions of memory film 54 ; each of gate electrodes 66 laterally surrounds a corresponding dielectric core 62 ; and contact pad structure 68 contacts a top end of a corresponding one of gate electrodes 66 .

[0142] refer to Fig. 22 The channel-level insulating layer 32C can be replaced by a channel-level insulating layer 132 having a material composition different from that of the inter-transistor-level insulating layer 32I. Figure 1 The first exemplary structure of the third exemplary structure according to the third embodiment of the present disclosure is obtained. Therefore, each instance of the unit layer stack within the multiple instances of the unit layer stack includes a source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel-level insulating layer 132, a doped semiconductor drain layer 26, a drain sacrificial material layer 42D, and a transistor-level insulating layer 32I. In an alternative configuration, one or both of the source sacrificial material layer 42S and / or the drain sacrificial material layer 42D may be omitted.

[0143] The channel-level insulating layer 132 includes a first insulating material, and the inter-transistor insulating layer 32I includes a second insulating material that can provide a smaller etching rate in an isotropic etching process. For example, the channel-level insulating layer 132 may include borosilicate glass or organic silicate glass, and the inter-transistor insulating layer 32I may include undoped silicate glass. In this case, the etching rate of the material of the channel-level insulating layer 132 in 100:1 diluted hydrofluoric acid may be at least 10 times, such as 100 times or more, the etching rate of the material of the inter-transistor insulating layer 32I in 100:1 diluted hydrofluoric acid. Each channel-level insulating layer 132 may have a thickness in the range of 5nm to 50nm, but smaller and larger thicknesses may also be used. Alternatively, the channel-level insulating layer 132 may include aluminum oxide, and if aluminum oxide selective etching is to be used, the inter-transistor insulating layer 32I may include undoped silicate glass (i.e., silicon oxide).

[0144] Multiple examples of unit layer stacking include alternating stacking of doped semiconductor source layers 24 and doped semiconductor drain layers 26. Channel-level insulating layers 132 are formed at the level of semiconductor channels to be formed later. For example, channel-level insulating layers 132 may be formed between each vertically adjacent pair of lower doped semiconductor source layers 24 and overlying doped semiconductor drain layers 26. Inter-transistor level insulating layers 32I may be disposed at the level of gaps between transistors to be formed later. For example, inter-transistor level insulating layers 32I may be formed between vertically adjacent pairs of overlying doped semiconductor source layers 24 and lower doped semiconductor drain layers 26. Therefore, insulating layers (131, 32I) are formed between each vertically adjacent pair of doped semiconductor source layers 24 and doped semiconductor drain layers 26.

[0145] refer to Fig.23 , executable Figure 2 The processing steps are performed to form a stepped cavity 69 in the stepped region (200A, 200B). A stepped surface is formed in the stepped region (200A, 200B). The steps of the anisotropic etching process for forming the stepped surface can be modified to provide an etching chemistry that effectively etches the channel-level insulating layer 132.

[0146] refer to Fig.24A and Fig. 24B , executable Figure 3A and Figure 3BThe processing steps of the memory opening 49 are formed through each layer of the multiple instances of the cell layer stack. As discussed above, the cell layer stack of the second exemplary structure may include a source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel-level insulating layer 132, a doped semiconductor drain layer 26, a drain sacrificial material layer 42D, and an inter-transistor level insulating layer 32I. The steps of the anisotropic etching process for forming the memory opening 49 may be modified to provide an etching chemistry that effectively etches the channel-level insulating layer 132.

[0147] refer to Fig.25 , a lateral annular cavity 349 can be formed at each level of the channel-level insulating layer 132 by laterally recessing the channel-level insulating layer 132 relative to the inter-transistor insulating layer 32I, the doped semiconductor source layer 24, the doped semiconductor drain layer 26, the source sacrificial material layer 42S, and the drain sacrificial material layer 42D. As discussed above, in an isotropic etching process, the first insulating material of the channel-level insulating layer 132 provides a greater etching rate than the second insulating material of the inter-transistor insulating layer 32I. In one embodiment, the first insulating material of the channel-level insulating layer 132 may include borosilicate glass or organosilicate glass, and the second insulating material of the inter-transistor insulating layer 32I may include undoped silicate glass. In this case, the etching rate of the first insulating material of the channel-level insulating layer 132 in 100:1 diluted hydrofluoric acid may be at least 10 times, such as 100 times or more, the etching rate of the second insulating material of the inter-transistor insulating layer 32I in 100:1 diluted hydrofluoric acid. The isotropic etching process may be a wet etching process using 100: 1 diluted hydrofluoric acid. The lateral recess distance of each of the annular cavities 349 may be in the range of 5 nm to 100 nm, such as 10 nm to 50 nm, although smaller and larger lateral recess distances may also be used.

[0148] refer to Fig.26 , a semiconductor material may be deposited in the annular cavity 349 by a conformal deposition process such as a chemical vapor deposition process. The semiconductor material deposited in the annular cavity 349 may have the same material composition as the continuous semiconductor channel layer 60L used in the first exemplary structure. Portions of the conformally deposited semiconductor material may be removed from the outside of the annular cavity 349 by performing an anisotropic etching process. The remaining portions of the conformally deposited semiconductor material in the annular cavity 349 constitute a vertical stack of semiconductor channels 360. Each vertical stack of semiconductor channels 360 is formed as a group of discrete semiconductor channels located in the annular cavity 349 and vertically spaced apart from each other (i.e., not in direct contact with each other). Each semiconductor channel 360 may have an annular shape (e.g., a hollow disk shape). For example, each semiconductor channel 360 may have an inner cylindrical sidewall, an outer cylindrical sidewall, a top annular surface, and a bottom annular surface.

[0149] Each of these discrete semiconductor channels 360 is in contact with the cylindrical sidewall of a corresponding one of the channel-level insulating layers 132. The insulating layers (132, 32I) in multiple instances of the unit layer stack include a channel-level insulating layer 132 in contact with the sidewall of a corresponding one of the semiconductor channels 360 and an inter-transistor-level insulating layer 32I that does not contact any of the semiconductor channels 360. The sidewalls of the channel-level insulating layer 132 are laterally recessed outward relative to the sidewalls of the inter-transistor-level insulating layer 32I and relative to the sidewalls of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26 around each memory opening 49. Each of the channel-level insulating layers 132 may be in direct contact with the horizontal surface of a corresponding one of the doped semiconductor source layers 24 and the doped semiconductor drain layer 26.

[0150] Before forming the memory film and the gate electrode, each of the semiconductor channels 360 is formed on the horizontal surface of a corresponding vertically adjacent pair of doped semiconductor source layers 24 and doped semiconductor drain layers 26. A vertical stack of semiconductor channels 360 is formed in each of the memory openings 49. Each of these semiconductor channels 360 is connected to a corresponding vertically adjacent pair of doped semiconductor source layers 24 and doped semiconductor drain layers 26.

[0151] In one embodiment, the entire outer sidewall of each semiconductor channel 360 contacts the cylindrical sidewall of the corresponding channel-level insulating layer 132 located between the corresponding vertically adjacent pair of doped semiconductor source layers 24 and doped semiconductor drain layers 26. In one embodiment, the outer sidewall includes an upper outer edge in contact with the horizontal surface of one of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26 in the corresponding vertically adjacent pair, and includes a lower outer edge in contact with the horizontal surface of the other of the doped semiconductor source layer 24 and the doped semiconductor drain layer 26 in the corresponding vertically adjacent pair.

[0152] refer to Fig. 27 , continuous material layers may be sequentially deposited in each of the memory openings 49. These continuous material layers may include a continuous memory film, a continuous conductive material layer, and an optional dielectric filling material layer. Excess portions of the continuous material layers may be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T and the top surface of the rear stepped dielectric material portion by a planarization process. The planarization process may employ chemical mechanical planarization and / or at least one recess etching process. Each portion of the continuous material layer remaining in the memory opening 49 constitutes a memory opening filling structure 58.

[0153] Each memory opening filling structure 58 includes a memory film 54, a gate electrode 66, and an optional dielectric core 62. Each memory film 54 is the remaining portion of a continuous memory film after a planarization process. Each gate electrode 66 is the remaining portion of a continuous conductive material layer after a planarization process. Each dielectric core 62 is the remaining portion of a dielectric filling material layer. Each vertical stack of semiconductor channels 360 laterally surrounds a corresponding memory film 54 and a corresponding gate electrode 66.

[0154] The memory film 54 includes at least one material layer that can store data bits in the form of trapped charge, polarization or magnetism. In one embodiment, each of the memory films includes a layer stack that includes, from the outside to the inside, a tunneling dielectric layer 542, a charge storage layer 544 in contact with the tunneling dielectric layer 542, and a blocking dielectric layer 546 in contact with the charge storage layer 544. The tunneling dielectric layer 542 may include a tunneling dielectric material, such as silicon oxide or an ONO stack (i.e., a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer). The charge storage layer 544 may include a charge storage material, such as silicon nitride. The blocking dielectric layer 546 may include a blocking dielectric material, such as silicon oxide and / or a dielectric metal oxide. In another embodiment, each of the memory films 54 includes a ferroelectric material layer (not shown) and at least one optional dielectric material layer (such as a silicon oxide layer) that can contact the semiconductor channel 360 or the gate electrode 66.

[0155] Each gate electrode 66 includes a conductive material, such as a metal material. For example, each gate electrode 66 may include a layer stack including a metal nitride liner including a conductive metal nitride (such as TiN, TaN or WN) and a metal layer including a metal (such as W, Co, Mo, Ru, Cu or alloys thereof).

[0156] Each dielectric core 62 includes a dielectric filler material, such as silicon oxide. In one embodiment, the dielectric core 62 may include a dielectric material having a higher etching rate in an etching process than the topmost insulating layer 32T. For example, the dielectric core 62 may include borosilicate glass, organosilicate glass, or phosphosilicate glass, and the topmost insulating layer 32T may include dense undoped silicate glass. In this case, the material of the dielectric core 62 may then be recessed relative to the material of the topmost insulating layer 32T.

[0157] A memory film 54 is formed on each of the vertical stacks of the semiconductor channels 360, and a gate electrode 66 is formed on each of the memory films 54. Each of the memory films 54 vertically extends through each of the doped semiconductor source layers 24 and the doped semiconductor drain layers 26 in the alternating stacks of the doped semiconductor source layers 24 and the doped semiconductor drain layers 26. Each of the gate electrodes 66 vertically extends through each of the alternating stacks of the doped semiconductor source layers 24 and the doped semiconductor drain layers 26. Each gate electrode 66 extends through each of the doped semiconductor source layers 24 and each of the doped semiconductor drain layers 26 in the alternating stacks of the doped semiconductor source layers 24 and the doped semiconductor drain layers 26.

[0158] Each memory film 54 includes a cylindrical portion and a bottom cap portion adjacent to the bottom outer edge of the cylindrical portion. Each gate electrode 66 may include a cylindrical portion and a bottom cap portion adjacent to the bottom outer edge of the cylindrical portion. The gate electrodes 66 may be vertically spaced apart from the substrate 9 by the horizontal portion of the memory film 54. Each of the gate electrodes 66 may laterally surround a corresponding dielectric core 62.

[0159] refer to Fig.28 , executable Figure 5 The processing steps are as follows to form the contact pad structure 68. Each memory opening filling structure 58 may include a corresponding contact pad structure 68 that contacts a top end of a corresponding one of the gate electrodes 66.

[0160] refer to Fig.29A and Fig.29B , executable Fig. 6A and Figure 6B The processing steps of the anisotropic etching process for forming the backside trenches 79 can be modified to provide an etching chemistry that effectively etches the channel-level insulating layer 132.

[0161] refer to Fig.30, an etchant that selectively etches the material of the source sacrificial material layer 42S and the drain sacrificial material layer 42D relative to the material of the insulating layer (132, 32I), the doped semiconductor source layer 24, the doped semiconductor drain layer 26, the backward stepped dielectric material portion 65, and the semiconductor channel 360 may be introduced into the backside trench 79, for example, by an etching process. The source-level backside recess 43S and the drain-level backside recess 43D are formed in the space from which the source sacrificial material layer 42S and the drain sacrificial material layer 42D are removed, respectively. In one embodiment, the source sacrificial material layer 42S and the drain sacrificial material layer 42D may include silicon nitride, and the material of the channel-level insulating layer 132, the inter-transistor-level insulating layer 32I, and the backward stepped dielectric material portion 65 may include a silicate glass material, such as undoped silicate glass, doped silicate glass, and / or organic silicate glass.

[0162] The etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced in a vapor phase into the backside trench 79. For example, if the source sacrificial material layer 42S and the drain sacrificial material layer 42D include silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials used in the art.

[0163] refer to Fig.31 , at least one metal material may be deposited in the source-level backside groove 43S and the drain-level backside groove 43D. The at least one metal material may include a metal nitride material (such as TaN, TiN or WN) forming a metal liner and a metal filling material (such as W, Co, Ru or Mo) filling the remaining space of the source-level backside groove 43S and the drain-level backside groove 43D that is not filled by the metal liner. The at least one metal material fills all the spaces of the source-level backside groove 43S and the drain-level backside groove 43D. The portion of the at least one metal material deposited on the outer edge portion of the backside trench 79 or above the topmost insulating layer 32T may be removed by an etching process, and the etching process may include an isotropic etching process and / or an anisotropic etching process. The remaining portion of the at least one metal material filling the source-level backside groove 43S constitutes the metal source layer 22. The remaining portion of the at least one metal material filling the drain-level backside groove 43D constitutes the metal drain layer 28. Each adjacent combination of the doped semiconductor source layer 24 and the metal source layer 22 constitutes a source layer (22, 24), which is used as a source region and source line of a corresponding two-dimensional array of vertical field effect transistors. Each adjacent combination of the doped semiconductor drain layer 26 and the metal drain layer 28 constitutes a drain layer (26, 28), which is used as a drain region and bit line of a corresponding two-dimensional array of vertical field effect transistors.

[0164] The source sacrificial material layer 42S and the drain-level sacrificial material layer 42D are optional elements that can be omitted. In the presence of the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D, the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D are replaced by the metal source layer 22 and the metal drain layer 28, respectively. In this case, each of the source layers (22, 24) includes a vertical stack of a doped semiconductor source layer 24 and a metal source layer 22, and each of the drain layers (26, 28) includes a vertical stack of a doped semiconductor drain layer 26 and a metal drain layer 28. In the case of omitting the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D, each of the source layers consists of a doped semiconductor source layer 24 or a doped semiconductor drain layer 26.

[0165] Dielectric material may be deposited in backside trenches 79 and over topmost insulating layer 32T. The portion of the dielectric material filling backside trenches 79 constitutes backside trench fill structure 76. The portion of the dielectric fill material overlying topmost insulating layer 32T constitutes contact-level dielectric layer 80.

[0166] refer to Fig.32 , executable Fig.9A The processing steps are to form contact via structures (88, 86) through the contact-level dielectric layer 80 and optionally through the rear stepped dielectric material portion 65. The contact via structures (88, 86) include word line contact via structures 88, each of which contacts a corresponding one of the contact pad structures 68 and is electrically connected to a corresponding gate electrode 66. In addition, the contact via structures (88, 86) include layer contact via structures 86 (e.g., 86S, 86D) that contact a corresponding one of the source layers (22, 24) and the drain layers (26, 28) within the corresponding stepped regions (200A, 200B). Specifically, each of these layer contact via structures (86S, 86D) can contact a horizontal surface of a corresponding one of the source layers (22, 24) or a corresponding one of the drain layers (26, 28) exposed in the stepped surface in the stepped region (200A, 200B). Then, a word line 98 is formed over the contact-level dielectric layer 80 (as well as over the gate electrode 66, the source layers (22, 24), and the drain layers (26, 28)), and is electrically contacted with the gate electrode 66 through the contact via structure 88 and the optional contact pad structure 68.

[0167] refer to Fig.33 , the channel-level insulating layer 32C can be replaced by the channel-level sacrificial material layer 232. Figure 1The first exemplary structure of the fourth exemplary structure according to the fourth embodiment of the present disclosure is obtained. Therefore, each instance of the unit layer stack within the multiple instances of the unit layer stack includes a source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel-level sacrificial material layer 232, a doped semiconductor drain layer 26, a drain sacrificial material layer 42D and a transistor-level insulating layer 32I.

[0168] The channel-level sacrificial material layer 232 includes a material that can be selectively removed relative to the material of the doped semiconductor source layer 24, the doped semiconductor drain layer 26, and the inter-transistor insulating layer 32I, and includes a material that can be selectively removed relative to the metal material of the metal source layer and the metal drain layer that will be used to replace the source sacrificial material layer 42S and the drain sacrificial material layer 42D later. For example, the channel-level sacrificial material layer 232 may include a material such as a dielectric metal oxide (e.g., aluminum oxide), a silicon-germanium alloy with a germanium atomic concentration greater than 20%, a polymer material, or a metal material different from the metal source layer and the metal drain layer that will be used to replace the source sacrificial material layer 42S and the drain sacrificial material layer 42D later. Each channel-level sacrificial material layer 232 may have a thickness in the range of 5nm to 50nm, but smaller and larger thicknesses may also be used.

[0169] Multiple examples of unit layer stacking include alternating stacking of doped semiconductor source layers 24 and doped semiconductor drain layers 26. Channel-level sacrificial material layers 232 are formed at the level of the semiconductor channel to be formed later. For example, channel-level sacrificial material layers 232 may be formed between each vertically adjacent pair of lower doped semiconductor source layers 24 and overlying doped semiconductor drain layers 26. Inter-transistor level insulating layers 32I may be disposed at the level of the gaps between transistors to be formed later. For example, inter-transistor level insulating layers 32I may be formed between vertically adjacent pairs of overlying doped semiconductor source layers 24 and lower doped semiconductor drain layers 26.

[0170] refer to Fig.34 , executable Figure 2 The processing steps are performed to form a stepped cavity 69 in the stepped region (200A, 200B). A stepped surface is formed in the stepped region (200A, 200B). The steps of the anisotropic etching process for forming the stepped surface can be modified to provide an etching chemistry that effectively etches the channel level sacrificial material layer 232.

[0171] refer to Fig.35A and Fig.35B , executable Figure 3A and Figure 3BThe processing steps of the memory opening 49 are formed through each layer of the multiple instances of the cell layer stack. As discussed above, the cell layer stack of the second exemplary structure may include a source sacrificial material layer 42S, a doped semiconductor source layer 24, a channel-level sacrificial material layer 232, a doped semiconductor drain layer 26, a drain sacrificial material layer 42D, and an inter-transistor level insulating layer 32I. The steps of the anisotropic etching process for forming the memory opening 49 may be modified to provide an etching chemistry that effectively etches the channel-level sacrificial material layer 232.

[0172] refer to Fig.36 , continuous material layers may be sequentially deposited in each of the memory openings 49. These continuous material layers may include a continuous memory film, a continuous conductive material layer, and an optional dielectric filling material layer. Excess portions of the continuous material layers may be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T and the top surface of the rear stepped dielectric material portion by a planarization process. The planarization process may employ chemical mechanical planarization and / or at least one recess etching process. Each portion of the continuous material layer remaining in the memory opening 49 constitutes a memory opening filling structure 58.

[0173] Each memory opening filling structure 58 includes a memory film 54, a gate electrode 66, and an optional dielectric core 62. Each memory film 54 is the remaining portion of a continuous memory film after a planarization process. Each gate electrode 66 is the remaining portion of a continuous conductive material layer after a planarization process. Each dielectric core 62 is the remaining portion of a dielectric filling material layer.

[0174] The memory film 54 includes at least one material layer that can store data bits in the form of trapped charge, polarization or magnetism. In one embodiment, each of the memory films includes a layer stack that includes, from the outside to the inside, a tunneling dielectric layer 542, a charge storage layer 544 in contact with the tunneling dielectric layer 542, and a blocking dielectric layer 546 in contact with the charge storage layer 544. The tunneling dielectric layer 542 may include a tunneling dielectric material, such as a silicon oxide layer or an ONO stack (i.e., a stack of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer). The charge storage layer 544 may include a charge storage material, such as silicon nitride. The blocking dielectric layer 546 may include a blocking dielectric material, such as silicon oxide and / or a dielectric metal oxide. In another embodiment, each of the memory films 54 includes a ferroelectric material layer (not shown) and at least one optional dielectric material layer (such as a silicon oxide layer) that can contact the channel-level sacrificial material layer 232 or the gate electrode 66.

[0175] Each gate electrode 66 includes a conductive material, such as a metal material. For example, each gate electrode 66 may include a layer stack including a metal nitride liner including a conductive metal nitride (such as TiN, TaN or WN) and a metal layer including a metal (such as W, Co, Mo, Ru, Cu or alloys thereof).

[0176] Each dielectric core 62 includes a dielectric filler material, such as silicon oxide. In one embodiment, the dielectric core 62 may include a dielectric material having a higher etching rate in an etching process than the topmost insulating layer 32T. For example, the dielectric core 62 may include borosilicate glass, organosilicate glass, or phosphosilicate glass, and the topmost insulating layer 32T may include dense undoped silicate glass. In this case, the material of the dielectric core 62 may then be recessed relative to the material of the topmost insulating layer 32T.

[0177] The memory film 54 may be formed on the sidewall of each layer of the plurality of repetitions of the unit layer stack, and the gate electrode 66 may be formed on each of the memory films 54. Each of the memory films 54 vertically extends through each of the doped semiconductor source layers 24 and the doped semiconductor drain layers 26 in the alternating stack of the doped semiconductor source layers 24 and the doped semiconductor drain layers 26. Each of the gate electrodes 66 vertically extends through each of the doped semiconductor source layers 24 and the doped semiconductor drain layers 26 in the alternating stack.

[0178] Each memory film 54 includes a cylindrical portion and a bottom cap portion adjacent to the bottom outer edge of the cylindrical portion. Each gate electrode 66 may include a cylindrical portion and a bottom cap portion adjacent to the bottom outer edge of the cylindrical portion. The gate electrodes 66 may be vertically spaced apart from the substrate 9 by the horizontal portion of the memory film 54. Each of the gate electrodes 66 may laterally surround a corresponding dielectric core 62.

[0179] refer to Fig.37 , executable Figure 5 The processing steps are as follows to form the contact pad structure 68. Each memory opening filling structure 58 may include a corresponding contact pad structure 68 that contacts a top end of a corresponding one of the gate electrodes 66.

[0180] refer to Fig.38A and Fig.38B , executable Fig. 6A and Figure 6B The processing steps of the anisotropic etching process for forming the backside trenches 79 can be modified to provide an etch chemistry that effectively etches the channel level sacrificial material layer 232.

[0181] refer to Fig.39, an etchant that selectively etches the material of the source sacrificial material layer 42S and the drain sacrificial material layer 42D relative to the material of the channel-level sacrificial material layer 232, the inter-transistor-level insulating layer 32I, the doped semiconductor source layer 24, the doped semiconductor drain layer 26, and the backward stepped dielectric material portion 65 may be introduced into the backside trench 79, for example, by an etching process. The source-level backside recess 43S and the drain-level backside recess 43D are respectively formed in the space from which the source sacrificial material layer 42S and the drain sacrificial material layer 42D are removed. In one embodiment, the source sacrificial material layer 42S and the drain sacrificial material layer 42D may include silicon nitride, the material of the transistor inter-level insulating layer 32I and the backward stepped dielectric material portion 65 may include a silicate glass material, such as undoped silicate glass, doped silicate glass and / or organic silicate glass; and the material of the channel-level sacrificial material layer 232 may include a dielectric metal oxide (e.g., aluminum oxide), a silicon-germanium alloy with a germanium atomic concentration greater than 20%, a polymer material, or a metal material different from the metal material of the metal source layer and the metal drain layer that will be used to subsequently replace the source sacrificial material layer 42S and the drain sacrificial material layer 42D.

[0182] The etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced in a vapor phase into the backside trench 79. For example, if the source sacrificial material layer 42S and the drain sacrificial material layer 42D include silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride relative to silicon oxide, silicon, and various other materials used in the art.

[0183] refer to Fig.40, at least one metal material may be deposited in the source-level backside groove 43S and the drain-level backside groove 43D. The at least one metal material may include a metal nitride material (such as TaN, TiN or WN) forming a metal liner and a metal filling material (such as W, Co, Ru or Mo) filling the remaining space of the source-level backside groove 43S and the drain-level backside groove 43D that is not filled by the metal liner. The at least one metal material fills all the spaces of the source-level backside groove 43S and the drain-level backside groove 43D. The portion of the at least one metal material deposited on the outer edge portion of the backside trench 79 or above the topmost insulating layer 32T may be removed by an etching process, and the etching process may include an isotropic etching process and / or an anisotropic etching process. The remaining portion of the at least one metal material filling the source-level backside groove 43S constitutes the metal source layer 22. The remaining portion of the at least one metal material filling the drain-level backside groove 43D constitutes the metal drain layer 28. Each adjacent combination of the doped semiconductor source layer 24 and the metal source layer 22 constitutes a source layer (22, 24), which is used as a source region and source line of a corresponding two-dimensional array of vertical field effect transistors. Each adjacent combination of the doped semiconductor drain layer 26 and the metal drain layer 28 constitutes a drain layer (26, 28), which is used as a drain region and bit line of a corresponding two-dimensional array of vertical field effect transistors.

[0184] The source sacrificial material layer 42S and the drain-level sacrificial material layer 42D are optional elements that can be omitted. In the case where the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D are present, the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D are replaced with the metal source layer 22 and the metal drain layer 28, respectively. In this case, each of the source layers (22, 24) includes a vertical stack of a doped semiconductor source layer 24 and a metal source layer 22, and each of the drain layers (26, 28) includes a vertical stack of a doped semiconductor drain layer 26 and a metal drain layer 28. In the case where the source sacrificial material layer 42S and the drain-level sacrificial material layer 42D are omitted, each of the source layers consists of a doped semiconductor source layer 24 or a doped semiconductor drain layer 26, as will be described below with respect to Figure 45 to Figure 47 If layers 42S and 42D are omitted, channel level sacrificial material layer 232 may include silicon nitride.

[0185] refer to Fig.41, channel-level backside grooves 233 may be formed by selectively removing a channel-level sacrificial material layer 232 relative to the materials of the doped semiconductor source layer 24, the doped semiconductor drain layer 26, the inter-transistor insulating layer 32I, the optional metal source layer 22, and the optional metal drain layer 28, and these channel-level backside grooves are physically exposed to the surface of the substrate 9 (which may be a semiconductor surface). In one embodiment, the channel-level sacrificial material layer 232 may include a material such as a dielectric metal oxide (e.g., aluminum oxide), a silicon-germanium alloy with a germanium atomic concentration greater than 20%, a polymer material, or a metal material different from the metal material of the metal source layer 22 and the metal drain layer 28, and the inter-transistor insulating layer 32I may include silicon oxide. Alternatively, if the metal source layer 22 and the metal drain layer 28 are omitted, the channel-level sacrificial material layer 232 may include silicon nitride and may be selectively removed by phosphoric acid etching.

[0186] refer to Fig.42 , the continuous doped semiconductor material layer may be conformally deposited in the channel level backside recess 233, at the outer edge region of the backside trench 79, and above the top surface of the topmost insulating layer 32T. The continuous doped semiconductor material layer includes a doped semiconductor material having a second conductivity type, which is opposite to the first conductivity type. The semiconductor material in the continuous doped semiconductor material layer may include silicon, a silicon-germanium alloy, or a compound semiconductor material. The atomic concentration of the second conductivity type dopant in the continuous doped semiconductor material layer may be between 1.0×10 14 / cm 3 Up to 3.0×10 17 / cm 3 The thickness of the continuous doped semiconductor material layer may be less than half the minimum height of the channel level backside recess 233 and may be in the range of 1 nm to 20 nm, such as 3 nm to 10 nm, but smaller and larger thicknesses may also be used.

[0187] An anisotropic etching process may be performed to remove portions of the continuous doped semiconductor material layer formed in the backside trench 79 and above the topmost insulating layer 32T. Each remaining portion of the continuous doped semiconductor material layer in the channel-level backside recess 233 constitutes a semiconductor channel material layer 460. The semiconductor channel material layer 460 may be a conformal material layer completely located within a corresponding one of the channel-level backside recesses 233. Each cylindrical portion of the semiconductor channel material layer 460 that laterally surrounds the memory film 54 constitutes a semiconductor channel 60'. Each vertical semiconductor channel 60' is in contact with the bottom surface of an overlying doped semiconductor layer (such as a doped semiconductor drain layer 26) and in contact with the top surface of an underlying doped semiconductor layer (such as a doped semiconductor source layer 24). After forming the memory film 54 and the gate electrode 66, a vertical stack of semiconductor channels 60' is formed on the horizontal surfaces of a corresponding vertically adjacent pair of doped semiconductor source and doped semiconductor drain layers 26. Each vertical stack of semiconductor channels 60 ′ laterally surrounds a corresponding memory film 54 and a corresponding gate electrode 66 .

[0188] refer to Fig.43 , a dielectric material may be deposited in the remaining space of the channel-level backside recess 233 by a conformal deposition process. The portion of the dielectric material filling the channel-level backside recess 233 constitutes a replacement insulating layer, which is referred to herein as a channel-level insulating layer 276. The portion of the dielectric material filling the backside trench 79 constitutes a backside trench filling structure 76. The portion of the dielectric filling material covering the topmost insulating layer 32T constitutes a contact-level dielectric layer 80. The dielectric materials of the channel-level insulating layer 276, the backside trench filling structure 76, and the contact-level dielectric layer 80 may have the same material composition as a whole, and may include doped silicate glass, undoped silicate glass, or organic silicate glass.

[0189] The insulating layer (276, 32I) is disposed between each vertically adjacent pair of source layers (22, 24) and drain layers (26, 28). In one embodiment, the insulating layer (276, 32I) may have the same dielectric material composition as a whole, which may be a composition of doped silicate glass, undoped silicate glass, or organic silicate glass. In another embodiment, the channel-level insulating layer 276 may have a different composition from the inter-transistor insulating layer 32I. For example, the channel-level insulating layer 276 in contact with a corresponding one of the semiconductor channels 60' may have a first dielectric material composition, and the inter-transistor insulating layer 32I not in contact with any of the semiconductor channels 60' may have a second dielectric material composition different from the first dielectric material composition. In one embodiment, each semiconductor channel of the vertical stack of semiconductor channels 60 ′ contacts the cylindrical sidewall of a corresponding channel-level insulating layer 276 located between a corresponding vertically adjacent pair of source ( 22 , 24 ) and drain ( 26 , 28 ) layers.

[0190] refer to Fig.44 , executable Fig.9A The processing steps are to form contact via structures (88, 86) through the contact-level dielectric layer 80 and optionally through the rear stepped dielectric material portion 65. The contact via structures (88, 86) include word line contact via structures 88, each of which contacts a corresponding one of the contact pad structures 68 and is electrically connected to a corresponding gate electrode 66. In addition, the contact via structures (88, 86) include layer contact via structures 86 (e.g., 86S, 86D) that contact a corresponding one of the source layers (22, 24) and the drain layers (26, 28) within the corresponding stepped regions (200A, 200B). Specifically, each of these layer contact via structures (86S, 86D) can contact a horizontal surface of a corresponding one of the source layers (22, 24) or a corresponding one of the drain layers (26, 28) exposed in the stepped surface in the stepped region (200A, 200B). Then, a word line 98 is formed over the contact-level dielectric layer 80 (as well as over the gate electrode 66, the source layers (22, 24), and the drain layers (26, 28)), and is electrically contacted with the gate electrode 66 through the contact via structure 88 and the optional contact pad structure 68.

[0191] refer to Fig.45 , the figure shows a fourth embodiment according to the present disclosure Fig.34 An alternative embodiment of the fourth exemplary structure is formed by omitting the source sacrificial layer 42S and the drain sacrificial layer 42D at the processing steps corresponding to the processing steps of . In this embodiment, the channel level sacrificial material layer 232 may include silicon nitride.

[0192] refer to Fig.46 , the figure shows that Fig.37 An alternative embodiment of the fourth exemplary structure at the processing steps corresponding to the processing steps of .

[0193] refer to Fig.47 , the figure shows that Fig.44 An alternative embodiment of the fourth exemplary structure at a processing step corresponding to the processing step of , wherein the channel-level sacrificial material layers 232 are removed by selective etching (e.g., by phosphoric acid etching) and replaced with vertical semiconductor channels 60'. Optionally, the vertical semiconductor channels 60' and the doped semiconductor source and drain layers 24 and 26 can be recessed by selectively etching the backside trenches 79 using a selective etch that etches the semiconductor material (e.g., silicon) relative to the remaining insulating layers in the stack. Then, metal is formed in the recesses to form conductive source lines 122 and conductive drain lines 128 in contact with the corresponding semiconductor source and drain layers 24 and 26. The metal may include tungsten, nickel, or cobalt. If necessary, a silicidation anneal may be performed to react the metal with the corresponding semiconductor source and drain layers 24 and 26, and to convert all or part of the conductive source and drain lines 122 and 128 into metal silicides, such as tungsten silicide, nickel silicide, or cobalt silicide. The conductive source line 122 and the conductive drain line 128 may be in contact with the semiconductor channel material layer 460 , or may be formed in a form not to be in contact with the semiconductor channel material layer 460 .

[0194] With reference to all the drawings of the third exemplary structure and the fourth exemplary structure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: an alternating stack of source layers (24 and optionally 22) and drain layers (26 and optionally 28) located above a substrate 9; an array of memory openings 49 vertically extending through the alternating stack; gate electrodes 66 each located within a corresponding one of the array of memory openings 49 and vertically extending through each of the alternating stack of source layers (24 and optionally 22) and drain layers (26 and optionally 28); and gate electrodes 66 each located within a corresponding one of the array of memory openings 49 and vertically extending through each of the alternating stack of source layers (24 and optionally 22) and drain layers (26 and optionally 28). 9 and a memory film 54 in a memory opening in the array and laterally surrounding a corresponding one of the gate electrodes 66; and a vertical stack of semiconductor channels (360, 60') laterally surrounding a corresponding one of the memory films 54, wherein each of the vertical semiconductor channels (360, 60') is in contact with a horizontal surface of a corresponding vertically adjacent pair of source layers (24 and optionally 22) and a drain layer (26 and optionally 28) in the drain layers (26 and optionally 28).

[0195] In one embodiment, word line 98 is located over gate electrode 66 and over the alternating stack of source and drain layers, where word line 98 is electrically connected to gate electrode 66 .

[0196] In one embodiment, an insulating layer (132, 270, 32I) is located between each vertically adjacent pair of source (24 and optionally 22) and drain (26 and optionally 28) layers.

[0197] In one embodiment, the insulating layer (132, 270, 32I) includes a channel-level insulating layer (132, 270) contacting a corresponding one of the semiconductor channels (360, 60') and an inter-transistor-level insulating layer 32I not contacting any of the semiconductor channels (360, 60').

[0198] In one embodiment, the sidewalls of the channel-level insulating layer 132 are laterally recessed outward relative to the sidewalls of the inter-transistor-level insulating layer 32I and relative to the sidewalls of the source layer ( 24 and optionally 22 ) and the drain layer ( 26 and optionally 28 ) around each memory opening 49 .

[0199] In one embodiment, each of the channel-level insulating layers 132 is in direct contact with a horizontal surface of a corresponding one of the source layer ( 24 and optionally 22 ) and the drain layer ( 26 and optionally 28 ).

[0200] In one embodiment, each of the channel-level insulating layers 270 is not in contact with the source layer ( 24 and optionally 22 ) and the drain layer ( 26 and optionally 28 ), and is vertically separated from these source and drain layers at least by the corresponding semiconductor channel material layer 460 .

[0201] In one embodiment, each of the vertical stacks of semiconductor channels (360, 60') includes a group of discrete semiconductor channels (360, 60') that are vertically spaced apart from one another and are not in direct contact with one another.

[0202] In one embodiment, the entire outer sidewall of each semiconductor channel (360, 60') contacts the cylindrical sidewall of the corresponding channel-level insulating layer (132, 270) located at the corresponding vertically adjacent pair of source layer (24 and optionally 22) and drain layer (26 and optionally 28).

[0203] In a third embodiment, the outer side wall of each semiconductor channel 360 includes an upper outer edge in contact with a horizontal surface of one of the source layer (24 and optionally 22) and the drain layer (26 and optionally 28) in a corresponding vertically adjacent pair, and includes a lower outer edge in contact with a horizontal surface of the other of the source layer (24 and optionally 22) and the drain layer (26 and optionally 28) in the corresponding vertically adjacent pair.

[0204] In a fourth embodiment, each of the semiconductor channels 60' comprises a hollow cylindrical section of a semiconductor channel material layer 460, the semiconductor channel material layer comprising: an upper semiconductor channel material layer section adjacent to the upper end of the corresponding semiconductor channel 60' and a lower semiconductor channel material layer section adjacent to the lower end of the corresponding semiconductor channel 60'. The upper semiconductor channel material layer section is an upper horizontal portion of the semiconductor channel material layer 460, which contacts an overlying doped semiconductor material layer (such as a doped semiconductor drain layer 26) at a first pn junction. The lower semiconductor channel material layer section is a lower horizontal portion of the semiconductor channel material layer 460, which contacts an underlying doped semiconductor material layer (such as a doped semiconductor source layer 24) at a second pn junction.

[0205] In one embodiment, the semiconductor channel material layer 460 includes a set of semiconductor channels 60 ′ including a hollow cylindrical segment and an additional cylindrical segment laterally surrounding the gate electrode 66 .

[0206] In one embodiment, each of the source layers ( 24 , 22 ) includes a vertical stack of a doped semiconductor source layer 24 and a metal source line 22 ; and each of the drain layers ( 26 , 28 ) includes a vertical stack of a doped semiconductor drain layer 26 and a metal bit line 28 .

[0207] In one embodiment, each of the memory films 54 includes a nested layer stack including: a tunneling dielectric layer 542; a charge storage layer 544 in contact with the tunneling dielectric layer 542; and a blocking dielectric layer 546 in contact with the charge storage layer 544. In another embodiment, each of the memory films 54 includes and / or consists of a ferroelectric material layer.

[0208] In one embodiment, the three-dimensional memory device includes: a source layer contact via structure 86S and a drain layer contact via structure 86D, wherein the source layer contact via structures are in contact with a corresponding one of the source layers (24 and optionally 22), and the drain layer contact via structures are in contact with a corresponding one of the drain layers (26 and optionally 28).

[0209] In one embodiment, the source layers (24 and optionally 22) in the alternating stack have different lateral extents that decrease with the vertical distance from the substrate 9; the drain layers (26 and optionally 28) in the alternating stack have different lateral extents that decrease with the vertical distance from the substrate 9; the first backward stepped dielectric material portion 65 contacts the horizontal surface of the source layer (24 and optionally 22) in the alternating stack and laterally surrounds the source layer contact via structure 86S; and the second backward stepped dielectric material portion 65 contacts the horizontal surface of the drain layer (26 and optionally 28) in the alternating stack and laterally surrounds the drain layer contact via structure 86D.

[0210] In one embodiment, gate electrodes 66 are vertically spaced apart from substrate 9 by horizontal portions of memory film 54 ; each of gate electrodes 66 laterally surrounds a corresponding dielectric core 62 ; and contact pad structure 68 contacts a top end of a corresponding one of gate electrodes 66 .

[0211] refer to Fig.48 , a circuit diagram of various embodiments of the three-dimensional memory device of the present disclosure is shown. Each source layer (24, 22) may be laterally bounded by a corresponding adjacent pair of backside trenches 79 and include source lines (22, 122) ("SL"). The source lines SL are arranged in a three-dimensional array extending in a vertical direction and in a horizontal direction parallel to the longitudinal direction of the backside trenches 79. Therefore, the source lines SL may be numbered with two-dimensional coordinates (i, j), where i refers to the level of the corresponding source line and j refers to the space determined by the corresponding adjacent pair of backside trenches 79. For example, if (n+1) source layers (24, 22) and (n+1) drain layers (26, 28) are present between each adjacent pair of backside trenches 79, at a corresponding distance from the substrate 9, the index i may be in the range of 0 to n. If there are (m+2) backside trenches 79, then (m+1) source layers (24, 22) are provided per source level, and (m+1) drain layers (26, 28) are provided per drain level. The index j may be in the range of 0 to m.

[0212] Each drain layer (26, 28) may be laterally bounded by a corresponding adjacent pair of backside trenches 79 and include bit lines (28, 128) ("BL"). The bit lines BL are arranged in a three-dimensional array extending in a vertical direction and in a horizontal direction parallel to the longitudinal direction of the backside trenches 79. Thus, the bit lines BL may be numbered with the same two-dimensional coordinates (i, j) as the corresponding source lines SL (i, j).

[0213] The gate electrodes 66 may be arranged in a two-dimensional array and used as control gate electrodes of memory vertical field effect transistors. Each transistor includes a corresponding semiconductor channel, which may include a portion of a semiconductor channel layer 60L, or may include a discrete semiconductor channel (60, 360), or may include a semiconductor channel 60' that is a portion of a semiconductor channel material layer 460. The gate electrodes 66 may be arranged in a two-dimensional array, which may be a hexagonal array or a rectangular array. The gate electrodes 66 extending through the same group of source lines SL and bit lines BL constitute a group of gate electrodes, and the group of source lines and bit lines are located between a pair of corresponding adjacent backside trenches 79 in the same memory block. Each gate electrode 66 in the same group (i.e., in the same memory block) is electrically contacted with a different word line 98 (WL).

[0214] The word lines 98 (WL) are arranged in a two-dimensional array extending in a horizontal direction that is perpendicular to the longitudinal direction of the backside trenches 79 (and perpendicular to the direction of the source lines SL and the bit lines SL). The total number of groups may be (m+1). Each gate electrode 66 within a group of gate electrodes may be individually numbered. If (x+1) gate electrodes exist within each group of electrodes, a two-dimensional coordinate system (k, j) may be used to label these gate electrodes, where k is an index from 0 to x and indicates a single gate electrode within the group, and j is an index from 0 to m and indicates the group to which the gate electrode belongs. Therefore, the three-dimensional coordinates (i, j, k) may uniquely indicate a memory cell.

[0215] In the first embodiment, the semiconductor channel is continuous in the vertical direction. Therefore, activating one word line 98 activates the corresponding gate electrode 66 electrically connected to the activated word line 98. A portion of the memory film 54 adjacent to a portion of the semiconductor channel layer 60L between a pair of activated source and drain regions is activated (e.g., programmed, erased, or read). The pair of source and drain regions can be activated by applying a voltage different from that of the drain region to the source region. The remaining, unselected source and drain regions (and their optional corresponding source and drain lines) are set to the source voltage of the selected memory cell to avoid activating the unselected memory cell.

[0216] In the second to fourth embodiments, the semiconductor channel is not continuous in the vertical direction. In these embodiments, one word line 98 is activated to activate the corresponding gate electrode 66 electrically connected to the activated word line 98. In these embodiments, all memory films 54 can be activated.

[0217] The disclosed embodiments provide a bit-addressable, high-density, three-dimensional memory array. The semiconductor channel can be wider, which provides a tighter threshold voltage distribution. The individual source lines (22, 122) and bit lines (28, 128) of each memory cell provide a higher cell current to increase memory speed.

[0218] Although specific preferred embodiments are mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Embodiments using specific structures and / or configurations are shown in the present disclosure, and it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered impossible by those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, comprising: an alternating stack of source layers and drain layers, the alternating stack of source layers and drain layers being located above a substrate; a gate electrode extending vertically through each of the source and drain layers of the alternating stack of source and drain layers; a memory film, each of the memory films laterally surrounding a corresponding gate electrode; and A semiconductor channel, each of the semiconductor channels laterally surrounds the corresponding memory film and contacts a sidewall of a corresponding vertically stacked adjacent pair of the alternating stacks of the source and drain layers.

2. The three-dimensional memory device according to claim 1, further comprising: word lines over the gate electrodes and over the alternating stacks of the source and drain layers, wherein respective ones of the word lines are electrically connected to respective ones of the gate electrodes; and An array of memory openings extends vertically through the alternating stacks of source and drain layers, wherein each respective one of the gate electrodes is located within a respective one of the memory openings. 3 . The three-dimensional memory device according to claim 1 , further comprising an insulating layer located between each vertically stacked adjacent pair of the alternating stacks of the source and drain layers. The three-dimensional memory device according to claim 3 , wherein the insulating layer has the same dielectric material composition throughout.

5. The three-dimensional memory device according to claim 3, wherein the insulating layer comprises: a channel-level insulating layer, the channel-level insulating layer being in contact with a corresponding one of the semiconductor channels and having a first dielectric material composition; and An inter-transistor insulating layer is not in contact with any of the semiconductor channels and has a second dielectric material composition different from the first dielectric material composition.

6. A three-dimensional memory device according to claim 1, wherein each of the semiconductor channels includes a corresponding portion of a continuous semiconductor channel layer, the corresponding portion of the continuous semiconductor channel layer extends through each source layer and each drain layer within the alternating stack of the source layer and the drain layer and has a hollow cylindrical shape.

7. The three-dimensional memory device of claim 1, wherein each of the semiconductor channels comprises one channel of a group of discrete semiconductor channels, the group of discrete semiconductor channels are vertically spaced apart from each other, and each channel of the group of discrete semiconductor channels has a hollow cylindrical shape.

8. The three-dimensional memory device of claim 7, wherein each channel in the set of discrete semiconductor channels comprises an annular top surface and an annular bottom surface, the annular top surface contacts the bottom surface of the corresponding overlying inter-transistor insulating layer, and the annular bottom surface contacts the corresponding underlying inter-transistor insulating layer.

9. The three-dimensional memory device according to claim 1, wherein each of the semiconductor channels contacts a cylindrical sidewall of a corresponding channel-level insulating layer located between a corresponding vertically-stacked adjacent pair of source and drain layers of the alternating stacks of the source and drain layers.

10. The three-dimensional memory device according to claim 1, wherein: Each of the source layers in the alternating stack of source and drain layers comprises a vertical stack of a doped semiconductor source layer and a metal source line; and Each of the drain layers in the alternating stack of source and drain layers includes a vertical stack of a doped semiconductor drain layer and a metal bit line.

11. The three-dimensional memory device of claim 1 , wherein each of the memory films comprises a layer stack, the layer stack comprising: Tunneling through a dielectric layer; a charge storage layer, the charge storage layer being in contact with the tunneling dielectric layer; and A blocking dielectric layer is in contact with the charge storage layer. 12 . The three-dimensional memory device of claim 1 , wherein each of the memory films comprises a ferroelectric material layer.

13. The three-dimensional memory device according to claim 1, further comprising: a source layer contact via structure, each of which contacts a corresponding source layer in the alternating stack of source and drain layers; and The drain layer contact via structures each of which contacts a corresponding drain layer in the alternating stack of source and drain layers.

14. The three-dimensional memory device according to claim 13, wherein: Respective ones of the source layers in the alternating stack of source and drain layers have different lateral extents that decrease with vertical distance from the substrate; Respective ones of the drain layers in the alternating stack of source and drain layers have different lateral extents that decrease with vertical distance from the substrate; a first backward stepped dielectric material portion in contact with a horizontal surface of the source layer in the alternating stack and laterally surrounding each of the source layer contact via structures; and A second backward stepped dielectric material portion contacts horizontal surfaces of the drain layers in the alternating stack and laterally surrounds each of the drain layer contact via structures.

15. The three-dimensional memory device according to claim 1, wherein: the gate electrode being vertically spaced apart from the substrate by a horizontal portion of the memory film; Each of the gate electrodes laterally surrounds a corresponding dielectric core; and A corresponding contact pad structure contacts a top end of each of the gate electrodes.

16. A method of forming a three-dimensional memory device, comprising: forming an alternating stack of doped semiconductor source layers and doped semiconductor drain layers over the substrate; forming a memory opening extending vertically through the alternating stacks of the doped semiconductor source layers and the doped semiconductor drain layers; forming a continuous semiconductor channel layer in each memory opening, wherein the semiconductor channel is formed on the sidewalls of a corresponding vertically adjacent pair of the doped semiconductor source layer and the doped semiconductor drain layer in the alternating stack of the doped semiconductor source layer and the doped semiconductor drain layer; forming a memory film over the semiconductor channel; as well as Gate electrodes are formed over the memory film, wherein each of the gate electrodes vertically extends through each of the doped semiconductor source layers and the doped semiconductor drain layers of the alternating stacks of the doped semiconductor source layers and the doped semiconductor drain layers. 17 . The method according to claim 16 , further comprising forming a channel-level insulating layer between each vertically stacked adjacent pair of the doped semiconductor source layers and the doped semiconductor drain layers in the alternating stacks of the doped semiconductor source layers and the doped semiconductor drain layers before forming the memory opening.

18. The method according to claim 16 also includes forming a contact via structure on the top surface of the gate electrode, wherein each of the semiconductor channels remains as part of the continuous semiconductor channel layer after forming the contact via structure, and the part of the continuous semiconductor channel layer extends through each doped semiconductor source layer and each doped semiconductor drain layer in the alternating stack of doped semiconductor source layers and doped semiconductor drain layers.

19. The method according to claim 16, further comprising: forming an inter-transistor level sacrificial material layer between each vertically stacked adjacent pair of the alternating stacks of the doped semiconductor source layers and the doped semiconductor drain layers before forming the memory opening; forming a backside recess by selectively removing the inter-transistor level sacrificial material layer relative to the doped semiconductor source layer and the doped semiconductor drain layer in the alternating stack of the doped semiconductor source layer and the doped semiconductor drain layer; dividing each of the continuous semiconductor channel layers into a set of discrete semiconductor channels vertically spaced apart from one another by removing a portion of each continuous semiconductor channel layer physically exposed to the backside recess; as well as An inter-transistor level insulating layer is deposited in each of the backside recesses.

20. The method of claim 16, further comprising: forming word lines over the gate electrodes and over the alternating stacks, wherein respective ones of the word lines are electrically connected to respective ones of the gate electrodes; forming a source-level sacrificial material layer and a drain-level sacrificial material layer before forming the memory opening, so that each of the source-level sacrificial material layers is formed below a corresponding doped semiconductor source layer in the alternating stack of the doped semiconductor source layers and the doped semiconductor drain layers, and each of the drain-level sacrificial material layers is formed above a corresponding doped semiconductor source layer in the alternating stack of the doped semiconductor source layers and the doped semiconductor drain layers; as well as The source level sacrificial material layer and the drain level sacrificial material layer are replaced with metal source lines and metal drain lines, respectively.

21. A three-dimensional memory device, comprising: an alternating stack of source and drain layers, the alternating stack being located above the substrate; an array of memory openings extending vertically through the alternating stacks; a gate electrode, each gate electrode being located in one memory opening in the memory opening array and vertically extending through each of the alternately stacked source and drain layers; a memory film, each memory film being located in one memory opening in the memory opening array and laterally surrounding a corresponding one of the gate electrodes; and A vertical stack of semiconductor channels laterally surrounding a corresponding one of the memory films, wherein each of the vertical semiconductor channels contacts a horizontal surface of one of a corresponding vertically adjacent pair of the source layers and one of the drain layers.

22. The three-dimensional memory device of claim 21, further comprising a word line over the gate electrode and over the alternating stacks of the source layer and the drain layer, wherein the word line is electrically connected to the gate electrode. 23 . The three-dimensional memory device according to claim 21 , further comprising an insulating layer between each vertically adjacent pair of the source layer and the drain layer.

24. The three-dimensional memory device according to claim 23, wherein the insulating layer comprises: a channel-level insulating layer, the channel-level insulating layer being in contact with a corresponding one of the semiconductor channels; and An inter-transistor insulating layer is provided, wherein the inter-transistor insulating layer does not contact any of the semiconductor channels. 25 . The three-dimensional memory device of claim 24 , wherein sidewalls of the channel-level insulating layer are laterally recessed outward relative to sidewalls of the inter-transistor-level insulating layer and relative to sidewalls of the source layer and the drain layer around each memory opening. 26 . The three-dimensional memory device of claim 24 , wherein each of the channel-level insulating layers is in direct contact with horizontal surfaces of a corresponding one of the source layers and a corresponding one of the drain layers. 27 . The three-dimensional memory device of claim 24 , wherein each of the channel-level insulating layers is not in contact with the source layer and the drain layer and is vertically spaced apart from the source layer and the drain layer at least by a corresponding semiconductor channel material layer.

28. The three-dimensional memory device of claim 21, wherein each of the vertical stacks of semiconductor channels comprises a group of discrete semiconductor channels that are vertically spaced apart from one another and are not in direct contact with one another. 29 . The three-dimensional memory device according to claim 28 , wherein an entire outer sidewall of each semiconductor channel contacts a cylindrical sidewall of a corresponding channel-level insulating layer located between a corresponding vertically adjacent pair of the source layer and the drain layer.

30. A three-dimensional memory device according to claim 29, wherein the outer side wall includes an upper outer edge that contacts the horizontal surface of one of the source layer and the drain layer in the corresponding vertically adjacent pair, and includes a lower outer edge that contacts the horizontal surface of the other of the source layer and the drain layer in the corresponding vertically adjacent pair.

31. The three-dimensional memory device of claim 29, wherein each of the semiconductor channels comprises a hollow cylindrical section of a semiconductor channel material layer, the semiconductor channel material layer comprising: an upper semiconductor channel material layer section, the upper semiconductor channel material layer section being adjacent to an upper end of a corresponding semiconductor channel; and A lower semiconductor channel material layer section is adjacent to a lower end of the corresponding semiconductor channel.

32. The three-dimensional memory device of claim 31, wherein the semiconductor channel material layer comprises a set of semiconductor channels, the set of semiconductor channels comprising the hollow cylindrical segment and an additional cylindrical segment laterally surrounding the gate electrode.

33. The three-dimensional memory device of claim 31 , wherein: Each of the source layers comprises a vertical stack of a doped semiconductor source layer and a metal source line; and Each of the drain layers includes a vertical stack of a doped semiconductor drain layer and a metal bit line.

34. The three-dimensional memory device of claim 31 , wherein each of the memory films comprises a layer stack, the layer stack comprising: Tunneling through a dielectric layer; a charge storage layer, the charge storage layer being in contact with the tunneling dielectric layer; and A blocking dielectric layer is in contact with the charge storage layer.

35. The three-dimensional memory device of claim 31, wherein each of the memory films comprises a ferroelectric material layer.

36. A method of forming a three-dimensional memory device, comprising: forming an alternating stack of doped semiconductor source layers and doped semiconductor drain layers over the substrate; forming a reservoir opening extending vertically through the alternating stack; forming a memory film and a gate electrode in each memory opening, wherein the memory film and the gate electrode vertically extend through each of the alternately stacked doped semiconductor source layers and the doped semiconductor drain layers; as well as A vertical stack of semiconductor channels is formed on horizontal surfaces of one of the doped semiconductor source layers and one of the doped semiconductor drain layers in a pair of corresponding vertically adjacent doped semiconductor source layers before or after forming the memory film and the gate electrode, wherein each vertical stack of semiconductor channels laterally surrounds the corresponding memory film and the corresponding gate electrode.

37. The method according to claim 36, further comprising forming an insulating layer between one of the doped semiconductor source layers and one of the doped semiconductor drain layers in each vertically adjacent pair of the doped semiconductor source layers and the doped semiconductor drain layers, wherein the insulating layer comprises: a channel-level insulating layer formed at the level of the semiconductor channel; and An inter-transistor level insulating layer is vertically spaced apart from the semiconductor channel.

38. The method of claim 37, wherein: forming the inter-transistor level insulating layer and the channel level insulating layer before forming the memory opening; and The method further comprises: forming an annular cavity by laterally recessing the sidewalls of the channel-level insulating layer relative to the sidewalls of the doped semiconductor source layer, the doped semiconductor drain layer, and the inter-transistor-level insulating layer; conformally depositing a semiconductor material in the annular cavity; and A portion of the conformally deposited semiconductor material is removed from outside the annular cavity, wherein a remaining portion of the conformally deposited semiconductor material in the annular cavity constitutes a vertical stack of the semiconductor channels.

39. The method of claim 37, wherein: Forming the inter-transistor level insulating layer and the channel level sacrificial material layer occurs before forming the memory opening, wherein the channel level sacrificial material layer is formed at a level where the channel level insulating layer is subsequently formed; forming a backside recess by selectively removing the channel-level sacrificial material layer relative to the doped semiconductor source layer, the doped semiconductor drain layer, and the inter-transistor level insulating layer; and A semiconductor channel material layer is deposited in each backside recess, wherein each cylindrical portion of the semiconductor channel material layer laterally surrounding the memory film constitutes one of the semiconductor channels. 40 . The method of claim 39 , wherein the channel-level insulating layer is formed by depositing an insulating material in an unfilled space of the backside recess after forming the semiconductor channel material layer.

Images