Shield Gate Trench Field Effect Transistor Structure and Its Manufacturing Method

Abstract

The present invention provides a shielded gate trench field effect transistor structure and a preparation method thereof, wherein the problem of asynchronous on and off states of the transistor is avoided by setting the first deep trench and the second deep trench in different deep trenches and arranging them in an intermittent manner, and making multiple resistors R with the same resistance value DS(on) In parallel, the total resistance is equivalent to R DS(on) / n, n is the number of cells, which greatly reduces the on-resistance and the static loss of the device; the bottom area of the first deep trench is filled with BSG material, which reduces the gate-drain overlap area of the device, thereby reducing the gate-drain capacitance, and then increasing the switching speed of the device and reducing the dynamic loss of the device; the first P-type annular layer and the second P-type annular layer are respectively depleted with the N-type epitaxial layer, and as the voltage increases, the depletion layers of the adjacent first deep trenches and the second deep trenches are connected, further reducing the drain-source leakage current Idss of the device, reducing the static loss of the device and preventing the occurrence of soft breakdown; the process steps are simple and the cost is low.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor device design and manufacturing, and particularly relates to a shielded gate trench field effect transistor structure and a preparation method thereof. Background Art

[0002] With the continuous development of semiconductor technology, the structure of metal oxide semiconductor field effect transistors (MOSFETs) has also been continuously improved. The shielded gate trench field effect transistor (Split Gate Trench MOSFET, abbreviated as SGT-MOSFET) is one of the improved structures. By introducing a shielded gate structure, the gate-drain overlap area of the device is reduced, and then the gate-drain capacitance is reduced, so as to achieve the purpose of improving the switching speed and reducing the dynamic loss of the device. Therefore, shielded gate trench MOS devices are widely used in various power electronic systems.

[0003] At present, shielded gate trench field effect transistors are divided into two common structures according to the positional relationship between the shielded gate and the control gate. The first is the up-down structure SGT as shown in Figure 1 In the figure, the control gate 30 and the shielded gate 31 are formed in the same deep trench 34, and the control gate 30 is located above the shielded gate 31. In order to achieve a good isolation effect between the shielded gate 31 and the control gate 30 to reduce the gate-source leakage current Igss, an HDPCVD process is required to deposit a high-quality oxide film, and the process is complex. Especially in medium and high voltage application scenarios, in order to bear a higher breakdown voltage, a deeper trench is required to reduce the on-resistance of the device, further increasing the process difficulty; the second is the left-right structure SGT as shown in Figure 2 In the figure, the shielded gate 31 and the control gate 30 are formed side by side in the same deep trench 34. No additional HDPCVD process is required to form a high-quality oxide film. However, since the two control gates 30 are formed in the same trench, the device has asynchronous turn-on and turn-off states. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a shielded gate trench field effect transistor structure and a preparation method thereof, which are used to solve the problems such as the complex preparation process of the shielded gate trench field effect transistor with the up-down structure and the asynchronous turn-on and turn-off states of the shielded gate trench field effect transistor with the left-right structure in the prior art.

[0005] To achieve the above purpose and other related purposes, the present invention provides a shielded gate trench field effect transistor structure, and the field effect transistor structure includes:

[0006] A substrate;

[0007] An N-type epitaxial layer formed on the substrate;

[0008] First and second deep trenches with an interval therebetween are formed in the N-type epitaxial layer;

[0009] A first BSG material layer and a second BSG material layer, wherein the first BSG material layer is filled upward from below in a partial area of the first deep trench, and the second BSG material layer is filled in the second deep trench;

[0010] A first P-type annular layer and a second P-type annular layer, wherein the first P-type annular layer is formed on the outer periphery of the first BSG material layer, and the second P-type annular layer is formed on the outer periphery of the second BSG material layer;

[0011] A gate oxide layer is formed on the inner wall of the remaining partial area of the first deep trench;

[0012] A gate polysilicon layer is filled in the remaining partial area of the first deep trench;

[0013] A P-type body region is formed in the N-type epitaxial layer;

[0014] An N-type source region is formed in the P-type body region;

[0015] A dielectric layer is formed on the N-type epitaxial layer, a gate contact hole is formed in the dielectric layer, and the gate contact hole is filled with a metal layer to form a gate end;

[0016] A source end is formed on the P-type body region, the N-type source region and the second deep trench;

[0017] A drain end is formed on the back surface of the substrate.

[0018] Optionally, the drain end includes a titanium layer, a nickel layer and a silver layer deposited in sequence.

[0019] Optionally, the depth of the P-type body region does not exceed that of the first P-type annular layer.

[0020] Optionally, the material of the substrate is silicon, the material of the N-type epitaxial layer is silicon, and the material of the gate oxide layer is silicon oxide.

[0021] Optionally, the first deep trench and the second deep trench are of equal depth and equally spaced.

[0022] The present invention further provides a method for manufacturing a shielded gate trench field effect transistor structure, and the manufacturing method includes the following steps:

[0023] Provide a substrate and form an N-type epitaxial layer on the substrate;

[0024] Form a first deep trench and a second deep trench at intervals in the N-type epitaxial layer;

[0025] Fill a first BSG material layer upward in a partial area of the first deep trench; fill a second BSG material layer in the second deep trench;

[0026] Form a gate oxide layer on the inner wall of the remaining area of the first deep trench;

[0027] Anneal and diffuse the above structure in a nitrogen atmosphere, so that the boron elements in the first BSG material layer and the second BSG material layer are diffused into the N-type epitaxial layer outside the first deep trench and the second deep trench respectively, to form a first P-type annular layer and a second P-type annular layer respectively;

[0028] Fill a gate polysilicon layer in the remaining area of the first deep trench;

[0029] Form a P-type body region in the N-type epitaxial layer, and form an N-type source region in the P-type body region;

[0030] Form a dielectric layer on the N-type epitaxial layer, form a gate contact hole in the dielectric layer, and fill a metal layer in the gate contact hole to form a gate end; deposit a metal layer on the P-type body region, N-type source region and the second deep trench to form a source end; form a drain end on the back surface of the substrate.

[0031] Optionally, the method for forming the first deep trench and the second deep trench includes:

[0032] Grow a first SiO2 layer, a SiN layer and a second SiO2 layer on the surface of the N-type epitaxial layer in sequence as a hard mask;

[0033] Perform a photolithography process using a trench photomask, and form the first deep trench and the second deep trench by dry etching;

[0034] Remove the photoresist layer.

[0035] Optionally, the method for forming the first BSG material layer and the second BSG material layer includes:

[0036] Deposit a BSG material layer on the surface of the hard mask by CVD process, so that the BSG material layer fills the first deep trench and the second deep trench;

[0037] Grind and remove the BSG material layer on the surface of the hard mask by CMP process, and at the same time grind and remove the second SiO2 layer;

[0038] Perform a photolithography process using a control gate photomask, and remove a part of the BSG material layer in the first deep trench by wet etching, so that the BSG material layers in the first deep trench and the second deep trench respectively form the first BSG material layer and the second BSG material layer;

[0039] Remove the photoresist layer and the remaining hard mask.

[0040] Optionally, the method for forming the gate oxide layer includes:

[0041] Grow a SiO2 layer by thermal oxidation to repair the defect damage caused by removing the BSG material layer, and then remove the SiO2 layer by wet etching;

[0042] Form a gate oxide layer on the inner wall of the remaining area of the first deep trench by CVD process.

[0043] Optionally, before forming the drain end on the back of the substrate, it further includes thinning the back of the substrate and making an ohmic contact on the back of the thinned substrate.

[0044] As described above, in the shielded gate trench field effect transistor structure and its manufacturing method of the present invention, by arranging the first deep trench (i.e., the control gate trench) and the second deep trench (i.e., the shielded gate trench) in different deep trenches and in a spaced-apart manner, multiple resistors R with the same resistance value DS(on) Form a parallel form, and the total resistance is equivalent to R DS(on) / n, where n is the number of cells, which greatly reduces the on-resistance and reduces the static loss of the device; the bottom region of the first deep trench is filled with a first BSG material layer, which reduces the gate-drain overlap area of the device, thereby reducing the gate-drain capacitance, and further improving the switching speed of the device and reducing the dynamic loss of the device; when the field effect transistor structure operates in the reverse breakdown voltage mode, the first P-type annular layer and the second P-type annular layer respectively form depletion layers with the N-type epitaxial layer depleted. While the depletion layer expands longitudinally, it also expands laterally. As the voltage increases, the depletion layers of adjacent first deep trenches and second deep trenches are connected, further reducing the drain-source leakage current Idss of the device, reducing the static loss of the device and preventing the occurrence of soft breakdown; finally, by arranging the first deep trench (i.e., the control gate trench) and the second deep trench (i.e., the shielded gate trench) in different deep trenches, the problem of asynchronous turn-on and turn-off states of the transistor is avoided, and the process steps are simple and the cost is low. Description of the Drawings

[0045] Figure 1 Shows a schematic structural diagram of a conventional shielded gate trench field effect transistor, where the control gate is located above the shielded gate in the same deep trench.

[0046] Figure 2 Shows a schematic structural diagram of a conventional shielded gate trench field effect transistor, where the shielded gate and the control gate are formed side by side in the same deep trench.

[0047] Figure 3It shows a schematic process flow diagram for the preparation of the shielded gate trench field effect transistor structure of the present invention.

[0048] Figures 4 to 17 It shows a schematic cross-sectional structure diagram presented in each step during the preparation of the shielded gate trench field effect transistor structure of the present invention. Among them, Figure 15 and Figure 16 are schematic cross-sectional structure diagrams presented based on different cross-sections. Figure 15 It shows the connection method of the gate end. Figure 16 It shows the connection method of the source end. Figure 17 It also shows a schematic structure diagram of the shielded gate trench field effect transistor structure of the present invention.

[0049] Component label description

[0050] 10 Substrate

[0051] 11 N-type epitaxial layer

[0052] 111 First deep trench

[0053] 112 Second deep trench

[0054] 113 First SiO2 layer

[0055] 114 SiN layer

[0056] 115 Second SiO2 layer

[0057] 12 First BSG material layer

[0058] 13 Second BSG material layer

[0059] 14 BSG material layer

[0060] 15 Gate oxide layer

[0061] 16 First P-type annular layer

[0062] 17 Second P-type annular layer

[0063] 18 Gate polysilicon layer

[0064] 19 P-type body region

[0065] 20 N-type source region

[0066] 21 Dielectric layer

[0067] 22 Gate contact hole

[0068] 23 Gate end

[0069] 24 Source end

[0070] 25 Drain end

[0071] 30 Control grid

[0072] 31 Shielding grid

[0073] 32 N-type source region

[0074] 33 P-type body region

[0075] 34 Deep trench

[0076] Steps S1 to S8 Specific implementation manner

[0077] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0078] Please refer to Figures 3 to 17 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components during actual implementation. The type, quantity, and ratio of each component during actual implementation can be changed according to actual needs, and the component layout type may also be more complex.

[0079] As Figures 15 to 17 shown, this embodiment provides a shielding gate trench field effect transistor structure. This field effect transistor structure is an N-type device, including: a substrate 10; an N-type epitaxial layer 11 formed on the substrate 10; a first deep trench 111 and a second deep trench 112 arranged at intervals (as Figure 6As shown in the figure, it is formed in the N-type epitaxial layer 11; a first BSG material layer 12 and a second BSG material layer 13, the first BSG material layer 12 is filled from bottom to top in a partial area of the first deep trench 111, and the second BSG material layer 13 is filled in the second deep trench 112; a first P-type annular layer 16 and a second P-type annular layer 17, the first P-type annular layer 16 is formed on the outer periphery of the first BSG material layer 12, and the second P-type annular layer 17 is formed on the outer periphery of the second BSG material layer 13; a gate oxide layer 15 is formed on the inner wall of the remaining area of the first deep trench 111; a gate polysilicon layer 18 is filled in the remaining area of the first deep trench 111; a P-type body region 19 is formed in the N-type epitaxial layer 11; an N-type source region 20 is formed in the P-type body region 19; a dielectric layer 21 is formed on the N-type epitaxial layer 11, a gate contact hole 22 is formed in the dielectric layer 21, and the gate contact hole 22 is filled with a metal layer to form a gate end 23 (as Figure 15 shown); a source end 24 is formed on the P-type body region 19, the N-type source region 20 and the second deep trench 112 (as Figure 16 shown); a drain end 25 is formed on the back surface of the substrate 10.

[0080] As described above, for the shielded gate trench field effect transistor structure proposed in this embodiment, by setting the first deep trench (i.e., the control gate trench) and the second deep trench (i.e., the shielded gate trench) in different deep trenches and arranging them at intervals, multiple resistors R with the same resistance value DS(on) form a parallel form, and the total resistance is equivalent to R DS(on) / n, where n is the number of cells, which greatly reduces the on-resistance and reduces the static loss of the device; the bottom area of the first deep trench is filled with the first BSG material layer, which reduces the gate-drain overlap area of the device, thereby reducing the gate-drain capacitance, and further improving the switching speed of the device and reducing the dynamic loss of the device; when the field effect transistor structure operates in the reverse breakdown voltage mode, the first P-type annular layer and the second P-type annular layer and the N-type epitaxial layer deplete to form a depletion layer. While the depletion layer broadens longitudinally, it also broadens laterally. As the voltage increases, the depletion layers of adjacent first deep trenches and second deep trenches are connected, further reducing the drain-source leakage current Idss of the device, reducing the static loss of the device and preventing the occurrence of soft breakdown; finally, by setting the first deep trench (i.e., the control gate trench) and the second deep trench (i.e., the shielded gate trench) in different deep trenches, the problem of asynchronous turn-on and turn-off states of the transistor is avoided.

[0081] As an example, the material of the substrate 10 is selected as silicon, the material of the N-type epitaxial layer 11 is selected as silicon, and the material of the gate oxide layer 15 is selected as silicon oxide. Preferably, the substrate 10 is an N++ type silicon substrate, and the N-type epitaxial layer 11 is an N- type silicon epitaxial layer.

[0082] As Figure 6 shown, as an example, the first deep trench 111 and the second deep trench 112 are equally deep and equally spaced.

[0083] As Figure 17 shown, as an example, the depth of the P-type body region 19 does not exceed that of the first P-type annular layer 16, that is, the P-type body region 19 does not overlap with the first P-type annular layer 16 in the depth direction, so as to reduce the channel length of the device and thus reduce the channel resistance.

[0084] As Figure 17 shown, as an example, the drain end 25 is generally selected as a metal layer suitable for making an electrode, which can be a single metal layer or a multi-layer metal composite layer. For example, the drain end 25 can be selected as a composite layer of a titanium layer, a nickel layer and a silver layer.

[0085] This embodiment also provides a preparation method for the above-mentioned shielded gate trench field effect transistor structure, but the preparation method of the above-mentioned field effect transistor structure is not limited thereto. This embodiment is only one example, and any preparation method suitable for preparing the above-mentioned field effect transistor structure can be used.

[0086] As Figure 3 shown, the preparation method includes the following steps:

[0087] As Figure 3 and Figure 4 shown, first, step S1 is carried out to provide a substrate 10 and form an N-type epitaxial layer 11 on the substrate 10.

[0088] As an example, the substrate 10 can be an existing conventional semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, etc. Preferably, the substrate 10 can be an N++ type substrate, and the N-type epitaxial layer 11 is an N- type epitaxial layer. In this embodiment, the substrate 10 is preferably an N++ type doped silicon substrate, and the N-type epitaxial layer 11 is an N- type doped single crystal silicon epitaxial layer.

[0089] As Figure 3 and Figure 6 shown, then step S2 is carried out to form the first deep trench 111 and the second deep trench 112 at intervals in the N-type epitaxial layer 11. The first deep trench 111 will be used to form a control gate later, and the second deep trench will be used to form a shielded gate later.

[0090] It should be noted here that for the convenience of describing this structure, only the structure of two first deep trenches 111 and one second deep trench 112 are shown in the figure. Those skilled in the art can easily understand that in specific applications, a plurality of first deep trenches 111 and a plurality of second deep trenches 112 will be formed on the substrate 10 according to actual needs.

[0091] As Figure 5 and Figure 6 shown, as an example, the specific method for forming the first deep trench 111 and the second deep trench 112 includes:

[0092] S2-1, as Figure 5 shown, a first SiO2 layer 113, a SiN layer 114 and a second SiO2 layer 115 are sequentially grown on the surface of the N-type epitaxial layer 11 as a hard mask. The first SiO2 layer 113 can be formed by thermal oxidation as a buffer layer, and its thickness is generally between Since this layer is relatively thin and cannot form a good blocking effect, a SiN layer 114 needs to be grown to play a major blocking role. The thickness of this layer is generally between Since the depth of the trench to be etched is relatively deep, generally a second SiO2 layer needs to be grown. The thickness of this layer is generally between The ONO structure formed by these three material layers serves as a hard mask for etching the first deep trench 111 and the second deep trench 112, and can play a good masking role.

[0093] S2-2, perform a photolithography process using a trench photomask and form the first deep trench 111 and the second deep trench 112 by dry etching. Perform a photolithography process using a trench photomask to expose the positions where trenches need to be dug. This part is not masked by photoresist, and the parts that do not require photolithography are masked with photoresist. Then, dry etching is used to etch the parts not masked by photoresist, thereby forming the first deep trench 111 and the second deep trench 112.

[0094] S2-3, as Figure 6 shown, remove the photoresist layer.

[0095] As Figure 6 shown, as an example, the etching depths of the first deep trench 111 and the second deep trench 112 are the same and they are equally spaced. The specific etching depth and spacing are set according to actual needs and are not limited here.

[0096] As Figure 3 and Figure 10As shown, then step S3 is carried out. The first BSG material layer 12 is filled from bottom to top in a partial area of the first deep trench 111; the second BSG material layer 13 is filled in the second deep trench 112.

[0097] As Figures 7 to 10 shown, as an example, the method for forming the first BSG material layer 12 and the second BSG material layer 13 includes:

[0098] S3-1, as Figure 7 shown, a BSG (boron-silicate glass) material layer 14 is deposited on the surface of the hard mask by using a CVD process, so that the BSG material layer 14 fills the first deep trench 111 and the second deep trench 112.

[0099] S3-2, as Figure 8 shown, the BSG material layer 14 on the surface of the hard mask is removed by using a CMP (chemical mechanical polishing) process, and at the same time the second SiO2 layer 115 is removed. This CMP process cannot remove the SiN layer 114, which is equivalent to the barrier layer being retained. Subsequently, the SiN layer 114 and the first SiO2 layer 113 are used as a hard mask for removing a part of the BSG material layer 14 in the first deep trench 111.

[0100] S3-3, as Figure 9 shown, a photolithography process is carried out by using a control gate photomask, and a part of the BSG material layer 14 in the first deep trench 111 is removed by using wet etching. Thus, the BSG material layer 14 in the first deep trench 111 and the second deep trench 112 respectively form the first BSG material layer 12 and the second BSG material layer 13. Since the actual depth of the control gate trench is relatively shallow, the SiN layer 114 and the first SiO2 layer 113 can be used as a hard mask. Since the control gate and the shielding gate are spaced apart, a mask is formed by using photoresist above the shielding gate, and the BSG material layer in the control gate (i.e., the first deep trench 111) is etched to the required depth by using isotropic wet etching. Generally, it is etched to a depth between 1 μm and 2 μm below the surface of the N-type epitaxial layer 11.

[0101] S3-4, as Figure 10 shown, the photoresist layer and the remaining hard mask are removed.

[0102] As Figure 3 and Figure 11 shown, then step S4 is carried out. A gate oxide layer 15 is formed on the inner wall of the remaining partial area of the first deep trench 111.

[0103] As an example, the specific method for forming the gate oxide layer includes:

[0104] S4-1. Grow a SiO2 layer by thermal oxidation method to repair the defect damage caused by removing the BSG material layer 14, and then remove the SiO2 layer by wet etching.

[0105] S4-2. Form a gate oxide layer 15 on the inner wall of the remaining area of the first deep trench 111 by CVD process. Since CVD process is a whole-surface deposition process, when forming the gate oxide layer 15, it will not only be formed on the inner wall of the remaining area of the first deep trench 111, but also on the surface of the N-type epitaxial layer 11. The gate oxide layer 15 formed on the surface of the N-type epitaxial layer 11 can be selectively removed, that is, it can be retained or removed. As Figure 11 shown, select to retain the gate oxide layer 15 on the surface of the N-type epitaxial layer 11, which can form a protection structure during the subsequent diffusion of the BSG material. Using CVD can form a high-quality gate oxide layer 15, thereby reducing the device gate-source leakage current Igss.

[0106] As an example, the material of the gate oxide layer 15 is selected as silicon oxide material.

[0107] As Figure 3 and Figure 12 shown, then proceed to step S5. Anneal and diffuse the above structure in a nitrogen atmosphere, so that the boron elements in the first BSG material layer 12 and the second BSG material layer 13 are respectively diffused into the N-type epitaxial layer 11 outside the first deep trench 111 and the second deep trench 112 to form a first P-type annular layer 16 and a second P-type annular layer 17 respectively. This step utilizes the easy diffusion characteristic of the BSG material at high temperature, which can make the first BSG material layer 12 and the second BSG material layer 13 diffuse into the N-type epitaxial layer 11 on their outer periphery, thereby forming the circumferentially wrapped first P-type annular layer 16 and second P-type annular layer 17.

[0108] It should be noted that the gate oxide layer 15 formed on the surface of the N-type epitaxial layer 11 in this step can also be selectively removed. As Figure 12 shown, select to retain the gate oxide layer 15 on the surface of the N-type epitaxial layer 11.

[0109] As Figure 3 and Figure 13 shown, then proceed to step S6. Fill the remaining area of the first deep trench 111 with a gate polysilicon layer 18.

[0110] As an example, the specific method for forming the gate polysilicon layer 18 includes: depositing a gate polysilicon material on the surface of the N-type epitaxial layer 11 by means of a CVD process so that the gate polysilicon material fills the first deep trench 111; removing the gate polysilicon material on the surface of the N-type epitaxial layer 11 by means of a CMP process, thereby forming the gate polysilicon layer 18.

[0111] As Figure 3 and Figure 14 shown, then step S7 is carried out to form a P-type body region 19 in the N-type epitaxial layer 11 and to form an N-type source region 20 in the P-type body region 19.

[0112] As an example, the surface of the N-type epitaxial layer 11 is ion-implanted with a P-type dopant, usually boron ions (Boron), to form the P-type body region 19 (P-Body); the N-type source region 20 (Source) is defined by lithography, a blocking photoresist is fabricated, and then the N-type epitaxial layer 11 is ion-implanted with an N-type dopant, usually arsenic ions (Arsenic), to form the N-type source region 20.

[0113] Note that before this step, the gate oxide layer 15 formed on the surface of the N-type epitaxial layer 11 can be selectively removed.

[0114] As Figure 3 and Figures 15 to 17 shown, finally step S8, the electrode lead-out step, specifically includes: forming a dielectric layer 21 on the N-type epitaxial layer 11 (as Figure 15 shown), forming a gate contact hole 22 in the dielectric layer 21, and filling the gate contact hole 22 with a metal layer to form a gate terminal 23 (as Figure 15 shown); depositing a metal layer on the P-type body region 19, the N-type source region 20, and the second deep trench 112 to form a source terminal 24 (as Figure 16 shown); forming a drain terminal 25 on the back surface of the substrate 10 (as Figure 17 shown).

[0115] As an example, the dielectric layer 21 is formed on the N-type epitaxial layer 11 by means of a CVD process; then a photoresist is spin-coated; part of the dielectric layer above the first deep trench 111 is removed by means of lithography and reactive ion etching to form the gate contact hole 22, and the gate contact hole 22 is filled with a metal layer to form the gate terminal 23; the dielectric layer on the P-type body region 19, the N-type source region 20, and the second deep trench 112 is removed by means of lithography and reactive ion etching and filled with a metal layer to form the source terminal 24.

[0116] As an example, the gate contact hole 22 extends into the gate polysilicon layer 18 located within the first deep trench 111.

[0117] As an example, before forming the drain end 25 on the back surface of the substrate 10, the method further includes back-thinning the substrate 10 and fabricating an ohmic contact on the back surface of the thinned substrate 10.

[0118] Compared with the prior art of the up-down structure SGT and the left-right structure SGT, the preparation method of this example has simple process steps and low cost.

[0119] In summary, the present invention provides a shielded gate trench field effect transistor structure and a preparation method thereof. By arranging the first deep trench (i.e., the control gate trench) and the second deep trench (i.e., the shielded gate trench) in different deep trenches and in a spaced-apart manner, a plurality of resistors R with the same resistance value DS(on) are formed in parallel, and the total resistance is equivalent to R DS(on) / n, where n is the number of cells, greatly reducing the on-resistance and the static loss of the device; the bottom region of the first deep trench is filled with a first BSG material layer, reducing the gate-drain overlap area of the device, thereby reducing the gate-drain capacitance, and further improving the switching speed of the device and reducing the dynamic loss of the device; when the field effect transistor structure operates in the reverse breakdown voltage mode, the first P-type ring layer and the second P-type ring layer respectively form depletion layers with the N-type epitaxial layer being depleted. While the depletion layer broadens longitudinally, it also broadens laterally. As the voltage increases, the depletion layers of adjacent first deep trenches and second deep trenches are connected, further reducing the drain-source leakage current Idss of the device, reducing the static loss of the device and preventing the occurrence of soft breakdown; finally, by arranging the first deep trench (i.e., the control gate trench) and the second deep trench (i.e., the shielded gate trench) in different deep trenches, the problem of asynchronous turn-on and turn-off states of the transistor is avoided, and the process steps are simple and the cost is low. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0120] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A shield gate trench field effect transistor structure, characterized in that, The field effect transistor structure includes: A substrate; An N-type epitaxial layer formed on the substrate; First and second deep trenches arranged at intervals and formed in the N-type epitaxial layer; A first BSG material layer and a second BSG material layer, where the first BSG material layer is filled from bottom to top in a partial area of the first deep trench, and the second BSG material layer is filled in the second deep trench; A first P-type annular layer and a second P-type annular layer, where the first P-type annular layer is formed on the outer periphery of the first BSG material layer, and the second P-type annular layer is formed on the outer periphery of the second BSG material layer; A gate oxide layer formed on the inner wall of the remaining area of the first deep trench; A gate polysilicon layer filled in the remaining area of the first deep trench; A P-type body region formed in the N-type epitaxial layer; An N-type source region formed in the P-type body region; A dielectric layer formed on the N-type epitaxial layer, with a gate contact hole formed in the dielectric layer, and the gate contact hole is filled with a metal layer to form a gate terminal; A source terminal formed on the P-type body region, N-type source region and the second deep trench; A drain terminal formed on the back surface of the substrate.

2. The shielded gate trench field effect transistor structure according to claim 1, characterized in that: The drain terminal includes a titanium layer, a nickel layer and a silver layer deposited in sequence.

3. The shield gate trench field effect transistor structure according to claim 1, characterized in that: The depth of the P-type body region does not exceed that of the first P-type annular layer.

4. The shield gate trench field effect transistor structure according to claim 1, wherein: The material of the substrate is silicon, the material of the N-type epitaxial layer is silicon, and the material of the gate oxide layer is silicon oxide.

5. The shielded gate trench field effect transistor structure according to claim 1, wherein: The first deep trench and the second deep trench are of equal depth and equally spaced.

6. A preparation method of a shield gate trench field effect transistor structure, characterized in that, The manufacturing method includes the following steps: Provide a substrate and form an N-type epitaxial layer on the substrate; Form first and second deep trenches at intervals in the N-type epitaxial layer; Fill the first BSG material layer from bottom to top in a partial area of the first deep trench; fill the second BSG material layer in the second deep trench; Form a gate oxide layer on the inner wall of the remaining area of the first deep trench; Anneal and diffuse the above structure in a nitrogen atmosphere, so that the boron elements in the first BSG material layer and the second BSG material layer are diffused into the N-type epitaxial layer outside the first deep trench and the second deep trench respectively to form a first P-type annular layer and a second P-type annular layer respectively; Fill the remaining area of the first deep trench with a gate polysilicon layer; Form a P-type body region in the N-type epitaxial layer and form an N-type source region in the P-type body region; Form a dielectric layer on the N-type epitaxial layer, form a gate contact hole in the dielectric layer, fill the gate contact hole with a metal layer to form a gate terminal; deposit a metal layer on the P-type body region, N-type source region and the second deep trench to form a source terminal; form a drain terminal on the back surface of the substrate.

7. The manufacturing method of the shield gate trench field effect transistor structure according to claim 6, characterized in that, The method for forming the first deep trench and the second deep trench includes: Grow a first SiO2 layer, a SiN layer and a second SiO2 layer on the surface of the N-type epitaxial layer in sequence as a hard mask; Perform a lithography process using a trench photomask and perform dry etching to form the first deep trench and the second deep trench; Remove the photoresist layer.

8. The manufacturing method of the shield gate trench field effect transistor structure according to claim 7, characterized in that, The method for forming the first BSG material layer and the second BSG material layer includes: Deposit a BSG material layer on the surface of the hard mask by using the CVD process so that the BSG material layer fills the first deep trench and the second deep trench; Remove the BSG material layer on the surface of the hard mask by using the CMP process, and at the same time remove the second SiO2 layer by grinding; Perform a photolithography process using a control gate photomask, and remove a part of the BSG material layer in the first deep trench by using wet etching, so that the BSG material layers in the first deep trench and the second deep trench respectively form the first BSG material layer and the second BSG material layer; Remove the photoresist layer and the remaining hard mask.

9. The manufacturing method of the shield gate trench field effect transistor structure according to claim 8, characterized in that, The method for forming the gate oxide layer includes: Grow a SiO2 layer by using the thermal oxidation method to repair the defect damage caused by removing the BSG material layer, and then remove this SiO2 layer by wet etching; Form a gate oxide layer on the inner wall of the remaining part of the first deep trench by using the CVD process.

10. The manufacturing method of the shield gate trench field effect transistor structure according to claim 6, characterized in that, Before forming the drain end on the back surface of the substrate, it also includes thinning the back surface of the substrate and making an ohmic contact on the back surface of the thinned substrate.

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