Drift compensation

Abstract

The present disclosure relates to drift compensation. The present disclosure relates to an electronic device, including: a first capacitor and a quartz crystal, serially coupled between a first node and a second node; an inverter, coupled between the first node and the second node; a first variable capacitor, coupled between the first node and a third node; and a second variable capacitor, coupled between the second node and the third node.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of French Application No. 2001755, filed on February 21, 2020, which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to electronic devices and methods, and particularly to electronic devices including an oscillating circuit and associated methods. Background Art

[0004] Electronic devices typically include an oscillating circuit in order to generate a desired center frequency.

[0005] Quartz crystals are often used in oscillating circuits. In fact, quartz crystals are characterized by generating relatively stable oscillations when a voltage is received. Summary of the Invention

[0006] One embodiment addresses all or some of the drawbacks of known electronic devices including quartz crystals.

[0007] One embodiment provides a method for controlling a device, the device including an oscillating circuit configured to provide a clock signal to a radio frequency circuit and including an antenna, wherein enabling the transfer of a signal from the circuit to the antenna is delayed relative to the moment when the power amplifier of the circuit is enabled.

[0008] According to one embodiment, enabling the transfer of a signal from the circuit to the antenna corresponds to the switch switching from a first position configured such that transmission via the antenna is not possible to a second position configured such that transmission via the antenna is possible.

[0009] According to one embodiment, a single control signal is generated to enable the power amplifier and enable the transfer of a signal from the circuit to the antenna, and a delay is added to the single control signal before the control signal reaches a switch coupled between the circuit and the antenna, the delay being relative to the control signal reaching the amplifier.

[0010] According to one embodiment, the duration of the delay is less than one second.

[0011] According to one embodiment, the duration of the delay is greater than 5 ms.

[0012] According to one embodiment, the duration of the delay depends on the temperature measured by a temperature sensor of the device.

[0013] According to one embodiment, the temperature or each temperature indicates the ambient temperature.

[0014] According to one embodiment, the device includes a plurality of delay duration values stored in a memory, each duration value corresponding to a range of temperatures.

[0015] According to one embodiment, the duration values associated with some of the temperatures are zero.

[0016] According to one embodiment, the duration value associated with at least one of the temperatures is different from zero.

[0017] According to one embodiment, the radio frequency circuit is a radio frequency transmitter.

[0018] According to one embodiment, the device includes a first variable capacitor, a first capacitor, a quartz crystal, and a second variable capacitor coupled in series, including controlling the capacitances of the first and second variable capacitors to be higher than 50% of their maximum capacitances.

[0019] According to one embodiment, the method includes the following steps: A) preheating the quartz; B) enabling the transmission of a signal as the temperature of the quartz decreases.

[0020] Another embodiment provides a device including: a radio frequency circuit and an antenna; an oscillation circuit configured to provide a clock signal to the RF circuit; and a control circuit configured to enable a power amplifier of the radio frequency circuit and enable the transfer of a signal from the circuit to the antenna, the enabling of the transfer of the signal from the circuit to the antenna being delayed relative to the moment when the power amplifier is enabled.

[0021] According to one embodiment, the device includes a sensor configured to measure temperature or a value representative of temperature.

[0022] According to one embodiment, the device includes a memory configured to store delay duration values corresponding to temperature ranges.

[0023] According to one embodiment, the device includes a first variable capacitor, a first capacitor, a quartz crystal, and a second variable capacitor coupled in series.

[0024] According to one embodiment, the device includes a heater configured to increase the temperature of the quartz.

[0025] Another embodiment provides an electronic device including: a first capacitor and a quartz crystal coupled in series between a first node and a second node; an inverter coupled between the first and second nodes; a first variable capacitor coupled between the first node and a third node; and a second variable capacitor coupled between the second node and the third node.

[0026] According to one embodiment, the value of the first capacitor is selected based on a target frequency to reduce the equivalent capacitance seen by the quartz relative to the capacitance generated by only two variable capacitors.

[0027] According to one embodiment, a first variable capacitor, a capacitor, a quartz crystal, and a second variable capacitor are included in an oscillator circuit.

[0028] According to one embodiment, the oscillator circuit is configured to provide a clock signal to a circuit.

[0029] According to one embodiment, the circuit is an RF transmitter.

[0030] According to one embodiment, the variable capacitor is part of an integrated circuit, and the quartz crystal and the capacitor are not part of the integrated circuit.

[0031] According to one embodiment, the capacitance value of the first capacitor is constant.

[0032] According to one embodiment, the device includes a second capacitor coupled between the quartz and the second variable capacitor.

[0033] According to one embodiment, the device includes: a radio frequency circuit and an antenna; an oscillator circuit configured to provide a clock signal to the RF circuit; and a control circuit configured to enable a power amplifier of the radio frequency circuit and to enable the transfer of a signal from the circuit to the antenna, delaying the enabling of the transfer of the signal from the circuit to the antenna relative to the moment when the power amplifier is enabled.

[0034] According to one embodiment, the device includes a heater configured to increase the temperature of the quartz.

[0035] Another embodiment provides a method for controlling a previous device, the method including controlling the capacitances of the first and second variable capacitors to be higher than 50% of their maximum capacitances.

[0036] According to one embodiment, the method includes controlling the capacitances of the first and second variable capacitors to be substantially equal.

[0037] According to one embodiment, the method includes an oscillator circuit configured to provide a clock signal to a radio frequency circuit and includes an antenna, wherein the enabling of the transfer of a signal from the circuit to the antenna is delayed relative to the moment when a power amplifier of the circuit is enabled.

[0038] According to one embodiment, the method includes the steps of: A) preheating the quartz; B) enabling the transmission of a signal as the temperature of the quartz decreases.

[0039] Another embodiment provides a device, comprising: an electronic circuit; an oscillating circuit including quartz, configured to provide a clock signal to the electronic circuit; and a heater, configured to increase the temperature of the quartz.

[0040] According to one embodiment, the electronic circuit is a radio frequency transmitter and is coupled to an antenna.

[0041] According to one embodiment, the device includes a control circuit configured to control the heater.

[0042] According to one embodiment, the heater is dedicated to preheating the quartz.

[0043] According to one embodiment, the heater is less than 10 mm away from the quartz.

[0044] According to one embodiment, the heater is a resistor.

[0045] According to one embodiment, the device includes: an antenna; a control circuit configured to enable a power amplifier of the circuit and enable the transfer of a signal from the circuit to the antenna, and to delay the enabling of the transfer of the signal from the circuit to the antenna relative to the moment when the power amplifier is enabled.

[0046] According to one embodiment, the device includes a first variable capacitor, a first capacitor, a quartz crystal, and a second variable capacitor coupled in series.

[0047] Another embodiment provides a method of controlling the previous device, comprising the steps of: A) preheating the quartz; B) enabling the transmission of a signal as the temperature of the quartz decreases.

[0048] According to one embodiment, step A) includes increasing the current flowing through a resistor.

[0049] According to one embodiment, during step A), the temperature is at least doubled.

[0050] According to one embodiment, the enabling of the transfer of the signal from the circuit to the antenna is delayed relative to the moment when the power amplifier of the circuit is enabled.

[0051] According to one embodiment, the method includes controlling the capacitance of the first and second variable capacitors to be higher than 50% of their maximum capacitance. Description of the Drawings

[0052] In the following description of specific embodiments given by way of example and not limitation, the above features and advantages and other features and advantages will be described in detail with reference to the accompanying drawings, in which:

[0053] Figure 1 An example of an electronic device capable of transmitting RF signals is very schematically illustrated;

[0054] Figure 2 is a graph showing the drift of the frequency of the device shown Figure 1 changing over time from an expected center frequency;

[0055] Figure 3 is a graph showing the drift of the frequency of the device shown Figure 1 changing over time from an expected center frequency and Figure 1 a graph of two signals of the device shown;

[0056] Figure 4 is a graph showing the drift of the frequency of the device shown Figure 1 changing over time from an expected center frequency for multiple ambient temperatures;

[0057] Figure 5 schematically represents a method for controlling a device shown Figure 1 ;

[0058] Figure 6 schematically illustrates an embodiment of a device including an oscillator circuit;

[0059] Figure 7 is a graph showing the drift of the frequency of the device shown Figure 6 changing with Figure 6 the capacitance value of a capacitor of the oscillator circuit shown;

[0060] Figure 8 very schematically illustrates an example of an electronic device capable of transmitting RF signals;

[0061] Figure 9 is a graph showing the effect of temperature change on quartz during the first 300 ms;

[0062] Figure 10 is a graph showing an example of the drift obtained using an embodiment shown Figure 8 ; and

[0063] Figure 11 illustrates an embodiment of a method for commanding a device shown Figure 8 ; DETAILED DESCRIPTION

[0064] In the various figures, like features have been designated by like reference numerals. In particular, structural and / or functional features common between the various embodiments may have the same reference numerals and may be arranged with the same structure, dimensions, and material properties.

[0065] For clarity, only the operations and elements useful for understanding the embodiments described herein have been illustrated and described in detail.

[0066] Unless otherwise indicated, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor; and when referring to two elements coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

[0067] In the following disclosure, unless otherwise indicated, when referring to absolute position modifiers (such as the terms "front", "rear", "top", "bottom", "left", "right", etc.) or relative position modifiers (such as, the terms "above", "below", "upper", "lower", etc.), or when referring to orientation modifiers (such as, "horizontal", "vertical", etc.), it refers to the orientation shown in the figure.

[0068] Unless otherwise specified, the expressions "about", "approximate", "substantially", and "approximately" mean within 10%, and preferably within 5%.

[0069] Figure 1 An example of an electronic device 10 capable of emitting RF signals is very schematically illustrated. For example, the device 10 is suitable for low - power and long - distance transmission. Preferably, the device is adapted to operate with a technology called LoRa (Long Range).

[0070] The device 10 includes an oscillation circuit 12. The oscillation circuit 12 includes a quartz crystal 14 and an oscillator (OSC) 16. The output of the oscillator 16 is coupled (preferably connected) to a transmit circuit (RF) 20. The oscillation circuit 16 provides a clock signal having a center frequency f to the circuit 20. The expected value of the center frequency f is, for example, equal to 32 MHz.

[0071] The oscillator 16 and the transmit circuit 20 are integrated in a single circuit or chip 24, while the quartz 14 constitutes an external component of the circuit 24.

[0072] The circuit 20 is coupled to an antenna 22. The circuit 20 is, for example, an RF transmitter. In other words, the circuit 20 is, for example, a transmitter that is capable of transmitting (emitting and receiving) signals at radio frequency (RF) (in other words, RF signals). The circuit 20 can transmit and receive RF signals. The circuit 20 constitutes a transmit and / or receive head, which is coupled to the antenna 22 through various analog front - end circuits 19 (matching networks, converters, switches, baluns, etc.). The front - end circuits are external to the chip 24.

[0073] Circuit 20 includes an output TX, on which a signal to be transmitted is provided. The output TX is provided by a power amplifier 21 (PA) of circuit 20. The power amplifier 21 includes an input, on which a signal T representing the signal to be transmitted is provided. The power amplifier 21 includes an enable input, which receives a control signal EN1 or an enable signal EN1. The signal EN1 is a signal configured to enable or disable the power amplifier 21. The signal EN1 is, for example, a binary signal. A first value of the signal EN1, for example, a high value '1', enables the power amplifier 21 and thus allows the output signal TX. A second value of the signal EN1, for example, a low value '0', disables the power amplifier 21. Thus, when the signal EN1 takes the second value, the signal cannot be transmitted by circuit 20.

[0074] Circuit 20 includes an input RX, on which a signal from antenna 22 can be received. More precisely, the signal received by antenna 22 is provided to input RX via a front-end circuit 19. For example, input RX is, for example, coupled (preferably connected) to the input of a low-noise amplifier 25 of circuit 20. The output of the low-noise amplifier provides a signal R representing the received signal RX.

[0075] Chip 24 includes a processing unit 27 (PU). The processing unit 27 is coupled (preferably connected) to circuit 20. The output of the low-noise amplifier 25 and the input of the power amplifier 21 are, for example, coupled to the processing unit 27. The processing unit 27 is configured to process data to be sent (and thus process signal T), and is configured to process received data (in other words, signal R). The link between the processing unit 27 and the power amplifier 21, and the link between the processing unit 27 and the low-noise amplifier 25 are not described in detail herein. Figure 1 The link between the processing unit 27 and the power amplifier 21, and the link between the processing unit 27 and the low-noise amplifier 25 are not described in detail herein.

[0076] Figure 1 Device 10 of is a half-duplex system. Thus, the device can transmit or receive signals, but not simultaneously. The output TX and input RX of circuit 20 are coupled to antenna 22 via a switch 29 (SW). The switch 29 is coupled to the output TX and input RX on one side and to the antenna on the other side. In a first state of the switch 29, the antenna is coupled to the output TX. In this first state, a signal can be transmitted via antenna 22. However, it is not possible to receive a signal. In a second state of the switch 29, the antenna is coupled to the input RX. In this second state, a signal can be received from antenna 22. However, it is not possible to transmit a signal.

[0077] The switch 29 may also include a third state, not shown, in which the antenna is coupled to a high-impedance node.

[0078] According to one embodiment, switch 29 receives a control signal EN2 or an enable signal EN2 that is different from the control signal EN1. Depending on the desired state of the switch, the control signal EN2 takes different values. For example, a first value of the signal EN2 ensures that the switch 29 is in a first state, and a second value of the signal EN2 ensures that the switch 29 is in a second state. If the switch can be in more than two states, the control signal EN2 can take more than two values.

[0079] Switch 29 is part of circuit 19 and is coupled to antenna 22 and circuit 24 via block 31 and blocks 33 and 35, respectively.

[0080] As Figure 1 shown, block 31 couples the common node of switch 29 to antenna 22, while blocks 33 and 35 couple the switched nodes of switch 29 to circuits 21 and 25, respectively.

[0081] Device 10 further includes a control circuit (CTRL) 32. The control circuit 32 is configured to control different elements of device 10. In particular, the control circuit 32 provides the control signals EN1 and EN2 to circuit 20 and switch 29, respectively. Circuit 32 is integrated into chip 24, for example.

[0082] When power amplifier 21 is enabled, a signal can be output on output TX. However, once the power amplifier is enabled, its temperature will increase significantly, which will cause an increase in the temperature of circuit 24. The increase in the temperature of circuit 24 at least partially causes a drift in the frequency of the clock signal, where the clock signal is provided by oscillator 16 to circuit 20. This drift corresponds to the difference between the actual center frequency of the signal that can be used by transmitter 20 to transmit a signal and the desired center frequency. The drift can also be caused at least in part by the heating of the quartz crystal. In Figure 2 is illustrated this drift.

[0083] Figure 2 is a graph showing Figure 1 the frequency of the device as it drifts (drift (32 MHz) (Hz)) from the desired center frequency over time (time (seconds)). Figure 2 The graph of

[0084] illustrates the effect of the heating of power amplifier 21 in circuit 20. The heating of power amplifier 21 causes a drift in the frequency f provided by oscillator circuit 12 to RF transmitter 20.

[0085] Before time t0, the power amplifier is disabled and cannot transmit, so the temperature is basically constant and there is no obvious drift. Therefore, the drift is basically equal to zero.

[0086] At time t0, the power amplifier 21 included in the RF circuit 20 is enabled. As a result, the temperature of the chip 24 increases and the frequency f of the clock signal drifts away from the desired center frequency.

[0087] After time t0, the value of the drift decreases and becomes negative. In other words, the absolute value of the drift increases.

[0088] Figure 2 Represents the drift during a period of approximately 1 second after enabling the power amplifier 21. During the initial second of this operation, the drift decreases and reaches a value that is substantially equal to -4 Hz. The value of the drift reaches -1.4 Hz at time t1.

[0089] For an RF transmitter such as circuit 20, it is particularly important that the frequency of the clock signal be as constant as possible during the operation of the transmitter (or receiver or emitter), especially during transmission or reception.

[0090] During the initial period of transmission, the drift can be particularly problematic. In some applications, such as in the case of the wide area network LoRa (LoRaWAN) Cl, for example, it is specified in the standard that preferably, during the initial second of transmission, for a desired center frequency of 915 MHz, the absolute value of the drift is less than a threshold th of 40 Hz. However, the drift is proportional to the desired center frequency. As a result, for a threshold of 40 Hz for a desired center frequency of 915 MHz, it corresponds to a threshold of approximately 1.4 Hz of drift for a desired center frequency of 32 MHz. This threshold is crossed at Figure 2 the moment t1 of the example.

[0091] A negative value of the drift means that the actual value of the frequency of the clock signal supplied to the RF transmitter 20 is lower than the expected value. A positive value of the drift means that the actual value of the frequency is higher than the expected value. A drift value equal to zero means that the actual value of the frequency of the clock signal supplied to the RF transmitter is equal to the expected value.

[0092] According to one embodiment, the control circuit is configured to ensure a delay that is the delay between the enabling of the power amplifier 21 and the enabling of the transmission of the signal to be sent from the output TX to the antenna. For example, the enabling of the transmission of the signal corresponds to placing the switch 29 in a state that allows the transmission of the signal to be transmitted and does not allow the transmission of the signal to be received. In other words, after enabling the power amplifier 21, the control signal EN2 of the switch 29 is set to a first value '1'. Thus, the signals EN1 and EN2 do not take their first values at the same instant. The control signal EN1 takes its first value, and after a delay, the control signal EN2 takes its first value. RegardingFigure 3 A method for more specifically describing such a control device 10.

[0093] Figure 3 Is a diagram Figure 1 showing the frequency f of the device drifting (drifting) from the desired center frequency over time (t) and Figure 1 a diagram of two corresponding enable signals (EN1, EN2) of the amplifier 21 and the switch 29 of the device.

[0094] The drift value is calculated compared to the desired center frequency of 32 MHz. Thus, the drift is equal to the difference between the actual value of the center frequency and the value 32 MHz.

[0095] Before time t0, the control signals EN1 and EN2 have a second value. In other words, before time t0, the power amplifier 21 is disabled, and the switch 29 is configured to allow signal reception but not transmission. Since the power amplifier is disabled, it does not generate heat, and the drift is substantially zero.

[0096] More generally, before time t0, the switch 29 can be in any state. In fact, since the power amplifier is disabled, signals cannot be transmitted via the output TX regardless of the state of the switch 29.

[0097] At time t0, Figure 1 the power amplifier 21 is enabled. In other words, the control signal generated by the control circuit 32 changes from the second value (‘0’) to the first value (‘1’). Additionally, the transfer of the signal from the output TX to the antenna is blocked. In Figure 2 the example, the control signal EN2 remains at the second value ‘0’ corresponding to the receiving state. However, the switch can be in any state that does not allow the transfer of the signal to be transmitted from the output TX to the antenna.

[0098] As the temperature of the power amplifier increases, the drift decreases. In other words, the absolute value of the drift increases. However, since the signal EN2 has the second value, there is no transmission.

[0099] At time t2 (later than time t0 and separated from time t0 by a delay D), the control signal EN2 takes the first value. Thus, at time t2, the signal to be transmitted can reach the antenna to be sent to the receiving device.

[0100] At time t2, transmission begins and the receiving device begins to receive the transmitted signal. The drift of the transmitted signal is drift A2, which corresponds to the difference between the actual frequency of the transmitted signal and the frequency value at the start of transmission.

[0101] The delay D is selected so as to ensure that the drift A2 is below the aforementioned threshold th. Further, when considering the threshold th, it is preferred to select the delay D as small as possible.

[0102] For example, the delay D is pre-programmed in the device, e.g., pre-programmed in the memory.

[0103] According to another embodiment, a single enable signal is generated by the control circuit 32, but the signal is delayed before reaching the switch 29. For example, the device 10 includes a component configured to add a delay equal to D to the single control signal before the control signal reaches the switch 29, the delay being relative to the moment when the control signal reaches the amplifier 21.

[0104] It is conceivable to use a temperature-compensated quartz crystal (TCXO or temperature-controlled crystal oscillator) in order to compensate for the drift caused by the enabling of the power amplifier. However, in many applications, the cost of such quartz will be considered too high.

[0105] The device 10 is preferably configured to operate using the technology LoRa. In this case, it is desirable to use a standard chip 24, the hardware of which cannot be modified. Any modification or improvement must involve the programming of the components of the chip 24 and / or components external to the chip 24, but without modifying the components of the chip 24.

[0106] Figure 4 is a graph showing, for several ambient temperatures, Figure 1 the frequency f of the clock signal of the device as a function of time (t(s)).

[0107] Figure 4 It includes three curves 41, 43, 45, each curve representing the frequency f for a different ambient temperature. Curve 41 corresponds to an ambient temperature of -40°C. Curve 43 corresponds to an ambient temperature of 80°C. Curve 45 corresponds to an ambient temperature of 25°C.

[0108] As can be seen, depending on the temperature, the drift has different behaviors depending on the ambient temperature. For example, curve 41 corresponding to a temperature of 85°C shows a more pronounced variation than the other curves.

[0109] The value of the moment t1 can be different for each value of the ambient temperature. For some temperature values, the moment t1 can be equal to the moment t0. Thus, for some temperatures, but not for all, the delay can be equal to zero. In fact, for some temperatures, during the first second after the moment t1, the absolute value of the drift remains below the threshold th.

[0110] According to one embodiment, the device 10 is programmed with a single delay D value. Preferably, this value is selected according to the worst case at time t1 corresponding to the temperature of the expected operation of the device.

[0111] According to a preferred embodiment, based on the value of the temperature measured by the temperature sensor (SENSOR), the delay D between the enabling of the power amplifier 21 and the enabling of the switch 29 is selected. The sensor is integrated in the chip 24. The temperature measured by the sensor is, for example, the temperature at the outer surface of the device and thus indicates, for example, the ambient temperature around the device. Alternatively, the temperature measured by the sensor is the temperature inside the device 10, such as the temperature on the chip 24.

[0112] Several delay D values can be programmed in the device 10. For example, each value of the delay D can be associated with an ambient temperature range.

[0113] The different times t1 and the corresponding temperature ranges, which are preferably programmed in the memory of the device, are generated, for example, during manufacturing or during a calibration process. For example, the variation of the drift is determined for multiple temperatures, where each of the multiple temperatures corresponds to a range of temperatures. This step is implemented on each device or on a device representative of a batch of devices. Alternatively, the calibration process may not be implemented. The different times t1 and the corresponding temperature ranges are, for example, predefined values.

[0114] Figure 5 Schematically represents a method for controlling Figure 1 the device. Preferably, the steps of the method are consecutive. The method is implemented, for example, by hardware or software. The method is implemented, for example, by a state engine.

[0115] For example, at the start of the transmission of each signal, or at the start of the transmission of each signal group (block 60, start), the method described regarding Figure 5 is executed.

[0116] During the first step of the method, the temperature sensor measures the temperature (block 62, MEA T°). The temperature is then compared with the value or range of values programmed in the device 10, and the value of the delay D is determined according to this value or temperature range (block 64, DET D).

[0117] During a subsequent step, the control circuit ensures that the power amplifier is enabled (block 66, EN1), while the transfer of the signal from the output TX to the antenna is prohibited. For example, the control circuit ensures that the signal EN1 takes a first value (‘1’), while the signal EN2 has a second value (‘0’). When the signal EN1 has the first value and the signal EN2 has the second value, a pseudo-signal T is applied, for example, at the input of the power amplifier 21.

[0118] The delay D starts when the power amplifier is enabled. For example, a counter starts counting when the power amplifier is enabled. When the value of the delay D is reached, the transmission of the signal to be transmitted is allowed (block 68, EN2). For example, when the counter reaches the value D, the control signal EN2 takes the first value '1', while the control signal EN1 remains at the first value. One or more transmissions can be made (block 70, EM).

[0119] After one or more signals have been transmitted (block 72, end), the power amplifier can be disabled and the transmission of the signal from the output TX to the antenna can be blocked, for example by setting the value of the control signal EN2 to a second value.

[0120] Regarding Figures 1 to 5 One advantage of the described embodiment is that the drift seen by the receiving device is reduced.

[0121] Regarding Figures 1 to 5 Another advantage of the described embodiment is that it can be implemented without structural modifications to the circuit 24.

[0122] Regarding Figures 6 to 8 Describe another aspect of this description.

[0123] Figure 6 Schematically illustrates an embodiment of a device 30 including an oscillator circuit. Although some elements may not be shown, the device 30 preferably includes all the elements already described with respect to Figure 1 They will not be described in detail again. In particular, the device 30 includes a quartz crystal 14 and includes an integrated circuit 24 having an RF transmitter 20. The device 30 may also include Figure 6 an antenna 22, a front-end circuit 19, a processing unit 27, etc. not shown in

[0124] The oscillator circuit 12 provides a clock signal (v f ) having a frequency f to the transmitter 20. The oscillator circuit 12 is, for example, a Pierce oscillator.

[0125] The oscillator circuit 12 includes an oscillator 16. The oscillator 16 includes an inverter 47. The output terminal of the inverter 47 is coupled (preferably connected) to a first node 34. The input terminal of the inverter is coupled (preferably connected) to a second node 36. The second node 36 constitutes the output node of the oscillator. The second node 36 is coupled (preferably connected) to the input terminal of the transmitter 20. The clock signal v f is provided at the second node 36.

[0126] The first node 34 is coupled (preferably connected) to the terminal of the variable capacitor (C1) 38. The other terminal of the capacitor 38 is coupled (preferably connected) to the reference node 39 that receives the reference voltage, or is coupled (preferably connected) to the node that applies the reference voltage. Preferably, the reference node 39 is ground.

[0127] The second node 36 is coupled (preferably connected) to the terminal of the variable capacitor (C2) 40. The other terminals of the capacitor 40 are coupled (preferably connected) to the reference node 39 that receives the reference voltage.

[0128] The variable capacitor 38, the inverter 47, and the variable capacitor 40 are coupled (preferably connected) in series with each other in this order.

[0129] The capacitors 38 and 40 are foot capacitors. The capacitors 38 and 40 are used to modify the capacitance seen by the quartz crystal 14 during the calibration phase of the component, so as to compensate for the manufacturing dispersion of the quartz 14. Preferably, the capacitors 38 and 40 are identical to each other (except for manufacturing tolerances).

[0130] The control circuit 32 is configured to control the variable capacitors 38 and 40.

[0131] As will be shown in more detail with respect to Figure 7 an increase in the capacitance values of the variable capacitors 38 and 40 advantageously causes a decrease in the absolute value of the drift of the frequency of the clock signal provided to the circuit 20. However, an increase in the capacitance values of the capacitors 38 and 40 also affects the capacitance value seen by the quartz, and thus affects the value of the center frequency f of the clock signal.

[0132] To compensate for the modification of the capacitance value seen by the quartz, the capacitor 42 (C SERIE ) is coupled (preferably connected) in series with the quartz crystal 14. The capacitor 42 allows a higher capacitance value to be used for the capacitors 38 and 40 while maintaining the capacitance value seen by the quartz substantially equal to the target capacitance C L .

[0133] The quartz crystal 14 and the capacitor 42 are coupled in series between the first node 34 and the second node 36. One terminal of the quartz crystal 14 is coupled (preferably connected) to one terminal of the capacitor 42. The other terminal of the quartz crystal is coupled (preferably connected) to the second node 36, for example. The other terminal of the capacitor 42 is coupled (preferably connected) to the first node 34, for example. As a result, the variable capacitor 38, the capacitor 42, the quartz crystal 14, and the variable capacitor 40 are coupled (preferably connected) in series in this order. The inverter is coupled (preferably connected) in parallel with the assembly of both the quartz 14 and the capacitor 42.

[0134] Alternatively, the variable capacitor 38, the quartz crystal 14, the capacitor 42, and the variable capacitor 40 may be coupled (preferably connected) in series with each other in this order.

[0135] Alternatively, the capacitor 42 may be replaced by two capacitors located on each side of the quartz 14, one between the quartz and the node 34 and the other between the quartz and the node 36. For example, the values of the two capacitors are chosen to be equal to the value of the capacitor 42 together.

[0136] Preferably, the capacitor 42 is a capacitor having a constant capacitance value C SERIE . Preferably, this capacitor is not a variable capacitor. In other words, preferably, the value of the capacitor 42 is not controlled by the control circuit 32. Preferably, the value of the first capacitor 42 is selected based on the target frequency to reduce the equivalent capacitance seen by the quartz relative to the capacitance generated by only the two variable capacitors.

[0137] Preferably, the capacitors 38 and 40 are controlled in such a way that their capacitances are substantially equal. In this example, the target capacitance C L seen by the quartz crystal 14 is equal to: [Mathematical Equation 1]

[0138]

[0139] where C1 is the capacitance value of the capacitor 38, C2 is the capacitance value of the capacitor 40, C SERIE is the capacitance value of the capacitor 42, and C STRAY is the capacitance value of the stray or parasitic capacitance.

[0140] Therefore, the capacitance C SERIE of the capacitor 42 is equal to:

[0141] [Mathematical Equation 2]

[0142]

[0143] where C L is the target value of the capacitance seen by the quartz crystal, and C B is equal to the value C1 and also equal to C2 (C B = C1 = C2).

[0144] For example, if the target value is substantially equal to 10 pF, then if the capacitances C1 and C2 are both equal to 27 pF, and the capacitance C STRAY is equal to 5 pF, then the capacitance C SERIE is equal to 60 pF. More generally, the capacitances C1, C2, and C SERIE are chosen to obtain a capacitance C L in the range of 8 pF to 15 pF.

[0145] Since the chip 24 generally cannot be modified to operate using LoRa technology, the capacitor 42 is not located in the chip 24, for example, but outside the chip 24 (external to the chip 24). In some other embodiments, the capacitor 42 may be located in the chip 24, for example.

[0146] Figure 7 is a graph showing Figure 6 the drift of the frequency of the device (drift (32 MHz) (Hz)) varying with the capacitance value of the foot capacitor (foot capa (pf)) of the oscillator circuit 16.

[0147] The drift value is in units of hertz (Hz), and the capacitance values C1 and C2 are in units of picofarads (pF). At approximately 700 ms after the power amplifier of the circuit 24 is enabled ( Figure 2 at the moment t0), the drift value is obtained. In this example, Figure 3 the moments t0 and t2 are the same. Therefore, these values are obtained during the first second after enabling the power amplifier and starting transmission.

[0148] Figure 7 The figure shows values obtained empirically through simulation or experiment. In the corresponding simulation or experiment, the capacitance value corresponds to the possible values of the variable capacitors 38 and 40. In other words, Figure 7 the capacitance value corresponds to the range of possible values of the variable capacitors 38 and 40. It is considered that the values of the two variable capacitors are equal. This capacitance value is in the range of 11.3 pF to 32.92 pF.

[0149] The drift value is in the range from -4.5 Hz (for capacitance values C1 and C2 that are substantially equal to 11 pF) to -1.5 Hz (for capacitance values C1 and C2 that are substantially equal to 33 pF).

[0150] This value depends on the experimental conditions. However, a general trend can be observed, where the absolute value of the drift decreases as the capacitance value increases. In other words, as the capacitance values of the capacitors 38 and 40 increase, the drift gets closer to zero.

[0151] Therefore, as described above, increasing the capacitance values of the capacitors 38 and 40 has the benefit of reducing the absolute value of the drift. Therefore, within the range of the values of the variable capacitors 38 and 40, it is useful to make the capacitance values of the capacitors 38 and 40 as high as possible. However, to maintain the possibility of slightly adjusting the capacitance values of the capacitors 38 and 40 during the operation of the oscillator circuit 12, it is preferable to select the capacitance values of the capacitors 38 and 40 below their maximum values (for example, with a margin substantially equal to 3 pF).

[0152] Preferably, capacitors 38 and 40 are controlled such that, at least during the first second after the oscillator starts, values C1 and C2 are equal to at least 50% of their maximum value, preferably strictly higher than 50% of their maximum value, preferably between 60% and 85% of their maximum value, for example substantially equal to 75% of their maximum value. As previously mentioned, the capacitance value C is selected SERIE , to correspond to capacitors 38 and 40 having values between 60% and 85% of their maximum value.

[0153] One advantage of the described embodiment is that the drift from the desired frequency is reduced. The drift can be reduced sufficiently to meet the requirements of the device.

[0154] Another advantage of the described embodiment is that relatively few components are added to the device.

[0155] Regarding Figures 8 to 11 describe another aspect of this description.

[0156] Figure 8 A very schematic example of an electronic device 60 capable of emitting RF signals is shown. Device 60 includes Figure 1 all the elements of device 10. Thus, device 60 includes quartz 14, antenna 22, front-end circuit 19, and chip 24. Chip 24 includes oscillator 16, RF circuit 20, processing unit 27, and control circuit 32.

[0157] Device 60 also includes a heater 62 (heater). The heater is a heat-dissipating electronic component. Heater 62 is, for example, a resistive element. For example, heater 62 is in circuit 12 and not in integrated circuit 24.

[0158] Heater 62 is positioned close enough to quartz 14 such that the change in temperature around the heater can affect the quartz. Preferably, the heater is as close as possible to the quartz. For example, the heater is located on the quartz. For example, the heater can be adjacent to the quartz. For example, the distance between heater 62 and quartz 14 is less than 10 mm, preferably less than 5 mm, preferably less than 2 mm. Preferably, the distance between heater 62 and quartz 14 is less than 1 mm. For example, the distance between heater 62 and quartz 14 is substantially equal to 1 mm. For example, the heater is in contact with the quartz.

[0159] Preferably, the heater is only used to heat the quartz. Preferably, the heater is dedicated to the function of preheating quartz 14.

[0160] The heater is, for example, a resistor. For example, the resistance value of the resistor is in the range between 50 ohms and 150 ohms, for example substantially equal to 75 ohms.

[0161] The heater is, for example, part of an electronic circuit that also includes components configured to control the heater 62. For example, if the heater is a resistor, the resistor is part of a circuit configured to send a current through the resistor in order to increase the heat dissipated by the resistor.

[0162] The control circuit 32 generates a control signal EN3 or an enable signal EN3. The control signal EN3 determines the state of the heater, in particular controls whether the heater generates heat. For example, if the heater is a resistor, the control circuit 28 controls the current flowing through the resistor. For example, the signal EN3 can take at least two values: a first value that ensures a given current can flow through the resistor; and a second value that ensures no current can flow through the resistor. In this case, when the control signal EN3 takes the first value, the temperature of the heater and thus the temperature of the quartz increases to a new temperature. When the control signal EN3 takes the second value, the temperature of the heater and thus the temperature of the quartz decreases, for example until the heater reaches the temperature before the control signal EN3 took the first value.

[0163] Figure 9 is a graph showing the effect of temperature variation on quartz. In particular, Figure 9 shows an example of the drift (or Hertz variation (32 MHz)) of the frequency of the clock signal around the carrier frequency (or frequency variation) over time (time (seconds)), where the clock signal is provided by the oscillator circuit to Figure 8 circuit 20.

[0164] The value of the drift corresponds to the desired carrier frequency of 32 MHz. The value of the drift is expressed in Hertz. The value of time is expressed in seconds.

[0165] Figure 9 The variations shown in are not related to the temperature variations caused by the power amplifier 21. For example, Figure 9 The variations shown in correspond to the case where the power amplifier 21 is disabled and has no effect on the temperature.

[0166] During the time range considered in the figure, it can be considered that the quartz and the oscillator have been turned on for a sufficient time to be in a steady state. Therefore, the variations described below are only caused by the temperature variations of the heater 62.

[0167] At time t3, the heater 62 starts to heat up and the first phase P1 starts. More precisely, the control circuit 32 controls the heater 62 in order to increase the temperature of the heater. For example, the control signal EN3 generated by the control circuit 32 takes the first value. For example, the control circuit 32 increases the current flowing through the heater.

[0168] During a first phase P1 after time t3, the temperature of the heater increases. For example, the temperature increases until a threshold and then the increase stops. During the first phase P1, the temperature of the heater is not deliberately decreased.

[0169] A decrease in the value of the drift due to the increase in temperature is observed. The absolute value of the drift decreases.

[0170] In Figure 9 the example, during the first phase, at about 0.30 seconds after time t3, the frequency decreases by about 3.8 Hz.

[0171] At time t4, the first phase P1 ends and the second phase P2 begins. The control circuit 32 stops heating the heater. For example, the control signal EN3 generated by the control circuit 32 takes a first value. For example, the control circuit 32 decreases, preferably stops, the current flowing through the resistor. Thus, during the second phase, the temperatures of the heater and the quartz decrease.

[0172] For example, the temperature decreases until it reaches the temperature at time t3.

[0173] An increase in the value of the drift during the second phase P2 is observed. As time elapses in the second phase P2, the value of the drift becomes further from 0. The absolute value of the drift increases.

[0174] In Figure 9 the example, after about 0.30 seconds, the drift reaches a value that is substantially equal to 3.8 Hz.

[0175] In the first phase P1, the increase in temperature causes a decrease in the drift and thus a decrease in the absolute value of the drift. In the second phase P2, the decrease in temperature causes an increase in the drift and thus an increase in the absolute value of the drift.

[0176] The change in the drift is inversely proportional to the change in temperature. Regarding Figures 8 to 11 the described embodiment, this feature is utilized in order to compensate for the drift caused by the power amplifier 21.

[0177] Figure 10 is a diagram showing an example of the drift obtained by using an embodiment of Figure 8

[0178] In particular, Figure 10 shows an example of the change (or frequency change) over time (time (seconds)) of the drift (or Hertz change (32 MHz)) of the frequency of the clock signal near the carrier frequency, where the clock signal is provided by the oscillator circuit to the Figure 8 circuit 20 of

[0179] The drift value corresponds to the desired carrier frequency of 32 MHz. The drift value is expressed in hertz. The time value is expressed in seconds.

[0180] Figure 10 Represents three curves. The first curve 65 is the same as Figure 8 the curve of, and represents the influence of the change in the temperature of the heater on the drift of the carrier frequency of the clock signal supplied to the circuit 20. The second curve 67 is the same as Figure 2 the curve of, and corresponds to the influence of the heating of the circuit 20 on the value of the drift of the carrier frequency of the clock signal supplied to the circuit 20. The third curve 69 corresponds to the sum of the first and second curves. Therefore, the third curve 69 represents the total drift and the actual drift of the carrier frequency of the clock signal supplied to the circuit 20.

[0181] During the first phase P1, that is, between times t3 and t4, the value of the curve 67 is equal to zero. Therefore, the curve 69 follows the change of the curve 65. Thus, the frequency decreases during the first phase.

[0182] During the first phase, as described with respect to Figure 9 the power amplifier is disabled. Therefore, the control signal EN1 has a second value. Since the circuit 20 is an RF transmitter, the transmitter does not transmit or receive signals during the first phase.

[0183] At the start of the second phase P2, in other words, after time t4, the heater has been stopped. In this example, the drift reaches zero and the frequency is stabilized, and since it may take some time for the quartz temperature to significantly decrease enough to affect the frequency, the drift caused by the quartz remains substantially equal to 0 for a short time (e.g., for less than 0.03 s). In another example, the value of the drift may be different from 0 during this time.

[0184] In addition, at time t4, the power amplifier is still disabled.

[0185] At time t5, the power amplifier is enabled. The time period between times t4 and t5 constitutes the first part P21 of the second phase P2, and the remaining part of the second phase P2 constitutes the second part P22. Alternatively, the first part P21 can be removed. In this variant, times t4 and t5 are simultaneous.

[0186] After time t5, the drift caused by the decreasing temperature of the quartz (curve 65) and the drift caused by the circuit 20 (curve 67) increase in absolute value. However, in relative value, the value of the drift caused by the decreasing temperature of the quartz is positive and increasing, while the value of the drift caused by the circuit 20 is negative and decreasing. Thus, these two components of the total drift tend to compensate each other. In fact, the variation of the total drift (curve 69) is not as pronounced as the variation of each of the two components. The value of the total drift is closer to zero than the value of either of the two component drifts.

[0187] Figure 8 The embodiment of utilizes this compensation in order to reduce the frequency drift (curve 67) caused by the startup of the power amplifier.

[0188] At Figure 10 In the example of Figure 10 , curve 69 varies between approximately -1.3 Hz and approximately 1 Hz during the second part P22, while the value of curve 67 varies between approximately 0 Hz and -4 Hz. During the first second of operation of the circuit 20, for a desired carrier frequency of 32 MHz, the value of curve 69 is within acceptable parameters, which is a drift with an absolute value less than 1.4 Hz.

[0189] Preferably, the duration of the first phase P1 (in other words, the difference between times t3 and t4) is chosen such that the drift caused by the heater reaches zero before time t4. Preferably, the duration of the first part P21 of the second phase is chosen to optimize the compensation of the drift. In fact, the decrease in the drift represented by curve 67 starts shortly after time t5, while the drift represented by curve 65 may take some time (depending on the temperature of the heater) before starting to increase. Thus, it may sometimes be useful to delay time t5 relative to time t4.

[0190] The characteristics of the heater, such as the value of the resistor, the temperature reached, the duration of the first phase, and the duration of part P21, can be chosen according to the application in order to optimize the compensation. In particular, the temperature of the heater and the duration of heating can depend on several factors, such as depending on the size of the device.

[0191] According to one embodiment, the duration between times t2 and t3 is chosen according to the temperature measured by the temperature sensor.

[0192] Figure 11 Illustrates one embodiment of a method for controlling Figure 8 the device of

[0192] .

[0193] At the start of the method (block 70, start), the quartz and the oscillator are already in operation, and a clock signal has been provided to the circuit 20. However, the power amplifier of the circuit 20 is disabled.

[0194] The heater 62 is started by the control circuit 32 (block 72, start heater). This corresponds to time t3. For example, the control signal EN3 takes a first value. As previously mentioned, the function and the temperature reached by the heater depend on the application. This corresponds to the preheating step.

[0195] At this time, the drift caused by the heating of the heater (by both the heater and its operation) is the main cause of the drift of the carrier frequency of the clock signal provided by the oscillator circuit.

[0196] After the duration of the preheating, the control circuit stops heating the heater (block 74, stop heater). This corresponds to time t4. For example, the control signal EN3 takes a second value. The heater and the quartz start to cool. The frequency drift stops decreasing.

[0197] After the step represented by block 74, it is preferred not to use the heater. Preferably, the heater is not used except for heating the quartz during the step represented by block 72, especially during the operation of the circuit 20.

[0198] After that, the transmission of the signal can be started (block 76, start chip). This corresponds to time t5.

[0199] One advantage of the described embodiment is that during the first second of the operation of the conveyor 20, the drift of the carrier frequency is compensated and maintained within the desired parameters.

[0200] Another advantage of the described embodiment is that it is implemented with few modifications and components.

[0201] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily occur to those skilled in the art. In particular, although the embodiments of Figure 6 and Figure 7 as well as the embodiments of Figures 8 to 11 have been described with respect to a half-duplex device, they can be readily adapted to be implemented on a full-duplex device. For example, a full-duplex device can include a switch or an ON / OFF relay between the output TX and the antenna, thereby allowing or stopping the signal from reaching the antenna from the output TX. As described for the switch 29 in this description, this switch will be controlled by the signal EN2.

[0202] In addition, the different described embodiments can be implemented all together or in pairs. For example, Figures 1 to 5 the embodiments of Figures 8 to 11 and Figure 10The moment t5 is enabled, and the transmission of the signal between the output TX and the antenna is enabled after the moment t5, with a delay of D.

[0203] Finally, based on the functional description provided above, the actual implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art.

Claims

1. An electronic device, comprising: A first capacitor and a quartz crystal, serially coupled between a first node and an output node; An inverter having an input terminal coupled to the output node and an output terminal coupled to the first node; A first variable capacitor coupled between the first node and a third node; And A second variable capacitor coupled between the output node and the third node.

2. The device according to claim 1, wherein a capacitance value of the first capacitor is selected based on a target frequency to reduce an equivalent capacitance seen by the quartz crystal relative to a variable capacitor capacitance generated only by the first variable capacitor and the second variable capacitor.

3. The device according to claim 1, wherein the first variable capacitor, the first capacitor, the quartz crystal, the inverter, and the second variable capacitor are included in an oscillator circuit.

4. The device according to claim 3, wherein the oscillator circuit is configured to provide a clock signal at the output node.

5. The device according to claim 4, wherein the output node is coupled to a radio frequency (RF) transmitter.

6. The device according to claim 1, wherein the inverter, and the first variable capacitor and the second variable capacitor are part of an integrated circuit, and wherein the quartz crystal and the first capacitor are not part of the integrated circuit.

7. The device according to claim 1, wherein a capacitance value of the first capacitor is fixed.

8. The device according to claim 1, further comprising a second capacitor coupled between the quartz crystal and the second variable capacitor.

9. The device according to claim 1, further comprising: An RF circuit having a clock input coupled to the output node; An antenna coupled to the RF circuit; An oscillator circuit configured to provide a clock signal to the RF circuit, wherein the oscillator circuit includes the first variable capacitor, the first capacitor, the quartz crystal, the inverter, and the second variable capacitor; And A control circuit configured to: Enable a power amplifier of the RF circuit; And Enable transmission of an RF signal from the RF circuit to the antenna, wherein transmission of the RF signal from the RF circuit to the antenna is delayed relative to a moment when the power amplifier is enabled.

10. The device according to claim 1, further comprising a heater configured to increase a temperature of the quartz crystal.

11. A method for controlling an electronic device, the electronic device including an oscillation circuit, the oscillation circuit comprising: A first capacitor and a quartz crystal, serially coupled between a first node and an output node; An inverter having an input terminal coupled to the output node and an output terminal coupled to the first node; A first variable capacitor coupled between the first node and a third node; And a second variable capacitor coupled between the output node and the third node, the method comprising: Controlling capacitances of the first variable capacitor and the second variable capacitor to be respectively higher than 50% of maximum capacitances of the first variable capacitor and the second variable capacitor; And The clock signal is provided to a radio frequency (RF) circuit and an antenna at the output node by the oscillation circuit.

12. The method according to claim 11 further comprises: The capacitances of the first variable capacitor and the second variable capacitor are controlled to be substantially equal.

13. The method according to claim 11, further comprising: Enabling a power amplifier of the RF circuit; And Enabling the transfer of an RF signal from the RF circuit to the antenna, wherein the transfer of the RF signal from the RF circuit to the antenna is delayed relative to the time when the power amplifier is enabled.

14. The method according to claim 13, further comprising: Selecting a duration of the delay based on a temperature measured by a temperature sensor of the electronic device.

15. The method according to claim 14, wherein the temperature measured by the temperature sensor indicates an ambient temperature.

16. The method according to claim 13, wherein the enabling of the transfer of the RF signal from the RF circuit to the antenna corresponds to a switch being switched from a first position to a second position, the first position being configured such that transmission cannot be transmitted via the antenna, and the second position being configured such that transmission can be transmitted via the antenna.

17. The method according to claim 13, further comprising: Generating a single control signal to enable the power amplifier and to enable the transfer of the RF signal from the RF circuit to the antenna; And Adding the delay to the single control signal before the single control signal reaches a switch coupled between the RF circuit and the antenna, the delay being relative to the single control signal reaching the power amplifier.

18. The method according to claim 13, wherein the duration of the delay is greater than 5 ms.

19. The method according to claim 11 further comprises: Selecting a capacitance value of the first capacitor based on a target frequency to reduce an equivalent capacitance seen by the quartz crystal relative to a variable capacitor capacitance generated only by the first variable capacitor and the second variable capacitor.

20. The method according to claim 11, further comprising: Preheating the quartz crystal by a heater; And Enabling the transmission of a signal as the temperature of the quartz crystal decreases.

Images