Integrated circuit device and method of forming the same, system of integrated circuits

Abstract

An integrated circuit device includes a plurality of first well tap cells of a first semiconductor type and a plurality of second well tap cells of a second semiconductor type different from the first semiconductor type. The plurality of first well tap cells are configured in at least two columns that are adjacent to each other in a first direction and extend in a second direction transverse to the first direction. Each of the plurality of first well tap cells has a first length in the first direction. The plurality of second well tap cells includes at least one second well tap cell that extends in the first direction between the at least two columns over a second length that is greater than the first length of each of the plurality of first well tap cells in the first direction. A method of forming an integrated circuit device and a system of integrated circuits are also disclosed herein.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an integrated circuit device and a method of forming the same, and a system of integrated circuits, and more particularly to an integrated circuit device having well tap cells of different semiconductor types and a method of forming the same, and a system of integrated circuits. BACKGROUND

[0002] An integrated circuit (IC) typically includes a number of semiconductor devices represented in an IC layout. The IC layout is hierarchical and includes modules that perform higher order functions according to the design specifications of the semiconductor devices. The modules are typically constructed from a combination of cells, each of which represents one or more semiconductor structures to perform a particular function. Cells with pre-designed layouts, sometimes referred to as standard cells, are stored in a standard cell library (hereinafter for simplicity, "library" or "cell library") and are accessible through various tools such as electronic design automation (EDA) tools to generate, optimize, and verify a design for an IC. SUMMARY

[0003] According to an embodiment of the present disclosure, an integrated circuit device includes a plurality of first well tap cells of a first semiconductor type, and a plurality of second well tap cells of a second semiconductor type different from the first semiconductor type. The plurality of first well tap cells are configured in at least two columns, the at least two columns being adjacent to each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first well tap cells has a first length in the first direction. The plurality of second well tap cells includes at least one second well tap cell, the at least one second well tap cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first well tap cells in the first direction.

[0004] According to one embodiment of this case, a method for forming an integrated circuit device is disclosed, comprising the following operations: arranging a plurality of first well tap cells of a first semiconductor type in two adjacent columns in an integrated circuit layout; and arranging two second well tap cells of a second semiconductor type different from the first semiconductor type in the integrated circuit layout. The two adjacent columns are adjacent to each other in a first direction, extend in a second direction transverse to the first direction, and are located between the two second well tap cells in the second direction. Each of the plurality of first well tap cells has a first length in the first direction. Each of the two second well tap cells extends continuously in the first direction between the two adjacent columns along a second length greater than the first length of each of the plurality of first well tap cells in the first direction. The arrangement of the plurality of first well tap cells or the arrangement of at least one of the two second well tap cells is performed by a processor.

[0005] According to one embodiment of this application, a system for an integrated circuit is disclosed, including a processor configured to perform well tap unit placement in an integrated circuit layout by arranging a plurality of first well tap units of a first semiconductor type in rows and columns, and arranging a plurality of second well tap units of a second semiconductor type different from the first semiconductor type. Rows extend in a first direction, and columns extend in a second direction transverse to the first direction. Each of the plurality of second well tap units extends in the first direction and overlaps a plurality of the first well tap units in the second direction. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, the appearance of one embodiment of this disclosure will be better understood in the following detailed description. It should be noted that, in accordance with standard industry practice, the various features are not depicted to scale. In fact, for clarity of explanation, the dimensions of various features may be arbitrarily increased or decreased.

[0007] FIG. 1A This is a schematic diagram of an IC layout according to some embodiments;

[0008] FIG. 1B This is a schematic enlarged view of a portion of an IC layout diagram according to some embodiments;

[0009] FIG. 1C A schematic cross-sectional view combined with a schematic circuit diagram of an IC device according to some embodiments;

[0010] FIG. 2 This is a schematic diagram of an IC layout according to some embodiments;

[0011] FIG. 3A This is a schematic diagram of an IC layout according to some embodiments;

[0012] FIG. 3B schematic view of an IC layout according to some embodiments;

[0013] FIG. 4A schematic view of an IC layout according to some embodiments;

[0014] FIG. 4B schematic cross-sectional view in combination with a schematic circuit diagram of an IC device according to some embodiments;

[0015] FIG. 5 flowchart of a method of generating an IC layout according to some embodiments;

[0016] FIG. 6 perspective view of an exemplary transistor with fin features according to some embodiments;

[0017] FIG. 7 block diagram of an EDA system according to some embodiments;

[0018] FIG. 8 block diagram of an IC manufacturing system and an IC manufacturing flow associated with the IC manufacturing system according to some embodiments.

[0019]

Symbolic Representation

[0020] A: unit height

[0021] A1: height

[0022] A2: height

[0023] CPP: pitch

[0024] d: spacing

[0025] 2*DX: first distance

[0026] 2*DY: second distance

[0027] L’, L: length

[0028] L OD : length

[0029] m: length

[0030] Q1 (PNP), Q2 (NPN), Q2’ (PNP), Q1’ (NPN): (parasitic) transistors

[0031] W: height

[0032] R NW ,R PW : resistor

[0033] R Psub ,RNsub : resistor

[0034] Y→Y1, Y'→Y1': arrow

[0035] 100: IC layout

[0036] 110-117: first TAP cell

[0037] 115: N-TAP cell

[0038] 115': P-TAP cell

[0039] 118, 119: column

[0040] 120: second TAP cell

[0041] 121: second TAP cell, P-TAP cell

[0042] 121': N-TAP cell

[0043] 122: first end

[0044] 123: second end

[0045] 124: middle portion

[0046] 130, 132, 134, 136: first well region, N-well

[0047] 134', 136': P-well

[0048] 130': well region

[0049] 131, 133, 135, 137, 139: second well region, P-well

[0050] 137', 139': N-well

[0051] 140: portion

[0052] 141: well region

[0053] 142: OD region

[0054] 143, 144: gate region

[0055] 150, 150': IC device

[0056] 151, 151': substrate

[0057] 151: P-type substrate

[0058] 151': N-type substrate

[0059] 152, 153: P-type active region

[0060] 152', 153': N-type active region

[0061] 155, 156: N-type active region

[0062] 155', 156': P-type active region

[0063] 154, 154', 157, 157': Gate region

[0064] 158, 158': Isolation region

[0065] VDD: First power supply voltage

[0066] VSS: Second power supply voltage

[0067] PMOS: P-channel metal-oxide-semiconductor

[0068] NMOS: N-channel metal-oxide-semiconductor

[0069] 200: IC layout

[0070] 201-20n: Portion

[0071] 300A, 300B: IC layout

[0072] 310: First TAP cell

[0073] 320, 321: Second TAP cell

[0074] 318, 319, 328, 329: Column

[0075] 330, 331: Series

[0076] 332, 333, 334, 335: Second TAP cell

[0077] 400: IC layout

[0078] 500: Method

[0079] 505, 515: Operation

[0080] 600: Circuit element

[0081] 602: Substrate

[0082] 604: Fin feature (or fin)

[0083] 606: Gate dielectric

[0084] 608: Gate electrode

[0085] 610: Source region

[0086] 612: Drain region

[0087] 700: EDA system

[0088] 702: hardware processor, processor

[0089] 704: (non-transitory) computer-readable storage medium, storage medium, memory

[0090] 706: computer program code (instructions)

[0091] 707: library of programs, standard cell library (including standard cells)

[0092] 708: bus

[0093] 710: I / O interface

[0094] 712: network interface

[0095] 714: network

[0096] 742: user interface / UI

[0097] 800: integrated circuit (IC) manufacturing system

[0098] 820: design factory

[0099] 822: IC design layout

[0100] 830: mask factory

[0101] 832: data preparation

[0102] 844: mask manufacturing

[0103] 845: mask

[0104] 850: IC manufacturer / fabricator, (IC) manufacturing

[0105] 852: wafer manufacturing

[0106] 853: semiconductor wafer

[0107] 860: IC device DETAILED DESCRIPTION

[0108] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. The following description of a particular instance of components, materials, values, steps, operations, materials, configurations, etc. is merely for simplicity of this embodiment of the present disclosure. Of course, these are just examples and are not intended to be limiting. Other components, values, operations, materials, configurations, etc. are contemplated. For example, the formation of a first feature above or on a second feature in the following description can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which additional features can be formed between the first and second features such that the first and second features can not be in direct contact. In addition, the present disclosure can repeat use of certain elements or / and letters in various examples. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0109] Furthermore, to facilitate description, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for describing the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0110] A well tap cell, referred to herein as a "TAP cell", is a standard cell that defines a region in a doped well, where the doped well is coupled to a bias, such as a power supply voltage. TAP cells are included in an IC layout to improve the latch-up immunity of an IC fabricated according to the IC layout.

[0111] With the current trend of scaling down semiconductor devices, the placement of TAP cells in an IC layout for fabricating an IC incurs one or more considerations, including but not limited to process bottlenecks due to reduced lithography critical dimensions (CDs), and mixed channel effects. To address one or more of these considerations, in an IC layout according to some embodiments, first TAP cells of a first semiconductor type (e.g., N-type or P-type) are placed in rows and columns, and second TAP cells of a different second semiconductor type (e.g., P-type or N-type) are placed in an elongated group or strip shape across multiple columns of the first TAP cells. Thus, in at least one embodiment, it is possible to achieve one or more effects, including but not limited to, relaxation of process constraints, increase in latch-up immunity, reduction in area occupied or blocked by TAP cells, and increase in area where standard cells other than TAP cells can be placed.

[0112] FIG. 1AA schematic view of an IC layout 100 of an IC device according to some embodiments. The IC layout 100 comprises a plurality of first TAP cells 110-117 of a first semiconductor type, and a plurality of second TAP cells 120, 121 of a second semiconductor type different from the first semiconductor type. The first TAP cells 110-117 are arranged in at least two columns 118, 119. For example, the first TAP cells 110, 112, 114, 116 are arranged in the column 118, and the first TAP cells 111, 113, 115, 117 are arranged in the column 119. The columns 118, 119 are adjacent to each other in a first direction, e.g. the X-direction, and extend in a second direction, e.g. the Y-direction, transverse to the first direction. At least one of the second TAP cells 120, 121 extends in the X-direction over a length L that is larger than a length L’ of each of the first TAP cells 110-117 in the X-direction, between the columns 118, 119. At least one of the second TAP cells 120, 121 overlaps at least one first TAP cell in at least one of the columns 118, 119 in the Y-direction along the page.

[0113] In FIG. 1A In an exemplary configuration in which the second TAP cell 120 is elongated in the X-direction, and has a length L in the X-direction that is larger than its height in the Y-direction. The second TAP cell 120 overlaps the first TAP cells 110-117 in the Y-direction. For example, the second TAP cell 120 extends continuously in the X-direction from a first end 122 thereof to a second end 123 thereof. The first end 122 of the second TAP cell 120 overlaps the first TAP cells 110, 112, 114, 116 in the column 118 in the Y-direction. The second end 123 of the second TAP cell 120 overlaps the first TAP cells 111, 113, 115, 117 in the column 119 in the Y-direction. An intermediate portion 124 of the second TAP cell 120 is between the first end 122 and the second end 123, and does not overlap any of the first TAP cells 110-117 in the Y-direction. The second TAP cell 121 has an elongated configuration similar to the configuration described above with respect to the second TAP cell 120. The second TAP cells 120, 121 are adjacent to each other in the Y-direction, and there are no other TAP cells of the second semiconductor type between the second TAP cells 120, 121. Between the second TAP cells 120, 121 are sandwiched multiple rows and columns of first TAP cells, namely two columns 118, 119, and four rows formed by the first TAP cells 110 and 111, the first TAP cells 112 and 113, the first TAP cells 114 and 115, and the first TAP cells 116 and 117, respectively.

[0114] The above with respect to FIG. 1AThe configurations described are examples, and other configurations are within the scope of various embodiments. For example, some embodiments include a different number of first TAP cells in each of columns 118, 119 and / or a different number of rows of first TAP cells between each pair of adjacent second TAP cells 120, 121. In at least one embodiment, at least one of second TAP cells 120, 121 has a different configuration than described above with respect to FIG. 1A The configurations described. For example, at least one of first end 122 or second end 123 of second TAP cell 120 does not overlap the corresponding column 118 or 119 in the Y direction. For another example, second TAP cells 120, 121 have different lengths in the X direction. In another example, at least one of second TAP cells 120, 121 is not a single second TAP cell that extends continuously in the X direction as described above with respect to FIG. 1A The configurations described. For example, at least one of first end 122 or second end 123 of second TAP cell 120 does not overlap the corresponding column 118 or 119 in the Y direction. For another example, second TAP cells 120, 121 have different lengths in the X direction. In another example, at least one of second TAP cells 120, 121 is not a single second TAP cell that extends continuously in the X direction as described above with respect to FIG. 3B The configurations described. For example, at least one of first end 122 or second end 123 of second TAP cell 120 does not overlap the corresponding column 118 or 119 in the Y direction. For another example, second TAP cells 120, 121 have different lengths in the X direction. In another example, at least one of second TAP cells 120, 121 is not a single second TAP cell that extends continuously in the X direction as described above with respect to

[0115] IC layout 100 further includes first well regions 130, 132, 134, 136 of a first semiconductor type and a plurality of second well regions 131, 133, 135, 137, 139 of a second semiconductor type. First well regions 130, 132, 134, 136 and second well regions 131, 133, 135, 137, 139 extend in the X direction and are alternately arranged in the Y direction. Each of first TAP cells 110-117 is in a corresponding one of first well regions 130, 132, 134, 136, and each of second TAP cells 120, 121 is in a corresponding one of second well regions 131, 133, 135, 137, 139. For example, first TAP cells 110 and 111 are in first TAP cell 130, first TAP cells 112 and 113 are in first TAP cell 132, first TAP cells 114 and 115 are in first TAP cell 134, and first TAP cells 116 and 117 are in first TAP cell 136, while second TAP cell 120 is in second well region 131 and second TAP cell 121 is in second well region 139.

[0116] In FIG. 1AIn the exemplary configuration of FIG. 1, the first semiconductor type is N-type and the second semiconductor type is P-type. In other words, the first well regions 130, 132, 134, 136 are N-type well regions (hereinafter “N-wells”), the second well regions 131, 133, 135, 137, 139 are P-type well regions (hereinafter “P-wells”), the first TAP cells 110-117 are N-type TAP cells (hereinafter “N-TAP cells”), and the second TAP cells 120, 121 are P-type TAP cells (hereinafter “P-TAP cells”). An N-well is a region that includes N-type dopants, and a P-well is a region that includes P-type dopants. In the figures, N-wells are labeled “NW”, P-wells are labeled “PW”, N-type dopants are labeled “N+”, and P-type dopants are labeled “P+”.

[0117] An N-TAP cell is a region in an N-well, but has a higher concentration of N-type dopants than the N-type dopants of the N-well itself. For example, the N-TAP cell 110 has a higher concentration of N-type dopants than the N-type dopants of the N-well 130 in which the N-TAP cell 110 is formed. A P-TAP cell is a region in a P-well, but has a higher concentration of P-type dopants than the P-type dopants of the P-well itself. For example, the P-TAP cell 120 has a higher concentration of P-type dopants than the P-type dopants of the P-well 131 in which the P-TAP cell 120 is formed.

[0118] In an N-well, P-type active regions having P-type dopants are disposed in regions not occupied or blocked by N-TAP cells to form one or more circuit elements. In a P-well, N-type active regions having N-type dopants are disposed in regions not occupied or blocked by P-TAP cells to form one or more circuit elements. Examples of circuit elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), etc., FinFETs, planar MOS transistors with elevated source / drain, etc. For example, in the N-wells 130, 132, 134, 136, P-type active regions (not shown in FIG. 1, but described herein with respect to FIG. 2) having P-type dopants are disposed in regions not occupied or blocked by N-TAP cells 110-117 to form one or more circuit elements. In the P-wells 131, 133, 135, 137, 139, N-type active regions (not shown in FIG. 1, but described herein with respect to FIG. 2) having N-type dopants are disposed in regions not occupied or blocked by P-TAP cells 120, 121 to form one or more circuit elements. FIG. 1A FIG. 1C ​The P-well 133, 135, 137 is configured in an area not occupied or blocked by the NTAP cells 110-117 to define a P-channel metal-oxide-semiconductor (PMOS) region for forming PMOS transistors. In the P-well 133, 135, 137, N-type active regions (not shown in FIG. 1A but described herein with respect to FIG. 1C The N-well 131 is configured in an area not occupied or blocked by the PTAP cells 120, 121 to define an N-channel metal-oxide-semiconductor (NMOS) region for forming NMOS transistors. The cells with the pre-designed layout are read from the cell library and placed in the IC layout 100 such that the NMOS transistors of the cells are configured in the NMOS region and the PMOS transistors of the cells are configured in the PMOS region. The NTAP cells, the PTAP cells, the N-type active regions, and the P-type active regions are sometimes collectively referred to as oxide-definition (OD) regions and are schematically illustrated in FIG. 1B with the label "OD".

[0119] The IC layout 100 further includes gate regions (not shown in FIG. 1A but described herein with respect to FIG. 1B The gate regions include an electrically conductive material, such as polysilicon, and are schematically illustrated in FIG. 1B with the label "Poly". Other electrically conductive materials for the gate regions, such as metal, are within the scope of various embodiments. The gate regions extend, or are elongated, in the Y direction across the OD regions. The Y direction is also referred to herein as the poly direction. In some embodiments, each OD region has one or more fin features configured therein. Such fin features extend, or are elongated, in the X direction and are spaced apart from each other in the Y direction. The X direction is also referred to herein as the fin direction. Examples of fin features are described with respect to FIG. 6 .

[0120] In at least one embodiment, the number of fin features in each of the first TAP cells 110-117 and the number of fin features in each of the second TAP cells 120, 121 satisfy the following relationship:

[0121] F2 / F1 ≥ (DY / DX)*(L / A) (1)

[0122] where F1 is the number of fin features in each of the first TAP cells 110-117, F2 is the number of fin features in each of the second TAP cells 120, 121 elongated in the X direction, DX is half of a first distance 2*DX in the X direction between facing sides of the first TAP cells in adjacent columns 118, 119, DY is half of a second distance 2*DY in the Y direction between facing sides of the second TAP cells 120, 121, L is a length of the second TAP cells 120 or 121 in the X direction, and A is a cell height in the Y direction, and is a sum of a height Al of the first well region (e.g., 132) and a height A2 of the adjacent second well region (e.g., 135).

[0123] In FIG. 1A an exemplary configuration, F1 is the number of fin features F NTAP in each NTAP cell, and F2 is the number of fin features F PTAP in each PTAP cell, and the relationship (1) becomes

[0124] F PTAP / F NTAP ≥ (DY / DX)*(L / A) (1’)

[0125] By configuring the NTAP cells and the PTAP cells to have different configurations and to satisfy the relationship (1) or (1’), it is possible in some embodiments to match or improve a latch-up (LUP) immunity index compared to another approach. In particular, the LUP immunity index of an IC device corresponding to the IC layout 100 is determined by the following relationship

[0126] V = Jbody*L*(A / 2)*(2DY / A)*(Rc / F PTAP ) (2)

[0127] where V is the LUP immunity index represented by a voltage drop caused by a leakage current Jbody in the IC device, and Rc is a unit resistance. The lower the voltage drop V, the better the LUP immunity of the IC device.

[0128] In another approach where the NTAP cells and the PTAP cells are configured similarly to each other and similarly to the NTAP cells 110-117, the LUP immunity index V’ of an IC device according to the other approach is determined by the following relationship

[0129] V’ = Jbody*2DX*(A / 2)*(Rc / F NTAP ) (3)

[0130] To match or improve the LUP immunity index compared to the other approach, the following relationship will be satisfied:

[0131] V≤ V' (4)

[0132] Based on relations (2), (3), and (4), relations (1') and (1) are obtained.

[0133] In some embodiments, the IC layout 100 satisfies at least one of DY from 0.5 pm to 1000 pm, DX from 0.05 pm to 100 pm, L from 0.1 pm to 5000 pm, or A from 0.025 pm to 0.300 pm. The range of 0.025 pm to 0.300 pm for the cell height A corresponds to one or more considerations and / or constraints in exemplary semiconductor manufacturing processes. At the range of 0.025 pm to 0.300 pm for the cell height A, if DX is below the range of 0.05 pm to 100 pm and / or if DY is below the range of 0.5 pm to 1000 pm, there is an excessive increase of the wafer area for the TAP cells and an associated decrease of the remaining wafer area for other functional cells of the IC layout 100. At the range of 0.025 pm to 0.300 pm for the cell height A, if DX exceeds the range of 0.05 pm to 100 pm and / or if DY exceeds the range of 0.5 pm to 1000 pm, there is an elevated risk of latching. The range of 0.1 pm to 5000 pm for the length L of the elongated TAP cell (e.g., 120 or 121) is derived from the respective range(s) for A, DX, and / or DY based on relation (1) or (1').

[0134] FIG. 1B A schematic zoomed-in view of a portion 140 of the IC layout 100 according to some embodiments for describing an example to determine a number of fin features in a TAP cell. The portion 140 includes a well region 141, an OD region 142, and a plurality of gate regions 143, 144. The well region 141 extends in the X-direction and encloses or encloses the OD region 142 therein. The OD region 142 includes one or more fin features (not shown) extending in the X-direction. The OD region 142 has a length L OD in the X-direction and a height W in the Y-direction. The gate regions 143, 144 extend across the OD region 142 in the Y-direction and are configured at a pitch CPP in the X-direction.

[0135] The number F of fin features in the OD region 142 is determined by the following relation

[0136] F = (L OD / CPP) * W * Fn (5)

[0137] where Fn is a number of fin features per unit height in the Y-direction. In at least one embodiment, CPP and W are the same for all TAP cells.

[0138] In one example, the portion 140 corresponds to a region of the first TAP cells 110 containing, for example, FIG. 1A In particular, the well region 141 corresponds to the first well region 130, the OD region 142 corresponds to the first TAP cell 110, L OD corresponds to the length L' of the first TAP cell 110, W corresponds to the height of the first TAP cell 110 in the Y-direction, and F corresponds to F1 or F NTAP Thus, the number of fin features in each first TAP cell can be determined from relation (5).

[0139] In another example, the portion 140 corresponds to a region of the second TAP cells 120 containing, for example, FIG. 1A In particular, the well region 141 corresponds to the second well region 131, the OD region 142 corresponds to the second TAP cell 120, L OD corresponds to the length L of the second TAP cell 120, W corresponds to the height of the second TAP cell 120 in the Y-direction, and F corresponds to F2 or F PTAP Thus, the number of fin features in each second TAP cell can also be determined from relation (5).

[0140] FIG. 1C is a schematic cross-sectional view of an IC device 150 according to some embodiments. The IC device 150 corresponds to a portion of the IC layout 100 indicated by the arrow Y→Y1 in FIG. 1A is a schematic cross-sectional view of an IC device 150 according to some embodiments. The IC device 150 corresponds to a portion of the IC layout 100 indicated by the arrow Y→Y1 in FIG. 1C is a schematic cross-sectional view of an IC device 150 according to some embodiments. The IC device 150 corresponds to a portion of the IC layout 100 indicated by the arrow Y→Y1 in

[0141] The IC device 150 includes a substrate 151, with respect to FIG. 1A and FIG. 1BThe described TAP cell, well region, active region, gate region, and fin features are formed on the substrate. For example, IC device 150 includes N-well 134, P-well 137, N-well 136, and P-well 139 on substrate 151. P-type active regions 152 and 153, and NTAP cell 115 are formed in N-well 134. Gate region 154 is formed above P-type active regions 152 and 153, and together with P-type active regions 152 and 153, defines a PMOS. N-type active regions 155 and 156 are formed in P-well 137. Gate region 157 is formed above N-type active regions 155 and 156, and together with N-type active regions 155 and 156, defines an NMOS. PTAP cell 121 is formed in P-well 139. IC device 150 further includes a plurality of isolation regions 158 between adjacent P-wells and N-wells. The P-type active region 152 of the PMOS is coupled to a first power supply voltage, such as VDD. The N-type active region 156 of the NMOS is coupled to a second power supply voltage, such as VSS, which is ground in at least one embodiment. The substrate 151 is a P-type substrate.

[0142] FIG. 1C A schematic circuit diagram of the IC device 150 shows parasitic transistors Q1 and Q2. Parasitic transistor Q1 is a PNP transistor formed through a P-type active region 152, an N-well 134, and a P-type substrate 151. Parasitic transistor Q2 is an NPN transistor formed through an N-well 134, a P-well 137, and an N-type active region 156. In the absence of NTAP cell 115 and / or PTAP cell 121, there is a problem that leakage current in one or more of the P-type substrate 151, P-well, and N-well of the IC device 150 is sufficient to turn on both parasitic transistors Q1 and Q2, creating a current path from VDD, through the turned-on parasitic transistors Q1 and Q2, to VSS. This current path between VDD and VSS is a latch-up condition that adversely affects the performance of the IC device 150.

[0143] The NTAP unit 115 coupled to VDD and the PTAP unit 121 coupled to VSS provide the possibility of reducing latch-up situations and improve the LUP immunity of the IC device 150. FIG. 1A In the schematic circuit diagram of IC device 150, resistor R NW The resistor R represents the TAP cell resistance between the NTAP cell represented by NTAP cell 115 and the substrate of parasitic transistor Q1. Psub This represents the TAP cell resistance between the PTAP cell represented by PTAP cell 121 and the substrate of parasitic transistor Q2. Resistor R NW and R Psub The lower the resistance, the lower the probability that parasitic transistors Q1 and Q2 will turn on separately, and the better the LUP immunity of the IC device 150. Resistor RNW The resistance depends on the configuration and / or setup of the NTAP unit. Resistor R Psub The resistance depends on the configuration and / or setup of the PTAP unit. For example, refer to... FIG. 1A When the distance 2*DY between adjacent extended second TAP units 120 and 121 increases, the resistor R Psub The resistance increases; however, when the length L or number of the fin features of the elongated second TAP units 120, 121 increases, the resistance R... Psub The resistance is reduced. By assembling and / or configuring NTAP units and / or PTAP units as described herein, it is possible to improve the LUP immunity of IC device 150 in at least one embodiment.

[0144] As described in this paper, some other methods for TAP cell placement suffer from potential problems. For example, in a first method, the TAP cell is placed in a half-cell height configuration spanning the boundary between the P-well and the N-well. This half-cell height configuration faces manufacturing difficulties, especially at CD below 100 nm. Conversely, as discussed in... FIG. 1A to FIG. 1B As described, in some embodiments, the TAP cells are completely surrounded within their respective well regions, thus avoiding the manufacturing difficulties associated with half-cell height configurations. For another instance, in the described first method and in various second methods, there is a problem with a mixed channel effect attributable to the placement discontinuity between closely configured NTAP cells and PTAP cells. Such problems with the mixed channel effect are eliminated by one or more embodiments described herein. In some embodiments, it is possible to achieve one or more effects, including but not limited to relaxing process constraints, particularly at advanced manufacturing process nodes, improving latch-up immunity, reducing the area occupied or blocked by TAP cells, and increasing the area where standard cells other than TAP cells can be placed. In some further embodiments, it is possible to improve latch-up immunity and / or reduce the area occupied or blocked by TAP cells even without process constraints at advanced manufacturing process nodes. In one example, the area occupied or blocked by TAP cells is reduced in at least one embodiment to about 85% of that area observed in other methods without sacrificing LUP immunity.

[0145] FIG. 2 This is a schematic diagram of an IC layout diagram 200 according to some embodiments. The IC layout diagram 200 includes a plurality of portions 201, 201, ... 20n, which are arranged at regular intervals in the X and Y directions. TAP units are similarly disposed in each of the portions 201, 201, ... 20n. For example, in each of the portions 201, 201, ... 20n, the TAP unit is as described in at least one embodiment regarding... FIG. 1A The described placement. (For example, regarding...) FIG. 3A ,FIG. 3B , and FIG. 4A other TAP cells described can be disposed in the context of various embodiments. Thus, the TAP cells are disposed on the IC layout 200 at regular intervals and in a repeating pattern to ensure a predetermined LUP immunity on the IC layout 200. In some embodiments, the configurations, modifications, advantages, or effects described with respect to FIG. 1A may be achieved in the IC layout 200.

[0146] FIG. 3A is a schematic diagram of an IC layout 300A according to some embodiments. In at least one embodiment, the IC layout 300A corresponds to any one of the portions 201, 201,... 20n in FIG. 2 Similar to the IC layout 100, the IC layout 300A includes a plurality of first TAP cells, represented by 310, and a plurality of second TAP cells 320, 321. The first TAP cells 310 correspond to the first TAP cells 110-117 of the IC layout 100, but are configured in more than two columns, e.g., in four columns 318, 319, 328, 329. The second TAP cells 320, 321 correspond to the second TAP cells 120, 121, and extend in the X-direction across the four columns 318, 319, 328, 329 of the first TAP cells 310. In some embodiments, the configurations, modifications, advantages, or effects described with respect to FIG. 1A may be achieved in the IC layout 300A.

[0147] FIG. 3B is a schematic diagram of an IC layout 300B according to some embodiments. In at least one embodiment, the IC layout 300B corresponds to any one of the portions 201, 201,... 20n in FIG. 2any one of the portions 201, 201,... 20n in the IC layout 100. Similar to the IC layout 300A, the IC layout 300B includes a plurality of first TAP cells 310 configured in four columns 318, 319, 328, 329. However, instead of each of the consecutive second TAP cells 320, 321 in the IC layout 300A, the IC layout 300B includes a series 330, 331 of discrete second TAP cells represented FIG. 1A The described configurations, modifications, advantages, or effects can be achieved in the IC layout 300B.

[0148] FIG. 4A is a schematic illustration of an IC layout 400 according to some embodiments. Except that the P-type regions, wells, or TAP cells in the IC layout 400 correspond to the N-type regions, wells, or TAP cells in the IC layout 100, and vice versa, FIG. 4A the IC layout 400 in FIG. 1A the IC layout 100 in FIG. 4A the elements in FIG. 1A are indicated by the same element symbols as the corresponding elements in FIG. 4A with a prime added to the FIG. 4A for example, the well region 130’ in FIG. 1A corresponds to the well region 130 in FIG. 4B In at least one embodiment, an IC device corresponding to the IC layout 400 is formed on an N-type substrate, as described with respect to

[0149] FIG. 4B is a schematic cross-sectional view of an IC device 150’ according to some embodiments. The IC device 150’ corresponds to the IC device 150 in FIG. 4AThe arrow Y'Y1' in the diagram indicates a portion of the IC layout diagram 400. FIG. 4B The cross-sectional view is also combined with the schematic circuit diagram of IC device 150'. Except that the P-type substrate, region, well, and TAP unit in IC device 150' correspond to the N-type substrate, region, well, and TAP unit in IC device 150, and vice versa, FIG. 4B The IC device 150' in the middle is similar to FIG. 1C IC device 150 in the middle. FIG. 4B The components in the middle are connected with FIG. 1C The corresponding element in the text has the same component symbol indication, but has been added to... FIG. 4B The single-stroke symbol. For example, FIG. 4B The substrate 151' in the middle corresponds to FIG. 1C Substrate 151 in the middle. Furthermore... FIG. 4B NMOS, PMOS, Q1' (NPN), Q2' (PNP), R PW and R Nsub Corresponding to FIG. 1C PMOS, NMOS, Q1 (PNP), Q2 (NPN), R NW and R Psub .

[0150] In some embodiments, regarding FIG. 1A IC layout diagram 100 and / or FIG. 1C The configuration, operation, modification, advantages or effects described in the IC device 150 can be found in FIG. 4A IC layout diagram 400 and / or FIG. 4B The IC device 150' is achieved in the IC layout. Some embodiments include IC layouts similar to IC layouts 300A or 300B, but with similar changes from P-type substrates, wells, regions or TAP cells to N-type substrates, wells, regions or TAP cells, and vice versa.

[0151] FIG. 5 This is a flowchart of a method 500 for placing TAP cells in an IC layout diagram according to some embodiments. In at least one embodiment, method 500 is executed wholly or partially by a processor as described herein to produce an IC layout diagram corresponding to at least one of IC layout diagrams 100, 200, 300A, 300B, and 400.

[0152] At operation 505, multiple first TAP units are arranged in the IC layout diagram such that the first TAP units are configured in two adjacent columns. For example, as per [reference to...] FIG. 1AAs described, a plurality of first TAP cells 110-117 are disposed in the IC layout 100 such that the first TAP cells 110-117 are configured in two adjacent columns 118, 119. The two adjacent columns 118, 119 are adjacent to each other in a first direction, e.g., the X direction, and extend in a second direction, e.g., the Y direction, that is transverse to the first direction. The first TAP cells 110-117 are of a first semiconductor type, e.g., N-type as in FIG. 1A or P-type as in FIG. 4A .

[0153] At operation 515, two second TAP cells of a second semiconductor type different from the first semiconductor type are disposed in the IC layout. Each of the two second TAP cells extends continuously between the two adjacent columns of the first TAP cells over a second length that is greater than a first length of each of the first TAP cells. For example, as described with respect to FIG. 1A , two second TAP cells 120, 121 are disposed in the IC layout 100. Each of the two second TAP cells 120, 121 extends continuously between the two adjacent columns 118, 119 of the first TAP cells 110-117 over a length L that is greater than a length L’ of each of the first TAP cells 110-117. The two adjacent columns 118, 119 of the first TAP cells 110-117 are located between the two second TAP cells 120, 121 in the Y direction. The second TAP cells 120, 121 are of a second semiconductor type, e.g., P-type as in FIG. 1A or N-type as in FIG. 4A .

[0154] In at least one embodiment, operations 505 and 515 occur, e.g., in parallel, at one place and route IC fabrication flow. In one or more embodiments, the first TAP cells and / or the second TAP cells are standard cells stored in and read from one or more cell libraries. In some embodiments, operations 505 and 515 are performed to dispose TAP cells on the IC layout at regular intervals and in a repeating pattern, as described with respect to FIG. 2 .

[0155] The described methods include exemplary operations, but these exemplary operations need not be performed in the order indicated. Operational combinations of different features and / or embodiments are within the scope of embodiments consistent with the present disclosure and will be apparent to persons of ordinary skill in the art upon review of the present disclosure. It is intended that any and all embodiments disclosed or described herein can be combined with one another, unless specific indications to the contrary are noted.

[0156] FIG. 6A perspective view of an exemplary circuit element 600 having fin features, in accordance with some embodiments. In FIG. 6 In an exemplary configuration in FIG. 6, the circuit element 600 is a fin field-effect transistor (FINFET). The FINFET 600 includes a substrate 602, at least one fin feature (or fin) 604 extending from the substrate 602 in the Z-direction, a gate dielectric 606 along a surface of the fin 604, and a gate electrode 608 over the gate dielectric 606. A source region 610 and a drain region 612 are disposed over the substrate 602 on opposite sides of the fin 604. The fin 604, the source region 610, and the drain region 612 are active regions (or OD regions), which in one or more embodiments correspond to any of the active regions described with respect to FIG. 1A to FIG. 4B The gate electrode 608 corresponds to any of the gate regions described with respect to FIG. 1A to FIG. 4B The described configuration of fin features in active regions is an example. Other configurations are within the scope of various embodiments.

[0157] In some embodiments, some or all of the methods discussed above are performed by an IC layout generation system. In some embodiments, the IC layout generation system can be used as part of a design factory for an IC manufacturing system discussed below.

[0158] FIG. 7 A block diagram of an EDA system 700, in accordance with some embodiments.

[0159] In some embodiments, the EDA system 700 includes an automated placement and routing (APR) system. The methods described herein of designing a layout and representing wire routing configurations, in accordance with one or more embodiments, are implementable, for example, using the EDA system 700, in accordance with some embodiments.

[0160] In some embodiments, the EDA system 700 is a general purpose computing device that includes a hardware processor 702 and a non-transitory computer-readable storage medium 704. Among other things, the storage medium 704 is encoded with computer program code 706, i.e., a set of executable instructions. Execution of the instructions 706 by the hardware processor 702 represents (at least in part) an EDA tool that implements some or all of the methods described herein, e.g., processes and / or methods, in accordance with one or more embodiments.

[0161] The processor 702 is electrically coupled through the bus 708 to the computer readable storage medium 704. The processor 702 is also electrically coupled through the bus 708 to the I / O interface 710. The network interface 712 is also electrically connected to the processor 702 through the bus 708. The network interface 712 is connected to a network 714 so that the processor 702 and the computer readable storage medium 704 can be connected to external elements through the network 714. The processor 702 is used to execute computer program code 706 encoded in the computer readable storage medium 704 in order to cause the EDA system 700 to perform part or all of the processes and / or methods. In one or more embodiments, the processor 702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0162] In one or more embodiments, the computer readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and / or a semi-conductor system (or apparatus or device). For example, the computer readable storage medium 704 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disc, and / or an optical disc. In one or more embodiments using optical discs, the computer readable storage medium 704 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disc (DVD).

[0163] In one or more embodiments, the storage medium 704 stores computer program code 706 to cause the EDA system 700 (where this execution represents (at least partially) an EDA tool) to perform part or all of the processes and / or methods. In one or more embodiments, the storage medium 704 also stores information that facilitates performing part or all of the processes and / or methods. In one or more embodiments, the storage medium 704 stores a library 707 of standard cells including HPC cells as disclosed herein.

[0164] EDA system 700 includes I / O interface 710. I / O interface 710 is coupled to external circuits. In one or more embodiments, I / O interface 710 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor direction keys for communicating information and commands to processor 702.

[0165] EDA system 700 also includes network interface 712, which is coupled to processor 702. Network interface 712 allows EDA system 700 to communicate with network 714, to which one or more other computer systems are connected. Network interface 712 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE- 1364. In one or more embodiments, some or all of the processes and / or methods are performed in two or more EDA systems 700.

[0166] EDA system 700 is configured to receive information through I / O interface 710. The information received through I / O interface 710 includes one or more of instructions, data, design rules, a library of standard cells, and / or other parameters for use in processes by processor 702. The information is passed through bus 708 to processor 702. EDA system 700 is configured to receive information related to a UI through I / O interface 710. The information is stored in computer-readable media 704 as user interface (UI) 742.

[0167] In some embodiments, some or all of the processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, some or all of the processes and / or methods are implemented as part of an additional software application. In some embodiments, some or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the processes and / or methods are implemented as a software application used by EDA system 700. In some embodiments, the placement of standard cells is generated using a tool such as the tool available from CADENCE DESIGN SYSTEMS, Inc. under the brand name LEGACY, or another suitable placement tool.

[0168] ​In some embodiments, the processes are implemented as functions of programs stored in a non-transitory computer readable recording medium. Examples of the non-transitory computer readable recording medium include, but are not limited to, one or more of external / transportable / internal / built-in storage or memory units, such as an optical disc like a DVD, a magnetic disc like a hard disk, a semiconductor memory like a ROM, a RAM, a memory card, and the like.

[0169] FIG. 8 A block diagram of an integrated circuit (IC) manufacturing system 800 and IC manufacturing processes associated with the IC manufacturing system according to some embodiments. In some embodiments, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is manufactured using the manufacturing system 800 based on a layout.

[0170] In FIG. 8 In some embodiments, the IC manufacturing system 800 includes entities such as a design house 820, a mask house 830, and an IC manufacturer / fabricator ("fab") 850 that interact with each other in a design, development, and manufacturing cycle and / or services related to manufacturing IC devices 860. The entities in the system 800 are connected through a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is various different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or receives services from one or more of the other entities. In some embodiments, two or more of the design house 820, the mask house 830, and the IC fab 850 are owned by a single larger company. In some embodiments, two or more of the design house 820, the mask house 830, and the IC fab 850 coexist in a common facility and use common resources.

[0171] A design factory (or design team) 820 generates an IC design layout 822. The IC design layout 822 includes various geometric patterns designed for the IC device 860. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various components of the IC device 860 to be fabricated. Various layers are combined to form various IC features. For example, a portion of the IC design layout 822 includes various IC features such as active regions, gate electrodes, source and drain, metal interconnects or vias of intermediate layers, and openings for spacers to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design factory 820 performs appropriate design procedures to form the IC design layout 822. The design procedures include one or more of logic design, physical design, or placement and routing. The IC design layout 822 is represented in one or more data files having information of geometric patterns. For example, the IC design layout 822 is expressed in a GDSII file format or a DFII file format.

[0172] The mask factory 830 includes data preparation 832 and mask fabrication 844. The mask factory 830 uses the IC design layout 822 to fabricate one or more masks 845 to be used in fabricating various layers of the IC device 860 according to the IC design layout 822. The mask factory 830 performs mask data preparation 832 in which the IC design layout 822 is converted into a representative data file ("RDF"). The mask data preparation 832 provides the RDF to the mask fabrication 844. The mask fabrication 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate such as a mask (reticle) 845 or a semiconductor wafer 853. The design layout 822 is manipulated by the mask data preparation 832 to conform to characteristics of the mask writer and / or requirements of the IC fabrication 850. In FIG. 8 In some embodiments, the mask data preparation 832 and the mask fabrication 844 can be collectively referred to as mask data preparation.

[0173] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for image errors such as can result from diffraction, interference, other process effects, and the like. OPC adjusts IC design layout 822. In some embodiments, mask data preparation 832 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0174] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that checks IC design layout 822 that has been processed in OPC with a set of mask creation rules that contain certain geometric and / or connectivity restrictions to ensure sufficient margins to address variability in semiconductor manufacturing processes, among other things. In some embodiments, MRC modifies IC design layout 822 to compensate for restrictions during mask fabrication 844, which can cancel out portions of the modifications performed by OPC in order to satisfy the mask creation rules.

[0175] In some embodiments, mask data preparation 832 includes lithography process checking (LPC) that simulates processing to be performed by IC fabrication 850 to fabricate IC device 860. LPC simulates this processing based on IC design layout 822 to create a simulated fabricated device, such as IC device 860. Processing parameters in LPC simulation can include parameters associated with various processes of an IC fabrication cycle, parameters associated with tools used to fabricate the IC, and / or other aspects of the fabrication process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated fabricated device has been created by LPC, if the simulated device is not sufficiently close in shape to satisfy design rules, then OPC and / or MRC are repeated to further refine IC design layout 822.

[0176] It should be appreciated that the above description of mask data preparation 832 has been simplified for clarity. In some embodiments, data preparation 832 includes additional features such as logic operations (LOPs) to modify IC design layout 822 according to fabrication rules. Additionally, the processes applied to IC design layout 822 during data preparation 832 can be performed in various different orders.

[0177] After mask data preparation 832 and during mask fabrication 844, a mask 845 or a set of masks 845 is fabricated based on modified IC design layout 822. In some embodiments, mask fabrication 844 includes performing one or more lithography exposures based on IC design layout 822. In some embodiments, an electron beam (e-beam) or multiple e-beam mechanisms are used to form a pattern on mask (reticle or pellicle) 845 based on modified IC design layout 822. Mask 845 can be formed in various techniques. In some embodiments, mask 845 is formed using binary techniques. In some embodiments, mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, is blocked by opaque regions and transmitted through transparent regions, which is used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer. In one example, a binary mask version of mask 845 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask 845 is formed using phase shift techniques. In a phase shift mask (PSM) version of mask 845, various features in the pattern formed on the phase shift mask are designed to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) resulting from mask fabrication 844 are used in various processes. For example, the mask(s) are used in ion implantation processes to form various doped regions in semiconductor wafer 853, used in etching processes to form various etched regions in semiconductor wafer 853, and / or used in other suitable processes.

[0178] IC manufacturing 850 includes wafer manufacturing 852. IC manufacturing 850 is an IC manufacturing operation that includes one or more manufacturing facilities for the manufacture of various IC products. In some embodiments, IC manufacturing 850 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end-of-line (FEOL) manufacturing of multiple IC products, a second manufacturing facility that provides back-end-of-line (BEOL) manufacturing for interconnection and packaging of IC products, and a third manufacturing facility that provides other services for the foundry operation.

[0179] IC manufacturing 850 uses masks (multiples) 845 manufactured by mask factory 830 to manufacture IC device 860. Therefore, IC manufacturing 850 uses IC design layout 822 at least indirectly to manufacture IC device 860. In some embodiments, semiconductor wafer 853 is manufactured by IC manufacturing 850 using masks (multiples) 845 to form IC device 860. In some embodiments, IC manufacturing includes performing one or more photolithography exposures at least indirectly based on IC design layout 822. Semiconductor wafer 853 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 853 further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed in subsequent manufacturing steps).

[0180] Regarding integrated circuit (IC) manufacturing systems (e.g., FIG. 8 Details of the system 800 and the IC manufacturing process associated with the manufacturing system can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published October 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entirety of which is hereby incorporated by reference.

[0181] In some embodiments, an integrated circuit (IC) device includes a plurality of first tap cells of a first semiconductor type, and a plurality of second tap cells of a second semiconductor type different from the first semiconductor type. The plurality of first tap cells is configured in at least two columns, the at least two columns being adjacent to each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first tap cells has a first length in the first direction. The plurality of second tap cells includes at least one second tap cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first tap cells in the first direction.

[0182] In some embodiments, the integrated circuit device further includes a substrate. The first and second well tap cells are configured on the substrate. Wherein the substrate has the second semiconductor type.

[0183] In some embodiments, wherein the second well tap cells further include at least another second well tap cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the first well tap cells in the first direction, and the first well tap cells are configured in the second direction between the at least one second well tap cell and the at least another second well tap cell.

[0184] In some embodiments, the integrated circuit device further includes a plurality of first well regions of the first semiconductor type, each of the first well tap cells being in a corresponding one of the first well regions. The IC device further includes a plurality of second well regions of the second semiconductor type, each of the second well tap cells being in a corresponding one of the second well regions, the first and second well regions extending in the first direction and being alternately configured in the second direction; and a plurality of fin features extending in the first direction. Wherein F2 / F1≥(DY / DX)*(L / A). F1 is a number of the fin features in each of the first well tap cells. F2 is a number of the fin features in each of the at least one second well tap cell and the at least another second well tap cell. DX is half of a first distance in the first direction between facing sides of the at least two columns. DY is half of a second distance in the second direction between facing sides of the at least one second well tap cell and the at least another second well tap cell. L is the second length of the at least one second well tap cell or the at least another second well tap cell in the first direction. A is a cell height in the second direction, and is a sum of a height of a first one of the first well regions and a height of an adjacent one of the second well regions.

[0185] In some embodiments, the IC device satisfies at least one of: DY is from 0.5 pm to 1000 pm, DX is from 0.05 pm to 100 pm, L is from 0.1 pm to 5000 pm, or A is from 0.025 pm to 0.300 pm.

[0186] In some embodiments, the IC device further includes a plurality of gate regions extending in the second direction. Each of F1 and F2 is defined by the following equation (L OD / CPP)*W*Fn. L OD is a first length for a corresponding first junction unit, or a second length for the at least one second junction unit or the at least another second junction unit. CPP is a pitch between adjacent gate regions in the first direction. W is a height of the corresponding first junction unit, the at least one second junction unit, or the at least another second junction unit in the second direction. Fn is a number of fin features per unit height in the second direction.

[0187] In some embodiments, the IC device further includes a plurality of first junction regions of a first semiconductor type, each of the first junction units being in a corresponding one of the first junction regions. It also includes a plurality of second junction regions of a second semiconductor type, each of the second junction units being in a corresponding one of the second junction regions; and a substrate on which the first junction regions, the second junction regions, the first junction units, and the second junction units are disposed. In which the first semiconductor type is N-type, the second semiconductor type is P-type, and the substrate is a P-type substrate, or the first semiconductor type is P-type, the second semiconductor type is N-type, and the substrate is an N-type substrate.

[0188] In some embodiments, in which the at least one second junction unit overlaps at least one of the first junction units in at least one of the at least two columns in the second direction.

[0189] In some embodiments, in which the at least one second junction unit overlaps all of the first junction units in all of the at least two columns in the second direction.

[0190] In some embodiments, in which the at least one second junction unit comprises a single second junction unit that extends continuously in the first direction between a first end and a second end thereof. The first end of the single second junction unit overlaps the first junction units in one of the at least two columns in the second direction, and the second end of the single second junction unit overlaps the first junction units in another of the at least two columns in the second direction.

[0191] In some embodiments, the at least one second well tap unit includes a series of second well tap units configured along the first direction. The series of second well tap units includes a first end well tap unit at a first end of the series of second well tap units and overlapping the first well tap units in one of the at least two columns in the second direction, a second end well tap unit at a second end of the series of second well tap units and overlapping the first well tap units in another of the at least two columns in the second direction, and an intermediate well tap unit between the first end and the second end of the series of second well tap units and not overlapping the first well tap units in the first well tap units in the at least two columns.

[0192] In some embodiments, the at least two columns include more than two columns, and the first well tap units in the more than two columns overlap the at least one second well tap unit in the second direction.

[0193] In some embodiments, a method includes disposing a plurality of first well tap units of a first semiconductor type in two adjacent columns in an integrated circuit (IC) layout. The method further includes disposing two second well tap units of a second semiconductor type different from the first semiconductor type in the IC layout. The two adjacent columns are adjacent to each other in a first direction, extend in a second direction transverse to the first direction, and are located between the two second well tap units in the second direction. Each of the plurality of first well tap units has a first length in the first direction. Each of the two second well tap units extends continuously in the first direction between the two adjacent columns over a second length greater than the first length of each of the plurality of first well tap units in the first direction. At least one of disposing the plurality of first well tap units or disposing the two second well tap units is performed by a processor.

[0194] In some embodiments, no other well tap units of the second semiconductor type are disposed in the IC layout between the two second well tap units.

[0195] In some embodiments, each of the two second well tap units has a first end overlapping the first well tap units in one of the two adjacent columns in the second direction and a second end overlapping the first well tap units in another of the at least two columns in the second direction.

[0196] In some embodiments, where the IC layout includes a plurality of first well regions of a first semiconductor type and a plurality of second well regions of a second semiconductor type, the first well regions and the second well regions extend in a first direction and are alternately arranged in a second direction. In arranging the first well tap cells, each of the first well tap cells is arranged in a corresponding one of the first well regions. In arranging the second well tap cells, each of the two second well tap cells is arranged in a corresponding one of the second well regions.

[0197] In some embodiments, where the IC layout further includes a plurality of fin features, the fin features extend in the first direction, and F2 / F1≥(DY / DX)*(L / A). Where F1 is a number of fin features in each of the first well tap cells, F2 is a number of fin features in each of the two second well tap cells. DX is half of a first distance between facing sides of two adjacent columns in the first direction. DY is half of a second distance between facing sides of the two second well tap cells in the second direction. L is a second length of each of the two second well tap cells in the first direction. A is a cell height in the second direction, and is a sum of a height of a first one of the first well regions and a height of an adjacent one of the second well regions.

[0198] In some embodiments, where arranging the first well tap cells and arranging the two second well tap cells are performed at regular intervals in the first direction and the second direction over a region of the IC layout.

[0199] In some embodiments, a system includes a processor to perform well tap cell arrangement in an integrated circuit (IC) layout by arranging a plurality of first well tap cells of a first semiconductor type in rows and columns, and arranging a plurality of second well tap cells of a second semiconductor type different from the first semiconductor type. The rows extend in a first direction, and the columns extend in a second direction transverse to the first direction. Each of the plurality of second well tap cells is elongated in the first direction and overlaps a plurality of the first well tap cells in the second direction.

[0200] In some embodiments, where the processor is to perform arranging the second well tap cells such that, among the second well tap cells, each pair of second well tap cells adjacent to each other in the second direction has a plurality of rows and columns of the first well tap cells sandwiched therebetween.

[0201] The foregoing summary of the illustrative embodiments serves to familiarize the reader with the features and advantages of one implementation of the disclosure. The skilled person will appreciate that the implementation of the disclosure can be readily used as a basis for the design or modification of other processes and structures for carrying out the same purposes and / or for achieving the same advantages of the embodiments introduced herein. The skilled person will also realize that such equivalent constructions do not depart from the spirit and scope of one implementation of the disclosure and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of one implementation of the disclosure.

Claims

1. An integrated circuit device, characterized by Comprising: a plurality of first well tap units of a first semiconductor type; a plurality of second well tap units of a second semiconductor type, the second semiconductor type being different from the first semiconductor type, wherein the plurality of first well tap units are arranged in at least two columns, the at least two columns being adjacent to each other in a first direction and extending in a second direction transverse to the first direction, each of the plurality of first well tap units has a first length in the first direction, and the plurality of second well tap units includes at least one second well tap unit having a second length in the first direction greater than the first length, wherein the at least one second well tap unit extends between the at least two columns along the first direction; a plurality of fin features extending in the first direction in the plurality of second well tap units; and a resistor coupled to one of the plurality of second well tap units, a resistance of the resistor increases as a distance between adjacent ones of the plurality of second well tap units increases, the resistance of the resistor decreases as a length of the plurality of fin features of the plurality of second well tap units increases. Further comprising:

2. The integrated circuit device of claim 1, wherein, a substrate on which the plurality of first well tap units and the plurality of second well tap units are arranged, wherein the substrate has the second semiconductor type.

3. The integrated circuit device of claim 1, wherein: the plurality of second well tap units further includes: at least another second well tap unit extending in the first direction between the at least two columns over the second length greater than the first length of each of the plurality of first well tap units in the first direction, and the plurality of first well tap units are arranged in the second direction between the at least one second well tap unit and the at least another second well tap unit. Further comprising:

4. The integrated circuit device of claim 3, wherein, a plurality of first well regions of the first semiconductor type, each of the plurality of first well tap units is in a corresponding one of the plurality of first well regions; a plurality of second well regions of the second semiconductor type, each of the plurality of second well tap units is in a corresponding one of the plurality of second well regions, the plurality of first well regions and the plurality of second well regions extend in the first direction and are alternately arranged in the second direction; and a plurality of fin features extending in the first direction, wherein F2 / F1 ≥ (DY / DX)*(L / A), F1 is a number of the plurality of fin features in each of the plurality of first well tap units, F2 is a number of the plurality of fin features in each of the at least one second well tap unit and the at least another second well tap unit, DX is half of a first distance in the first direction between facing sides of the at least two columns, ​ DY is half of a second distance in the second direction between facing sides of the at least one second well tap unit and the at least another second well tap unit, L is the second length in the first direction of the at least one second well tap unit or the at least another second well tap unit, A is a unit height in the second direction, and is a sum of a height of a first well region among the plurality of first well regions and a height of an adjacent second well region among the plurality of second well regions.

5. The integrated circuit device of claim 4, wherein, satisfies at least one of: DY is from 0.5 pm to 1000 pm, DX is from 0.05 pm to 100 pm, L is from 0.1 pm to 5000 pm or A is from 0.025 pm to 0.300 pm.

6. The integrated circuit device of claim 4, wherein, further comprises: a plurality of gate regions extending in the second direction, wherein each of Fl and F2 is defined by the following formula (L OD / CPP)*W*Fn, L OD corresponding to the first length of the plurality of first well tap subunit cells, or the second length of the at least one second well tap subunit cell or the at least one other second well tap subunit cell, CPP is a pitch between adjacent gate regions in the first direction, W is a height in the second direction of a corresponding one of the first well tap units, the at least one second well tap unit, or the at least another second well tap unit, Fn is a number of fin features per unit height in the second direction.

7. The integrated circuit device of claim 1, wherein, further comprises: a plurality of first well regions of the first semiconductor type, a corresponding one of the plurality of first well tap units being in a corresponding one of the plurality of first well regions; a plurality of second well regions of the second semiconductor type, a corresponding one of the plurality of second well tap units being in a corresponding one of the plurality of second well regions; and a substrate on which the plurality of first well regions, the plurality of second well regions, the plurality of first well tap units, and the plurality of second well tap units are disposed, wherein the first semiconductor type is N-type, the second semiconductor type is P-type, and the substrate is a P-type substrate, or the first semiconductor type is P-type, the second semiconductor type is N-type, and the substrate is an N-type substrate.

8. The integrated circuit device of claim 1, wherein: the at least one second well tap unit overlaps at least one first well tap unit in at least one of the at least two columns in the second direction.

9. The integrated circuit device of claim 1, wherein: the at least one second well tap unit overlaps all of the plurality of first well tap units in all of the at least two columns in the second direction.

10. The integrated circuit device of claim 1, wherein: the at least one second well tap unit comprises a single second well tap unit that extends continuously in the first direction between a first end and a second end thereof, the first end of the single second well tap unit overlaps the plurality of first well tap units in one of the at least two columns in the second direction, and the second end of the single second well tap unit overlaps the plurality of first well tap units in another of the at least two columns in the second direction.

11. The integrated circuit device of claim 1, wherein: The at least one second well tap unit comprises a plurality of second well tap unit series configured along the first direction, the plurality of second well tap unit series comprising: a first end well tap unit at a first end of the plurality of second well tap unit series and overlapping the plurality of first well tap units in one of the at least two columns in the second direction, a second end well tap unit at a second end of the plurality of second well tap unit series and overlapping the plurality of first well tap units in another of the at least two columns in the second direction, and an intermediate well tap unit between the first end and the second end of the plurality of second well tap unit series and not overlapping the plurality of first well tap units among the plurality of first well tap units in the at least two columns.

12. The integrated circuit device of claim 1, wherein: the at least two columns comprise more than two columns, and the plurality of first well tap units in the more than two columns overlap the at least one second well tap unit in the second direction.

13. A method of forming an integrated circuit device, characterized by: comprises: disposing, in an integrated circuit layout, a plurality of first well tap units of a first semiconductor type in two adjacent columns; and disposing, in the integrated circuit layout, two second well tap units of a second semiconductor type different from the first semiconductor type, wherein two adjacent columns are adjacent to each other in a first direction, extend in a second direction transverse to the first direction, and are located between the two second well tap units in the second direction, each of the plurality of first well tap units has a first length in the first direction, each of the two second well tap units extends continuously in the first direction between the two adjacent columns over a second length greater than the first length of each of the plurality of first well tap units in the first direction, disposing the plurality of first well tap units or disposing at least one of the two second well tap units is performed by a processor, the integrated circuit layout comprises a plurality of fin features extending in the first direction, wherein F2 / F1 ≥ (DY / DX)*(L / A), F1 is a number of the plurality of fin features in each of the plurality of first well tap units, F2 is a number of the plurality of fin features in each of the two second well tap units, DX is half of a first distance between facing sides of the two columns in the first direction, DY is half of a second distance between facing sides of the two second well tap units in the second direction, L is the second length of the two second well tap units in the first direction, and A is a width of each of the plurality of fin features in the first direction. A is a unit height in the second direction, and is a sum of a height of a first well region among a plurality of first well regions and a height of an adjacent second well region among a plurality of second well regions.

14. The method of claim 13, wherein, No other well tap cell of the second semiconductor type is disposed between the two second well tap cells in the integrated circuit layout.

15. The method of claim 13, wherein, Each of the two second well tap cells has: a first end overlapping a plurality of first well tap cells in one of the two adjacent columns in the second direction, and a second end overlapping a plurality of first well tap cells in another of the at least two columns in the second direction.

16. The method of claim 13, wherein, The integrated circuit layout includes a plurality of first well regions of the first semiconductor type and a plurality of second well regions of the second semiconductor type, the plurality of first well regions and the plurality of second well regions extending in the first direction and being alternately arranged in the second direction, In disposing the plurality of first well tap cells, each of the plurality of first well tap cells is disposed in a corresponding first well region among the plurality of first well regions, In disposing the plurality of second well tap cells, each of the two second well tap cells is disposed in a corresponding second well region among the plurality of second well regions.

17. The method of claim 13, wherein, The disposing the plurality of first well tap cells and the disposing the two second well tap cells are performed at regular intervals in the first direction and the second direction over a region of the integrated circuit layout.

18. A system of integrated circuits, characterized in that An apparatus comprising a processor to perform well tap cell disposition in an integrated circuit layout by disposing a plurality of first well tap cells of a first semiconductor type in a plurality of rows and a plurality of columns, the plurality of rows extending in a first direction, and the plurality of columns extending in a second direction transverse to the first direction, and disposing a plurality of second well tap cells of a second semiconductor type different from the first semiconductor type, one of the plurality of second well tap cells being elongated in the first direction and overlapping a number of first well tap cells among the plurality of first well tap cells in the second direction, wherein within a same column of the plurality of columns, a number of the plurality of first well tap cells is different from a number of the plurality of second well tap cells, The system of the integrated circuit further comprises: a plurality of fin features extending in the first direction in the plurality of second well tap cells; and a resistor coupled to one of the plurality of second well tap cells, an electrical resistance of the resistor increasing as a distance between adjacent ones of the plurality of second well tap cells increases, the electrical resistance of the resistor decreasing as a number of the plurality of fin features of the plurality of second well tap cells increases.

19. The system of claim 18, wherein, The processor to perform disposing the plurality of second well tap cells such that, among the plurality of second well tap cells, each pair of second well tap cells adjacent to each other in the second direction has a number of rows and a number of columns of the plurality of first well tap cells sandwiched therebetween.

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