Integrated circuit and method of forming an integrated circuit

Abstract

The present invention relates to a magnetoresistive random access memory (MRAM) cell with an extended upper electrode and a method for forming the same. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged above a conductive lower electrode. Two protective layers sequentially surround the sidewalls of the MTJ. The two protective layers have etching selectivity with respect to each other. Embodiments of the present application also relate to an integrated circuit and a method for forming the integrated circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuits and methods of forming integrated circuits. Background Art

[0002] Magnetoresistive random access memory (MRAM) is a promising non-volatile data storage technology. The core (or "bit") of an MRAM memory cell is a magnetic tunnel junction (MTJ), in which a dielectric layer is sandwiched between a magnetic fixed layer (reference layer) and a magnetic free layer (free layer) that can change its magnetization orientation. Due to the tunnel magnetoresistance effect, the resistance value between the reference layer and the free layer changes as the magnetization orientation in the free layer switches. Parallel magnetization (P state) results in lower resistance, while antiparallel magnetization (AP state) results in higher resistance. The two states of resistance value are considered to be the two logical states "1" or "0" stored in the MRAM cell.

[0003] In a spin transfer torque MRAM (STT-MRAM) cell, a write current is applied through the entire MTJ (i.e., reference layer, dielectric layer, and free layer), which sets the magnetization orientation of the free layer through the spin transfer torque effect. That is, the write current passes through the same path as the read path of the MRAM. In a spin-orbit torque MRAM (SOT-MRAM) cell, the MTJ structure is located on a heavy metal layer with a large spin-orbit interaction. The free layer is in direct contact with the heavy metal layer. Under the spin-orbit coupling effect, the in-plane current injected through the heavy metal layer induces a spin torque, which typically includes one or more of the Rashba effect or the spin Hall effect (SHE effect). The write current does not pass through the perpendicular MTJ. Instead, the write current passes through the heavy metal layer. The magnetization orientation in the free layer is set by the spin-orbit torque effect. More specifically, when the current is injected into the heavy metal layer in-plane, the spin-orbit coupling causes an orthogonal spin current, which generates a spin torque and causes a magnetization reversal in the free layer. Summary of the invention

[0004] Some embodiments of the present application provide an integrated circuit, comprising: a vertical magnetic tunnel junction stack, having a first magnetic layer, a second magnetic layer, and a blocking layer located between the first magnetic layer and the second magnetic layer; a first electrode located below the vertical magnetic tunnel junction stack; a second electrode located above the vertical magnetic tunnel junction stack; a first dielectric layer laterally wrapping the vertical magnetic tunnel junction stack; and a second dielectric layer laterally wrapping the first dielectric layer.

[0005] Some other embodiments of the present application provide a method for forming an integrated circuit, comprising: forming a first dielectric layer over a first region of a wafer, the first region including a vertical magnetic tunnel junction structure over an etch stop layer, the etch stop layer extending through a second region of the wafer laterally located next to the first region; forming a second dielectric layer over the first region of the wafer and sealing the first dielectric layer; forming a third dielectric layer over the first and second regions of the wafer and sealing the second dielectric layer; in a first etching operation, forming a first opening in the third dielectric layer exposing a first portion of the second dielectric layer located over the vertical magnetic tunnel junction structure and a second opening exposing a second portion of the etch stop layer located in the second region; in a second etching operation, removing the first portion of the second dielectric layer exposed from the first opening, exposing the third portion of the first dielectric layer through the first opening, and removing the second portion of the etch stop layer exposed from the second opening; removing the third portion of the first dielectric layer by wet cleaning; and forming a first interconnect structure in the first opening contacting the vertical magnetic tunnel junction structure, and forming a second interconnect structure in the second opening extending through the etch stop layer.

[0006] Some other embodiments of the present application provide an integrated circuit, comprising: a substrate; a first interlayer dielectric layer located above the substrate; a first metallization component and a second metallization component located in the first interlayer dielectric layer; an etch stop layer located above the first interlayer dielectric layer; a second interlayer dielectric layer located above the etch stop layer; a vertical magnetic tunnel junction stack located in the second interlayer dielectric layer, the vertical magnetic tunnel junction stack having a first magnetic layer, a second magnetic layer and a barrier layer vertically located between the first magnetic layer and the second magnetic layer; a first protective layer surrounding the sidewalls of the vertical magnetic tunnel junction stack; a second protective layer surrounding the first protective layer; a first electrode located below the vertical magnetic tunnel junction stack, extending through the etch stop layer and contacting the first metallization component; a second electrode located above the vertical magnetic tunnel junction stack; a first interconnect structure extending from a surface of the second interlayer dielectric layer to the second electrode; and a second interconnect structure extending from the surface of the second interlayer dielectric layer to the second metallization component. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same elements or steps unless the context otherwise indicates. The sizes and relative positions of the elements in the accompanying drawings are not necessarily drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is an exemplary MRAM structure according to an exemplary embodiment of the present invention.

[0009] Figure 2 is an exemplary MRAM cell according to an exemplary embodiment of the present invention.

[0010] FIG. 3A to FIG. 3D A wafer is shown at various stages of a first manufacturing process according to an exemplary embodiment of the present invention.

[0011] Figures 4A to 4K The wafer is shown at various stages of a second manufacturing process according to an exemplary embodiment of the present invention.

[0012] FIG. 5A to FIG. 5D A wafer is shown at various stages of a third manufacturing process according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the described subject matter. Specific examples of components and arrangements are described below to simplify this description. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] In the following description, certain specific details are set forth to provide a thorough understanding of various embodiments of the present invention. However, those skilled in the art will appreciate that the present invention can be practiced without these specific details. In other cases, well-known structures associated with electronic components and manufacturing techniques are not described in detail to avoid unnecessarily obscuring the description of the embodiments of the present invention.

[0016] Unless the context requires otherwise, throughout the following specification and claims, the word "comprise" and variations thereof, such as "comprises" and "comprising", are to be interpreted in an open, inclusive sense, i.e., "including, but not limited to",.

[0017] The use of ordinal numbers such as first, second, and third does not necessarily imply a sense of order or hierarchy but may simply distinguish between multiple instances of a step or structure.

[0018] Throughout the specification, references to "one embodiment" or "an embodiment" mean that a particular component, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, various appearances of the phrase "in one embodiment" or "in an embodiment" throughout the specification do not necessarily all refer to the same embodiment. Furthermore, in one or more embodiments, particular components, structures, or characteristics may be combined in any suitable manner.

[0019] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and / or" unless the content clearly dictates otherwise.

[0020] The present application is directed to a method for forming an interconnect structure to a magnetic tunnel junction (MTJ) structure and a connecting component of a logic device in an integrated process. The MTJ structure is formed above a metallization layer to which the connecting component belongs. Therefore, the first interconnect structure to the MTJ structure is shorter than the second interconnect structure to the connecting component of the logic device, and is generally wider than the second interconnect structure to the connecting component of the logic device. In an integrated hole etching process, for example, the hole of the MTJ structure and the hole of the connecting component are etched together, and the MTJ structure is exposed to a larger dose of etchant.

[0021] Two layers of dielectric material are formed above the MTJ structure. The two layers of dielectric material prevent large doses of etchant from damaging the MTJ structure. In some embodiments, the outer / upper layer of the two layers of dielectric material includes the same dielectric material as the etch stop layer, which is located between the interlayer dielectric layers, for example, above the connection part of the logic device. Therefore, the same etching process will remove the outer layer of the dielectric material in the hole to the MTJ, and will remove the etch stop layer in the hole to the connection part. The inner / lower layer of the two layers of dielectric material has a high etching selectivity greater than the outer / upper layer. Therefore, the etching process does not completely remove the inner layer of the dielectric material at least. That is, after the etching process of forming the hole to the MTJ structure and the hole to the connection part of the logic device, respectively, the MTJ structure is still covered by the inner layer. The inner layer of the dielectric material is sensitive to the acidic solution used for wet cleaning of the hole to the connection part and the hole to the MTJ structure. Therefore, the wet cleaning process removes the inner / lower layer of the dielectric material exposed in the hole to the MTJ structure, and exposes the MTJ structure in the corresponding hole.

[0022] After wet cleaning, conductive material is formed in the holes to the MTJ structure and in the holes to the connecting features in the same metal deposition process.

[0023] In an integrated circuit (IC), an MTJ structure is formed as part of a back-end process. The MTJ structure includes a vertical MTJ stack having a free magnetic layer, a fixed magnetic layer, and a barrier layer between the free magnetic layer and the fixed magnetic layer. A spacer (e.g., of SiN) wraps the MTJ stack laterally. The top electrode and the bottom electrode contact the MTJ stack from the top or bottom surface of the MTJ stack, respectively. Two protective layers of dielectric material are located outside the spacer. The bottom electrode via (BEVA) contacts the bottom electrode from below the bottom electrode. The top electrode via (TEVA) contacts the top electrode from above the top electrode.

[0024] In some embodiments, the two protection layers also laterally wrap at least partially around the sidewalls of the bottom electrode and the top electrode.

[0025] The MTJ stack is located in the interlayer dielectric (ILD) layer ILD X Middle, vertically located in the ILD X ILD below the layer X-1 In some embodiments, the ILD X Layers such as SiC etch stop layer and oxygen-rich silicon oxide layer SRO and ILD X-1 In the logic area of ​​the IC, the connection parts of the logic devices are located in the ILD X-1 The connection components may include wiring and / or interconnect components, such as connection islands and / or jumper structures.

[0026] In some embodiments, the outer one of the two protective layers (external protective layer) includes the same dielectric material as the etch stop layer, for example, SiC. The inner one of the two protective layers (internal protective layer) includes a dielectric material having a high selectivity greater than the outer protective layer and having an etch selectivity greater than the material of the connecting component, which may include one or more of copper, tungsten, and cobalt. The inner protective layer and the outer protective layer do not exist in the logic area.

[0027] Figure 1 1. A portion of an exemplary integrated circuit (IC) 100 is shown above a substrate 102. The IC 100 includes a first portion 110 having a plurality of MRAM cells, of which MRAM cells 112, 114 are shown for illustration. The IC 100 also includes other circuit elements ( Figure 1 A second part 120 (not shown) such as a logic circuit element. Figure 1 BEOL layers and structures of the IC circuit 100 are shown. The MRAM cells 112, 114 are formed in a BEOL process over one or more ILD layers 122, one ILD layer 122 being shown for illustration. In some embodiments, metallization features 116, 118, such as metal interconnect structures or metal line structures, are formed in or between the one or more ILD layers 122. For example, the metallization feature 116 is located in the first portion 110 and below the MRAM cells 112, 114, and the metallization feature 118 is located in the second portion 120. For illustration purposes, the metallization feature 116 and the metallization feature 118 are located in the same ILD layer 122.

[0028] The MRAM cells 112, 114 each include an MTJ structure 124, 126, respectively. The MTJ structures 124, 126 are each vertically adjacent to a bottom electrode (BE) 128, 130 and a top electrode (TE) 132, 134, respectively. Interconnect structures (e.g., connection vias (BEVA) 136, 138) connect the BE 128, 130 to the corresponding metallization features 116 below, respectively. In some embodiments, the MTJ structures 124, 126 and the corresponding bottom electrodes (BE) 128, 130 and top electrodes (TE) 132, 134 are formed in an ILD layer 123 having the same dielectric material as the ILD layer 122 below the MTJ structures 124, 126. The ILD layers 122, 123 are silicon oxide or low-k dielectric materials or other suitable dielectric materials. A composite etch stop layer 125 is located between the ILD layer 122 and the ILD layer 123. In some embodiments, the composite etch stop layer 125 includes a laminate of two dielectric layers 127, 129 having an etch selectivity to each other. In some embodiments, the lower one 129 of the two layers 127, 129 has an etch selectivity greater than the ILD layer 123 and serves as an etch stop layer. In some embodiments, the composite etch stop layer 125 includes an etch stop layer 129 of SiC and a silicon-rich oxide SRO layer 127 above the SiC layer 129. Layer 127 may also include a TEOS material.

[0029] In some embodiments, BE 128, 130 is formed over composite etch stop layer 125, and BEVA 136, 138 is formed in composite etch stop layer 125. Some embodiments are also possible. For example, BE 128, 130 may be formed in composite etch stop layer 125.

[0030] The laminate 140 of the two protective layers 142, 144 seals the sidewalls 143, 145 of the MTJ structures 124, 126. The two protective layers 142, 144 include materials that have etching selectivity with respect to each other. In some embodiments, the outer one 142 of the two protective layers 142, 144 includes the same material as the etch stop layer 129 or a material similar to the etch stop layer 129 in etching selectivity characteristics. For example, in the case where the etch stop layer 129 is SiC, the outer protective layer 142 is SiC, SiOC, other dielectric materials formed using a plasma enhanced atomic layer deposition "PEALD" process, or other suitable materials having etching characteristics similar to SiC with respect to the etchant. In some embodiments, the inner protective layer 144 is aluminum oxide (AlO x ) or other suitable materials having an etch selectivity relative to the outer layer 142.

[0031] In some embodiments, the outer protective layer 142 has a thickness of about to about The inner protective layer 144 has a thickness in the range of about to about The thickness of the outer protective layer 142 and the inner protective layer 144 is in the range of between . The different thickness values ​​of the outer protective layer 142 and the inner protective layer 144 are configured to facilitate forming holes in the outer protective layer 142 and the inner protective layer 144 to expose the top electrodes 132, 134. As will be described in detail herein, wet etching will be used to form holes in the inner protective layer 144 to expose the top electrodes 132, 134. It is generally difficult to etch away aluminum nitride or aluminum oxide in wet etching. Therefore, the thickness value of the inner protective layer 144 of aluminum oxide or aluminum nitride is configured to be relatively small. In some embodiments, the outer protective layer 142 is SiC or SiOC, which is the same as layer 129. As discussed herein, the same etching process opens holes in the outer protective layer 142 and layer 129. In the SiC etching process, the outer protective layer 142 is subjected to more etchant load than layer 129 because the outer protective layer 142 is close to the etchant source. Therefore, the thickness value of the outer protective layer 142 is configured to be relatively large.

[0032] In some embodiments, the spacer layers 146, 148 surround the sidewalls 143, 145 of the MTJ structures 124, 126, respectively. The spacer layers 146, 148 are laterally located between the sidewalls 143, 145 and the laminate 140. In some embodiments, the spacer layers 146, 148 are located over the BEs 128, 130, respectively. The spacer layers 146, 148 are SiN or other suitable dielectric materials.

[0033] In some embodiments, the laminate 140 also at least partially seals the sidewalls 133, 135 of the top electrodes 132, 134. Upper portions of the top electrodes 132, 134, for example, include upper surfaces 137, 139 of the top electrodes 132, 134, and in some embodiments, upper portions of the sidewalls 133, 135 are exposed from the laminate 140. Metal interconnect structures 152, 154 are formed over the top electrodes 132, 134 that contact the upper portions of the top electrodes 132, 134 that are exposed from the laminate 140. In some embodiments, the laminate 140 extends over the entire surface of the first region 110, except for the upper portions of the top electrodes 132, 134 that are exposed from the laminate 140. The laminate does not extend over the second region 120.

[0034] In some embodiments, a metal interconnect structure 156 is formed in the second region 120 to contact the metallization feature 118. Specifically, the metal interconnect structure 156 extends through the ILD 123 and the composite etch stop layer 125, and contacts the metallization feature 118. The metal interconnect structures 152, 154, 156 are formed in the same process and all extend downward from the upper surface 158 of the ILD 123. The metal interconnect structures 152, 154, 156 are coplanar with each other relative to the upper surface 158 of the ILD 123.

[0035] In an embodiment, the BEs 128, 130 include a conductive nitride having magnetic properties suitable for operation of the corresponding MTJ structures 124, 126. For example, the conductive nitride material of the BEs 128, 130 does not affect the magnetic polarization of the fixed layer of the fixed MTJ structures 124, 126. In an embodiment, the BEs 128, 130 are one or more of TaN or TiN. The BEVA 136 includes a material that matches the electrical and magnetic properties of the BEs 128, 130. In an embodiment, the BEVA 136 is TiN. In some embodiments, the BEVA 136 also includes a barrier layer or liner layer (not shown for simplicity) that prevents the TiN material from penetrating into one or more of Ta or TaN in the surrounding SiC layer 129 and SRO / TEOS layer 127.

[0036] Figure 2 An exemplary MRAM cell 112 is shown. Figure 2 , the MRAM cell 112 includes a BE 128. An antiferromagnetic layer 204 is disposed over the conductive lower electrode 128, and a fixed magnetic layer 206 is disposed over the antiferromagnetic layer 204. The antiferromagnetic layer 204 includes a material having strong exchange coupling, which has atoms with magnetic moments aligned in a regular pattern with adjacent spins pointing in opposite directions. The strong exchange coupling allows the antiferromagnetic layer 204 to pin (i.e., fix) the magnetic polarization of the fixed magnetic layer 206, thereby preventing the switching of the magnetic polarization of the fixed magnetic layer 206, for example, during a write operation of the MRAM cell 112. To this extent, the fixed magnetic layer 206 is also referred to as the fixed layer 206 of the MTJ structure 124. In some embodiments, a synthetic antiferromagnetic (SAF) layer (not shown for simplicity) can be disposed between the antiferromagnetic layer 204 and the fixed magnetic layer 206.

[0037] In the MTJ structure 124, the fixed magnetic layer 206 is vertically separated from the free magnetic layer 210 by a dielectric barrier layer 208. The free magnetic layer 210 or free layer 210 includes a magnetic polarization that can be switched between a parallel configuration and an antiparallel configuration relative to the magnetic properties of the fixed magnetic layer 206. An upper / top electrode 132 is disposed above the free magnetic layer 210. Optionally, a dielectric cap or spacer layer 146 of, for example, silicon nitride (SiN) is disposed around the MTJ structure 124. The spacer layer 146 can also be carbide (SiC), silicon dioxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC) and / or a low-k dielectric material.

[0038] The fixed magnetic layer 206, the dielectric barrier layer 208, and the free magnetic layer 210 form a magnetic tunnel junction (MTJ) 124. Within the MTJ 124, electrons can tunnel through the dielectric barrier layer 208 when a differential voltage is applied between the conductive lower electrode 128 and the conductive upper electrode 132. As the electrons tunnel through the dielectric barrier layer 208, the magnetic polarization of the free magnetic layer 210 can change, thereby changing the resistance value of the MTJ 124. For example, if the polarity of the free magnetic layer 210 is aligned with the polarity of the fixed magnetic layer 206, the MTJ 124 has a first resistance value corresponding to a first data state (e.g., a logical "0"). If the polarity of the free magnetic layer 210 is not aligned with the polarity of the fixed magnetic layer 206, the MTJ 124 has a second resistance value corresponding to a second data state (e.g., a logical "1").

[0039] In some embodiments, the conductive lower or bottom electrode BE 128 may include titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), and / or tantalum (Ta). In some embodiments, the BE 128 may have a thickness in a range between about 10 nm and about 100 nm. In some embodiments, the antiferromagnetic layer 204 may include iridium manganese (IrMn), iron manganese (FeMn), ruthenium manganese (RuMn), nickel manganese (NiMn), and / or palladium platinum manganese (PdPtMn). In some embodiments, the fixed magnetic layer 206 may include cobalt (Co), iron (Fe), boron (B), and / or ruthenium (Ru). In some embodiments, the fixed magnetic layer 206 may have a thickness in a range between about 5 nm and about 10 nm.

[0040] In some embodiments, the dielectric barrier layer 208 may include magnesium oxide (MgO) and / or aluminum oxide (Al2O3), and may have a thickness in a range between about 0.5 nm and about 2 nm. In some embodiments, the free magnetic layer 210 may include one or more of cobalt (Co), iron (Fe), and boron (B), and may have a thickness in a range between about 1 nm and about 3 nm.

[0041] In some embodiments, the conductive upper electrode 132 may include titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tungsten (W), and / or tantalum (Ta).

[0042] In some embodiments, the cross-sections of the conductive upper electrode 132, the free magnetic layer 210, the dielectric barrier layer 208, the fixed magnetic layer 206, the antiferromagnetic layer 204, and the conductive upper electrode 132 are substantially acute-angled trapezoidal, either individually or together as a group. The widths of the conductive lower electrode 128, the free magnetic layer 210, the dielectric barrier layer 208, the fixed magnetic layer 206, and the antiferromagnetic layer 204 keep increasing in the downward direction of the z-axis. In some embodiments, the acute-angled trapezoidal cross-sectional shape is formed by an ion beam etching (IBE) process for forming the sidewalls 143 of the MTJ structure 124 and the sidewalls 133 of the upper electrode 132. In other words, the free magnetic layer 210, the dielectric barrier layer 208, the fixed magnetic layer 206, the antiferromagnetic layer 204, and the top electrode 132 have substantially aligned and tilted sidewalls.

[0043] FIG. 3A to FIG. 3D Wafer 300 is shown at various stages of fabrication in forming IC 100, MRAM cell 112, or other semiconductor structure. Figure 3A , receiving a wafer 300. Wafer 300 includes a semiconductor body 302. Semiconductor body 302 may be a silicon substrate of a crystalline structure and / or other elemental semiconductors such as germanium. Alternatively or additionally, semiconductor body 302 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide and / or indium phosphide. In addition, semiconductor body 302 may also include a silicon-on-insulator (SOI) structure. Semiconductor body 302 may include an epitaxial layer and / or may be strained for enhanced performance. Semiconductor body 302 may also include various doping configurations (such as a p-type substrate and / or an n-type substrate) and various doped regions (such as a p-well and / or an n-well) according to design requirements known in the art. One or more selection transistors 304 are arranged in or above semiconductor body 302. In some embodiments, one or more selection transistors 304 are arranged between isolation regions 305 (e.g., STI regions).

[0044] In some embodiments, one or more selection transistors 304 may include a MOSFET (metal oxide silicon field effect transistor) device. The transistor 304 may be of various types, such as a planar transistor, a finFET transistor, a full-ring gate transistor, a vertical transistor, or other types of transistors, which do not limit the scope of the present invention. In such an embodiment, one or more selection transistors 304 include a source region 306 and a drain region 308 separated by a channel region 307, respectively. The source region 306 includes a first doping type (e.g., an n-type dopant), the channel region 307 includes a second doping type different from the first doping type, and the drain region 308 includes a first doping type. In some embodiments, the first doping type includes n-type doping, while in other embodiments, the first doping type includes p-type doping. A gate structure 310 including a gate electrode 311 separated from the channel region 307 by a gate oxide layer 309 is configured to control the flow of charge carriers between the source region 306 and the drain region 308. In various embodiments, the gate structure 310 may include a doped polysilicon material or a metal material (e.g., TiN, Al, etc.). In some embodiments, sidewall spacers 312 (eg, SiN spacers) may be disposed on opposite sides of the gate electrode 311 .

[0045] Back-end-of-line (BEOL) metal features 318, 320 or metallization features are disposed over the semiconductor body 302, some of which contact the terminals of the transistor 304 through contact vias 314 (shown as 314a, 314b, 314c). The metallization features 318, 320 are stacked vertically, some of which eventually lead to the metallization features 116 in the first region 110 and the metallization features 118 in the second region 120. The metallization features are formed in an ILD layer 322 including the ILD layer 122 forming the metallization features 116 and 118. In some embodiments, the interlayer dielectric (ILD) layers 322, 122 are separated from each other by an etch stop layer 329, such as SiC or SiN.

[0046] exist Figure 3B In the embodiment of the present invention, a composite etch stop layer 125 (including a layer 127 of SRO or TEOS and a layer 129 of SiC) is formed over the ILD layer 122. The composite etch stop layer made of a tetraethyl orthosilicate (TEOS) oxide layer on top of a conventional silicon-based SiC etch stop layer can further reduce the overall thickness and dielectric constant of the composite etch stop layer 125.

[0047] exist Figure 3CIn the embodiment of the present invention, a BEVA structure 136 is formed in the composite etch stop layer 125 in the first region 110, contacting the metallization feature 116 in the ILD layer 122. The BEVA via structure 136 includes a material different from that of the metallization feature 116. In some embodiments, the BEVA via structure 136 is TiN, and the metallization feature 116 is copper. The layer 127 is a material suitable for depositing the BEVA via structure 136, such as TiN. In some embodiments, the layer 127 is one or more of SRO or TEOS or other suitable dielectric materials. In some embodiments, a barrier layer or liner layer 328 is formed between the BEVA via structure 136 and the surrounding composite etch stop layer 125. The barrier layer 328 is one or more of Ta or TaN. The barrier layer 328 prevents the TiN element from penetrating into the surrounding composite etch stop layer 125. In some embodiments, the BEVA via structure 136 is formed only in the layer 127, and the BEVA via structure 136 is not formed in the layer 129 of SiC. That is, another interconnect structure is formed in layer 129 between the BEVA via structure 136 and the metallization feature.

[0048] exist Figure 3D In the embodiment, an MRAM cell 112 is formed in the first region 110 above the BEVA via structure and the composite etch stop layer 125. The MRAM cell includes an MTJ structure 124, a top electrode 132, and a bottom electrode 128. In some embodiments, a spacer layer 146 surrounds at least the MTJ structure 124 of the MRAM cell 112.

[0049] Figures 4A to 4K Further formation of the MRAM cell 112 and metallization features over the MRAM cell 112 is shown.

[0050] exist Figure 4A In, an exemplary wafer 400 is received. In FIG. 3A to FIG. 3D After the processes of FIG. 4 , the exemplary wafer 400 may be the same wafer as the wafer 300. The exemplary wafer 400 is shown as having a first region 110 for MRAM cells and a second region 120 for other circuit elements (eg, logic elements).

[0051] exist Figure 4B In the embodiment, a laminate of two layers 402, 404 is formed integrally over wafer 400. The two layers 402, 404 have high etch selectivity with respect to each other. In some embodiments, layer 402 is the same material as etch stop layer 129 or a material having similar etching characteristics as etch stop layer 129. In the case where etch stop layer 129 is SiC, layer 402 is SiC, SiOC, or other dielectric material formed using PEALD. Layer 404 is aluminum oxide (AlO x) or aluminum nitride (AlN) or a material having similar etching characteristics. Layer 404 is deposited to have a thickness from about to about Layer 402 is deposited to have a thickness ranging from about to about Thickness within the range.

[0052] exist Figure 4C In the embodiment, for example, the layers 402 and 404 are selectively removed from the second region 120 by etching, while the first region 110 is covered by a mask layer (not shown for simplicity). Portions of the layer 127 of SRO or TEOS may also be removed by etching, so that the thickness of the layer 127 in the second region 120 is less than the thickness of the layer 127 in the first region 110. x ) or aluminum nitride (AiN) and the etch stop layer 129 of SiC, the etch stop layer 129 still remaining after the layers 402 and 404 have been removed from the second region 120.

[0053] exist Figure 4D In the embodiment, an ILD layer 123 is formed entirely or completely over the wafer 400. Specifically, the ILD layer 123 is formed over the first region 110 and the second region 120. In some embodiments, the ILD layer 123 is an extremely low-k (ELK) material such as SiCOH, porous SiCOH, nanoglass, or other dielectric materials having a dielectric constant k≤3. A polishing CMP process is performed to planarize the surface 410 of the ILD layer 123.

[0054] FIG. 5A to FIG. 5D An exemplary process for planarizing the surface 410 of the ILD 123 is shown. Figure 5A In FIG. 1 , an ILD layer 123 is entirely formed over the first region 110 and the second region 120 . Because of the MTJ structure 124 , the ILD layer 123 includes a bump or step height 510 over the MTJ structure 124 . Figure 5B In the embodiment, a coating 520 of a low-k dielectric material is applied over the ILD layer 123. The coating 520 covers the bump 510 and has a relatively flat surface 522. Figure 5C In the embodiment, an etch-back process is performed to remove the coating 520 and the bump 510. In some embodiments, after the etch-back process, a remaining portion 524 of the bump 510 remains. Figure 5D In the embodiment, a polishing CMP process is performed to remove the remaining portion 524 and planarize the surface 410 of the IRD layer 123 .

[0055] exist Figure 4E, an anti-reflective layer 412 and a hard mask layer 414 are sequentially formed over the ILD layer 123. In some embodiments, the anti-reflective layer 412 is a nitrogen-free anti-reflective coating (NFARC) layer, and the hard mask layer 414 is a TiN / TaN layer. Both layers 412 and 414 are used as sacrificial layers. The hard mask layer 414 is patterned to have a hole 420 in the first region 110 and a hole 422 in the second region 120. The holes 420, 422 define positions to form metallization features to be formed in the ILD layer 123 in the first region 110 and the second region 120. In some embodiments, the holes 420, 422 in the first region 110 and the second region 120, respectively, may have the same size, for example, the same surface area. In some embodiments, a sacrificial dielectric hard mask layer 416 is formed between the ILD layer 123 and the NFARC layer 412. Layer 416 is used to prevent kink defects at the surface of the low-k dielectric layer 123. For example, the sacrificial dielectric hard mask layer 416 is formed of a silicon-containing dielectric material such as silicon nitride using methods such as plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP-CVD), and atmospheric pressure chemical vapor deposition (APCVD).

[0056] exist Figure 4F In the embodiment of the present invention, a partial via etching process is performed to form partial vias or trenches 424, 426 through the holes 420, 422. Specifically, the partial via etching opens the NFARC layer 412 to partially remove the material of the ILD layer 123 at a location designated to form a via or trench leading to the MRAM cell 112 in the first region 110 or the metallization feature 118 in the second region 120. The holes 420, 422 are formed together in an integrated etching process. That is, when the partial via etching process is performed on the other of the first region 110 or the second region 120, neither covers the first region 110 or the second region 120. In some embodiments, the partial vias or trenches 424, 426 have substantially the same size, for example, in depth and shape.

[0057] exist Figure 4G In the embodiment of the present invention, a main etching process is performed through holes 420, 422 to form a through hole 430 leading to the MRAM cell 112 and a through hole 432 leading to the metallization feature 118. The etching process also removes the SRO or TEOS layer 127 of the composite etch stop layer 125 in the second region 120. Therefore, the layer 404 of SiC, SiOC or other dielectric layer and the layer 129 of SiC formed using plasma enhanced ALD (PEALD) are used as an etch stop layer for the main etching process. In some embodiments, the main etching process uses a dry plasma etching process.

[0058] As a result of the partial vias 424, 426, the vias 430, 432 each have a staggered shape and include wider portions 434, 436 and narrower portions 438, 440, respectively. The wider portions 434, 436 are close to the surface 410 of the ILD 123. The narrower portions 438, 440 are lower than the wider portions 434, 436 and are close to the MRAM cell 112 or the metallization feature 118, respectively. In some embodiments, the wider portions 434, 436 have the same dimensions, for example, in terms of surface area, shape, and depth / length. The narrower portion 438 in the first region 110 has a dimension 439 that is shallower / shorter than the dimension 441 of the narrower portion 440 in the second region 120. Therefore, the SiC layer 404 above the MRAM cell 112 is exposed to more etchant than the SiC layer 129 in the second region 120. More SiC material is removed from the SiC layer 404 exposed in the via 430 than from the SiC layer 129 exposed in the via 432. However, because AlO x Layer 402 has a greater etch selectivity than SiC, so AlO x The layer 402 remains to cover the MRAM cell 112 including the top electrode 132, the MTJ structure 124, and the bottom electrode 128. On the other hand, because the SiC layer 404 seals the AlO x Layer 402 and AlO x Layer 402 is previously exposed to the etchant of the main etching process, so AlO x Layer 402 does not need to be relatively thick. x Layer 402 has approximately to about Relatively low thickness.

[0059] In some embodiments, the wider portions 434 , 436 and the narrower portions 438 , 440 all have a tapered shape that represents a trench in which a metal line is filled.

[0060] exist Figure 4H In the embodiment, a liner removal method (LRM) etching process is applied to remove a selected portion of the SiC etch stop layer 129 from the through hole 432 downward, and a selected portion of the SiC layer 404 from the through hole 430 downward. Other etching techniques may also be used to remove the SiC layers 127, 404. In some embodiments, the etching is highly anisotropic, with little lateral etching applied. This can be achieved with lower pressure (e.g., less than 40mTorr) and higher bias power (e.g., greater than 100W). Because AlO x Layer 402 has a high etch selectivity over SiC, so AlO xThe layer 402 remains covering the MRAM cell 112 and is exposed in the via 430. In the second region 120, the SiC layer 129 beneath the via 432 is removed to expose the metallization feature 118 in the via 432.

[0061] exist Fig. 4I In the embodiment, a wet cleaning process is applied to the first region 110 and the second region 120 together. The wet cleaning (eg, using deionized water) removes the AlO exposed in the through hole 430. x The wet cleaning will not damage or affect the metallization features 118, such as copper, exposed in the via 432, and will not damage or affect the top electrode 132, such as tungsten. x The relatively small thickness of layer 402 (approximately to about ), so it is relatively easier or faster to remove AlO by wet cleaning x Therefore, the removal of AlO x Layer 402 will not bring additional time cost in the manufacturing process, because wet cleaning is also performed to clean the debris and residue in the through hole 432. x After the portion of layer 402 is exposed in through hole 430, the remaining layers 402, 404 become Figure 1 protective layers 142, 144.

[0062] exist Figure 4J In the embodiment, a conductive material 439 (e.g., copper) is deposited together in the vias 430, 432, which extend down to the top electrode 132 and the metallization 118, respectively. Because the sidewalls of the MTJ structure 124 and the top electrode 132 are covered by the remaining layers 402, 404, even if the via 430 is misaligned and the conductive material 439 is deposited over the sidewalls of the top electrode 132 and the MTJ structure 124, the sidewalls of the MTJ structure 124 are not damaged or affected. Therefore, the via 430 can have more margin and flexibility in surface size. Given that the vias 430, 432 are formed together, this margin and flexibility is also beneficial to the process design of the via 432.

[0063] exist Figure 4K In the embodiment, chemical mechanical polishing is applied to remove the layers above the top surface 410 of the ILD layer 123, which include excess conductive material 440, hard mask layer 414, NFARC layer 412, and ESLK layer 416. The conductive material in the via 430 becomes an interconnect structure 442 to the top electrode 132 of the MRAM cell 112. The conductive material in the via 432 becomes an interconnect structure 444 to the metallization feature 118 in the second region 120.

[0064] As shown herein, the MRAM cell 112 is sealed using layers 402, 404, and the processes of forming an interconnect structure 442 to the MRAM cell 112 in the first region 110 and an interconnect structure 444 to the metallization feature 118 in the second region 120 are integrated in the same process. In the process of forming the interconnect structure in the other region, neither the first region 110 nor the second region 120 is covered. Such an integrated process saves the cost and time of the BEOL process. In addition, the layers 402, 404 protect the MRAM cell 112 from being damaged in the process of forming the interconnect structure 442.

[0065] The present invention can be further understood with reference to the following embodiments:

[0066] In some embodiments, an integrated circuit includes: a vertical magnetic tunnel junction stack having a first magnetic layer, a second magnetic layer, and a barrier layer located between the first magnetic layer and the second magnetic layer; a first electrode located below the vertical magnetic tunnel junction stack; a second electrode located above the vertical magnetic tunnel junction stack; a first dielectric layer laterally wrapping the vertical magnetic tunnel junction stack; and a second dielectric layer laterally wrapping the first dielectric layer.

[0067] In some embodiments, the integrated circuit further comprises: a spacer layer laterally located between the first dielectric layer and the vertical magnetic tunnel junction stack. In some embodiments, the spacer layer is located on the first electrode. In some embodiments, the spacer layer at least partially laterally wraps the second electrode. In some embodiments, the first dielectric layer laterally wraps the first electrode and at least partially wraps the second electrode. In some embodiments, the vertical magnetic tunnel junction stack is located in the first interlayer dielectric layer and above the etch stop layer below the first interlayer dielectric layer, and wherein the second dielectric layer comprises a dielectric material that can be etched away using the same etchant as the etch stop layer. In some embodiments, the second dielectric layer comprises one or more of silicon carbide or oxygen-rich silicon carbide. In some embodiments, the integrated circuit further comprises: a first interconnect structure contacting the second electrode through a first hole in the first dielectric layer and the second dielectric layer and vertically contacting the second dielectric layer. In some embodiments, the integrated circuit further comprises: a second interconnect structure extending through the first interlayer dielectric layer and the etch stop layer and located beside the vertical magnetic tunnel junction stack. In some embodiments, the first interconnect structure vertically contacts the first dielectric layer. In some embodiments, the integrated circuit further comprises: a spacer layer laterally located between the first dielectric layer and the vertical magnetic tunnel junction stack.

[0068] In some embodiments, the method includes: selectively forming a first dielectric layer over a first region of a wafer, the first region including a vertical magnetic tunnel junction structure over an etch stop layer, the etch stop layer extending through a second region of the wafer laterally adjacent to the first region; selectively forming a second dielectric layer over the first region of the wafer and sealing the first dielectric layer; forming a third dielectric layer over the first region and the second region of the wafer and sealing the second dielectric layer; in a first etching operation, forming a first hole in the third dielectric layer exposing a first portion of the second dielectric layer over the vertical magnetic tunnel junction structure and a second hole exposing a second portion of the etch stop layer in the second region; in a second etching operation, removing a first portion of the second dielectric layer exposed from the first hole, exposing a third portion of the first dielectric layer through the first hole, and removing a second portion of the etch stop layer exposed from the second hole; removing the third portion of the first dielectric layer by wet cleaning; and forming a first interconnect structure in the first hole contacting the vertical magnetic tunnel junction structure and a second interconnect structure in the second hole extending through the etch stop layer.

[0069] In some embodiments, the second dielectric layer includes a dielectric material that can be etched away by the same etchant as the etch stop layer. In some embodiments, the first dielectric layer includes one or more of aluminum oxide or aluminum nitride. In some embodiments, the first etching operation includes: a partial through-hole etching process to form a first partial opening in the third dielectric layer in the first region before reaching the vertical magnetic tunnel junction structure, and a second partial opening in the second region; and a main through-hole etching process to form the first opening through the first partial opening and form the second opening from the second partial opening. In some embodiments, the first opening includes a first portion and a second portion vertically coupled to the first portion, the first portion being wider than the second portion; and wherein the second opening includes a third portion and a fourth portion vertically coupled to the third portion, the third portion being wider than the fourth portion. In some embodiments, the first portion and the third portion have substantially the same size in one or more of surface area, shape, and length.

[0070] In some embodiments, an integrated circuit includes: a substrate; a first interlayer dielectric layer located above the substrate; a first metallization component and a second metallization component located in the first interlayer dielectric layer; an etch stop layer located above the first interlayer dielectric layer; a second interlayer dielectric layer located above the etch stop layer; a vertical magnetic tunnel junction stack located in the second interlayer dielectric layer, the vertical magnetic tunnel junction stack having a first magnetic layer, a second magnetic layer, and a barrier layer vertically located between the first magnetic layer and the second magnetic layer. A first protective layer surrounding a sidewall of the vertical magnetic tunnel junction stack; a second protective layer surrounding the first protective layer; a first electrode located below the vertical magnetic tunnel junction stack, extending through the etch stop layer and contacting the first metallization component; a second electrode located above the vertical magnetic tunnel junction stack; a first interconnect structure extending from a surface of the second interlayer dielectric layer to the second electrode; and a second interconnect structure extending from a surface of the second interlayer dielectric layer to the second metallization component.

[0071] In some embodiments, the etch stop layer is one or more of SiC or SiOC, and the second protective layer is one or more of SiC, SiOC, or a dielectric material that can be etched away in the same etching process as one or more of SiC or SiOC. In some embodiments, the first protective layer is one or more of aluminum oxide or aluminum nitride.

[0072] The features of several embodiments or examples are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments or examples introduced herein. Those skilled in the art should also appreciate that this equivalent construction does not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit, comprising: a perpendicular magnetic tunnel junction stack having a first magnetic layer, a second magnetic layer, and a barrier layer between the first magnetic layer and the second magnetic layer; A first electrode is located below the vertical magnetic tunnel junction stack, wherein the first electrode includes a top surface, the top surface includes a first region in contact with the vertical magnetic tunnel junction stack, and a second region, the first region and the second region constitute the entirety of the top surface; a second electrode located above the vertical magnetic tunnel junction stack; a first dielectric layer laterally wrapping the vertical magnetic tunnel junction stack; a second dielectric layer laterally wrapping the first dielectric layer; and a spacer layer laterally disposed between the first dielectric layer and the vertical magnetic tunnel junction stack, wherein a bottom surface of the spacer layer contacts the top surface of the first electrode and in a cross-sectional view, the bottom surface of the spacer layer completely covers the second region, Wherein, in the cross-sectional view, the second dielectric layer completely covers the side surfaces of the first dielectric layer.

2. The integrated circuit according to claim 1, wherein: The spacer layer includes silicon nitride, silicon carbide, silicon dioxide, silicon oxynitride, or silicon oxycarbide.

3. The integrated circuit according to claim 1, wherein: The material of the first dielectric layer and the material of the second dielectric layer have an etching selectivity with respect to each other.

4. The integrated circuit according to claim 1, wherein: The spacer layer at least partially laterally wraps the second electrode.

5. The integrated circuit according to claim 1, wherein: The first dielectric layer laterally wraps the first electrode and at least partially wraps the second electrode.

6. The integrated circuit of claim 1, wherein: The vertical magnetic tunnel junction stack is located in a first interlayer dielectric layer and above an etch stop layer below the first interlayer dielectric layer, and wherein the second dielectric layer includes a dielectric material that can be etched away using the same etchant as the etch stop layer.

7. The integrated circuit according to claim 1, wherein: The second dielectric layer includes one or more of silicon carbide or oxygen-rich silicon carbide.

8. The integrated circuit of claim 6, further comprising: A first interconnect structure contacts the second electrode through first holes in the first dielectric layer and the second dielectric layer and vertically contacts the second dielectric layer.

9. The integrated circuit of claim 8, further comprising: A second interconnect structure extends through the first interlayer dielectric layer and the etch stop layer and is located beside the vertical magnetic tunnel junction stack.

10. The integrated circuit of claim 9, wherein: The first interconnect structure vertically contacts the first dielectric layer.

11. The integrated circuit of claim 1 , wherein: The first dielectric layer is one or more of aluminum oxide and aluminum nitride.

12. A method of forming an integrated circuit, comprising: forming a first dielectric layer over a first region of the wafer, the first region including a perpendicular magnetic tunnel junction structure over an etch stop layer, the etch stop layer extending through a second region of the wafer laterally adjacent to the first region; forming a second dielectric layer over the first region of the wafer and sealing the first dielectric layer; forming a third dielectric layer over the first region and the second region of the wafer and sealing the second dielectric layer; In a first etching operation, forming a first opening in the third dielectric layer that exposes a first portion of the second dielectric layer located above the vertical magnetic tunnel junction structure and a second opening that exposes a second portion of the etch stop layer located in the second region; In a second etching operation, removing the first portion of the second dielectric layer exposed from the first opening, exposing a third portion of the first dielectric layer through the first opening, and removing the second portion of the etch stop layer exposed from the second opening; removing the third portion of the first dielectric layer by wet cleaning; as well as A first interconnect structure is formed in the first opening contacting the perpendicular magnetic tunnel junction structure, and a second interconnect structure is formed in the second opening extending through the etch stop layer.

13. The method according to claim 12, wherein: The second dielectric layer includes a dielectric material that can be etched away by the same etchant as the etch stop layer.

14. The method according to claim 12, wherein: The first dielectric layer includes one or more of aluminum oxide or aluminum nitride.

15. The method according to claim 12, wherein: The first etching operation comprises: a partial via etching process to form a first partial opening in the third dielectric layer in the first region before reaching the perpendicular magnetic tunnel junction structure and to form a second partial opening in the second region; and A main via etching process forms the first opening through the first partial opening and forms the second opening from the second partial opening.

16. The method according to claim 15, wherein: The first opening includes a first portion and a second portion vertically coupled to the first portion, the first portion being wider than the second portion; and The second opening includes a third portion and a fourth portion vertically coupled to the third portion, and the third portion is wider than the fourth portion.

17. The method according to claim 16, wherein: The first portion and the third portion have substantially the same dimensions in one or more of surface area, shape and length.

18. An integrated circuit comprising: substrate; A first interlayer dielectric layer located above the substrate; A first metallization component and a second metallization component are located in the first interlayer dielectric layer; an etch stop layer, located above the first interlayer dielectric layer; a second interlayer dielectric layer located above the etch stop layer; a vertical magnetic tunnel junction stack located in the second interlayer dielectric layer, the vertical magnetic tunnel junction stack having a first magnetic layer, a second magnetic layer, and a barrier layer vertically located between the first magnetic layer and the second magnetic layer, the vertical magnetic tunnel junction stack including a first bottom surface; a first protection layer surrounding the sidewalls of the vertical magnetic tunnel junction stack; a second protective layer surrounding the first protective layer; a first electrode underlying the vertical magnetic tunnel junction stack, extending through the etch stop layer and contacting the first metallization; a second electrode located above the vertical magnetic tunnel junction stack; a first interconnect structure extending from a surface of the second interlayer dielectric layer to the second electrode; a second interconnect structure extending from the surface of the second interlayer dielectric layer to the second metallization feature; as well as a spacer layer laterally disposed between the first protection layer and the vertical magnetic tunnel junction stack, the first protection layer surrounding and disposed above the spacer layer, the second protection layer disposed above the first protection layer and the spacer layer, wherein a second bottom surface of the spacer layer contacts a top surface of the first electrode, and in a cross-sectional view, the second bottom surface of the spacer layer and the first bottom surface of the vertical magnetic tunnel junction stack completely cover the top surface of the first electrode, Wherein, in the cross-sectional view, the second protective layer completely covers the side surfaces of the first protective layer.

19. The integrated circuit of claim 18, wherein: The etching stop layer is one or more of SiC or SiOC, and the second protection layer is one or more of SiC, SiOC, or a dielectric material that can be etched away in the same etching process as one or more of SiC or SiOC.

20. The integrated circuit of claim 19, wherein: The first protective layer is one or more of aluminum oxide and aluminum nitride.

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