An enhanced trench gate IGBT and a method of forming the same

Abstract

The application discloses an enhanced trench gate IGBT and a forming method thereof, and sets an emitter, an N+ emission area, a P base area, a trench gate, a virtual polysilicon, a floating P area, an n-cut-off area and an n-drift area; the floating P area is arranged between the two sides of the virtual polysilicon and the trench gate, the P base area is arranged in the region between the trench gates except the virtual polysilicon and the floating P area, the N+ emission area is arranged on the two sides of the surface of the P base area, and the P base area and the floating P area are arranged above the n-drift area; the n-cut-off area is arranged below the n-drift area, the p-type collector area is arranged below the n-type cut-off area, and the collector is connected below the p-type collector area. Due to the connection between the p area in the virtual channel and the polysilicon and the external emitter electrode and the introduction of the unique gate structure, the displacement current from the floating p area to the active gate electrode is small, thereby good di / dt controllability is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power semiconductor devices, in particular to an enhanced trench gate IGBT and a forming method thereof. BACKGROUND

[0002] IGBT is the most widely used power device in power electronic applications such as home appliances, industry, renewable energy, UPS, railway, motor drive and EV&HEV applications, and has very high current handling capability due to the presence of bipolar junction transistors in its structure. About hundreds of these IGBTs can control hundreds of kilowatts of load, which is very useful in many applications. IGBT is particularly suitable for low duty cycle, low frequency, high voltage and load variation, making it possible to be used in locomotive trains, electric vehicles and hybrid electric vehicles. The growth of renewable energy sources such as solar and wind energy has led to a huge demand for high-power IGBTs. The motors used in wind turbines are variable speed, which requires the use of high-power IGBTs to improve efficiency. With the growth of infrastructure activities in developing countries, the demand for high-voltage machinery is expected to grow, thereby driving the market demand for high-power IGBTs. The application of IGBT in electric vehicles (EV) and hybrid electric vehicles (HEV) includes their application in power systems and chargers for delivering and controlling power to the motor.

[0003] Based on market demand, IGBT technology has made great progress in the past 30 years, and continues to develop the trend of technology development. In the past decade, with the progress of electric vehicles and hybrid vehicles, IGBT technology has been more advanced, and the competition between global leading automobile manufacturers has become increasingly fierce.

[0004] It is expected that the IGBT market for electric vehicles / hybrid vehicles will grow threefold during the forecast period, accounting for more than 50% of the total market. In the above-mentioned case of huge demand for IGBT, in order to significantly improve this trade-off, IGBT with floating p region, namely IEGT (Injection Enhanced IGBT), is developed, which has an electrically separated floating p region on the surface side of IGBT. The IEGT structure is shown in Figure 1 IEGT has become the main power device concept in the field of power electronics such as electric vehicles, trains and high-power applications.

[0005] In recent years, the noise problem caused by high di / dt and waveform oscillation in the inverter circuit using IGBT and IEGT has become a very serious problem. SUMMARY

[0006] The present application aims to propose an enhanced trench gate IGBT to improve IEGT electromagnetic compatibility and reduce power loss. The present application adopts the following technical solutions.

[0007] Firstly, an enhanced trench gate IGBT is provided, comprising: an emitter, an N+ emitter region, a P base region, a trench gate, a dummy polysilicon, a floating P region, an n- cutoff region and an n- drift region; the floating P region is arranged between the two sides of the dummy polysilicon and the trench gate, the P base region is arranged in the region between the trench gates except for the dummy polysilicon and the floating P region, the N+ emitter region is arranged on both sides of the surface of the P base region, and the P base region and the floating P region are arranged above the n- drift region; the n- cutoff region is arranged below the n- drift region, the p-type collector region is arranged below the n-type cutoff region, and the collector is connected below the p-type collector region.

[0008] Further, the gate oxide layer near the floating P region of the outer layer of the trench gate is thicker than the gate oxide layer near the P base region.

[0009] Further, the thickness of the gate oxide film at the bottom of the trench gate is increased.

[0010] Further, the dummy polysilicon is parallel to the trench gate.

[0011] Further, the dummy polysilicon is two, and the two dummy polysilicons are separated and have a narrow P base region in the middle, and the two dummy polysilicons are connected to the emitter.

[0012] Further, the floating P region is connected to the emitter.

[0013] On the other hand, the application provides a manufacturing process of an enhanced trench gate IGBT, comprising the following steps:

[0014] Step 1: after p-base diffusion, trench etching and deposition of doped polysilicon gate, and after subsequent RIE, CDE and wet etching of the trench gate region;

[0015] Step 2: CVD SiO2;

[0016] CVD is chemical vapor deposition

[0017] Step 3: CMP and photolithography process are performed;

[0018] Step 4: RIE and CDE are performed, sacrificial SiO2 is grown, and then SiO2 etching is performed

[0019] Deposition of doped polysilicon and CMP, and finally n+ emitter and p+ base diffusion. The advanced trench gate structure is realized by the above manufacturing process steps.

[0020] The beneficial technical effects achieved by the application are:

[0021] 1) Due to the connection between the p-region in the virtual channel and the polysilicon and the external emitter electrode and the introduction of a unique gate structure, the displacement current from the floating p-region to the active gate electrode is small, thus obtaining good di / dt controllability.

[0022] 2) Excellent performance is achieved in di / dt controllability without sacrificing Vce(sat). So far, these technologies proposed by people cannot be realized without sacrificing Vce(sat), switching time and di / dt controllability.

[0023] 3) Due to the significant reduction of Cgc mirror capacitance, fast turn-off switching speed is achieved, and the turn-off time is one-third of that of the traditional IEGT. The low conduction di / dt controllability of IEGT is improved, thus completely overcoming electromagnetic interference and catastrophic failure. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a cross-sectional view of a conventional IEGT (Injection Enhanced IGBT);

[0025] Figure 2 is a capacitance equivalent circuit of a conventional IEGT with a floating p-region;

[0026] Figure 3 is an operating schematic diagram of a conventional IEGT with a floating p-region during turn-on;

[0027] Figure 4 is a cross-sectional view of an enhanced trench gate IGBT structure provided by an embodiment of the present application;

[0028] Figure 5 is a manufacturing process step flow of an enhanced trench gate IGBT structure of an embodiment of the present application;

[0029] Figure 6 is an improved equivalent circuit of an enhanced trench gate IGBT provided by an embodiment of the present application;

[0030] Figure 7 is a cross-sectional view and a plan view of a partial active region and a termination region of an embodiment, wherein 7(a) is a cross-sectional view and 7(b) is a plan view;

[0031] Figure 8 is a partial plan view of an edge termination and an active cell region of an embodiment;

[0032] Figure 9 is a partial cross-sectional view of an embodiment along the line shown in Figure 8 . DETAILED DESCRIPTION

[0033] Figure 1This is a cross-sectional view of a conventional IEGT (Injection Enhancement IGBT); the P-floating region in the figure is the floating P-region. Channel-gate IEGTs with floating P-regions significantly improve the trade-off between on-state voltage drop and off-state switching power consumption. However, it is well known that IEGTs with floating P-regions have poor on-state di / dt controllability. Therefore, high di / dt leads to high reverse recovery dVce / dt, which in turn causes electromagnetic interference noise problems, current / voltage oscillations, and ultimately catastrophic failures. Since this is one of the most serious problems in the inverter power supplies used by IEGTs, it is essential to completely avoid this very serious problem faced by power devices. The purpose of this invention is to improve the low on-state di / dt controllability of IEGTs, thereby completely overcoming electromagnetic interference and catastrophic failures.

[0034] Figure 2 This is the equivalent capacitance circuit for a traditional IGBT with a floating p-region. The additional parasitic capacitances of the IGBT are Ccgf1 and Ccgf2, such as... Figure 2 As shown, the floating p-region introduces additional parasitic capacitances Ccgf1 and Ccgf2. During conduction, these additional capacitances cause a large displacement current to flow into the active gate electrode, resulting in a rapid increase in Vge.

[0035] Previous studies have shown that the rapid increase in gate voltage during conduction is caused by displacement current from the floating p-region, which leads to uncontrolled Vge gate voltage and consequently poor di / dt controllability.

[0036] Figure 3 This is a schematic diagram of the operation of a traditional IEGT with a floating p-region during turn-on. During turn-on, holes accumulate at the collector near the floating p-region and the bottom of the channel gate, causing the potential of the floating p-region, Vfp, to increase rapidly, resulting in an increase in dVfp / dt. dVfp / dt causes a displacement current to enter the channel gate facing the floating p-region, leading to a rapid increase in Vge. At this time, the applied Vge and Rg cannot control the turn-on of di / dt. When hole carriers increase, holes also accumulate around the bottom of the channel gate, and the p-channel region around the bottom of the channel is formed because the potential of the floating p-channel region and the bottom region is higher than the potential of the gate electrode. The holes accumulated in the floating p-region can flow into the p-base through the p-channel formed at the bottom of the trench and out to the emitter region. Therefore, the voltage of the floating p-region cannot be increased further.

[0037] Now, according to Figure 3 A detailed explanation of the mechanism of poor di / dt controllability. Figure 3is a schematic diagram of how the process occurs during turn-on. When the n-channel is formed during the conduction process, electrons flow from the n+ emitter to the n-drift region. At the same time, holes are injected from the p-collector to the n-drift region. The holes accumulate inside and below the floating p-region, and the accumulation of holes increases the potential of the floating p-region.

[0038] During conduction, the potential of the floating p-region increases rapidly, and the rapid increase in potential causes Figure 3 The displacement current shown by the arrow flows into the gate. The additional displacement current into the gate electrode results in a higher gate voltage than the externally applied gate voltage Vge.

[0039] In short, the gate electrode facing the floating p-region is charged by the displacement current, and the charging current is added to the general charging current through the gate resistor Rg. During the conduction process, the collector current Ic produces an overshoot current waveform, resulting in poor di / dt controllability. The holes of the collector not only accumulate in the floating p-region, but also accumulate in the n-drift region around the bottom of the channel gate. It can be said that the p-channel MOSFET is composed of a floating p-region, an n-drift region, and a p-base region, formed near the channel gate.

[0040] When excess hole carriers accumulate in this region, the p-channel MOSFET can form a p-channel at the bottom of the channel gate. At this time, the hole carriers in the floating p-region can flow out to the emitter region via the p-base region. Therefore, the floating p-region voltage never exceeds the floating p-region voltage formed by the p-channel around the channel gate. The threshold voltage of the p-channel MOSFET can now be formulated as follows:

[0041] Vth= (qN d tox ) / ( Kɛ0 ) + 2ɸn

[0042] where q is the electronic charge, K is a constant, N represents the donor concentration in the n-drift, d represents the depletion width, tox represents the oxide thickness, ɛ0 represents the vacuum permittivity, and ɸn represents the Fermi potential in n-type Si.

[0043] Therefore, in order to overcome this shortcoming, some new device structures have been proposed, such as no floating p-region or separating the p-region from the active channel gate. However, in this new structure, there is a trade-off between the breakdown voltage and Vce(sat).

[0044] In order to enable those skilled in the art to more clearly understand the scheme and principles of the present application, the following will be described in detail in conjunction with the drawings and specific embodiments. The content of the present application is not limited to any specific embodiment, nor is it the best embodiment, and general alternatives known to those skilled in the art are also covered within the scope of protection of the present application.

[0045] Example 1: An enhanced trench-gate IGBT, such as Figure 4As shown, it comprises: setting the emitter, N+ emission area, P base area, trench gate, virtual polysilicon, floating P area, n- cutoff area and n- drift area; The two sides of the virtual polysilicon are respectively provided with the floating P area between the trench gates, and the P base area is provided in the area between the trench gates except the virtual polysilicon and the floating P area, the N+ emission area is provided on both sides of the surface of the P base area, and the P base area and the floating P area are both provided above the n- drift area; The n- cutoff area is provided below the n- drift area, the p-type collector area is provided below the n-type cutoff area, and the collector is connected below the p-type collector area.

[0046] The technical breakthrough made by the present application is as follows:

[0047] 1) Additional virtual channel polysilicon area in the active channel gate region to obtain additional hole passing lines.

[0048] 2) Connect the floating p area in the virtual channel and the polysilicon with the emitter electrode along the external active area, and the hole carriers flow out through the large resistance formed in the virtual channel.

[0049] 3) The reduction of displacement current leads to a slow increase in the potential of the p area, which can be achieved by a unique active channel gate structure.

[0050] 4) In order to avoid the formation of p channel, a high threshold voltage is provided around the active channel gate, so as to generate a higher FP potential in the conduction process.

[0051] 5) A unique gate structure is adopted, which reduces the mirror capacitance Cgc, shortens the turn-off time, and realizes higher performance.

[0052] Some ideas in the embodiments of the present patent are based on some concepts described above, and the detailed description of the specific embodiments is shown in Figure 4 、 Figure 5 、 Figure 6 and Figure 7 .

[0053] Figure 4 The cross-sectional view of the device structure proposed in the present patent is shown.

[0054] Figure 4 The circle part 1 in the figure shows that the channel gate facing the floating p area has a thicker gate oxide film, and the gate capacitance can be significantly reduced. Therefore, its structure greatly reduces the charging caused by displacement current.

[0055] Figure 4Circle 2 in the diagram shows that the gate oxide film around the bottom of the active channel gate is thicker, resulting in a higher threshold voltage and a significantly reduced Cgc in the region surrounding the channel gate. During turn-on, a higher initial float voltage means a higher threshold voltage for the p-channel MOSFET, thus the float voltage in the p-region increases more slowly compared to a lower initial float voltage. Consequently, the increase in di / dt during turn-on becomes even lower.

[0056] Figure 4 The portions of circles 3 and 4 in the middle represent an additional virtual channel polysilicon, parallel to the active channel gate and located between the active channel gates, as shown below. Figure 4 As shown. Part 3 indicates that it has a very small contact area and a very narrow p-region in the channel virtual polysilicon, and the contact area is connected to the outermost emitter electrode of the active region, and the polysilicon in the virtual channel is connected to the outermost emitter electrode of the active region.

[0057] The improved equivalent circuit of the IEGT structure proposed in this invention is as follows: Figure 6 As shown. The connection between the floating p-region and the external emitter electrode is achieved through a large resistance formed in the narrow p-region. Figure 6 and Figure 7 The small contact area shown results in a quasi-connected p-region during conduction, while a quasi-floating p-region can be achieved during static conduction. A more detailed explanation of the structure is provided. Figure 8 and Figure 9 The complex structure becomes clearer.

[0058] Figure 5 (a), (b), (c), (d), (e), and (f) show the following: Figure 4 The manufacturing process flow for the proposed new channel gate structure is shown. As mentioned above, the unique channel gate structure can significantly reduce displacement charging current and parasitic mirror capacitance.

[0059] according to Figure 5 The manufacturing process steps for the unique channel gate are shown. Figure 5 (a) shows the channel gate region after p-based diffusion, dry trench etching, and doped polysilicon gate deposition, as well as after subsequent RIE, CDE, and wet etching, as shown. Figure 5 As shown in (b). The next process step is CVD (chemical vapor deposition) of SiO2, as... Figure 5 As shown in (c), CMP (Chemical Mechanical Polishing) and photolithography processes are then performed, as follows: Figure 5(d) as shown, followed by RIE (Reactive ion etching) and CDE (Chemical Dry Etch) of the sacrificial SiO2 growth, followed by SiO2 etching, as shown in Figure 5 (e) as shown. As shown in Figure 5 (f) as shown, deposition of doped polysilicon and CMP, and finally n+ emitter and p+ base diffusion. The advanced trench gate structure is achieved by the above manufacturing process steps. The advanced trench structure enables small displacement current into the active trench gate and the p-channel MOSFET at the bottom of the trench gate has a higher threshold voltage, thus reducing the di / dt rise rate.

[0060] As shown in Figure 6 and Figure 7 the introduction of a very narrow dummy trench and connection to the emitter electrode along the outside of the active cell area results in bypassing of the resistance for the charging current and the change in Vge becomes very small. The introduction of dummy trench polysilicon enables a fast rise of the floating p potential due to the formation of an equal p-channel along the bottom of the dummy trench during conduction.

[0061] In short, it can be said that the additional dummy trench polysilicon results in good di / dt controllability without sacrificing performance such as Vce(sat) and switching time. Because the IE (Injection Enhancement) effect is still maintained during the static on period. The dummy trench polysilicon and the p-region connected to the outermost emitter form an additional hole current path, resulting in a fast increase in the floating potential of the p-region. During the static period, no p-channel can be formed around the dummy polysilicon due to the additional connection of the emitter electrode.

[0062] As mentioned earlier, the purpose of this patent is to overcome the drawbacks, poor di / dt controllability and long turn-off delay time.

[0063] As shown in Figure 4 , Figure 4 circle 1 in Figure 4 results in lower displacement current because of the thicker gate oxide facing the floating p-region. At the same time, the thicker oxide around the bottom of the trench gate results in a higher threshold voltage around the bottom of the trench gate, as shown in Figure 4 circle 2. It results in a higher potential Vfp during the initial phase of the on period and results in good di / dt controllability.

[0064] Figure 4The circles 3 and 4 in the figure cause the polysilicon in the virtual p-zone and virtual channel to be connected to the emitter electrode through a higher resistance in the polar core p-zone along the outermost active area of the emitter electrode, and cause a lower displacement current to pass through the virtual channel during conduction due to the additional hole current path, the IE effect still exists during static conduction, because the current through the high resistance is very small, there is no p-channel as a hole pass, low Vce(sat) can be achieved.

[0065] Figure 5 The processing step flow of the forming method of the new structure is shown. Figure 6 The improved equivalent circuit of the proposed IRGT structure.

[0066] Figure 7 The cross-sectional view (a) and plan view (b) of the local active area and termination area are shown. Figure 8 The local plan view of the edge termination and active cell area is shown, Figure 9 The local cross-sectional view along the line shown. Figure 8 The local cross-sectional view along the line shown.

[0067] Figure 8 And Figure 9 It is shown that the polysilicon in the virtual channel and the p-zone along the outside of the active area in circle 1 are connected to the emitter electrode, and the virtual channel between the channel gates has an island-shaped p-zone connected to the emitter electrode as shown in circle 2.

[0068] The present patent has the following beneficial technical effects:

[0069] 1) Due to the connection between the p-zone in the virtual channel and the polysilicon and the outer emitter electrode, and the introduction of the unique gate structure, the displacement current from the floating p-zone to the active gate electrode is small, so good di / dt controllability is obtained.

[0070] 2) Excellent performance is achieved in di / dt controllability without sacrificing Vce(sat). So far, these technologies proposed by people cannot be achieved without sacrificing Vce(sat), switching time and di / dt controllability.

[0071] 3) Due to the significant reduction of Cgc mirror capacitance, fast turn-off switching speed is achieved, and the turn-off time is one-third of that of traditional IEGT.

[0072] The present application is not limited to the embodiments discussed above. The above description of the specific embodiments is intended to describe and illustrate the technical solutions involved in the present application. Any obvious changes or substitutions based on the technical ideas of the present application should be considered to fall within the protection scope of the present application. The above specific embodiments are used to disclose the best implementation methods of the present application, so that those skilled in the art can apply various embodiments and various alternatives of the present application to achieve the purpose of the present application.

Claims

1. An enhanced trench gate IGBT, characterized in that, include: The system comprises an emitter, an N+ emitter region, a P-base region, a trench gate, a dummy polysilicon, a floating P-region, an n-cutoff region, and an n-drift region. Floating P-regions are positioned between the two sides of the dummy polysilicon and the trench gate. A P-base region is positioned in the area between the trench gate, excluding the dummy polysilicon and floating P-regions. N+ emitter regions are positioned on both sides of the P-base region. Both the P-base region and the floating P-region are positioned above the n-drift region. An n-cutoff region is positioned below the n-drift region, and a p-type collector region is positioned below the n-type cutoff region. A collector electrode is connected below the p-type collector region. The gate oxide layer on the outer layer of the trench gate closer to the floating P-region is thicker than the gate oxide layer closer to the P-base region. The thickness of the gate oxide film at the bottom of the trench gate is increased. There are two dummy polysilicon units, separated and separated by a narrow P-base region. Both dummy polysilicon units are connected to the emitter.

2. The enhanced trench gate IGBT according to claim 1, characterized in that, The virtual polysilicon is parallel to the trench gate.

3. The enhanced trench gate IGBT according to claim 1, characterized in that, The floating P-region is connected to the emitter.

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