Clock generation circuit and semiconductor device using the same

Abstract

The present disclosure relates to a clock generation circuit and a semiconductor device using the clock generation circuit. The clock generation circuit may include a clock receiver, a first delay loop and a second delay loop. The clock receiver may receive a first clock signal and a second clock signal, and generate a first received clock signal and a second received clock signal. The first delay loop may receive the first received clock signal and the second received clock signal, and generate a reference clock signal. The first delay loop may perform a delay locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop may delay the first received clock signal and the second received clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0024488 filed on February 27, 2020 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments relate generally to integrated circuit technology, and more particularly to clock generation circuits and semiconductor devices using the same. Background Art

[0004] Electronic devices include many electronic components. A computer system of electronic components may include many semiconductor devices configured with semiconductors. The semiconductor devices constituting the computer system may communicate with each other by transmitting and receiving clock signals and data. The semiconductor device may operate synchronously with the clock signal. The semiconductor device may output or receive data synchronously with the clock signal. Therefore, in order to perform smooth data communication between semiconductor devices, it is necessary to generate a clock signal with an accurate phase and a small skew. The semiconductor device is equipped with various clock generation circuits to generate a multi-phase clock signal according to the clock signal. For example, the clock generation circuit may include a phase-locked loop, a delay-locked loop, etc. The delay-locked loop may include a digital delay-locked loop controlled according to a digital method and an analog delay-locked loop controlled according to an analog method. In order to generate a multi-phase clock signal with a constant phase difference between the phase-locked loop and the delay-locked loop regardless of voltage and / or process changes, a phase-locked loop or a delay-locked loop with high performance may be used. However, the use of a clock generation circuit with high performance may inevitably require a large amount of power, which may not conform to the technical trend of low power of semiconductor devices. Summary of the invention

[0005] In an embodiment, the clock generation circuit may include a clock receiver, a first delay loop, and a second delay loop. The clock receiver may be configured to receive a first clock signal and a second clock signal to generate a first received clock signal and a second received clock signal. The first delay loop may be configured to receive the first received clock signal and the second received clock signal to generate a reference clock signal. The first delay loop may be configured to perform a delay locking operation on the reference clock signal to generate a first delay locked clock signal. The second delay loop may be configured to delay the first received clock signal and the second received clock signal based on the first delay locked clock signal and the internal clock signal to generate a first internal clock signal.

[0006] In an embodiment, the clock generation circuit may include a clock receiver, a first delay loop, and a second delay loop. The clock receiver may be configured to receive a first clock signal and a second clock signal to generate a first received clock signal and a second received clock signal. The first delay loop may be configured to receive the first received clock signal and the second received clock signal to generate a first reference clock signal. The first delay loop may be configured to delay the first reference clock signal based on a first delay locked clock signal and a first internal clock signal to generate a first delay locked clock signal. The second delay loop may be configured to perform a delay locking operation on the first received clock signal and the second received clock signal to generate a first internal clock signal.

[0007] In an embodiment, a semiconductor device may include a clock receiver, a first delay loop, a second delay loop, a command decoder, a command delay line, a time delay shift circuit, and a gating circuit. The clock receiver may be configured to receive a first clock signal and a second clock signal to generate a first received clock signal and a second received clock signal. The first delay loop may include a single-ended CMOS clock delay line. The first delay loop may be configured to delay a reference clock signal to generate a first delay locked clock signal based on a reference clock signal and a first delay locked clock signal generated according to the first received clock signal and the second received clock signal. The second delay loop may include a differential current mode logic (CML) clock delay line. The second delay loop may be configured to delay the first received clock signal and the second received clock signal to generate a first internal clock signal based on the first delay locked clock signal and the first internal clock signal. The command decoder may be configured to decode the command signal to generate an internal command signal. The command delay line may be configured to delay the internal command signal by substantially the same time as the following to generate a delayed command signal: the reference clock signal is delayed by the single-ended CMOS clock delay line for a required duration. The delay shift circuit may be configured to delay the delay command signal by a time corresponding to the delay based on the first delay locked clock signal to generate a synchronization command signal. The gating circuit may be configured to synchronize the synchronization command signal with the first internal clock signal to generate an output control signal.

[0008] In an embodiment, a semiconductor device may include a clock receiver, a first delay loop, a second delay loop, a command decoder, a command delay line, a time delay shift circuit, and a gating circuit. The clock receiver may be configured to receive a first clock signal and a second clock signal to generate a first received clock signal and a second received clock signal. The first delay loop may include a single-ended CMOS clock delay line. The first delay loop may be configured to delay the first reference clock signal to generate a first delay locked clock signal based on a first reference clock signal and a first internal clock signal generated according to the first received clock signal and the second received clock signal. The second delay loop may include a differential current mode logic (CML) clock delay line. The second delay loop may be configured to delay the first received clock signal and the second received clock signal to generate a first internal clock signal based on a first internal clock signal and a second reference clock signal generated according to the first received clock signal and the second received clock signal. The command decoder may be configured to decode the command signal to generate an internal command signal. The command delay line may be configured to delay the internal command signal for a duration substantially the same as the following duration to generate a delayed command signal: the first reference clock signal is delayed by the single-ended CMOS clock delay line for a required duration. The delay shift circuit may be configured to delay the delay command signal by a time corresponding to the delay based on the first internal clock signal to generate a synchronization command signal. The gating circuit may be configured to synchronize the synchronization command signal with the first internal clock signal to generate an output control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a diagram illustrating a configuration of a clock generation circuit according to an embodiment;

[0010] Figure 2 It is a graphic Figure 1 A diagram of the configuration of the first delay loop shown;

[0011] Figure 3 It is a graphic Figure 2 A diagram showing a configuration of an enable control circuit as shown;

[0012] Figure 4 It is a graphic Figure 1 a diagram of the configuration of the second delay loop shown;

[0013] Figure 5 It is a graphic Figure 4 A diagram showing the configuration of a clock frequency dividing circuit;

[0014] Figure 6 It is a graphic Figure 5 A diagram showing the configuration of a CML clock divider;

[0015] Figure 7 It is a graphic Figure 6 A timing diagram of the operation of the CML clock divider is shown;

[0016] Figure 8 It is a graphic Figure 5 A diagram of a configuration of a CML to CMOS converter is shown;

[0017] Fig. 9 It is a graphic Figure 8 A diagram of the configuration of the first converter shown;

[0018] Fig.10 is a diagram illustrating a configuration of a semiconductor device according to an embodiment;

[0019] Fig.11 is a diagram illustrating a configuration of a clock generation circuit according to an embodiment;

[0020] Fig.12 is a diagram illustrating a configuration of a clock generation circuit according to an embodiment;

[0021] Fig.13 is a diagram illustrating a configuration of a semiconductor device according to an embodiment;

[0022] Fig.14 is a diagram illustrating a configuration of a delay line according to an embodiment;

[0023] Fig.15 It is a graphic Fig.14 A diagram of the configuration of a coarse delay line is shown;

[0024] Fig.16 is a diagram illustrating a configuration of a CML buffer 1600 according to an embodiment of the present disclosure; and

[0025] Fig.17 is a diagram illustrating a configuration of a CML multiplexer according to an embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments are described with reference to the accompanying drawings.

[0027] Figure 1 1 is a diagram illustrating a configuration of a clock generation circuit 100 according to an embodiment. Figure 1, the clock generation circuit 100 can generate multiple output clock signals by receiving clock signals CLK and CLKB. The clock generation circuit 100 may include at least two delay loops. At least two delay loops may have different characteristics. At least two delay loops may generate output signals with different characteristics by delaying the received clock signals respectively. One delay loop may consume less power than another delay loop to delay the clock signal. Another delay loop may consume more power than a delay loop to delay the clock signal. However, another delay loop may generate an output clock signal with higher performance than a delay loop, and the output clock signal has an accurate phase and an accurate duty cycle. In addition, another delay loop can minimize the phase skew between multiple output clock signals. One delay loop may include a single-ended CMOS clock delay line. Another delay loop may include a differential current mode logic (CML) clock delay line. Therefore, another delay loop may consume more power than a delay loop, but perform accurate delay operations.

[0028] The clock generation circuit 100 may include a clock receiver (RX) 101, a first delay loop 110, and a second delay loop 120. The clock receiver 101 may receive a first clock signal CLK and a second clock signal CLKB. The clock receiver 101 may generate a first receive clock signal RCLK and a second receive clock signal RCLKB by differentially amplifying the first clock signal CLK and the second clock signal CLKB. The second clock signal CLKB may be a complementary signal having a phase opposite to that of the first clock signal CLK. The first clock signal CLK and the second clock signal CLKB may be system clock signals transmitted by an external device of a semiconductor device including the clock generation circuit 100. In an embodiment, the first clock signal CLK and the second clock signal CLKB may be clock signals generated by a ring oscillator, a phase-locked loop, or the like. The second receive clock signal RCLKB may be a complementary signal having a phase opposite to that of the first receive clock signal RCLK. The first receive clock signal RCLK may have a phase corresponding to that of the first clock signal CLK. The second receive clock signal RCLKB may have a phase corresponding to that of the second clock signal CLKB.

[0029] The first delay loop 110 may receive a first receive clock signal RCLK and a second receive clock signal RCLKB. The first delay loop 110 may generate a first delay locked clock signal DCLK1 by delaying the first receive clock signal RCLK and the second receive clock signal RCLKB. The first delay loop 110 may generate a reference clock signal according to the first receive clock signal RCLK and the second receive clock signal RCLKB, and may generate the first delay locked clock signal DCLK1 by performing a delay locking operation on the reference clock signal. The first delay loop 110 may include a clock delay line, and the clock delay line of the first delay loop 110 consumes a relatively small amount of power and requires relatively low performance compared to the clock delay line of the second delay loop 120 in order to delay the first receive clock signal RCLK and the second receive clock signal RCLKB and / or the reference clock signal. The first delay loop 110 may include a single-ended CMOS clock delay line. The reference clock signal may be generated as a single-ended signal. The single-ended CMOS clock delay line may include a plurality of CMOS delay units that sequentially delay the single-ended signal. The first delay loop 110 may control whether to activate the second delay loop 120 based on the operation mode and the delay locking operation. The first delay loop 110 may deactivate the second delay loop 120 under certain conditions in order to minimize the power consumption of the clock generation circuit 100. The first delay loop 110 may generate an enable signal EN2 based on the operation mode and the delay locking operation. For example, in a power-off mode and / or a low-power mode, when the phase of the first delay-locked clock signal varies within a given range, the first delay loop 110 may deactivate the second delay loop 120 by maintaining the state of the enable signal EN2 in a disabled state. When the phase of the first delay-locked clock signal varies beyond a given range, the first delay loop 110 may activate the second delay loop 120 by enabling the enable signal EN2. The given range may be defined by a threshold value related to the number of updates of the first delay loop 110. When an update for increasing the delay amount of the first delay loop 110 occurs continuously for a threshold number of times or more, or an update for reducing the delay amount of the first delay loop 110 occurs continuously for a threshold number of times or more, the first delay loop 110 may activate the second delay loop 120 by enabling the enable signal EN2. When an update for increasing the delay amount of the first delay loop 110 and an update for reducing the delay amount of the first delay loop 110 occur alternately or any one of the updates does not occur continuously for a number of times corresponding to the threshold, the first delay loop 110 may maintain the state of the enable signal EN2 in a disabled state and deactivate the second delay loop 120.

[0030] The second delay loop 120 may generate at least one internal clock signal by delaying the first received clock signal RCLK and the second received clock signal RCLKB. The second delay loop 120 may generate a first internal clock signal ICLK by delaying the first received clock signal RCLK and the second received clock signal RCLKB. The second delay loop 120 may generate a first internal clock signal ICLK by delaying the first received clock signal RCLK and the second received clock signal RCLKB based on the first delay locked clock signal DCLK1 generated by the first delay loop 110 and the first internal clock signal ICLK. The second delay loop 120 may generate a first internal clock signal ICLK having substantially the same phase as the first delay locked clock signal DCLK1 by comparing the phases of the first delay locked clock signal DCLK1 and the first internal clock signal ICLK. The second delay loop 120 may also generate a second internal clock signal QCLK, a third internal clock signal IBCLK, and a fourth internal clock signal QBCLK by delaying the first received clock signal RCLK and the second received clock signal RCLKB. The first to fourth internal clock signals ICLK, QCLK, IBCLK and QBCLK may have the same phase difference in sequence. The second internal clock signal QCLK may have a phase 90° later than the phase of the first internal clock signal ICLK. The third internal clock signal IBCLK may have a phase 90° later than the phase of the second internal clock signal QCLK. The fourth internal clock signal QBCLK may have a phase 90° later than the phase of the third internal clock signal IBCLK. The first internal clock signal ICLK may have a phase 90° later than the phase of the fourth internal clock signal QBCLK. The second delay loop 120 may be selectively activated by the first delay loop 110. The second delay loop 120 may receive an enable signal EN2 generated by the first delay loop 110. When the enable signal EN2 is enabled, the second delay loop 120 may be activated to generate the first internal clock signal ICLK. When the enable signal EN2 is disabled, the second delay loop 120 may be deactivated and may not generate the first internal clock signal ICLK.

[0031] Figure 2 It is a graphic Figure 1 FIG. 1 is a diagram showing the configuration of the first delay loop 110. Figure 2, the first delay loop 110 may include a first clock buffer 210, a first clock delay line 220, a replicator 230, a first phase detector 240, and a first delay control circuit 250. The first clock buffer 210 may receive a first received clock signal RCLK and a second received clock signal RCLKB. The first clock buffer 210 may buffer the first received clock signal RCLK and the second received clock signal RCLKB, and may provide the buffered clock signal 211 as a reference clock signal REFCLK. The first clock delay line 220 may receive a reference clock signal REFCLK, and may generate a first delay locked clock signal DCLK1 by delaying the reference clock signal REFCLK. The first clock delay line 220 may delay the reference clock signal REFCLK based on a first delay control signal DC1. The delay amount of the first clock delay line 220 may be changed based on the first delay control signal DC1. The first clock delay line 220 may be a single-ended CMOS delay line, and may include a plurality of CMOS delay cells. In an embodiment, the first clock delay line 220 may further include a shift register circuit for changing the number of activated CMOS delay cells based on the first delay control signal DC1.

[0032] The replica 230 may receive the first delay locked clock signal DCLK1, and may generate the feedback clock signal FBCLK by delaying the first delay locked clock signal DCLK1 by the modeling delay time. The replica 230 may be designed to have a given delay amount. The replica 230 may model a clock path along which the clock signals CLK and CLKB are transmitted through the clock generation circuit 100 and / or an internal circuit of a semiconductor device including the clock generation circuit 100. The replica 230 may have a delay amount corresponding to the delay time that contributes to the clock path of the semiconductor device including the clock generation circuit 100.

[0033] The first phase detector 240 may receive a reference clock signal REFCLK and a feedback clock signal FBCLK. The first phase detector 240 may generate a first phase detection signal PD1 by comparing the phases of the reference clock signal REFCLK and the feedback clock signal FBCLK. The first phase detector 240 may change the logic level of the first phase detection signal PD1 by detecting whether the phase of the reference clock signal REFCLK is earlier or later than the phase of the feedback clock signal FBCLK. For example, when the phase of the reference clock signal REFCLK is earlier than the phase of the feedback clock signal FBCLK, the first phase detector 240 may generate the first phase detection signal PD1 having a logic high level. When the phase of the reference clock signal REFCLK is later than the phase of the feedback clock signal FBCLK, the first phase detector 240 may generate the first phase detection signal PD1 having a logic low level.

[0034] The first delay control circuit 250 may receive the first phase detection signal PD1 generated by the first phase detector 240. The first delay control circuit 250 may generate the first delay control signal DC1 based on the first phase detection signal PD1. The first delay control signal DC1 may be an update signal for changing the delay amount of the first clock delay line 220. The first delay control signal DC1 may include a phase increase signal INC and a phase decrease signal DEC. The phase increase signal INC may be a signal for increasing the delay amount of the first clock delay line 220. The phase increase signal INC may be a signal for increasing the number of activated CMOS delay cells. The phase decrease signal DEC may be a signal for reducing the delay amount of the first clock delay line 220. The phase decrease signal DEC may be a signal for reducing the number of activated CMOS delay cells. The first delay control circuit 250 may generate the phase increase signal INC and the phase decrease signal DEC based on the first phase detection signal PD1 until the phases of the reference clock signal REFCLK and the feedback clock signal FBCLK become substantially the same. When the phase increase signal INC and the phase decrease signal DEC are alternately generated, the first delay control circuit 250 can determine that the phases of the reference clock signal REFCLK and the feedback clock signal FBCLK have been matched, and can fix the delay amount of the first clock delay line 220 by generating a lock signal. In an embodiment, the first delay control circuit 250 may include a filter. The filter may include one of an average filter and a sliding average filter. For example, when the first phase detection signal PD1 having a logic high level is continuously generated a number of times corresponding to a threshold, the filter may generate a phase increase signal INC. When the first phase detection signal PD1 having a logic low level is continuously generated a number of times corresponding to a threshold, the filter may generate a phase decrease signal DEC. When the difference between the number of times the first phase detection signal PD1 having a logic high level is generated and the number of times the first phase detection signal PD1 having a logic low level is generated corresponds to the threshold, the filter may generate one of the phase increase signal INC and the phase decrease signal DEC.

[0035] The first delay loop 110 may further include a clock divider 260. The clock divider 260 may be coupled between the first clock buffer 210 and the first clock delay line 220. The clock divider 260 may divide the frequency of the buffered clock signal 211 output by the clock buffer 210, and may provide the divided clock signal as the reference clock signal REFCLK. For example, the clock divider 260 may generate a reference clock signal REFCLK by dividing the buffered clock signal 211, the reference clock signal REFCLK having a lower frequency and a longer period than the first reception clock signal RCLK and the second reception clock signal RCLKB.

[0036] The first delay loop 110 may further include an enable control circuit 270. The enable control circuit 270 may generate an enable signal EN2 by receiving the first delay control signal DC1 and the power-off signal PWRD. The power-off signal PWRD may be a signal indicating that the clock generation circuit 100 and / or a semiconductor device including the clock generation circuit 100 operates in a power-off mode and / or a low-power mode. When the semiconductor device operates in a power-off mode and / or a low-power mode, the power-off signal PWRD may be enabled. In the case where the power-off signal PWRD has been disabled, that is, when the semiconductor device does not operate in a power-off mode and / or a low-power mode, the enable control circuit 270 may enable the enable signal EN2 regardless of the first delay control signal DC1. In the case where the power-off signal PWRD has been enabled, the enable control circuit 270 may selectively enable the enable signal EN2 based on the first delay control signal DC1. In the case where the power-down signal PWRD has been enabled, when the phase difference between the reference clock signal REFCLK and the feedback clock signal FBCLK is not large, the enable control circuit 270 may maintain the state of the enable signal EN2 in a disabled state. When the phase difference between the reference clock signal REFCLK and the feedback clock signal FBCLK is within a given range, the enable control circuit 270 may maintain the state of the enable signal EN2 in a disabled state. On the contrary, when the phase difference between the reference clock signal REFCLK and the feedback clock signal FBCLK increases, the enable control circuit 270 may enable the enable signal EN2. When the phase difference between the reference clock signal REFCLK and the feedback clock signal FBCLK is outside a given range, the enable control circuit 270 may enable the enable signal EN2.

[0037] Figure 3 It is a graphic Figure 2 FIG. 2 is a diagram showing a configuration of the enable control circuit 270. Figure 3, the enable control circuit 270 may include an up-down counter 310, an inverter 321, a first OR gate 331, a second OR gate 332, and a third OR gate 333. The up-down counter 310 may receive the first delay control signal DC1 and count the first delay control signal DC1. The up-down counter 310 may generate a maximum signal MAX and a minimum signal MIN by counting the first delay control signal DC1. The up-down counter 310 may generate a maximum signal MAX and a minimum signal MIN by counting the phase increase signal INC and the phase decrease signal DEC, respectively. When one of the phase increase signal INC and the phase decrease signal DEC is continuously counted a number of times corresponding to a threshold value, the up-down counter 310 may generate a maximum signal MAX and a minimum signal MIN each having a logic high level. When one of the phase increase signal INC and the phase decrease signal DEC is not continuously generated a number of times corresponding to the threshold value, the up-down counter 310 may maintain each level of the maximum signal MAX and the minimum signal MIN at a logic low level. For example, assuming that the threshold is 4, when one of the phase increase signal INC and the phase decrease signal DEC is generated four times in succession, the up-down counter 310 can generate a maximum signal MAX and a minimum signal MIN each having a logic high level. When the phase increase signal INC and the phase decrease signal DEC are alternately generated, the up-down counter 310 can maintain each level of the maximum signal MAX and the minimum signal MIN at a logic low level. The up-down counter 310 can receive the power-off signal PWRD. The up-down counter 310 can be selectively activated based on the power-off signal PWRD. In the case where the power-off signal PWRD has been disabled, the up-down counter 310 can be deactivated. When the power-off signal PWRD is enabled, the up-down counter 310 can be activated to perform a counting operation.

[0038] The inverter 321 may receive the power-off signal PWRD and output an inverted power-off signal by inverting the power-off signal PWRD. The first OR gate 331 may receive the maximum signal MAX and the output signal of the inverter 321. When any one of the maximum signal MAX and the output signal of the inverter 321 has a logic high level, the first OR gate 331 may output a signal having a logic high level. The second OR gate 332 may receive the minimum signal MIN and the output signal of the inverter 321. When any one of the minimum signal MIN and the output signal of the inverter 321 has a logic high level, the second OR gate 332 may output a signal having a logic high level. The third OR gate 333 may receive the output signal of the first OR gate 331 or the second OR gate 332, and output an enable signal EN2. When any one of the output signals of the first OR gate 331 or the second OR gate 332 has a logic high level, the third OR gate 333 may enable the logic level of the enable signal EN2 to a logic high level.

[0039] Figure 4 It is a graphic Figure 1 FIG. 1 is a diagram showing the configuration of the second delay loop 120. Figure 4 , the second delay loop 120 may include a second clock delay line 410, a clock frequency dividing circuit 420, a second phase detector 430, and a second delay control circuit 440. The second clock delay line 410 may generate a second delay locked clock signal DCLK2 and a complementary second delay locked clock signal DCLK2B by receiving a first received clock signal RCLK and a second received clock signal RCLKB. The second clock delay line 410 may delay the first received clock signal RCLK and the second received clock signal RCLKB, and provide delayed clock signals 411 and 412 as the second delay locked clock signal DCLK2 and the complementary second delay locked clock signal DCLK2B. The second clock delay line 410 may receive a second delay control signal DC2, and delay the first received clock signal RCLK and the second received clock signal RCLKB based on the second delay control signal DC2. The delay amount of the second clock delay line 410 may be changed based on the second delay control signal DC2. The second clock delay line 410 may be a differential CML delay line and may include a plurality of CML delay cells 410-1, 410-2, 410-3, ..., and 410-n. The plurality of CML delay cells 410-1, 410-2, 410-3, ..., and 410-n may be sequentially coupled in series. The plurality of CML delay cells 410-1, 410-2, 410-3, ..., and 410-n may generate output clock signals having opposite phases by differentially amplifying input clock signals. At least one of the plurality of CML delay cells 410-1, 410-2, 410-3, ..., and 410-n may receive an enable signal EN2 (not shown). For example, the CML delay cell 410-1 located at the front of the plurality of CML delay cells 410-1, 410-2, 410-3, ..., and 410-n and receiving the first reception clock signal RCLK and the second reception clock signal RCLKB may receive the enable signal EN2. The CML delay cell 410-1 may be selectively activated based on the enable signal EN2. When the enable signal EN2 is enabled, the CML delay cell 410-1 may be activated so that the second delay locked clock signal DCLK2 and the complementary second delay locked clock signal DCLK2B are generated through the second clock delay line 410.

[0040] The clock frequency division circuit 420 may receive the second delay locked clock signal DCLK2 and the complementary second delay locked clock signal DCLK2B. The clock frequency division circuit 420 may generate at least the first internal clock signal ICLK, the second internal clock signal QCLK, the third internal clock signal IBCLK, and the fourth internal clock signal QBCLK by dividing the frequencies of the second delay locked clock signal DCLK2 and the complementary second delay locked clock signal DCLK2B. The clock frequency division circuit 420 may divide the frequencies of the second delay locked clock signal DCLK2 and the complementary second delay locked clock signal DCLK2B at a CML voltage level. The clock frequency division circuit 420 may convert the voltage level of the divided clock signal to a CMOS voltage level, and output the first internal clock signal ICLK, the second internal clock signal QCLK, the third internal clock signal IBCLK, and the fourth internal clock signal QBCLK. The CML voltage level may represent a limited voltage level. The clock signal divided by the clock frequency division circuit 420 may swing at a limited voltage level. The CMOS voltage level may represent an unlimited voltage level.The first to fourth internal clock signals ICLK, QCLK, IBCLK, and QBCLK may substantially fully swing.

[0041] The second phase detector 430 may receive the first internal clock signal ICLK and the first delay locked clock signal DCLK1 generated by the first delay loop 110. The second phase detector 430 may generate a second phase detection signal PD2 by comparing the phases of the first internal clock signal ICLK and the first delay locked clock signal DCLK1. The second phase detector 430 may have a Figure 2 1. The second phase detector 430 may be configured substantially the same as the first phase detector 240 shown in FIG. The second phase detector 430 may change the logic level of the second phase detection signal PD2 based on whether the phase of the first internal clock signal ICLK is earlier or later than the phase of the first delay locked clock signal DCLK1. The second phase detector 430 may receive an enable signal EN2. The second phase detector 430 may be selectively activated based on the enable signal EN2. When the enable signal EN2 is enabled, the second phase detector 430 may be activated to perform a phase detection operation. When the enable signal EN2 is disabled, the second phase detector 430 may not perform a phase detection operation.

[0042] The second delay control circuit 440 may receive the second phase detection signal PD2 and generate a second delay control signal DC2 based on the second phase detection signal PD2. The second delay control signal DC2 may be an update signal for changing the delay amount of the second clock delay line 410. The second delay control circuit 440 may generate the second delay control signal DC2 and change the delay amount of the second clock delay line 410 in various ways. In an embodiment, the second delay control circuit 440 may perform a function similar to the first delay control circuit 250. Similar to the first delay control signal DC1, the second delay control signal DC2 may include a phase increase signal and a phase decrease signal. The second clock delay line 410 may increase the number of activated delay cells when receiving a phase increase signal, and may reduce the number of activated delay cells when receiving a phase decrease signal. In an embodiment, the second delay control circuit 440 may include a charge pump, and the second delay control signal DC2, i.e., an analog voltage, may be generated by the charge pump. The second delay control signal DC2 may be input to the plurality of CML delay cells 410-1, 410-2, 410-3, ..., and 410-n constituting the second clock delay line 410, and the delay amount of the second clock delay line 410 may be adjusted by adjusting the current amount of the plurality of CML delay cells 410-1, 410-2, 410-3, ..., and 410-n. In an embodiment, the second delay control circuit 440 may further include an analog-to-digital converter, and may generate the second delay control signal DC2 by converting an analog voltage generated based on the second phase detection signal PD2 into a digital signal. The second delay control signal DC2 may be input to the plurality of CML delay cells 410-1, 410-2, 410-3, ..., and 410-n constituting the second clock delay line 410, and the delay amount of the second clock delay line 410 may be adjusted by adjusting the current amount of the plurality of CML delay cells 410-1, 410-2, 410-3, ..., and 410-n. The second delay control circuit 440 may receive an enable signal EN2. The second delay control circuit 440 may be selectively activated based on the enable signal EN2. When the enable signal EN2 is enabled, the second delay control circuit 440 may be activated to generate a second delay control signal DC2. When the enable signal EN2 is disabled, the second delay control circuit 440 may be deactivated and may not generate the second delay control signal DC2.

[0043] The second delay loop 120 may further include a second clock buffer 450. The second clock buffer 450 may buffer the first received clock signal RCLK and the second received clock signal RCLKB, and may provide the buffered clock signals 451 and 452 to the second clock delay line 410. The buffered clock signals 451 and 452 may be differential signals having opposite phases. The second clock delay line 410 may be modified to generate a second delay locked clock signal DCLK2 and a complementary second delay locked clock signal DCLK2B by delaying the buffered clock signals 451 and 452 output by the second clock buffer 450. The second clock buffer 450 may receive an enable signal EN2. If the second clock buffer 450 is configured to receive the enable signal EN2, at least one of the plurality of CML delay cells 410-1, 410-2, 410-3, ..., and 410-n constituting the second clock delay line 410 may not receive the enable signal EN2. That is, the CML delay unit 410-1 may be designed not to receive the enable signal EN2. The second clock buffer 450 may be selectively activated based on the enable signal EN2. When the enable signal EN2 is enabled, the second clock buffer 450 may provide the buffered clock signals 451 and 452 to the second clock delay line 410. When the enable signal EN2 is disabled, the second clock buffer 450 may prevent the buffered clock signals 451 and 452 from being output to the second clock delay line 410.

[0044] The second delay loop 120 may further include a duty cycle corrector 460. The duty cycle corrector 460 may be coupled between the second clock delay line 410 and the clock dividing circuit 420. The duty cycle corrector 460 may receive the clock signals 411 and 412 delayed by the second clock delay line 410, and may generate a second delay locked clock signal DCLK2 and a complementary second delay locked clock signal DCLK2B by correcting the duty cycles of the delayed clock signals 411 and 412. For example, the duty cycle corrector 460 may detect the duty cycles of the delayed clock signals 411 and 412 output by the second clock delay line 410, and may generate a second delay locked clock signal DCLK2 and a complementary second delay locked clock signal DCLK2B having a duty cycle of 50:50 by correcting the duty cycles of the second delay locked clock signal DCLK2 and the complementary second delay locked clock signal DCLK2B based on the detected duty cycle. Duty cycle corrector 460 may be implemented using any known duty cycle correction circuit.

[0045] The second delay loop 120 may further include a dummy circuit 470. The dummy circuit 470 may be coupled to a node from which the second internal clock signal QCLK, the third internal clock signal IBCLK, and the fourth internal clock signal QBCLK are output. The dummy circuit 470 may model the second phase detector 430. The node from which the first internal clock signal ICLK is output may be coupled to the second phase detector 430. Therefore, the node from which the first internal clock signal ICLK is output may be affected by a load of the second phase detector 430. The second delay loop 120 couples the dummy circuit 470 modeling the second phase detector 430 to a node from which the second to fourth internal clock signals QCLK, IBCLK, and QBCLK are output, so that the first to fourth internal clock signals ICLK, QCLK, IBCLK, and QBCLK have a constant phase difference, and allows substantially the same load to affect the node from which the first to fourth internal clock signals ICLK, QCLK, IBCLK, and QBCLK are output.

[0046] Figure 5 It is a graphic Figure 4 The configuration of the clock frequency dividing circuit 420 is shown in FIG. Figure 5, the clock dividing circuit 420 may include a CML clock divider 510 and a CML to CMOS converter 520. The CML clock divider 510 may generate a first divided clock signal ICLKD, a second divided clock signal QCLKD, a third divided clock signal IBCLKD, and a fourth divided clock signal QBCLKD by receiving the second delay locked clock signal DCLK2 and the complementary second delay locked clock signal DCLK2B. The CML clock divider 510 may generate a first divided clock signal ICLKD and a third divided clock signal IBCLKD using the second delay locked clock signal DCLK2, the complementary second delay locked clock signal DCLK2B, the second divided clock signal QCLKD, and the fourth divided clock signal QBCLKD. The CML clock divider 510 may generate a second divided clock signal QCLKD and a fourth divided clock signal QBCLKD using the second delay locked clock signal DCLK2, the complementary second delay locked clock signal DCLK2B, the first divided clock signal ICLKD, and the third divided clock signal IBCLKD. The CML clock divider 510 may generate first to fourth divided clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD, each having a CML voltage level. For example, when the CML clock divider 510 operates by receiving a high power voltage having a higher voltage level and a low power voltage having a lower voltage level, the first to fourth divided clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD may each have a swing width that is less than a level difference between a high power supply voltage and a low power supply voltage. Since the CML clock divider 510 generates the first to fourth divided clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD, each having a CML voltage level, the CML clock divider 510 can perform a fast and accurate division operation and minimize the phase skew between the first to fourth divided clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD.

[0047] The CML-CMOS converter 520 may generate the first to fourth internal clock signals ICLK, QCLK, IBCLK, and QBCLK by receiving the first to fourth divided clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD. The CML-to-CMOS converter 520 may generate the first to fourth internal clock signals ICLK, QCLK, IBCLK, and QBCLK by converting the respective swing widths of the first to fourth divided clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD from the CML voltage level to the CMOS voltage level. The CML-to-CMOS converter 520 may generate the first to fourth internal clock signals ICLK, QCLK, IBCLK, and QBCLK, each fully swinging at the CMOS voltage level, based on the first to fourth divided clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD, each swinging at the CML voltage level with limited swing. The first internal clock signal ICLK may have a phase corresponding to the first divided clock signal ICLKD. The second internal clock signal QCLK may have a phase corresponding to the second divided clock signal QCLKD. The third internal clock signal IBCLK may have a phase corresponding to the third divided clock signal IBCLKD. The fourth internal clock signal QBCLK may have a phase corresponding to the fourth divided clock signal QBCLKD. The CML to CMOS converter 520 may generate the first internal clock signal ICLK and the third internal clock signal IBCLK based on the first divided clock signal ICLKD and the third divided clock signal IBCLKD, and may generate the second internal clock signal QCLK and the fourth internal clock signal QBCLK based on the second divided clock signal QCLKD and the fourth divided clock signal QBCLKD.

[0048] Figure 6 It is a graphic Figure 5 FIG. 5 is a diagram showing the configuration of the CML clock divider 510. Figure 6 , the CML clock divider 510 may include a first divider 610 and a second divider 620. The first divider 610 may include a first level shift circuit 611 and a first level holding circuit 612. The first level shift circuit 611 may change the logic level of the first divided clock signal ICLKD and the third divided clock signal IBCLKD based on the second delay locked clock signal DCLK2, the second divided clock signal QCLKD, and the fourth divided clock signal QBCLKD. The first level holding circuit 612 may maintain the logic level of the first divided clock signal ICLKD and the third divided clock signal IBCLKD based on the complementary second delay locked clock signal DCLK2B, the first divided clock signal ICLKD, and the third divided clock signal IBCLKD.

[0049] The first level shift circuit 611 may include a first transistor T11, a second transistor T12, and a third transistor T13. The first to third transistors T11, T12, and T13 may be N-channel MOS transistors. The first transistor T11 may have a gate to which the second delay locked clock signal DCLK2 is input, and may have a source coupled to the terminal 601 through the current source S11, and the low power voltage is supplied to the terminal 601. The second transistor T12 may have a gate to which the second divided clock signal QCLKD is input, may have a drain coupled to the first output node ON11, and may have a source coupled to the drain of the first transistor T11. The first divided clock signal ICLKD may be output through the first output node ON11. The third transistor T13 may have a gate to which the fourth divided clock signal QBCLKD is input, may have a drain coupled to the second output node ON12, and may have a source coupled to the drain of the first transistor T11. The third divided clock signal IBCLKD may be output through the second output node ON12. The first resistor R11 may be coupled between the first output node ON11 and the terminal 602 supplied with the high power voltage. The second resistor R12 may be coupled between the second output node ON12 and the terminal 602 supplied with the high power voltage. The first resistor R11 and the second resistor R12 may have substantially the same resistance value. The high power voltage may have a higher voltage level than the low power voltage.

[0050] The first level holding circuit 612 may include a fourth transistor T14, a fifth transistor T15, and a sixth transistor T16. The fourth to sixth transistors T14, T15, and T16 may be N-channel MOS transistors. The fourth transistor T14 may have a gate to which the complementary second delay locked clock signal DCLK2B is input, and may have a source coupled to the terminal 601 through the current source S11, and the low power voltage is supplied to the terminal 601. The fifth transistor T15 may have a gate coupled to the second output node ON12, may have a drain coupled to the first output node ON11, and may have a source coupled to the drain of the fourth transistor T14. The sixth transistor T16 may have a gate coupled to the first output node ON11, may have a drain coupled to the second output node ON12, and may have a source coupled to the drain of the fourth transistor T14.

[0051] The second frequency divider 620 may include a second level shift circuit 621 and a second level holding circuit 622. The second level shift circuit 621 may change the logic levels of the second divided clock signal QCLKD and the fourth divided clock signal QBCLKD based on the complementary second delay locked clock signal DCLK2B, the first divided clock signal ICLKD, and the third divided clock signal IBCLKD. The second level holding circuit 622 may hold the logic levels of the second divided clock signal QCLKD and the fourth divided clock signal QBCLKD based on the second delay locked clock signal DCLK2, the second divided clock signal QCLKD, and the fourth divided clock signal QBCLKD.

[0052] The second level shift circuit 621 may include a first transistor T21, a second transistor T22, and a third transistor T23. The first to third transistors T21, T22, and T23 may be N-channel MOS transistors. The first transistor T21 may have a gate to which the complementary second delay locked clock signal DCLK2B is input, and may have a source coupled to the terminal 601 through the current source S21, and the low power voltage is supplied to the terminal 601. The second transistor T22 may have a gate to which the third frequency-divided clock signal IBCLKD is input, may have a drain coupled to the third output node ON21, and may have a source coupled to the drain of the first transistor T21. The second frequency-divided clock signal QCLKD may be output through the third output node ON21. The third transistor T23 may have a gate to which the first frequency-divided clock signal ICLKD is input, may have a drain coupled to the fourth output node ON22, and may have a source coupled to the drain of the first transistor T21. The fourth frequency-divided clock signal QBCLKD may be output through the fourth output node ON22. The first resistor R21 may be coupled between the third output node ON21 and the terminal 602 supplied with the high power voltage. The second resistor R22 may be coupled between the fourth output node ON22 and the terminal 602 supplied with the high power voltage. The first resistor R21 and the second resistor R22 may have substantially the same resistance value.

[0053] The second level holding circuit 622 may include a fourth transistor T24, a fifth transistor T25, and a sixth transistor T26. The fourth and sixth transistors T24, T25, and T26 may be N-channel MOS transistors. The fourth transistor T24 may have a gate to which the second delay locked clock signal DCLK2 is input, and may have a source coupled to the terminal 601 through the current source S21, and the low power voltage is supplied to the terminal 601. The fifth transistor T25 may have a gate coupled to the fourth output node ON22, may have a drain coupled to the third output node ON21, and may have a source coupled to the drain of the fourth transistor T24. The sixth transistor T26 may have a gate coupled to the third output node ON21, may have a drain coupled to the fourth output node ON22, and may have a source coupled to the drain of the fourth transistor T24.

[0054] Figure 7 It is a graphic Figure 6 The timing diagram of the operation of the CML clock divider 510 is shown below. Figure 6 and Figure 7 The operation of the CML clock divider 510 according to the embodiment is described. At T1, when the logic level of the second delay locked clock signal DCLK2 is turned into a logic high level, the first transistor T11 of the first divider 610 may be turned on and the fourth transistor T14 thereof may be turned off. The voltage level of the first output node ON11 may become higher than the voltage level of the second output node ON12 because the second divided clock signal QCLKD has a logic low level and the fourth divided clock signal QBCLKD has a logic high level. Therefore, the first divided clock signal ICLKD having a logic high level may be output from the first output node ON11, and the third divided clock signal IBCLKD having a logic low level may be output from the second output node ON12.

[0055] At T2, when the logic level of the complementary second delay locked clock signal DCLK2B is turned into a logic high level, the fourth transistor T14 of the first frequency divider 610 can be turned on and the first transistor T11 thereof can be turned off. The amount of current flowing through the sixth transistor T16 can become greater than the amount of current flowing through the fifth transistor T15, because the gate of the fifth transistor T15 is coupled to the second output node ON12 and the gate of the sixth transistor T16 is coupled to the first output node ON11. Therefore, the logic level of the first output node ON11 coupled to the drain of the fifth transistor T15 can be maintained at a logic high level. The first frequency-divided clock signal ICLKD can be maintained at a logic high level. The logic level of the second output node ON12 coupled to the drain of the sixth transistor T16 can be maintained at a logic low level. The third frequency-divided clock signal IBCLKD can be maintained at a logic low level. When the logic level of the complementary second delay locked clock signal DCLK2B is turned into a logic high level, the first transistor T21 of the second frequency divider 620 can be turned on and the fourth transistor T24 thereof can be turned off. The voltage level of the third output node ON21 may become higher than the voltage level of the fourth output node ON22 because the third frequency-divided clock signal QCLKD has a logic low level and the first frequency-divided clock signal ICLKD has a logic high level. Therefore, the second frequency-divided clock signal QCLKD having a logic high level may be output from the third output node ON21, and the fourth frequency-divided clock signal QBCLKD having a logic low level may be output from the fourth output node ON22.

[0056] At T3, when the logic level of the second delay locked clock signal DCLK2 is turned to a logic high level again, the first transistor T11 of the first frequency divider 610 can be turned on again and the fourth transistor T14 thereof can be turned off again. The voltage level of the second output node ON12 can become higher than the voltage level of the first output node ON11 because the logic level of the second frequency-divided clock signal QCLKD has been turned to a logic high level and the logic level of the fourth frequency-divided clock signal QBCLKD has been turned to a logic low level. Therefore, the first frequency-divided clock signal ICLKD having a logic low level can be output through the first output node ON11, and the third frequency-divided clock signal IBCLKD having a logic high level can be output through the second output node ON12. At this time, the fourth transistor T24 of the second frequency divider 620 can be turned on, and the first transistor T21 thereof can be turned off. The amount of current flowing through the sixth transistor T26 may become greater than the amount of current flowing through the fifth transistor T25 because the gate of the fifth transistor T25 is coupled to the fourth output node ON22 and the gate of the sixth transistor T26 is coupled to the third output node ON21. Therefore, the logic level of the third output node ON21 coupled to the drain of the fifth transistor T25 may be maintained at a logic high level, and the second frequency-divided clock signal QCLKD may be maintained at a logic high level. The logic level of the fourth output node ON22 coupled to the drain of the sixth transistor T26 may be maintained at a logic low level, and the fourth frequency-divided clock signal QBCLKD may be maintained at a logic low level.

[0057] At T4, when the logic level of the complementary second delay locked clock signal DCLK2B turns to a logic high level again, the fourth transistor T14 of the first frequency divider 610 may be turned on and the first transistor T11 thereof may be turned off. The amount of current flowing through the fifth transistor T15 may become greater than the amount of current flowing through the sixth transistor T16 because the gate of the fifth transistor T15 is coupled to the second output node ON12 and the gate of the sixth transistor T16 is coupled to the first output node ON11. Therefore, the logic level of the first output node ON11 coupled to the drain of the fifth transistor T15 may remain at a logic low level, and the first frequency-divided clock signal ICLKD may remain at a logic low level. The logic level of the second output node ON12 coupled to the drain of the sixth transistor T16 may remain at a logic high level, and the third frequency-divided clock signal IBCLKD may remain at a logic high level. When the logic level of the complementary second delay locked clock signal DCLK2B turns to a logic high level, the first transistor T21 of the second frequency divider 620 may be turned on and the fourth transistor T24 thereof may be turned off. The voltage level of the fourth output node ON22 can become higher than the voltage level of the third output node ON21 because the third frequency-divided clock signal IBCLKD has a logic high level and the first frequency-divided clock signal ICLKD has a logic low level. Therefore, the second frequency-divided clock signal QCLKD having a logic low level can be output from the third output node ON21, and the fourth frequency-divided clock signal QBCLKD having a logic high level can be output from the fourth output node ON22. Thereafter, whenever the logic levels of the second delay-locked clock signal DCLK2 and the complementary second delay-locked clock signal DCLK2B are each transformed into a logic high level, the logic levels of the first to fourth frequency-divided clock signals ICLKD, QCLKD, IBCLKD, and QBCLKD are transformed or maintained. Therefore, each of the first to fourth frequency-divided clock signals ICKD, QCLKD, IBCLKD, and QBCLKD can be generated, each of which has a lower frequency and a longer period than the second delay-locked clock signal DCLK2 and the complementary second delay-locked clock signal DCLK2B.

[0058] Figure 8 It is a graphic Figure 5 FIG. 5 is a diagram showing the configuration of a CML to CMOS converter 520. Figure 8, the CML to CMOS converter 520 may include a first converter 810, a second converter 820, a third converter 830, and a fourth converter 840. Each of the first to fourth converters 810, 820, 830, and 840 may receive two clock signals each swinging at a CML level, and may output a single clock signal swinging at a CMOS level. The first converter 810 may generate a first internal clock signal ICLK by receiving a first divided clock signal ICLKD and a third divided clock signal IBCLKD. The first converter 810 may generate a first internal clock signal ICLK by detecting a phase of the first divided clock signal ICLKD and amplifying it to a phase of the third divided clock signal IBCLKD. The first converter 810 may generate a first internal clock signal ICLK having substantially the same phase as the first divided clock signal ICLKD, and the first internal clock signal ICLK has a larger amplitude than the first divided clock signal ICLKD. The second converter 820 may generate a second internal clock signal QCLK by receiving the second divided clock signal QCLKD and the fourth divided clock signal QBCLKD. The second converter 820 may generate a second internal clock signal QCLK by detecting the phase of the second amplified clock signal QCLKD and amplifying it to the phase of the fourth divided clock signal QBCLKD. The second converter 820 may generate a second internal clock signal QCLK having substantially the same phase as the second divided clock signal QCLKD, and the second internal clock signal QCLK has a larger amplitude than the second divided clock signal QCLKD. The third converter 830 may generate a third internal clock signal IBCLK by receiving the third divided clock signal IBCLKD and the first divided clock signal ICLKD. The third converter 830 may generate a third internal clock signal IBCLK by detecting the phase of the third divided clock signal IBCLKD and amplifying it to the phase of the first divided clock signal ICLKD. The third converter 830 may generate a third internal clock signal IBCLK having substantially the same phase as the third frequency-divided clock signal IBCLKD, and the third internal clock signal IBCLK has a larger amplitude than the third frequency-divided clock signal IBCLKD. The fourth converter 840 may generate a fourth internal clock signal QBCLK by receiving the fourth frequency-divided clock signal QBCLKD and the second frequency-divided clock signal QCLKD. The fourth converter 840 may generate a fourth internal clock signal QBCLK by detecting the phase of the fourth frequency-divided clock signal QBCLKD and amplifying it to the phase of the second frequency-divided clock signal QCLKD.The fourth converter 840 may generate the fourth internal clock signal QBCLK having substantially the same phase as the fourth frequency-divided clock signal QBCLKD, and the third internal clock signal IBCLK has a greater amplitude than the fourth frequency-divided clock signal QBCLKD.

[0059] Fig. 9 It is a graphic Figure 8 FIG. 8 is a diagram showing a configuration of the first converter 810. Fig. 9 , the first converter 810 may include a first transistor T31, a second transistor T32, a third transistor T33, a fourth transistor T34, a fifth transistor T35, a sixth transistor T36, a seventh transistor T37 and an inverter IV. The first transistor T31, the second transistor T32, the fifth transistor T35 and the seventh transistor T37 may be N-channel MOS transistors. The third transistor T33, the fourth transistor T34 and the sixth transistor T36 may be P-channel MOS transistors. The first to fifth transistors T31, T32, T33, T34 and T35 may form a CMOS buffer structure. The first transistor T31 may be coupled between the negative output node NO and the terminal 901 supplied with a low power voltage, and may have a gate to which the first frequency-divided clock signal ICLKD is input. The second transistor T32 may be coupled between the positive output node PO and the terminal 901 supplied with a low power voltage, and may have a gate to which the third frequency-divided clock signal IBCLKD is input. The third transistor T33 may be coupled between the negative output node NO and the terminal 902 supplied with a high power voltage. The fourth transistor T34 may be coupled between the positive output node PO and the terminal 902 supplied with the high power voltage. The gate of the fourth transistor T34 may be coupled to the negative output node NO together with the gate of the third transistor T33. The third transistor T33 and the fourth transistor T34 may form a current mirror so that substantially the same amount of current may be supplied to the negative output node NO and the positive output node PO. The fifth transistor T35 may be coupled between the first transistor T31 and the second transistor T32 and the terminal 901 supplied with the low power voltage, and may have a gate coupled to the terminal 902, to which the high power voltage is supplied. The fifth transistor T35 may be used as a current source forming a current path from the first transistor T31 and the second transistor T32 to the terminal 901 supplied with the low power voltage.

[0060] The sixth transistor T36 may be coupled between the inverting output node IO and the terminal 902 supplied with the high power voltage, and may have a gate coupled to the positive output node PO. The seventh transistor T37 may be coupled between the inverting output node IO and the terminal 901 supplied with the low power voltage, and may have a gate coupled to the positive output node PO. The sixth transistor T36 and the seventh transistor T37 may form an inverter, may invert the signal output from the positive output node PO, and may output the inverted signal through the inverting output node IO. The input terminal of the inverter IV may be coupled to the inverting output node IO. The first internal clock signal ICLK may be generated from the output terminal of the inverter IV. The voltage level of the positive output node PO may vary according to the voltage level of the first frequency-divided clock signal ICLKD, because the third frequency-divided clock signal IBCLKD has a phase opposite to the phase of the first frequency-divided clock signal ICLKD. The sixth transistor T36 and the seventh transistor T37 may invert the signal output from the positive output node PO, and may output the inverted signal to the inverting output node IO. The inverter IV can invert the signal output from the inverted output node IO, and can output the inverted signal as the first internal clock signal ICLK. The first frequency-divided clock signal ICLKD swinging at the CML voltage level can be converted into the first internal clock signal ICLKD swinging at the CMOS voltage level while being driven through the CMOS buffer and the inverter. Except for the input signal and the output signal, the second to fourth converters 820, 830 and 840 can each have the same configuration as the first converter 810.

[0061] Fig.10 1 is a diagram illustrating a configuration of a semiconductor device 1000 according to an embodiment. Fig.10, the semiconductor device 1000 may include a clock generation circuit 1010, a command receiver 1020, a command decoder 1030, a command delay line 1040, a delay shift circuit 1050, a gating circuit 1060, a clock tree 1070, a data transmitter 1080, and a data gating transmitter 1090. The clock generation circuit 1010 may include a clock receiver 1011, a first delay loop 1012, and a second delay loop 1013. The clock receiver 1011 may generate a first reception clock signal RCLK and a second reception clock signal RCLKB by receiving a first clock signal CLK and a second clock signal CLKB. The first delay loop 1012 may generate a first delay locked clock signal DCLK1 based on the first reception clock signal RCLK and the second reception clock signal RCLKB. The first delay loop 1012 may include a single-ended CMOS clock delay line, and may delay a reference clock signal generated according to a first received clock signal RCLK and a second received clock signal RCLKB based on a reference clock signal and a first delay locked clock signal DCLK1 to generate a first delay locked clock signal DLCK1. The second delay loop 1013 may generate a first internal clock signal ICLK based on the first received clock signal RCLK and the second received clock signal RCLKB. The second delay loop 1013 may include a differential current mode logic (CML) clock delay line, and may delay the first received clock signal RCLK and the second received clock signal RCLKB based on the first delay locked clock signal DCLK1 and the first internal clock signal ICLK to generate a first internal clock signal ICLK. The second delay loop 1013 may generate a second internal clock signal QCLK, a third internal clock signal IBCLK, and a fourth internal clock signal QBCLK as well as the first internal clock signal ICLK. Reference Figures 1 to 8 The configuration and operation of the described clock generation circuit 100 may be applied to the clock generation circuit 1010 , and descriptions of the same or similar elements are omitted herein.

[0062] The command receiver 1020 may receive a command signal CMD. The command signal CMD may be a signal transmitted by an external device of the semiconductor device 1000. The command signal CMD may be a signal including a plurality of bits. The command decoder 1030 may generate an internal command signal by decoding the command signal CMD received from the command receiver 1020. The command decoder 1030 may generate an internal command signal by latching the output of the command receiver 1020 synchronously with the first reception clock signal RCLK and decoding the latched command signal. The internal command signal may include various signals that enable the semiconductor device 1000 to perform various operations. For example, the internal command signal may include a read signal RD and an on-chip termination signal ODT. The read signal RD may be generated so that the semiconductor device 1000 can perform an operation of outputting data DQ to an external device based on the internal data DIN. The on-chip termination signal ODT may be generated so that the semiconductor device 1000 can perform an operation of setting an impedance value of a data bus through which the data DQ is transmitted.

[0063] The command delay line 1040 may generate a delayed command signal by receiving an internal command signal. The command delay line 1040 may generate a delayed command signal by delaying the internal command signal. Figure 2 and 10 , the command delay line 1040 may delay the internal command signal by substantially the same time as the time when the reference clock signal REFCLK is delayed by the first clock delay line 220 in the first delay loop 1012. The command delay line 1040 may include a first command delay line 1041 and a second command delay line 1042. The first command delay line 1041 may receive a read signal RD and generate a delayed read signal RDD by delaying the read signal RD. The second command delay line 1042 may receive an on-chip termination signal ODT and generate a delayed on-chip termination signal ODTD by delaying the on-chip termination signal ODT. The delayed command signal may include a delayed read signal RDD and a delayed on-chip termination signal ODTD. The first command delay line 1041 and the second command delay line 1042 may each have the same delay amount as the clock delay line included in the first delay loop 1012. For example, the first command delay line 1041 and the second command delay line 1042 may each have the same delay amount as the first clock delay line 220. The first command delay line 1041 and the second command delay line 1042 may each receive the first delay control signal DC1 generated by the first delay loop 1012. The delay amounts of the first command delay line 1041 and the second command delay line 1042 may be set based on the first delay control signal DC1.

[0064] The delay shift circuit 1050 can generate a synchronous command signal by delaying the delay command signal by a time corresponding to the delay in synchronization with at least one internal clock signal ICLK. The delay shift circuit 1050 can receive the delayed read signal RDD and the delayed on-chip termination signal ODTD output by the first command delay line 1041 and the second command delay line 1042, and can receive the first delay locked clock signal DCLK1 from the first delay loop 1012. In addition, the delay shift circuit 1050 can receive the delay signal LATC. The delay signal LATC may include information about the delay. The delay signal LATC may be a signal provided by a mode register group and / or a state machine for storing operation information of the semiconductor device 1000. The delay included in the delay signal LATC may be an integer equal to or greater than 1. The time corresponding to the delay may be a delay*1tCK. 1tCK may be a time corresponding to one cycle of the first clock signal CLK. The delay may include various types of time information, such as CAS delay, read delay, write delay, CAS write delay, and additional delay. The delay shift circuit 1050 may generate a synchronous read signal RDS by delaying the read signal RD by a time corresponding to the delay included in the delay signal LATC in synchronization with at least one of the first delay locked clock signal DCLK1 and the complementary signal of the first delay locked clock signal DCLK1. The delay shift circuit 1050 may generate a synchronous on-chip termination signal ODTS by delaying the on-chip termination signal ODT by a time corresponding to the delay in synchronization with at least one of the first delay locked clock signal DCLK1 and the complementary signal of the first delay locked clock signal. The synchronous command signal may include the synchronous read signal RDS and the synchronous on-chip termination signal ODTS. The semiconductor device 1000 may further include an in-phase buffer 1051 and an inverting buffer 1052. The in-phase buffer 1051 may perform in-phase buffering on the first delay locked clock signal DCLK1, and may provide the in-phase buffered first delay locked clock signal to the delay shift circuit 1050. The inversion buffer 1052 may perform inversion buffering on the first delay locked clock signal DCLK1 , and may provide a complementary signal of the inversion buffered first delay locked clock signal DCLK1 to the delay shift circuit 1050 .

[0065] The gating circuit 1060 may generate an output control signal by synchronizing the synchronous command signal with at least one internal clock signal. The gating circuit 1060 may receive the synchronous read signal RDS and the synchronous on-chip termination signal ODTS output by the delay shift circuit 1050. The gating circuit 1060 may receive the first internal clock signal ICLK and the second internal clock signal QCLK output by the second delay loop 1013. The gating circuit 1060 may generate an output enable signal OEN by synchronizing the synchronous read signal RDS with the first internal clock signal ICLK. The gating circuit 1060 may generate an on-chip termination enable signal ODTEN by synchronizing the synchronous on-chip termination signal ODTS with the second internal clock signal QCLK. The output control signal may include the output enable signal OEN and the on-chip termination enable signal ODTEN. In an embodiment, the gating circuit 1060 may receive the third internal clock signal IBCLK and the first internal clock signal ICLK, and may generate the output enable signal OEN by synchronizing the synchronous read signal RDS with at least one of the first internal clock signal ICLK and the third internal clock signal IBCLK. The gating circuit 1060 may receive the fourth internal clock signal QBCLK and the second internal clock signal QCLK, and may generate the on-chip termination enable signal ODTEN by synchronizing the synchronous on-chip termination signal ODTS with at least one of the second internal clock signal QCLK and the fourth internal clock signal QCLKB.

[0066] The clock tree 1070 may receive the first to fourth internal clock signals ICLK, QCLK, IBCLK, and QBCLK, and may generate the first to fourth output clock signals ICLKO, QCLKO, IBCLKO, and QBCLKO by delaying the first to fourth internal clock signals ICLK, QCLK, IBCLK, and QBCLK. The clock tree 1070 may generate the first output clock signal ICLKO by delaying the first internal clock signal ICLK, may generate the second output clock signal QCLKO by delaying the second internal clock signal QCLK, may generate the third output clock signal IBCLKO by delaying the third internal clock signal IBCLK, and may generate the fourth output clock signal QBCLKO by delaying the fourth internal clock signal QBCLK.

[0067] The data transmitter 1080 may output data DQ based on the internal data DIN of the semiconductor device 1000. The data transmitter 1080 may receive the internal data DIN, the output enable signal OEN, the on-chip termination enable signal ODTEN, and the first to fourth output clock signals ICLKO, QCLKO, IBCLKO, and QBCLKO. The internal data DIN may include a plurality of data signals. When the data transmitter 1080 is activated based on the output enable signal OEN, the data transmitter 1080 may output a plurality of data signals to the data DQ in sequence in synchronization with the first to fourth output clock signals ICLKO, QCLKO, IBCLKO, and QBCLKO. The impedance of the data transmitter 1080 may be set based on the on-chip termination enable signal ODTEN.

[0068] The data strobe transmitter 1090 may receive the first to fourth output clock signals ICLKO, QCLKO, IBCLKO, and QBCLKO from the clock tree 1070. The data strobe transmitter 1090 may output a pair of data strobe signals DQS and DQSB based on the first to fourth output clock signals ICLKO, QCLKO, IBCLKO, and QBCLKO. For example, the data strobe transmitter 1090 may output the data strobe signal DQS based on the first output clock signal ICLK and the third output clock signal ICLKO. The data strobe transmitter 1090 may output a complementary signal DQSB of the data strobe signal based on the second output clock signal QCLKO and the fourth output clock signal QBCLKO.

[0069] The semiconductor device 1000 can set the delay amount of the command delay line 1040 through the first delay loop 1012. The delay shift circuit 1050 can operate based on the first delay lock clock signal DCLK1 generated by the first delay loop 1012. Therefore, the power consumption required to delay the internal command signal can be minimized. In order to enable the semiconductor device 1000 to perform smooth data communication with an external device, it is necessary to output the data selection signal pair DQS and DQSB at an accurate timing with an accurate phase difference. Therefore, the semiconductor device 1000 can generate the data selection signal pair DQS and DQSB based on the first to fourth internal clock signals ICLK, QCLK, IBCLK and QBCLK generated by the second delay loop 1013, and the second delay loop 1013 has relatively large power consumption, but has high performance. In addition, the selection circuit 1060 operates based on the first internal clock signal ICLK and the second internal clock signal QCLK generated by the second delay loop 1013. Therefore, the synchronous read signal RDS and the synchronous on-chip termination signal ODTS, which are delayed by the first delay loop 1012 , may be generated as the output enable signal OEN and the on-chip termination enable signal ODTEN at more precise timing.

[0070] Fig.11 1 is a diagram illustrating a configuration of a clock generation circuit 1100 according to an embodiment. Fig.11 The clock generation circuit 1100 may include a clock receiver 1101, a first delay loop 1110, and a second delay loop 1120. The clock generation circuit 1100 may have Figure 1 The clock generation circuit 100 shown in FIG. 1 is similar to the configuration of the clock generation circuit 100, and therefore redundant descriptions of the same elements are omitted herein. The clock receiver 1101 can receive a first clock signal CLK and a second clock signal CLKB. The clock receiver 1101 can generate a first receive clock signal RCLK and a second receive clock signal RCLKB by differentially amplifying the first clock signal CLK and the second clock signal CLKB. The first delay loop 1110 can receive the first receive clock signal RCLK and the second receive clock signal RCLKB. The first delay loop 1110 can generate a first delay locked clock signal DCLK1 by delaying the first receive clock signal RCLK and the second receive clock signal RCLKB. The first delay loop 1110 can receive a first internal clock signal ICLK generated by a second delay loop 1120. The first delay loop 1110 can change the delay amount of the first delay locked clock signal DCLK1 by comparing the phases of the first delay locked clock signal DCLK1 and the first internal clock signal ICLK. The first delay loop 1110 may generate a first delay locked clock signal DCLK1 having substantially the same phase as the first internal clock signal ICLK.

[0071] The second delay loop 1120 can receive the first reception clock signal RCLK and the second reception clock signal RCLKB, and can generate the first internal clock signal ICLK by performing a delay locking operation on the first reception clock signal RCLK and the second reception clock signal RCLKB. The second delay loop 1120 can also generate the second internal clock signal QCLK, the third internal clock signal IBCLK, and the fourth internal clock signal QBCLK by performing a delay locking operation on the first reception clock signal RCLK and the second reception clock signal RCLKB. Figure 1 In the clock generation circuit 100, the first delay loop 110 may perform a delay locking operation on the reference clock signal REFCLK generated according to the first reception clock signal RCLK and the second reception clock signal RCLKB, and the second delay loop 120 may receive the first delay locked clock signal DCLK1 output by the first delay loop 110, and may generate a first internal clock signal ICLK having substantially the same phase as the first delay locked clock signal DCLK1. In contrast, in Fig.11In the clock generating circuit 1100, the second delay loop 1120 can perform a delay locking operation on the first received clock signal RCLK and the second received clock signal RCLKB, and the first delay loop 1110 can receive the first internal clock signal ICLK output by the second delay loop 1120, and can generate a first delay locked clock signal DCLK1 having a phase substantially the same as that of the first internal clock signal ICLK.

[0072] Fig.12 1 is a diagram illustrating a configuration of a clock generation circuit 1200 according to an embodiment. Fig.12 , the clock generation circuit 1200 may include a clock receiver 1201, a first delay loop 1210 and a second delay loop 1220. The first delay loop 1210 may include a first clock buffer 1211, a first clock delay line 1212, a first phase detector 1213 and a first delay control circuit 1214. The second delay loop 1220 may include a second clock delay line 1221, a clock frequency division circuit 1222, a replicator 1223, a second phase detector 1224 and a second delay control circuit 1225. The first delay loop 1210 may have Figure 2 The first delay loop 1210 is similar to the first delay loop 110 shown in FIG. 1 , except that the first delay loop 1210 does not include a replica and the first phase detector 1213 compares the phases of the first delay locked clock signal DCLK1 and the first internal clock signal ICLK. The second delay loop 1220 may have a configuration similar to the first delay loop 110 shown in FIG. Figure 4 The second delay loop 120 is similarly configured as shown, except that the second delay loop 1220 includes a replica 1223 and a second phase detector 1224 compares the output of the replica 1223 with the phase of the received clock signal RCLK. Redundant descriptions of the same elements are omitted herein.

[0073] The first clock buffer 1211 may buffer the first received clock signal RCLK and the second received clock signal RCLKB, and provide the buffered clock signals as the first reference clock signal REFCLK1. The first clock delay line 1212 may generate a first delay locked clock signal DCLK1 by delaying the first reference clock signal REFCLK1. The first clock delay line 1212 may delay the first reference clock signal REFCLK1 based on the first delay control signal DC1. The delay amount of the first clock delay line 1212 may be changed based on the first delay control signal DC1.

[0074] The first phase detector 1213 may receive the first delay locked clock signal DCLK1 and the first internal clock signal ICLK output by the second delay loop 1220. The first phase detector 1213 may generate a first phase detection signal PD1 by comparing the phases of the first delay locked clock signal DCLK1 and the first internal clock signal ICLK. The first phase detector 1213 may detect whether the phase of the first delay locked clock signal DCLK1 is earlier or later than the phase of the first internal clock signal ICLK, and may change the logic level of the first phase detection signal PD1. The first delay control circuit 1214 may receive the first phase detection signal PD1 generated by the first phase detector 1213. The first delay control circuit 1214 may generate a first delay control signal DC1 based on the first phase detection signal PD1.

[0075] The first delay loop 1210 may further include a first clock divider 1215. The first clock divider 1215 may be coupled between the first clock buffer 1211 and the first clock delay line 1212. The first clock divider 1215 may divide the frequency of the buffered clock signal output by the first clock buffer 1211, and may provide the divided clock signal as the first reference clock signal REFCLK1.

[0076] The second clock delay line 1221 can generate a second delay locked clock signal DCLK2 and a complementary second delay locked clock signal DCLK2B by delaying the first received clock signal RCLK and the second received clock signal RCLKB. The second clock delay line 1221 can receive a second delay control signal DC2, and can delay the first received clock signal RCLK and the second received clock signal RCLKB based on the second delay control signal DC2. The delay amount of the second clock delay line 1221 can be changed based on the second delay control signal DC2. The clock frequency division circuit 1222 can receive the second delay locked clock signal DCLK2 and the complementary second delay locked clock signal DCLK2B. The clock frequency division circuit 1222 can generate a first internal clock signal ICLK, a second internal clock signal QCLK, a third internal clock signal IBCLK, and a fourth internal clock signal QBCLK by dividing the frequencies of the second delay locked clock signal DCLK2 and the complementary second delay locked clock signal DCLK2B.

[0077] The replicator 1223 may receive a first internal clock signal ICLK, and may generate a feedback clock signal FBCLK by delaying the first internal clock signal ICLK by a modeling delay time. The second phase detector 1224 may generate a second phase detection signal PD2 by comparing the phase of the feedback clock signal FBCLK with the second reference clock signal REFCLK2. The second phase detection signal PD2 may change the logic level of the second phase detection signal PD2 based on whether the phase of the second reference clock signal REFCLK2 is earlier or later than the phase of the feedback clock signal FBCLK. The second reference clock signal REFCLK2 may be generated based on the first received clock signal RCLK and the second received clock signal RCLKB. The second delay control circuit 1225 may receive the second phase detection signal PD2, and may generate a second delay control signal DC2 based on the second phase detection signal PD2. The second delay control signal DC2 may be an update signal for changing the delay amount of the second clock delay line 1221.

[0078] The second delay loop 1220 may further include a second clock buffer 1226. The second clock buffer 1226 may be coupled between the clock receiver 1201 and the second clock delay line 1221. The second clock buffer 1226 may buffer the first received clock signal RCLK and the second received clock signal RCLKB, and provide the buffered clock signals to the second clock delay line 1221. The buffered clock signals may have phases corresponding to the first received clock signal RCLK and the second received clock signal RCLKB, and may be differential signals having opposite phases. The second clock delay line 1221 may be modified to generate a second delay locked clock signal DCLK2 and a complementary second delay locked clock signal DCLK2B by delaying the buffered clock signals.

[0079] The second delay loop 1220 may further include a third clock buffer 1227 and a second clock divider 1228. The third clock buffer 1227 and the second clock divider 1228 may be sequentially coupled in series between the clock receiver 1201 and the second phase detector 1224. The third clock buffer 1227 may buffer the first received clock signal RCLK and the second received clock signal RCLKB, and output the buffered clock signals. The third clock buffer 1227 may have a structure substantially the same as the first clock buffer 1211. The second clock divider 1228 may receive the clock signal buffered by the third clock buffer 1227, and may generate a second reference clock signal REFCLK2 by dividing the frequency of the buffered clock signal. The second clock divider 1228 may provide the second reference clock signal REFCLK2 to the second phase detector 1224. In an embodiment, the division ratio of the second clock divider 1228 may be less than the division ratio of the first clock divider 1215. For example, when the first clock divider 1215 divides the frequency of the clock signal buffered by the first clock buffer 1211 by 4, the second clock divider 1228 may divide the frequency of the clock signal buffered by the third clock buffer 1227 by 2. The division ratio of the clock divider may determine the update period of the delay loop. The update period of the delay loop may represent a period during which the delay amount of the clock delay circuit included in the delay loop is changed. The update period of the second delay loop 1220 may be shorter than the update period of the first delay loop 1210.

[0080] The second delay loop 1220 may further include a duty cycle corrector 1229. The duty cycle corrector 1229 may be coupled between the second clock delay line 1221 and the clock frequency dividing circuit 1222. The duty cycle corrector 1229 may receive the clock signal output by the second clock delay line 1221, and may generate a second delay locked clock signal DCLK2 and a complementary second delay locked clock signal DCLK2B by correcting the duty cycle of the clock signal. The second delay loop 1220 may further include a dummy circuit 1231. The dummy circuit 1231 may be coupled to a node from which the second internal clock signal QCLK, the third internal clock signal IBCLK, and the fourth internal clock signal QBCLK are output. The dummy circuit 1231 may model the second phase detector 1224.

[0081] Fig.13 1 is a diagram illustrating a configuration of a semiconductor device 1300 according to an embodiment. The semiconductor device 1300 may have Fig.10 The semiconductor device 1000 shown in FIG. 1 is similar in configuration to the semiconductor device 1000 shown in FIG. 1 , except for certain elements. Redundant descriptions of the same elements are omitted herein. Fig.13, the semiconductor device 1300 may include a clock generation circuit 1310, a command receiver 1320, a command decoder 1330, a command delay line 1340, a delay shift circuit 1350, a gating circuit 1360, a clock tree 1370, a data transmitter 1380, and a data gating transmitter 1390. The clock generation circuit 1310 may include a clock receiver 1311, a first delay loop 1312, and a second delay loop 1313, and the clock generation circuit 1310 may have Fig.11 The clock receiver 1311 may generate a first received clock signal RCLK and a second received clock signal RCLKB by receiving a first clock signal CLK and a second clock signal CLKB. The first delay loop 1312 may include a single-ended CMOS clock delay line, and may delay the first reference clock signal to generate a first delay locked clock signal DCLK1 based on a first reference clock signal and a first internal clock signal ICLK generated according to the first received clock signal RCLK and the second received clock signal RCLKB. The second delay loop 1313 may include a differential current mode logic (CML) clock delay line, and may delay the first received clock signal RCLK and the second received clock signal RCLKB based on a first internal clock signal ICLK and a second reference clock signal generated according to the first received clock signal RCLK and the second received clock signal RCLKB to generate a first internal clock signal ICLK. The second delay loop 1313 may generate the second, third, and fourth internal clock signals QCLK, IBCLK, and QBCLK as well as the first internal clock signal ICLK.

[0082] The command receiver 1320 may receive a command signal CMD. The command decoder 1330 may generate an internal command signal by latching the command signal CMD received from the command receiver 1320 in synchronization with the first reception clock signal RCLK and decoding the latched command signal. The internal command signal may include a read signal RD and an on-chip termination signal ODT. The command delay line 1340 may include a first command delay line 1341 and a second command delay line 1342. The first command delay line 1341 may generate a delayed read signal RDD by delaying the read signal RD output by the command decoder 1330. The second command delay line 1342 may generate a delayed on-chip termination signal ODTD by delaying the on-chip termination signal ODT output by the command decoder 1330. The first command delay line 1341 and the second command delay line 1342 may each receive a first delay control signal DC1 generated by the first delay loop 1312. The delay amounts of the first command delay line 1341 and the second command delay line 1342 may be changed based on the first delay control signal DC1.

[0083] The delay shift circuit 1350 may receive the delayed read signal RDD and the on-chip delay termination signal ODTD from the command delay line 1340. Fig.10 In the case where the delay shift circuit 1050 shown receives the first delay locked clock signal DCLK1 generated by the first delay loop 1012, the delay shift circuit 1350 may receive the first internal clock signal ICLK and the third internal clock signal IBCLK generated by the second delay loop 1313. The delay shift circuit 1350 may generate a synchronous read signal RDS and a synchronous on-chip termination signal ODTS by synchronizing the delayed read signal RDD and the delayed on-chip termination signal ODTD with the first internal clock signal ICLK and the third internal clock signal IBCLK based on the delay signal LATC.

[0084] The gating circuit 1360 may receive a synchronous read signal RDS, a synchronous on-chip termination signal ODTS, a first internal clock signal ICLK, and a second internal clock signal QCLK. The gating circuit 1360 may generate an output enable signal OEN by synchronizing the synchronous read signal RDS with the first internal clock signal ICLK, and may generate an on-chip termination enable signal ODTEN by synchronizing the synchronous on-chip termination signal ODTS with the second internal clock signal QCLK. The delay shifting circuit 1350 generates a synchronous read signal RDS and a synchronous on-chip termination signal ODTS using the first internal clock signal ICLK and the third internal clock signal IBCLK. Therefore, the output enable signal OEN and the on-chip termination enable signal ODTEN may be output through the gating circuit 1360 at a more precise timing.

[0085] The clock tree 1370 can generate a first output clock signal ICLKO, a second output clock signal QCLKO, a third output clock signal IBCLKO, and a fourth output clock signal QBCLKO by delaying a first internal clock signal ICLK, a second internal clock signal QCLK, a third internal clock signal IBCLK, and a fourth internal clock signal QBCLK. When the output enable signal OEN is enabled, the data transmitter 1380 can output the internal data DIN as data DQ in synchronization with the first to fourth output clock signals ICLKO, QCLKO, IBCLKO, and QBCLKO. The impedance of the data transmitter 1380 can be set based on the on-chip termination enable signal ODTEN. The data strobe transmitter 1390 can output the data strobe signal pair DQS and DQSB based on the first to fourth output clock signals ICLKO, QCLKO, IBCLKO, and QBCLKO.

[0086] Fig.141400 is a diagram illustrating a configuration of a delay line 1400 according to an embodiment of the present disclosure. The delay line 1400 may be applied as Figure 4 and 12 Each of the second clock delay lines 410 and 1221 shown. Fig.14 , the delay line 1400 may receive the first input clock signal CLKIN and the second input clock signal CLKINB, and may generate the first output clock signal CLKOUT and the second output clock signal CLKOUTB by delaying the first input clock signal CLKIN and the second input clock signal CLKINB.

[0087] The delay line 1400 may include a coarse delay circuit 1410 and a fine delay circuit 1420. The coarse delay circuit 1410 may receive a first input clock signal CLKIN, a second input clock signal CLKINB, and a coarse control signal DCC, and may generate a first delayed clock signal pair FCLK and FCLKB and a second delayed clock signal pair SCLK and SCLKB. For example, when the delay line 1400 is applied as Figure 4When the second clock delay line 410 is shown, the first input clock signal CLKIN and the second input clock signal CLKINB may correspond to the first received clock signal RCLK and the second received clock signal RCLKB, or to the buffered clock signals 451 and 452 output from the second clock buffer 450, and the coarse control signal DCC may correspond to the second delay control signal DC2 generated from the second delay control circuit 440 during the coarse delay locking operation. The coarse delay circuit 1410 may generate a first delayed clock signal pair FCLK and FCLKB and a second delayed clock signal pair SCLK and SCLKB by delaying the first input clock signal CLKIN and the second input clock signal CLKINB based on the coarse control signal DCC. The second input clock signal CLKINB may be a complementary clock signal of the first input clock signal CLKIN. The second input clock signal CLKINB may have a phase difference of 180 degrees from the first input clock signal CLKIN. The first delayed clock signal pair FCLK and FCLKB may include two delayed clock signals having a phase difference of 180 degrees. The second delayed clock signal pair SCLK and SCLKB may include two delayed clock signals having a phase difference of 180 degrees. The coarse delay circuit 1410 may generate each of the first delayed clock signal pair FCLK, FCLKB and the second delayed clock signal pair SCLK and SCLKB by delaying the first input clock signal CLKIN and the second input clock signal CLKINB by a unit delay time based on the coarse control signal DCC. The coarse delay circuit 1410 may generate the first delayed clock signal pair FCLK and FCLKB having the same phase or having a phase difference corresponding to the unit delay time according to the second delayed clock signal pair SCLK and SCLKB. The coarse delay circuit 1410 may change each of the phases of the first delayed clock signal pair FCLK, FCLKB and the second delayed clock signal pair SCLK and SCLKB by a unit delay time.

[0088] The fine delay circuit 1420 can receive the first delayed clock signal pair FCLK and FCLKB, the second delayed clock signal pair SCLK and SCLKB, and the fine control signal DCF, and can generate a first output clock signal CLKOUT and a second output clock signal CLKOUTB. Figure 4When the second clock delay line 410 is shown, the first output clock signal CLKOUT and the second output clock signal CLKOUTB may correspond to the delayed clock signals 411 and 412 output from the second clock delay line 410, or to the second delay locked clock signal DCLK2 and the complementary second delay locked clock signal DCLK2B, and the fine control signal DCF may correspond to the second delay control signal DC2 generated from the second delay control circuit 440 during the fine delay locking operation. The fine delay circuit 1420 may generate the shift clock signal pair SSCLK and SSCLKB by delaying the second delayed clock signal pair SCLK and SCLKB by a phase corresponding to substantially half of the unit delay time. The fine delay circuit 1420 may generate the first output clock signal CLKOUT and the second output clock signal CLKOUTB by mixing the phases of the first delayed clock signal pair FCLK and FCLKB and the shift clock signal pair SSCLK and SSCLKB based on the fine control signal DCF. The second output clock signal CLKOUTB may be a complementary clock signal of the first output clock signal CLKOUT. The second output clock signal CLKOUTB may have a phase difference of 180 degrees from the first output clock signal CLKOUT.

[0089] The resolution of the fine delay circuit 1420 can be improved and the phases of the first output clock signal CLKOUT and the second output clock signal CLKOUTB can be adjusted more accurately due to the following reasons: the coarse delay circuit 1410 provides the first delayed clock signal pair FCLK and FCLKB, the first delayed clock signal pair FCLK and FCLKB has the same phase as the second delayed clock signal pair SCLK and SCLKB, or its phase lags behind the second delayed clock signal pair SCLK and SCLKB by a phase corresponding to the unit delay time, and the fine delay circuit 1420 mixes the phases of the shift clock signal pair SSCLK and SSCLKB and the first delayed clock signal pair FCLK and FCLKB, the shift clock signal pair SSCLK and SSCLKB is generated by delaying the second delayed clock signal pair SCLK and SCLKB by a phase corresponding to substantially half of the unit delay time. For example, when the fine delay circuit 1420 is designed to be able to change the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB in a predetermined number of steps, the phase difference between the clock signals whose phases are to be mixed can determine the resolution of the fine delay circuit 1420. Assume that the fine delay circuit 1420 can perform phase mixing through eight steps. When the phase difference between the clock signals whose phases are to be mixed by the fine delay circuit 1420 is a phase corresponding to a unit delay time, the fine delay circuit 1420 can change the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB by a phase corresponding to 1 / 8 of the unit delay time. However, when the phase difference between the clock signals whose phases are to be mixed by the fine delay circuit 1420 is a phase corresponding to substantially half of the unit delay time, the fine delay circuit 1420 can change the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB by a phase corresponding to 1 / 16 of the unit delay time, thereby achieving double resolution. Therefore, by mixing the phase of the shifted clock signal pair SSCLK and SSCLKB with the phase of the first delayed clock signal pair FCLK and FCLKB, the fine delay circuit 1420 can change the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB by a phase corresponding to 1 / 16 of the unit delay time, even without increasing the number of drivers and the number of control signals of the fine delay circuit 1420, thereby improving the resolution of the delay line 1400.

[0090] The coarse delay circuit 1410 may include a coarse shift register 1411 and a coarse delay line 1412. The coarse shift register 1411 may generate an enable signal EN<1:n>, a first selection signal SEL1<1:n>, and a second selection signal SEL2<1:n> based on a coarse control signal DCC. Here, n may be an integer equal to or greater than 3. The number of bits in each of the enable signal EN<1:n>, the first selection signal SEL1<1:n>, and the second selection signal SEL2<1:n> may correspond to the number of delay units included in the coarse delay line 1412. The coarse control signal DCC may include a coarse increase signal INCC and a coarse decrease signal DECC. Based on the coarse increase signal INCC, the coarse shift register 1411 can sequentially increase the number of bits with a logic high level in each of the enable signals EN<1:n>, and can sequentially change the number of bits with a logic high level in each of the first selection signal SEL1<1:n> and the second selection signal SEL2<1:n>. Based on the coarse decrease signal DECC, the coarse shift register 1411 can sequentially reduce the number of bits with a logic high level in each of the enable signals EN<1:n>, and can sequentially change the number of bits with a logic high level in each of the first selection signal SEL1<1:n> and the second selection signal SEL2<1:n>.

[0091] The coarse delay line 1412 may receive a first input clock signal CLKIN and a second input clock signal CLKINB, and may generate a first delayed clock signal pair FCLK and FCLKB, and a second delayed clock signal pair SCLK and SCLKB by delaying the first input clock signal CLKIN and the second input clock signal CLKINB. The coarse delay line 1412 may include first to nth delay units 1412-1, 1412-2, ..., and 1412-n. The first to nth delay units 1412-1, 1412-2, ..., and 1412-n may be CML delay units. Each of the first to nth delay units 1412-1, 1412-2, ..., and 1412-n may have a delay time corresponding to a unit delay time of the coarse delay line 1412. The total delay time of the coarse delay line 1412 may be changed according to the number of delay units to be activated. The coarse delay line 1412 may change the number of delay cells to be enabled based on the enable signal EN<1:n>. The first delay cell 1412-1 may be enabled based on the first bit EN of the enable signal EN<1:n>. <1> The second delay unit 1412-2 can be activated based on the second bit EN of the enable signal EN<1:n>. <2> The nth delay unit 1412 - n may be activated based on the nth bit EN of the enable signal EN<1:n>. <n>To be activated. The first delay unit 1412-1 can receive the first input clock signal CLKIN and the second input clock signal CLKINB, and the first and second delayed clock signal pairs FCLK, FCLKB, SCLK and SCLKB can be output from the first delay unit 1412-1. As the second to nth delay units 1412-2, ..., and 1412-n are sequentially activated, the number of paths through which the first input clock signal CLKIN and the second input clock signal CLKINB pass can increase, and therefore, the delay time of the first delayed clock signal pair FCLK, FCLKB and the second delayed clock signal pair SCLK and SCLKB can increase. As the nth to second delay units 1412-n, ..., and 1412-2 are sequentially deactivated, the number of paths through which the first input clock signal CLKIN and the second input clock signal CLKINB pass can be reduced, and therefore, the delay time of the first delayed clock signal pair FCLK, FCLKB and the second delayed clock signal pair SCLK and SCLKB can be reduced. Each of the first to nth delay units 1412-1, 1412-2, ..., and 1412-n can receive a bit assigned to each delay unit among the bits of the first and second selection signals SEL1<1:n> and SEL2<1:n>. Each of the first to nth delay units 1412-1, 1412-2, ..., and 1412-n can output one of a pair of clock signals delayed by each delay unit itself and a pair of clock signals delayed by a delay unit set at a next stage based on the first selection signal SEL1<1:n> and the second selection signal SEL2<1:n>. For example, the first delay unit 1412-1 can output a clock signal pair delayed by each delay unit itself and a clock signal pair delayed by a delay unit set at a next stage based on the first bit SEL1<1:n> of the first selection signal SEL1<1:n>. <1> The first delay unit 1412-1 can select one of the clock signal pair delayed by the first delay unit 1412-1 and the clock signal pair delayed by the delay unit (i.e., the second delay unit 1412-2) set at the next stage, and can output the selected clock signal pair as the first delayed clock signal pair FCLK and FCLKB. The first delay unit 1412-1 can select the clock signal pair delayed by the first delay unit 1412-1 and the clock signal pair delayed by the delay unit (i.e., the second delay unit 1412-2) set at the next stage, and can output the selected clock signal pair as the first delayed clock signal pair FCLK and FCLKB. <1> , to select one of the clock signal pair delayed by the first delay unit 1412-1 and the clock signal pair delayed by the delay unit set at the next level (i.e., the second delay unit 1412-2), and the selected clock signal pair can be output as the second delayed clock signal pair SCLK and SCLKB.

[0092] The fine delay circuit 1420 may include a fine shift register 1421 and a phase mixing circuit 1422. The fine shift register 1421 may receive a fine control signal DCF and generate a weight R<1:m>. The fine shift register 1421 may change the weight R<1:m> based on the fine control signal DCF. The fine control signal DCF may include a fine increase signal INCF and a fine decrease signal DECF. For example, the fine shift register 1421 may increase or decrease the value of the weight R<1:m> in a step-by-step manner based on the fine increase signal INCF, and may decrease or increase the value of the weight R<1:m> in a step-by-step manner based on the fine decrease signal DECF. The weight R<1:m> may be a digital signal having a plurality of bits. Here, m may be an integer equal to or greater than 2.

[0093] The phase mixing circuit 1422 may receive a first delayed clock signal pair FCLK and FCLKB, a second delayed clock signal pair SCLK and SCLKB, and a weight R<1:m>. The phase mixing circuit 1422 may generate a shifted clock signal pair SSCLK and SSCLKB by delaying the phase of the second delayed clock signal pair SCLK and SCLKB by a phase corresponding to substantially half of the unit delay time. The phase mixing circuit 1422 may generate a first output clock signal CLKOUT and a second output clock signal CLKOUTB by mixing the phases of the first delayed clock signal pair FCLK and FCLKB and the shifted clock signal pair SSCLK and SSCLKB based on the weight R<1:m>.

[0094] The phase mixing circuit 1422 may include a CML buffer 1422-1, a first variable driver 1422-2, and a second variable driver 1422-3. The CML buffer 1422-1 may receive the second delayed clock signal pair SCLK and SCLKB, and may generate a shift clock signal pair SSCLK and SSCLKB by delaying and buffering the second delayed clock signal pair SCLK and SCLKB. The time at which the CML buffer 1422-1 generates the shift clock signal pair SSCLK and SSCLKB according to the second delayed clock signal pair SCLK and SCLKB may correspond to substantially half of the unit delay time. The first variable driver 1422-2 may receive the first delayed clock signal pair FCLK and FCLKB and the weight R<1:m>, and may drive the first delayed clock signal pair FCLK and FCLKB based on the weight R<1:m>. The second variable driver 1422-3 may receive the shift clock signal pair SSCLK and SSCLKB and the weight R<1:m>, and may drive the shift clock signal pair SSCLK and SSCLKB based on the weight R<1:m>. When the phases of the first delayed clock signal FCLK driven by the first variable driver 1422-2 and the shift clock signal SSCLK driven by the second variable driver 1422-3 are mixed, a first output clock signal CLKOUT may be generated. When the phases of the first delayed clock signal FCLKB driven by the first variable driver 1422-2 and the shift clock signal SSCLKB driven by the second variable driver 1422-3 are mixed, a second output clock signal CLKOUTB may be generated. Based on the weight R<1:m>, the driving force of the first variable driver 1422-2 may be changed complementarily with the driving force of the second variable driver 1422-3. For example, as the logical value of the weight R<1:m> becomes smaller, the driving force of the first variable driver 1422-2 can be increased, while the driving force of the second variable driver 1422-3 can be reduced. On the contrary, as the logical value of the weight R<1:m> becomes larger, the driving force of the first variable driver 1422-2 can be reduced, while the driving force of the second variable driver 1422-3 can be increased. As the logical value of the weight R<1:m> becomes smaller, the phase mixing circuit 1422 can generate a first output clock signal CLKOUT and a second output clock signal CLKOUTB whose phases are close to the phases of the first delayed clock signal pair FCLK and FCLKB; as the logical value of the weight R<1:m> becomes larger, the phase mixing circuit 1422 can generate a first output clock signal CLKOUT and a second output clock signal CLKOUTB whose phases are close to the phases of the shifted clock signal pair SSCLK and SSCLKB.

[0095] Fig.15 It is a graphic Fig.14 FIG. 14A is a diagram showing the configuration of the coarse delay line 1412. Fig.15 , the coarse delay line 1412 may include a plurality of delay units. The coarse delay line 1412 may include a first delay unit 1412-1, a second delay unit 1412-2, ..., and an nth delay unit 1412-n. The first to nth delay units 1412-1, 1412-2, ..., and 1412-n may have substantially the same structure, except that the signal to be received and the signal to be output are different. The first delay unit 1412-1 may receive a first input clock signal CLKIN and a second input clock signal CLKINB, and may output a first delayed clock signal pair FCLK and FCLKB and a second delayed clock signal pair SCLK and SCLKB. The first delay unit 1412-1 may receive an enable signal EN <1> , the first selection signal SEL1 <1> and the second selection signal SEL2 <1> The first delay unit 1412-1 can be based on the enable signal EN <1> The first delay unit 1412-1 may delay the first input clock signal CLKIN and the second input clock signal CLKINB based on the first selection signal SEL1. <1> , to output one of the clock signal pair delayed by the first delay unit 1412-1 and the clock signal pair delayed by the second delay unit 1412-2 as the first delayed clock signal pair FCLK and FCLKB. The first delay unit 1412-1 may be based on the second selection signal SEL2 <1> , to output one of the clock signal pair delayed by the first delay unit 1412-1 and the clock signal pair delayed by the second delay unit 1412-2 as the second delayed clock signal pair SCLK and SCLKB. The first delay unit 1412-1 may include a CML buffer 1511, a first CML multiplexer 1512, and a second CML multiplexer 1513. The CML buffer 1511 may receive a first input clock signal CLKIN and a second input clock signal CLKINB, and may output a delayed clock signal pair by buffering and delaying the first input clock signal CLKIN and the second input clock signal CLKINB. The time by which the CML buffer 1511 delays the first input clock signal CLKIN and the second input clock signal CLKINB may correspond to substantially half of the unit delay time. The first CML multiplexer 1512 may receive a first selection signal SEL1 <1> , a clock signal pair delayed by the CML buffer 1511, and a clock signal pair delayed by the second delay unit 1412-2. The first CML multiplexer 1512 may be configured based on the first selection signal SEL1 <1> , to output one of the clock signal pair delayed by the CML buffer 1511 and the clock signal pair delayed by the second delay unit 1412-2 as the first delayed clock signal pair FCLK and FCLKB.For example, when the first selection signal SEL1 <1> When the first selection signal SEL1 is at a logic high level, the first CML multiplexer 1512 can output the clock signal pair delayed by the CML buffer 1511 as the first delayed clock signal pair FCLK and FCLKB. <1> When the first CML multiplexer 1512 is at a logic low level, the first CML multiplexer 1512 may output the clock signal pair delayed by the second delay unit 1412-2 as the first delayed clock signal pair FCLK and FCLKB. The delay time of the first CML multiplexer 1512 may correspond to substantially half of the unit delay time, and the sum of the delay time of the CML buffer 1511 and the delay time of the first CML multiplexer 1512 may correspond to the unit delay time. The second CML multiplexer 1513 may receive the second selection signal SEL2 <1> , a clock signal pair delayed by the CML buffer 1511, and a clock signal pair delayed by the second delay unit 1412-2. The second CML multiplexer 1513 may be based on the second selection signal SEL2 <1> , to output one of the clock signal pair delayed by the CML buffer 1511 and the clock signal pair delayed by the second delay unit 1412-2 as the second delayed clock signal pair SCLK and SCLKB. <1> When the second selection signal SEL2 is at a logic high level, the second CML multiplexer 1513 can output the clock signal pair delayed by the CML buffer 1511 as the second delayed clock signal pair SCLK and SCLKB. <1> When the delay time of the second CML multiplexer 1513 is a logic low level, the second CML multiplexer 1513 may output the clock signal pair delayed by the second delay unit 1412-2 as the second delayed clock signal pair SCLK and SCLKB. The delay time of the second CML multiplexer 1513 may correspond to substantially half of the unit delay time, and the delay time of the CML buffer 1511 and the delay time of the second CML multiplexer 1513 may correspond to the unit delay time.

[0096] The second delay unit 1412-2 may receive the clock signal pair delayed by the CML buffer 1511 of the first delay unit 1412-1. The second delay unit 1412-2 may receive the enable signal EN <2> , the first selection signal SEL1 <2> and the second selection signal SEL2 <2> The second delay unit 1412-2 can be based on the enable signal EN <2> The second delay unit 1412-2 may delay the clock signal pair delayed by the CML buffer 1511 of the first delay unit 1412-1 based on the first selection signal SEL1 <2> , outputs one of the clock signal pair delayed by the second delay unit 1412-2 and the clock signal pair delayed by the third delay unit (not shown) provided at the next stage of the second delay unit 1412-2 to the first delay unit 1412-1. The second delay unit 1412-2 may be based on the second selection signal SEL2 <2> , outputs one of the clock signal pair delayed by the second delay unit 1412-2 and the clock signal pair delayed by the third delay unit to the first delay unit 1412-1. The second delay unit 1412-2 may include a CML buffer 1521, a first CML multiplexer 1522, and a second CML multiplexer 1523. The CML buffer 1521 may receive the clock signal pair delayed by the CML buffer 1511 of the first delay unit 1412-1, and may output the delayed clock signal pair by buffering and delaying the clock signal pair delayed by the CML buffer 1511 of the first delay unit 1412-1. The first CML multiplexer 1522 may receive a first selection signal SEL1 <2> , a clock signal pair delayed by the CML buffer 1521, and a clock signal pair delayed by the third delay unit. The first CML multiplexer 1522 may be based on the first selection signal SEL1 <2> The first CML multiplexer 1512 of the first delay unit 1412-1 outputs one of the clock signal pair delayed by the CML buffer 1521 and the clock signal pair delayed by the third delay unit. <2> When the first selection signal SEL1 is at a logic high level, the first CML multiplexer 1522 may output the clock signal pair delayed by the CML buffer 1521 to the first CML multiplexer 1512 of the first delay unit 1412-1. <2> When the first CML multiplexer 1522 is at a logic low level, the first CML multiplexer 1522 may output the clock signal pair delayed by the third delay unit to the first CML multiplexer 1512 of the first delay unit 1412-1. The second CML multiplexer 1523 may receive the second selection signal SEL2 <2> , a clock signal pair delayed by the CML buffer 1521, and a clock signal pair delayed by the third delay unit.The second CML multiplexer 1523 may be configured based on the second selection signal SEL2 <2> , outputs one of the clock signal pair delayed by the CML buffer 1521 and the clock signal pair delayed by the third delay unit to the second CML multiplexer 1513 of the first delay unit 1412-1. <2> When the second selection signal SEL2 is at a logic high level, the second CML multiplexer 1523 may output the clock signal pair delayed by the CML buffer 1521 to the second CML multiplexer 1513 of the first delay unit 1412-1. <2> When the third delay unit 1412 - 1 is at a logic low level, the second CML multiplexer 1523 may output the clock signal pair delayed by the third delay unit to the second CML multiplexer 1513 of the first delay unit 1412 - 1 .

[0097] The nth delay unit 1412-n may receive a clock signal pair delayed by a delay unit disposed at a previous stage (ie, the (n-1)th delay unit (not shown)). The nth delay unit 1412-n may receive an enable signal EN <n>, the first selection signal SEL1 <n>and the second selection signal SEL2 <n>The nth delay unit 1412 - n can be based on the enable signal EN <n>The nth delay unit 1412-n may be based on the first selection signal SEL1 <n>The nth delay unit 1412-n may output the clock signal pair delayed by the nth delay unit 1412-n to the (n-1)th delay unit. <n>The clock signal pair delayed by the nth delay unit 1412-n is output to the (n-1)th delay unit. The nth delay unit 1412-n may include a CML buffer 15n1, a first CML multiplexer 15n2, and a second CML multiplexer 15n3. The CML buffer 15n1 may receive the clock signal pair delayed by the CML buffer of the (n-1)th delay unit, and may output the delayed clock signal pair by buffering and delaying the clock signal pair delayed by the CML buffer of the (n-1)th delay unit. The first CML multiplexer 15n2 may receive a first selection signal SEL1 <n>, a clock signal pair delayed by the CML buffer 15n1, and a ground voltage VSS. The first CML multiplexer 15n2 may be based on the first selection signal SEL1 <n>, outputs one of the clock signal pair delayed by the CML buffer 15n1 and the ground voltage VSS to the first CML multiplexer of the (n-1)th delay unit. <n>When the first CML multiplexer 15n2 is at a logic high level, the first CML multiplexer 15n2 may output the clock signal pair delayed by the CML buffer 15n1 to the first CML multiplexer of the (n-1)th delay unit. The second CML multiplexer 15n3 may receive the second selection signal SEL2 <n>, a clock signal pair delayed by the CML buffer 15n1, and a ground voltage VSS. The second CML multiplexer 15n3 may be based on the second selection signal SEL2 <n>, outputs one of the clock signal pair delayed by the CML buffer 15n1 and the ground voltage VSS to the second CML multiplexer of the (n-1)th delay unit. <n>When the CML buffer 15n1 is at a logic high level, the second CML multiplexer 15n3 may output the clock signal pair delayed by the CML buffer 15n1 to the second CML multiplexer of the (n-1)th delay unit.

[0098] Fig.16 1 is a diagram illustrating a configuration of a CML buffer 1600 according to an embodiment of the present disclosure. The CML buffer 1600 may be applied as Fig.15 Each of the CML buffers 1511, 1521, ..., and 15n1 shown. Fig.16 , the CML buffer 1600 can generate an output signal pair OUT1 and OUT1B by differentially amplifying an input signal pair IN and INB. The CML buffer 1600 may include a first transistor T11, a second transistor T12, and a third transistor T13. Each of the first to third transistors T11, T12, and T13 may be an N-channel MOS transistor. The first transistor T11 may be coupled between a common node CN1 and a terminal supplied with a ground voltage VSS, and a gate of the first transistor T11 may receive an enable signal EN. When the enable signal EN is enabled, the first transistor T11 may form a current path from the common node CN1 to a terminal supplied with a ground voltage VSS. The second transistor T12 may be coupled between a negative output node ON1 and the common node CN1, and a gate of the second transistor T12 may receive a first input signal IN. The second transistor T12 may change the voltage level of the negative output node ON1 by coupling the negative output node ON1 to the common node CN1 based on the voltage level of the first input signal IN. The negative output signal OUT1B may be output from the negative output node ON1. The third transistor T13 may be coupled between the positive output node OP1 and the common node CN1, and the gate of the third transistor T13 may receive the second input signal INB. The second input signal INB may be a complementary signal having a logic level opposite to the logic level of the first input signal IN. The third transistor T13 may change the voltage level of the positive output node OP1 by coupling the positive output node OP1 to the common node CN1 based on the voltage level of the second input signal INB. The positive output signal OUT1 may be output from the positive output node OP1. The CML buffer 1600 may further include a first load resistor R11 and a second load resistor R12. The first load resistor R11 may be coupled between a terminal supplied with a power supply voltage VDD and the negative output node ON1. The second load resistor R12 may be coupled between a terminal supplied with a power supply voltage VDD and the positive output node OP1. The CML buffer 1600 may further include a current source IS1. The current source IS1 may be coupled between the common node CN1 and a terminal supplied with the ground voltage VSS, and the current source IS1 may allow a constant current to flow from the common node CN1 to the terminal supplied with the ground voltage VSS.

[0099] Fig.17 1 is a diagram illustrating a configuration of a CML multiplexer 1700 according to an embodiment of the present disclosure. The CML multiplexer 1700 may be applied as Fig.15 Each of the CML multiplexers 1512, 1513, 1522, 1523, 15n2, and 15n3 shown. The CML multiplexer 1700 may include two amplifier circuits that selectively operate based on a selection signal SEL. The CML multiplexer 1700 may include a first amplifier circuit 1710 and a second amplifier circuit 1720. When the selection signal SEL has a first logic level, the first amplifier circuit 1710 may generate an output signal pair OUT and OUTB by differentially amplifying the first input signal pair IN1 and IN1B. When the selection signal SEL has a second logic level, the second amplifier circuit 1720 may generate an output signal pair OUT and OUTB by differentially amplifying the second input signal pair IN2 and IN2B.

[0100] The first amplifier circuit 1710 may include a first transistor T21, a second transistor T22, and a third transistor T23. Each of the first to third transistors T21, T22, and T23 may be an N-channel MOS transistor. The first transistor T21 may be coupled between the first common node CN21 and a terminal supplied with a ground voltage VSS, and the gate of the first transistor T21 may receive a selection signal SEL. When the selection signal SEL is enabled as a logic high level, the first transistor T21 may form a current path from the first common node CN21 to the terminal supplied with a ground voltage VSS. The second transistor T22 may be coupled between the negative output node ON2 and the first common node CN21, and the gate of the second transistor T22 may receive a first input signal IN1. The second transistor T22 may change the voltage level of the negative output node ON2 by coupling the negative output node ON2 to the first common node CN21 based on the first input signal IN1. The negative output signal OUTB may be output from the negative output node ON2. The third transistor T23 may be coupled between the positive output node OP2 and the first common node CN21, and the gate of the third transistor T23 may receive the complementary signal IN1B of the first input signal IN1. The third transistor T23 may change the voltage level of the positive output node OP2 by coupling the positive output node OP2 to the first common node CN21 based on the complementary signal IN1B of the first input signal IN1. The positive output signal OUT may be output from the positive output node OP2.

[0101] The second amplifier circuit 1720 may include a fourth transistor T24, a fifth transistor T25, and a sixth transistor T26. Each of the fourth to sixth transistors T24, T25, and T26 may be an N-channel MOS transistor. The fourth transistor T24 may be coupled between the second common node CN22 and the terminal supplied with the ground voltage VSS, and the gate of the fourth transistor T24 may receive the complementary signal SELB of the selection signal SEL. When the complementary signal SELB of the selection signal SEL is a logic high level, the fourth transistor T24 may form a current path from the second common node CN22 to the terminal supplied with the ground voltage VSS. The fifth transistor T25 may be coupled between the negative output node ON2 and the second common node CN22, and the gate of the fifth transistor T25 may receive the second input signal IN2. The fifth transistor T25 may change the voltage level of the negative output node ON2 by coupling the negative output node ON2 to the second common node CN22 based on the second input signal IN2. The sixth transistor T26 may be coupled between the positive output node OP2 and the second common node CN22, and a gate of the sixth transistor T26 may receive a complementary signal IN2B of the second input signal IN2. The sixth transistor T26 may change a voltage level of the positive output node OP2 by coupling the positive output node OP2 to the second common node CN22 based on the complementary signal IN2B of the second input signal IN2.

[0102] The CML multiplexer 1700 may further include a first load resistor R21, a second load resistor R22, and a current source IS2. The first load resistor R21 may be coupled between a terminal supplied with a power supply voltage VDD and a negative output node ON2. The second load resistor R22 may be coupled between a terminal supplied with a power supply voltage VDD and a positive output node OP2. The current source IS2 may be coupled between the first transistor T21 of the first amplifier circuit 1710, the fourth transistor T24 of the second amplifier circuit 1720, and a terminal supplied with a ground voltage VSS. The current source IS2 may allow a constant current to flow from the first transistor T21 and the fourth transistor T24 to the terminal supplied with the ground voltage VSS. The first amplifier circuit 1710 and the second amplifier circuit 1720 of the CML multiplexer 1700 may selectively operate based on a selection signal SEL. Each of the first amplifier circuit 1710 and the second amplifier circuit 1720 may have a Fig.16 Therefore, the delay times of the CML buffer 1600 and the CML multiplexer 1700 may be substantially the same and may be set to substantially half of the unit delay time.

[0103] The following will refer to Figures 14 to 17 The operation of the delay line 1400 according to an embodiment of the present disclosure is described. First, a coarse delay locking operation may be performed to set the delay amount of the delay line 1400. For example, in a default state, the coarse shift register 1411 may enable the enable signal EN <1> , the first selection signal SEL1 <1> and the second selection signal SEL2 <1> Enabled to a logic high level. The CML buffer 1511 of the first delay unit 1412-1 may delay the first input clock signal CLKIN and the second input clock signal CLKINB, the first CML multiplexer 1512 may output the clock signal pair delayed by the CML buffer 1511 as the first delayed clock signal pair FCLK and FCLKB, and the second CML multiplexer 1513 may output the clock signal pair delayed by the CML buffer 1511 as the second delayed clock signal pair SCLK and SCLKB. The first delayed clock signal pair FCLK and FCLKB may have a phase obtained as the first input clock signal CLKIN and the second input clock signal CLKINB are delayed by two stages (i.e., the CML buffer 1511 and the first CML multiplexer 1512). The delay time of these two stages may correspond to the unit delay time. The second delayed clock signal pair SCLK and SCLKB may have a phase obtained as the first input clock signal CLKIN and the second input clock signal CLKINB are delayed by two stages (i.e., the CML buffer 1511 and the second CML multiplexer 1513). Therefore, the coarse delay line 1412 may output the first delayed clock signal pair FCLK and FCLKB having the same phase as the second delayed clock signal pair SCLK and SCLKB. During the coarse delay locking operation, the weight R<1:m> may have a preset value or a default value, and the fine delay circuit 1420 may generate the first output clock signal CLKOUT and the second output clock signal CLKOUTB by mixing the phases of the first delayed clock signal pair FCLK, FCLKB and the second delayed clock signal pair SCLK and SCLKB output from the coarse delay circuit 1410 based on the weight R<1:m>. The fine delay circuit 1420 can generate the shift clock signal pair SSCLK and SSCLKB by further delaying the second delayed clock signal pair SCLK and SCLKB by one stage (i.e., CML buffer 1422-1). Therefore, the shift clock signal pair SSCLK and SSCLKB can have a phase obtained as the first input clock signal CLKIN and the second input clock signal CLKINB are delayed by three stages, and can have a phase difference corresponding to one stage compared to the first delayed clock signal pair FCLK and FCLKB (i.e., a phase difference corresponding to substantially half of the unit delay time).

[0104] If the coarse increase signal INCC of the coarse control signal DCC is enabled, the coarse shift register 1411 may maintain the enable signal EN <1> The enable state, and the second selection signal SEL2 <1> The first selection signal SEL1 can be <1> Disable to logic low and can enable the EN signal <2> and the first selection signal SEL1 <2> Enabled to a logic high level. The CML buffer 1521 of the second delay unit 1412-2 may receive the clock signal pair delayed by the CML buffer 1511 of the first delay unit 1412-1, and may delay the received clock signal pair. The first CML multiplexer 1522 of the second delay unit 1412-2 may output the clock signal pair delayed by the CML buffer 1521 to the first CML multiplexer 1512 of the first delay unit 1412-1, and the first CML multiplexer 1512 of the first delay unit 1412-1 may output the clock signal pair output from the first CML multiplexer 1522 of the second delay unit 1412-2 as the first delayed clock signal pair FCLK and FCLKB. The second CML multiplexer 1513 of the first delay unit 1412-1 may output the clock signal pair delayed by the CML buffer 1511 as the second delayed clock signal pair SCLK and SCLKB. The first delayed clock signal pair FCLK and FCLKB may have a phase obtained as the first input clock signal CLKIN and the second input clock signal CLKINB are delayed by four stages (i.e., the CML buffer 1511 of the first delay unit 1412-1, the CML buffer 1521 of the second delay unit 1412-2, the first CML multiplexer 1522 of the second delay unit 1412-2, and the first CML multiplexer 1512 of the first delay unit 1412-1). The second delayed clock signal pair SCLK and SCLKB may have a phase obtained as the first input clock signal CLKIN and the second input clock signal CLKINB are delayed by two stages. The shifted clock signal pair SSCLK and SSCLKB may have a phase obtained as the first input clock signal CLKIN and the second input clock signal CLKINB are delayed by three stages, and the first delayed clock signal pair FCLK and FCLKB and the shifted clock signal pair SSCLK and SSCLKB may have a phase difference corresponding to one stage. The phase of the shifted clock signal pair SSCLK and SSCLKB may be advanced by a phase corresponding to substantially half of the unit delay time compared to the first delayed clock signal pair FCLK and FCLKB.

[0105] If the coarse increase signal INCC of the coarse control signal DCC is enabled again, the coarse shift register 1411 may maintain the enable signal EN <1> , enable signal EN <2> and the first selection signal SEL1 <2> The enable state can be the second selection signal SEL2 <1> Disable to logic low level, and the second selection signal SEL2 can be <2> The first CML multiplexer 1522 of the second delay unit 1412-2 may output the clock signal pair delayed by the CML buffer 1521 to the first CML multiplexer 1512 of the first delay unit 1412-1, and the first CML multiplexer 1512 of the first delay unit 1412-1 may output the clock signal pair output from the first CML multiplexer 1522 of the second delay unit 1412-2 as the first delayed clock signal pair FCLK and FCLKB. The second CML multiplexer 1523 of the second delay unit 1412-2 may output the clock signal pair delayed by the CML buffer 1521 of the second delay unit 1412-2 to the second CML multiplexer 1513 of the first delay unit 1412-1, and the second CML multiplexer 1513 of the first delay unit 1412-1 may output the clock signal pair output from the second CML multiplexer 1523 of the second delay unit 1412-2 as the second delayed clock signal pair SCLK and SCLKB. The first delayed clock signal pair FCLK and FCLKB may have a phase obtained as the first input clock signal CLKIN and the second input clock signal CLKINB are delayed by four stages. The second delayed clock signal pair SCLK and SCLKB may have a phase obtained as the first input clock signal CLKIN and the second input clock signal CLKINB are delayed by four stages (i.e., the CML buffer 1511 of the first delay unit 1412-1, the CML buffer 1521 of the second delay unit 1412-2, the second CML multiplexer 1523 of the second delay unit 1412-2, and the second CML multiplexer 1513 of the first delay unit 1412-1). The shifted clock signal pair SSCLK and SSCLKB may have a phase obtained as the first input clock signal CLKIN and the second input clock signal CLKINB are delayed by five stages, and the first delayed clock signal pair FCLK and FCLKB and the shifted clock signal pair SSCLK and SSCLKB may have a phase difference corresponding to one stage. Compared with the phase-shifted clock signal pair SSCLK and SSCLKB, the phase of the first delayed clock signal pair FCLK and FCLKB may be advanced by a phase corresponding to substantially half of the unit delay time.

[0106] When the coarse delay lock operation is completed, a fine delay lock operation can be performed. When the fine delay lock operation is performed, the logic value of the weight R<1:m> can be changed by the fine control signal DCF. When the logic value of the weight R<1:m> changes in a step-by-step manner, the phase mixing circuit 1422 can change the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB by 1 / m of the phase corresponding to one level. The weight R<1:m> can be changed like a thermometer code. If the weight R<1:m> reaches a minimum or maximum value, one of the coarse increase signal INCC and the coarse decrease signal DECC of the coarse control signal DCC can be enabled, and the weight R<1:m> can be increased from the minimum value or decreased from the maximum value. For example, it is assumed that the phases of the first delayed clock signal pair FCLK, FCLKB and the second delayed clock signal pair SCLK and SCLKB are set to be the same during the coarse delay lock operation. When the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB is ahead of the phase of the target clock signal during the fine delay lock operation, the fine increase signal INCF may be enabled. Whenever the fine increase signal INCF is enabled, the fine shift register 1421 may continuously increase the logic value of the weight R<1:m>. As the logic value of the weight R<1:m> increases, the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB may be close to the phase of the shift clock signal pair SSCLK and SSCLKB. When the weight R<1:m> reaches a maximum value and the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB is still ahead of the phase of the target clock signal, the coarse increase signal INCC may be enabled, and the first delayed clock signal pair FCLK and FCLKB may be generated from the coarse delay circuit 1410, and the phase of the first delayed clock signal pair FCLK and FCLKB lags behind the second delayed clock signal pair SCLK and SCLKB by a unit delay time. Since the weight R<1:m> is a maximum value, the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB can still be close to the phase of the shift clock signal pair SSCLK and SSCLKB. When the fine increase signal INCF is continuously enabled, the logic value of the weight R<1:m> can be reduced from the maximum value in a step-by-step manner. As the logic value of the weight R<1:m> decreases, the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB can be close to the first delayed clock signal pair FCLK and FCLKB, and can lag behind 1 / 16 of the unit delay time.Therefore, even when the coarse delay circuit 1410 changes the phase of the first delayed clock signal pair FCLK, FCLKB and the second delayed clock signal pair SCLK and SCLKB by a phase corresponding to the unit delay time during the coarse delay locking operation, the fine delay circuit 1420 can change the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUTB by a phase corresponding to substantially half of the unit delay time. In addition, since the fine delay circuit 1420 can change the phase of the first output clock signal CLKOUT and the second output clock signal CLKOUT by 1 / 16 of the unit delay time in a stepwise manner during the fine delay locking operation, the fine delay circuit 1420 can perform a seamless phase mixing operation and have a high resolution.

[0107] Those skilled in the art to which the present disclosure belongs should understand that the embodiments are merely illustrative in all aspects and are not restrictive, because the present disclosure can be implemented in various other forms without departing from the technical spirit or basic features of the present disclosure. Therefore, the scope of the present disclosure is defined by the appended claims rather than by the specific implementation methods, and all modifications or changes derived from the meaning and scope of the claims and their equivalents should be understood to be included in the scope of the present disclosure.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A clock generation circuit, comprising: a clock receiver configured to receive the first clock signal and the second clock signal to generate a first received clock signal and a second received clock signal; a first delay loop including a single-ended complementary metal oxide semiconductor (CMOS) clock delay line and configured to receive the first received clock signal and the second received clock signal to generate a reference clock signal, and to perform a delay locking operation on the reference clock signal via the single-ended CMOS clock delay line to generate a first delay locked clock signal; as well as The second delay loop includes a differential current mode logic (CML) clock delay line and is configured to delay the first receiving clock signal and the second receiving clock signal based on the first delay locked clock signal and an internal clock signal to generate a first internal clock signal. 2 . The clock generation circuit of claim 1 , wherein the first delay loop is configured to activate the second delay loop based on an operation mode and the delay locking operation.

3. The clock generation circuit according to claim 2, wherein the first delay loop generates an enable signal based on the operation mode and the delay lock operation, and The second delay loop is deactivated in response to receiving the enable signal having a disabled state, and is activated in response to receiving the enable signal having an enabled state. 4 . The clock generation circuit of claim 1 , wherein the first delay loop is configured to activate the second delay loop based on a phase of the first delay locked clock signal. 5 . The clock generating circuit according to claim 1 , wherein the first delay loop is configured to deactivate the second delay loop when a phase of the first delay-locked clock signal changes within a given range in a power-down mode.

6. The clock generation circuit according to claim 1, wherein the first delay loop comprises: a first clock buffer configured to buffer the first received clock signal and the second received clock signal and provide the buffered clock signals as the reference clock signal; The single-ended CMOS clock delay line is configured to delay the reference clock signal based on a first delay control signal to generate the first delay locked clock signal; a replicator configured to delay the first delay-locked clock signal by a modeling delay time to generate a feedback clock signal; a first phase detector configured to compare the phases of the reference clock signal and the feedback clock signal to generate a first phase detection signal; as well as The first delay control circuit is configured to generate the first delay control signal based on the first phase detection signal. 7 . The clock generating circuit of claim 6 , wherein the clock divider is configured to divide the frequency of the buffered clock signal to generate the reference clock signal. 8 . The clock generation circuit according to claim 6 , wherein the first delay loop further comprises an enable control circuit configured to generate an enable signal for activating the second delay loop based on a power-off signal and the first delay control signal.

9. The clock generating circuit according to claim 8, The first delay control signal includes a phase increase signal and a phase decrease signal, and The enable control circuit is configured to: when the power-off signal is enabled, when one of the phase increase signal and the phase decrease signal is not continuously generated a number of times corresponding to a threshold, maintain the state of the enable signal in a disabled state, and enable the enable signal when one of the phase increase signal and the phase decrease signal is continuously generated a number of times corresponding to the threshold.

10. The clock generation circuit according to claim 1, wherein the second delay loop comprises: the single-ended CML clock delay line configured to delay the first received clock signal and the second received clock signal based on a second delay control signal to generate a second delay locked clock signal and a complementary second delay locked clock signal; a clock frequency dividing circuit configured to divide the frequency of the second delay locked clock signal and the complementary second delay locked clock signal to generate the first internal clock signal; a second phase detector configured to compare the phases of the first internal clock signal and the first delay locked clock signal to generate a second phase detection signal; as well as The second delay control circuit is configured to generate the second delay control signal based on the second phase detection signal.

11. The clock generation circuit according to claim 10, The second delay control signal includes a coarse control signal and a fine control signal, and The differential CML clock delay line comprises: a coarse delay circuit configured to generate a first delayed clock signal pair and a second delayed clock signal pair by delaying the first received clock signal and the second received clock signal based on the coarse control signal, the first delayed clock signal pair having a phase that is the same as or delayed by a unit delay time compared to a phase of the second delayed clock signal pair; as well as A fine delay circuit is configured to generate a shift clock signal pair by delaying the second delayed clock signal pair by a phase corresponding to substantially half of the unit delay time, and to generate the second delay locked clock signal and a complementary second delay locked clock signal by mixing the phases of the first delayed clock signal pair and the shifted clock signal pair based on the fine control signal. 12 . The clock generation circuit of claim 10 , wherein the differential CML clock delay line comprises a plurality of current mode logic (CML) delay cells configured to sequentially delay the first reception clock signal and the second reception clock signal based on the second delay control signal.

13. The clock generating circuit according to claim 10, wherein the clock frequency dividing circuit comprises: a CML clock divider configured to divide the frequency of the second delay locked clock signal and the complementary second delay locked clock signal to generate a plurality of divided clock signals; as well as The CML to CMOS converter is configured to generate the first internal clock signal based on at least two divided clock signals among the plurality of divided clock signals.

14. The clock generation circuit according to claim 13, wherein: The CML clock divider is configured to generate a first divided clock signal, a second divided clock signal, a third divided clock signal and a fourth divided clock signal, wherein the first divided clock signal, the second divided clock signal, the third divided clock signal and the fourth divided clock signal each have a phase difference of 90 degrees in sequence, and The CML to CMOS converter is configured to generate the first and third internal clock signals based on the first and third frequency-divided clock signals, and to generate the second and fourth internal clock signals based on the second and fourth frequency-divided clock signals.

15. The clock generating circuit according to claim 14, wherein the second delay loop further includes a dummy circuit coupled to a node from which the second internal clock signal, the third internal clock signal, and the fourth internal clock signal are output, and wherein the dummy circuit models the second phase detector.

16. The clock generation circuit of claim 10, wherein the second delay loop further comprises a second clock buffer configured to buffer the first received clock signal and the second received clock signal and provide the buffered clock signals to the differential CML clock delay line.

17. The clock generation circuit of claim 10, wherein the second delay loop further comprises a duty cycle corrector configured to correct a duty cycle of a clock signal output by the differential CML clock delay line to generate the second delay locked clock signal and the complementary second clock signal.

18. A clock generation circuit, comprising: a clock receiver configured to receive the first clock signal and the second clock signal to generate a first received clock signal and a second received clock signal; a first delay loop including a single-ended complementary metal oxide semiconductor (CMOS) clock delay line and configured to receive the first received clock signal and the second received clock signal to generate a first reference clock signal, and delay the first reference clock signal via the single-ended CMOS delay line based on a first delay locked clock signal and a first internal clock signal to generate the first delay locked clock signal; as well as The second delay loop includes a differential current mode logic (CML) clock delay line and is configured to perform a delay locking operation on the first receiving clock signal and the second receiving clock signal to generate the first internal clock signal.

19. The clock generation circuit according to claim 18, wherein the first delay loop comprises: a first clock buffer configured to buffer the first received clock signal and the second received clock signal and provide the buffered clock signals as the first reference clock signal; The single-ended CMOS delay line is configured to delay the first reference clock signal based on a first delay control signal to generate the first delay locked clock signal; a first phase detector configured to compare phases of the first delay locked clock signal and the first internal clock signal to generate a first phase detection signal; as well as The first delay control circuit is configured to generate the first delay control signal based on the first phase detection signal. 20 . The clock generation circuit of claim 19 , the first clock divider being configured to divide the frequency of the buffered clock signal to generate the first reference clock signal.

21. The clock generation circuit according to claim 18, wherein the second delay loop comprises: the single-ended CML clock delay line configured to delay the first received clock signal and the second received clock signal based on a second delay control signal to generate a second delay locked clock signal and a complementary second delay locked clock signal; a clock frequency dividing circuit configured to divide the frequency of the second delay locked clock signal and the complementary second delay locked clock signal to generate the first internal clock signal; a replicator configured to delay the first internal clock signal by a modeling delay time to generate a feedback clock signal; a second phase detector configured to compare the phases of the feedback clock signal and a second reference clock signal to generate a second phase detection signal, the second reference clock signal being generated based on the first receive clock signal and the second receive clock signal; as well as The second delay control circuit is configured to generate the second delay control signal based on the second phase detection signal.

22. The clock generating circuit according to claim 21, The second delay control signal includes a coarse control signal and a fine control signal, and The differential CML clock delay line comprises: a coarse delay circuit configured to generate a first delayed clock signal pair and a second delayed clock signal pair by delaying the first received clock signal and the second received clock signal based on the coarse control signal, the first delayed clock signal pair having a phase that is the same as or delayed by a unit delay time compared to a phase of the second delayed clock signal pair; as well as A fine delay circuit is configured to generate a shift clock signal pair by delaying the second delayed clock signal pair by a phase corresponding to substantially half of the unit delay time, and to generate the second delay locked clock signal and the complementary second delay locked clock signal by mixing the phases of the first delayed clock signal pair and the shifted clock signal pair based on the fine control signal. 23 . The clock generation circuit of claim 21 , wherein the differential CML clock delay line comprises a plurality of current mode logic (CML) delay cells configured to sequentially delay the first reception clock signal and the second reception clock signal based on the second delay control signal.

24. The clock generating circuit according to claim 21, wherein the clock frequency dividing circuit comprises: a CML clock divider configured to divide the frequency of the second delay locked clock signal and the complementary second delay locked clock signal to generate a plurality of divided clock signals; as well as The CML to CMOS converter is configured to generate the first internal clock signal based on at least two divided clock signals among the plurality of divided clock signals.

25. The clock generation circuit according to claim 24, wherein: The CML clock divider is configured to generate a first divided clock signal, a second divided clock signal, a third divided clock signal and a fourth divided clock signal, wherein the first divided clock signal, the second divided clock signal, the third divided clock signal and the fourth divided clock signal each have a phase difference of 90 degrees in sequence, and The CML to CMOS converter is configured to generate the first and third internal clock signals based on the first and third frequency-divided clock signals, and to generate the second and fourth internal clock signals based on the second and fourth frequency-divided clock signals.

26. The clock generation circuit according to claim 25, wherein: The second delay loop further includes a dummy circuit coupled to a node from which the second internal clock signal, the third internal clock signal, and the fourth internal clock signal are output, and The dummy circuit models the second phase detector.

27. The clock generation circuit of claim 21, wherein the second delay loop further comprises a second clock buffer configured to buffer the first received clock signal and the second received clock signal and provide the buffered clock signals to the differential CML clock delay line.

28. The clock generation circuit of claim 21, wherein the second delay loop further comprises: a third clock buffer configured to buffer the first received clock signal and the second received clock signal to generate a buffered clock signal; as well as A second clock divider is configured to divide the frequency of the buffered clock signal to generate the second reference clock signal.

29. The clock generation circuit of claim 21, wherein the second delay loop further comprises a duty cycle corrector configured to correct a duty cycle of a clock signal output by the differential CML clock delay line to generate the second delay locked clock signal and the complementary second clock signal.

30. A semiconductor device comprising: a clock receiver configured to receive the first clock signal and the second clock signal to generate a first received clock signal and a second received clock signal; a first delay loop including a single-ended complementary metal oxide semiconductor (CMOS) clock delay line and configured to delay the reference clock signal to generate the first delay locked clock signal based on a reference clock signal and a first delay locked clock signal generated according to the first received clock signal and the second received clock signal; a second delay loop including a differential current mode logic (CML) clock delay line and configured to delay the first received clock signal and the second received clock signal based on the first delay locked clock signal and the first internal clock signal to generate the first internal clock signal; a command decoder configured to decode the command signal to generate an internal command signal; a command delay line configured to generate a delayed command signal by delaying the internal command signal for a time substantially the same as the duration required for the reference clock signal to be delayed by the single-ended CMOS clock delay line; a delay shift circuit configured to delay the delay command signal by a time corresponding to a delay based on the first delay locked clock signal to generate a synchronization command signal; as well as A gating circuit is configured to synchronize the synchronization command signal with the first internal clock signal to generate an output control signal.

31. A semiconductor device comprising: a clock receiver configured to receive the first clock signal and the second clock signal to generate a first received clock signal and a second received clock signal; a first delay loop including a single-ended complementary metal oxide semiconductor (CMOS) clock delay line and configured to delay the first reference clock signal to generate a first delay locked clock signal based on a first reference clock signal and a first internal clock signal generated according to the first received clock signal and the second received clock signal; a second delay loop including a differential current mode logic (CML) clock delay line and configured to delay the first received clock signal and the second received clock signal based on the first internal clock signal and a second reference clock signal generated according to the first received clock signal and the second received clock signal to generate the first internal clock signal; a command decoder configured to decode the command signal to generate an internal command signal; a command delay line configured to delay the internal command signal for a duration substantially the same as: a duration required for the first reference clock signal to be delayed by the single-ended CMOS clock delay line to generate a delayed command signal; a time delay shift circuit configured to delay the delay command signal by a time corresponding to the time delay based on the first internal clock signal to generate a synchronization command signal; as well as A gating circuit is configured to synchronize the synchronization command signal with the first internal clock signal to generate an output control signal.

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