Process angle detection method, system, device and storage medium

Abstract

A process angle detection method and system, device, and storage medium, the process angle detection method is used to obtain the worst process angle of an SRAM unit device, the SRAM unit device includes a pull-up transistor, a pull-down transistor, and a transmission gate transistor, including: obtaining electrical data of multiple SRAM unit devices, and the electrical data of the pull-up transistor, the pull-down transistor, and the transmission gate transistor in the same SRAM unit device constitute a first data group; using multiple first data groups to establish a three-dimensional normal distribution model, the shape of the three-dimensional normal distribution model is an ellipsoid; extracting multiple groups of test data groups corresponding to the surface position of the ellipsoid from the first data group; simulating multiple groups of test data groups to obtain multiple corresponding write noise tolerances; extracting the test data group corresponding to the minimum value of the multiple write noise tolerances as the worst process angle. The present invention improves the accuracy of process angle detection.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a process corner detection method, system, device, and storage medium. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three major types: logic, memory, and analog circuits, and storage devices account for a relatively large proportion in integrated circuit products. Among them, due to the advantages of low power consumption and fast operating speed of the static random access memory (SRAM), the SRAM cell devices have received more and more attention.

[0003] The SRAM cell devices mainly include a pull-up (PU) transistor, a pull-down (PD) transistor, and a pass gate (PG) transistor. Among them, the pull-down transistor and the pass gate transistor are NMOS transistors, and the pull-up transistor is a PMOS transistor.

[0004] Currently, by obtaining the characteristics of the SRAM such as the read noise margin (RNM), write noise margin (WNM), read current, and off-state leakage current, etc., to characterize its performance. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a process corner detection method, system, device, and storage medium to improve the accuracy of process corner detection.

[0006] To solve the above problems, an embodiment of the present invention provides a process corner detection method for obtaining the worst process corner of an SRAM cell device, where the SRAM cell device includes a pull-up transistor, a pull-down transistor, and a pass gate transistor, including: obtaining electrical property data of a plurality of the SRAM cell devices, and the electrical property data of the pull-up transistor, the pull-down transistor, and the pass gate transistor in the same SRAM cell device form a set of first data groups; establishing a three-dimensional normal distribution model by using multiple sets of the first data groups, and the shape of the three-dimensional normal distribution model is an ellipsoid; extracting multiple sets of data groups to be measured corresponding to the surface positions of the ellipsoid from the first data groups; simulating the multiple sets of data groups to be measured to obtain a plurality of corresponding write noise margins; extracting the data group to be measured corresponding to the minimum value among the plurality of write noise margins as the worst process corner of the write noise margin.

[0007] Accordingly, an embodiment of the present invention further provides a process corner detection system for obtaining the worst process corner of an SRAM cell device. The SRAM cell device includes a pull-up transistor, a pull-down transistor, and a transmission gate transistor, and the system includes: a test module for obtaining electrical property data of a plurality of the SRAM cell devices, and the electrical property data of the pull-up transistor, the pull-down transistor, and the transmission gate transistor in the same SRAM cell device form a set of first data groups; a modeling module for establishing a three-dimensional normal distribution model using multiple sets of the first data groups, and the shape of the three-dimensional normal distribution model is an ellipsoid; a first data extraction module for extracting multiple sets of data groups to be measured corresponding to the surface positions of the ellipsoid from the first data groups; a simulation module for simulating the multiple sets of data groups to be measured to obtain a plurality of corresponding write noise margins; and a second data extraction module for extracting the data group to be measured corresponding to the minimum value among the plurality of write noise margins as the worst process corner of the write noise margin.

[0008] Accordingly, an embodiment of the present invention further provides a device, including at least one memory and at least one processor. The memory stores one or more computer instructions, and wherein the one or more computer instructions are executed by the processor to implement the process corner detection method according to the embodiment of the present invention.

[0009] Accordingly, an embodiment of the present invention further provides a storage medium storing one or more computer instructions for implementing the process corner detection method according to the embodiment of the present invention.

[0010] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0011] An embodiment of the present invention provides a process corner detection method. The detection method uses a set of first data groups formed by the electrical property data of three types of transistors in a plurality of SRAM cell devices to establish a three-dimensional normal distribution model. The shape of the three-dimensional normal distribution model is an ellipsoid. Subsequently, multiple sets of data groups to be measured corresponding to the surface positions of the ellipsoid are extracted from the first data groups, and the multiple sets of data groups to be measured are simulated to obtain a plurality of corresponding write noise margins. Then, the data group to be measured corresponding to the minimum value among the plurality of write noise margins is extracted as the worst process corner of the write noise margin. The embodiment of the present invention performs detection by establishing a three-dimensional normal distribution model to obtain more data, thereby analyzing the worst process corner of the write noise margin of the SRAM cell device while considering the variation of the electrical property data, and further improving the accuracy of the process corner detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1It is a process corner schematic diagram of a MOS transistor;

[0013] Figure 2 It is a flowchart of an embodiment of the process corner detection method of the present invention;

[0014] Figure 3 It is Figure 2 a schematic circuit diagram of an SRAM cell device corresponding to step S1 in

[0015] Figure 4 It is Figure 2 a flowchart of an embodiment of step S2 in

[0016] Figure 5 It is Figure 4 a flowchart of an embodiment of step S23 in

[0017] Figure 6 It is Figure 2 a schematic diagram of a three-dimensional normal distribution model corresponding to step S2 in

[0018] Figure 7 It is Figure 2 a schematic diagram of the surface contour of an ellipsoid corresponding to step S3 in

[0019] Figure 8 It is a functional block diagram of an embodiment of the process corner detection system of the present invention;

[0020] Figure 9 It is Figure 8 a functional block diagram of an embodiment of the modeling module in

[0021] Figure 10 It is Figure 9 a functional block diagram of an embodiment of the model establishment unit in

[0022] Figure 11 It is the hardware structure diagram of the device provided by an embodiment of the present invention. Specific embodiments

[0023] The performance range of MOS transistors is usually given in the form of process corners, which is called the corner model.

[0024] Figure 1 It is a process corner schematic diagram of a MOS transistor. The abscissa represents the threshold voltage of the pull-down transistor (PDVtsat), and the ordinate represents the threshold voltage of the pull-up transistor (PU Vtsat).

[0025] When performing process corner detection on SRAM cell devices, the fluctuation ranges of the electrical property data of NMOS transistors and PMOS transistors are restricted within the region determined by four process corners (i.e., four process critical points): FF (fast NMOS transistor and fast PMOS transistor), FS (fast NMOS transistor and slow PMOS transistor), SF (slow NMOS transistor and fast PMOS transistor), and SS (slow NMOS transistor and slow PMOS transistor). That is to say, for the performance of SRAM cell devices, the data within this region range is acceptable.

[0026] Among them, FF corresponds to the situation where the saturation currents of both the NMOS transistor and the PMOS transistor are at their maximum values, and the threshold voltages are at their minimum values; FS corresponds to the situation where the saturation current of the NMOS transistor is at its maximum value and the threshold voltage is at its minimum value, while the saturation current of the PMOS transistor is at its minimum value and the threshold voltage is at its maximum value; SF corresponds to the situation where the saturation current of the NMOS transistor is at its minimum value and the threshold voltage is at its maximum value, while the saturation current of the PMOS transistor is at its maximum value and the threshold voltage is at its minimum value; SS corresponds to the situation where the saturation currents of both the NMOS transistor and the PMOS transistor are at their minimum values, and the threshold voltages are at their maximum values.

[0027] Among them, in order to obtain the write noise margin of SRAM cell devices, the electrical property data corresponding to each process corner is used to simulate and calculate the maximum and minimum values of the write noise margin. And based on the principle of the write operation of SRAM cell devices, the write noise margin of SRAM cell devices is related to the electrical properties of the pull-up transistor, pull-down transistor, and transmission gate transistor.

[0028] Although the write noise margin of SRAM cell devices is affected by the electrical properties of each MOS transistor, due to the fluctuations in the electrical property data of each MOS transistor, the distribution characteristics of the write noise margin do not have a direct corresponding relationship with the distribution of the electrical properties of MOS transistors.

[0029] For example, as Figure 1 shown, taking the corner model composed of a pull-down transistor and a pull-up transistor as an example, when the write noise margin is the smallest, the NMOS transistor and the PMOS transistor are not at the SF process corner, but at another position (such as Figure 1 the position indicated by arrow A in

[0030] Therefore, the traditional corner model of MOS transistors does not accurately correspond one-to-one with the write noise margin of SRAM cell devices, there are deviations, resulting in relatively low accuracy in the current process corner detection.

[0031] To solve the above technical problems, an embodiment of the present invention provides a process corner detection method for obtaining the worst process corner of an SRAM cell device. The SRAM cell device includes a pull-up transistor, a pull-down transistor, and a transmission gate transistor. The method includes: obtaining electrical property data of a plurality of the SRAM cell devices, and the electrical property data of the pull-up transistor, the pull-down transistor, and the transmission gate transistor in the same SRAM cell device form a set of first data groups; establishing a three-dimensional normal distribution model using the plurality of the first data groups, and the shape of the three-dimensional normal distribution model is an ellipsoid; extracting a plurality of sets of data groups to be measured corresponding to the surface positions of the ellipsoid from the first data groups; simulating the plurality of sets of data groups to be measured to obtain a plurality of corresponding write noise margins; extracting the set of data groups to be measured corresponding to the minimum value among the plurality of write noise margins as the worst process corner of the write noise margin.

[0032] An embodiment of the present invention performs detection by establishing a three-dimensional normal distribution model to obtain more data, so as to analyze the worst process corner of the write noise margin of the SRAM cell device while considering the variation of the electrical property data, thereby improving the accuracy of the process corner detection.

[0033] Reference Figure 2 , which shows a flowchart of an embodiment of the process corner detection method of the present invention. The process corner detection method of this embodiment is used to obtain the worst process corner of an SRAM cell device. The SRAM cell device includes a pull-up transistor, a pull-down transistor, and a transmission gate transistor. The process corner detection method includes the following basic steps:

[0034] Step S1: Obtain electrical property data of a plurality of the SRAM cell devices, and the electrical property data of the pull-up transistor, the pull-down transistor, and the transmission gate transistor in the same SRAM cell device form a set of first data groups;

[0035] Step S2: Establish a three-dimensional normal distribution model using multiple sets of the first data groups, and the shape of the three-dimensional normal distribution model is an ellipsoid;

[0036] Step S3: Extract a plurality of sets of data groups to be measured corresponding to the surface positions of the ellipsoid from the first data groups;

[0037] Step S4: Simulate the plurality of sets of data groups to be measured to obtain a plurality of corresponding write noise margins;

[0038] Step S5: Extract the set of data groups to be measured corresponding to the minimum value among the plurality of write noise margins as the worst process corner of the write noise margin.

[0039] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description will be given of specific embodiments of the present invention with reference to the accompanying drawings.

[0040] Refer to Figure 2 , perform step S1 to obtain electrical property data of multiple said SRAM cell devices, and the electrical property data of the pull-up transistor, pull-down transistor, and transmission gate transistor in the same SRAM cell device form a set of first data groups.

[0041] After obtaining the electrical property data of multiple said SRAM cell devices, multiple sets of first data groups are correspondingly obtained, thus preparing for establishing a three-dimensional normal distribution model later.

[0042] In this embodiment, the SRAM cell device is a 6T SRAM cell device.

[0043] Combined with reference Figure 3 , a schematic circuit structure diagram of the SRAM cell device is shown. The SRAM cell device includes six transistors, namely a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4.

[0044] The drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1, the gate of the first PMOS transistor P1 is connected to the gate of the first NMOS transistor N1, and the first PMOS transistor P1 and the first NMOS transistor N1 form a first CMOS transistor 101.

[0045] The drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, the gate of the second PMOS transistor P2 is connected to the gate of the second NMOS transistor N2, and the second PMOS transistor P2 and the second NMOS transistor N2 form a second CMOS transistor 102.

[0046] The input end of the first CMOS transistor 101 is connected to the output end of the second CMOS transistor 102, and the output end of the first CMOS transistor 101 is connected to the input end of the second CMOS transistor 102.

[0047] The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are both connected to the power supply voltage Vdd, and the sources of the first NMOS transistor N1 and the second NMOS transistor N2 are both connected to the power supply voltage Vss.

[0048] The source of the third NMOS transistor N3 is connected to the bit line BL, the drain is connected to the drain of the first PMOS transistor P1, and the gate is connected to the word line WL; the source of the fourth NMOS transistor N4 is connected to the drain of the second PMOS transistor, the gate is connected to the word line WL, and the drain is connected to another bit line BLB.

[0049] In the SRAM cell device, the first PMOS transistor P1 and the second PMOS transistor P2 serve as pull-up transistors, the first NMOS transistor N1 and the second NMOS transistor N2 serve as pull-down transistors, and the third NMOS transistor N3 and the fourth NMOS transistor N4 serve as transmission gate transistors.

[0050] Subsequently, by simulating the electrical data of each SRAM cell device, the key performance of the SRAM cell device can be obtained.

[0051] In this embodiment, the process corner detection method is used to detect the write noise margin of the SRAM cell device.

[0052] Specifically, the process corner detection method is used to detect the worst process corner of the SRAM cell device when the write noise margin is at its minimum value.

[0053] Therefore, the electrical data is related to the write noise margin of the SRAM cell device. The electrical data includes the threshold voltage, saturation current, or linear region current, and the electrical data types of the pull-up transistor, pull-down transistor, and transmission gate transistor are the same.

[0054] In this embodiment, the electrical data is the threshold voltage. By selecting the threshold voltage, it is easy to perform data calculations when establishing a three-dimensional normal distribution model.

[0055] Continue to refer to Figure 2 , perform step S2, and establish a three-dimensional normal distribution model using multiple sets of the first data group. The shape of the three-dimensional normal distribution model is an ellipsoid.

[0056] Compared with the traditional MOS transistor corner model, in this embodiment, a three-dimensional normal distribution model is established to obtain more data, so as to analyze the worst process corner of the write noise margin of the SRAM cell device while taking into account the variation of the electrical data, thereby improving the accuracy of the process corner detection.

[0057] Combined with reference to Figure 4 , Figure 4 is Figure 2 a flowchart of an embodiment of step S2 in

[0058] The steps of establishing a three-dimensional normal distribution model using multiple sets of the first data group include:

[0059] Step S21: For the multiple SRAM cell devices, calculate the average value and standard deviation of the electrical property data of the pull-up transistor, pull-down transistor, and transmission gate transistor respectively.

[0060] Step S22: For each of the SRAM cell devices, use the average value and standard deviation of the electrical property data to calculate the deviation degree values of the electrical property data of the pull-up transistor, pull-down transistor, and transmission gate transistor respectively. The deviation degree value is the ratio of the deviation amount of the electrical property data relative to the average value to the standard deviation.

[0061] Step S23: Use the deviation degree values to establish the three-dimensional normal distribution model.

[0062] In step S21, through statistical analysis of the electrical property data, the average value and standard deviation of the electrical property data corresponding to each transistor are calculated.

[0063] It should be noted that the electrical property data usually has fluctuations, that is, the electrical property data corresponding to each transistor usually has a probability distribution approximately normal. For example, about 68.4% of the values are distributed within the range of 1 standard deviation from the average value of the electrical property data, about 95.4% of the values are distributed within the range of 2 standard deviations from the average value of the electrical property data, and about 99.7% of the values are distributed within the range of 3 standard deviations from the average value of the electrical property data. This has been widely known as the "empirical rule".

[0064] Therefore, after obtaining the average value and standard deviation of the electrical property data corresponding to each transistor, step S22 is executed to calculate the deviation degree values of the electrical property data of the pull-up transistor, pull-down transistor, and transmission gate transistor respectively.

[0065] The deviation degree value is the ratio of the deviation amount of the electrical property data relative to the average value to the standard deviation, that is, the difference between the electrical property data of any transistor and the average value of the electrical property data is represented by the standard deviation. For example, if the deviation degree value of the electrical property data of any transistor is 1 standard deviation, it means that the difference between the electrical property data of this transistor and the average value of the electrical property data is the value corresponding to 1 standard deviation.

[0066] In this embodiment, for any type of transistor in each of the SRAM cell devices, the deviation degree value is calculated using formula (Ⅰ).

[0067]

[0068] where VT_SIGMA is the deviation degree value of any type of transistor in each of the SRAM cell devices, and Vtsat is the electrical property data of any type of transistor in each of the SRAM cell devices. is the average value of the electrical property data of transistors of the same type in the multiple SRAM cell devices, and σ is the standard deviation of the electrical property data of transistors of the same type in the multiple SRAM cell devices.

[0069] For example, for any SRAM cell device, the average value and standard deviation of the electrical property data of the pull-up transistor are calculated using formula (Ⅰ) to obtain the offset degree value of the pull-up transistor; the average value and standard deviation of the electrical property data of the pull-down transistor are calculated using formula (Ⅰ) to obtain the offset degree value of the pull-down transistor; the average value and standard deviation of the electrical property data of the transmission gate transistor are calculated using formula (Ⅰ) to obtain the offset degree value of the transmission gate transistor.

[0070] In this embodiment, the offset degree values of the pull-up transistor, the pull-down transistor, and the transmission gate transistor in the same SRAM cell device form a set of second data groups.

[0071] By obtaining the second data groups, it is prepared for establishing a three-dimensional space coordinate system subsequently. Among them, the three-dimensional normal distribution model established subsequently is located in the three-dimensional space coordinate system.

[0072] For example, when establishing the three-dimensional space coordinate system corresponding to the three-dimensional normal distribution model, the offset degree value of the transmission gate transistor can be used as the X-axis, the offset degree value of the pull-down transistor can be used as the Y-axis, and the offset degree value of the pull-up transistor can be used as the Z-axis.

[0073] It should be noted that the number of the SRAM cell devices is multiple, so the number of the second data groups is multiple. The multiple sets of second data groups are used to form a database, and subsequently, according to actual needs, the offset degree values within a preset distribution interval can be selected from the database as the modeling data groups for establishing a three-dimensional normal distribution model.

[0074] Therefore, after calculating the offset degree values of the electrical property data of the pull-up transistor, the pull-down transistor, and the transmission gate transistor respectively, step S23 can be executed, and the three-dimensional normal distribution model is established using the offset degree values.

[0075] Using the offset degree values to establish the three-dimensional normal distribution model, it is possible to, according to actual needs, by determining the preset distribution interval of the offset degree values, use the data included in the preset distribution interval to establish the three-dimensional normal distribution model, thereby adjusting the amount of data included in the three-dimensional normal distribution model, which improves the flexibility of the detection method.

[0076] Combined with reference Figure 5 , Figure 5 is Figure 4Flowchart of an embodiment of step S23

[0077] In this embodiment, the steps of establishing the three-dimensional normal distribution model by using the offset degree value include:

[0078] Step S231: Determine the preset distribution interval of the offset degree value;

[0079] Step S232: According to the preset distribution interval, screen out multiple data groups for modeling from the multiple groups of second data groups;

[0080] Step S233: Use the data groups for modeling of the same SRAM cell device as vectors to establish a correlation coefficient matrix;

[0081] Step S234: Use the correlation coefficient matrix to establish a three-dimensional normal distribution model.

[0082] By executing step S231, the preset distribution interval is determined.

[0083] Among them, the shape of the subsequently established three-dimensional normal distribution model is an ellipsoid, and the preset distribution interval is used to determine the size R_SIGMA of the ellipsoid. Correspondingly, the preset distribution interval determines the amount of data included in the three-dimensional normal distribution model.

[0084] The preset distribution interval is determined according to actual needs. The larger the range of the preset distribution interval, the larger the amount of data included in the three-dimensional normal distribution model.

[0085] The range of the preset distribution interval should not be too small or too large. If the range of the preset distribution interval is too small, the amount of data included in the three-dimensional normal distribution model will be too small, and it will be difficult to accurately obtain the minimum value of the write noise margin through the three-dimensional normal distribution model subsequently; when the preset distribution interval increases to a certain range, it is also difficult to cover more data. That is to say, most of the electrical property data is within a reasonable preset distribution interval. Therefore, in this embodiment, the preset distribution interval is (-n*σ, +n*σ), the value of n is 3 to 6, and σ is the standard deviation of the electrical property parameter data of the transistors of the same type among the multiple SRAM cell devices. Correspondingly, the size R_SIGMA of the ellipsoid is n*σ.

[0086] After determining the preset distribution interval, execute step S232, and screen out multiple data groups for modeling from the multiple groups of second data groups according to the preset distribution interval.

[0087] The multiple second data groups are complete data. By screening out multiple data groups for modeling from the multiple groups of second data groups, the dimensions of the ellipsoid corresponding to the three-dimensional normal distribution model are determined, which improves the flexibility of the detection method.

[0088] According to the preset distribution interval, after screening out multiple data groups for modeling from the multiple groups of second data groups, step S233 is executed. Using the data groups for modeling of the same SRAM cell device as vectors, a matrix is established.

[0089] The data groups for modeling of each SRAM cell device form a vector, and the number of SRAM cell devices is multiple. Therefore, the matrix includes multiple vectors. The matrix is prepared for establishing the three-dimensional normal distribution model subsequently. The vector corresponding to each SRAM cell device is used to determine its specific position in the three-dimensional space coordinate system, so that a three-dimensional normal distribution model of the 3D shape can be established through multiple SRAM cell devices.

[0090] After establishing the correlation coefficient matrix using the data groups for modeling of the same SRAM cell device as vectors, step S234 is executed: using the correlation coefficient matrix, a three-dimensional normal distribution model is established.

[0091] In this embodiment, the three-dimensional normal distribution model is established using formula (Ⅱ).

[0092]

[0093] Among them, f(Y) is the probability of the offset degree value of any one of the transistors of the same type among the multiple SRAM cell devices, Y is the vector coordinate of the offset degree values of the pull-up transistor, pull-down transistor, and transmission gate transistor in any one of the SRAM cell devices, S is the correlation coefficient matrix of the electrical property data of any one of the SRAM cell devices, and Y' is the transpose of the vector coordinate.

[0094] Figure 6 It is a schematic diagram of the three-dimensional normal distribution model described in this embodiment.

[0095] As Figure 6 shown, in the three-dimensional space coordinate system corresponding to the three-dimensional normal distribution model, the X-axis represents the offset degree value (PG VT_SIGMA) of the transmission gate transistor, the Y-axis represents the offset degree value (PDVT_SIGMA) of the pull-down transistor, and the Z-axis represents the offset degree value (PU VT_SIGMA) of the pull-up transistor. Among them, Figure 5 each point in corresponds to an SRAM cell device, and the darker the color area, the more data is located within the range of that area.

[0096] In this embodiment, the shape of the three-dimensional normal distribution model is an ellipsoid.

[0097] Refer to Figure 5 , perform step S3 to extract multiple groups of data sets to be measured corresponding to the surface position of the ellipsoid from the first data set.

[0098] Generally, the greater the offset degree value of the electrical property data, the smaller the write noise margin. Therefore, by extracting multiple groups of data sets to be measured corresponding to the surface position of the ellipsoid from the first data set, it prepares for obtaining the worst process angle of the write noise margin subsequently.

[0099] In this embodiment, the surface of the ellipsoid is determined by using the lower limit value and the upper limit value of the preset distribution interval. Specifically, the electrical property data corresponding to the surface of the ellipsoid is determined by using formula (Ⅲ),

[0100] Y'×S -1 ×Y=R_SIGMA 2 (Ⅲ)

[0101] wherein, when the size R_SIGMA of the ellipsoid is determined, the electrical property data corresponding to the surface of the ellipsoid can be obtained.

[0102] As Figure 7 shown, Figure 7 is a schematic diagram of the surface contour of the ellipsoid in this embodiment.

[0103] Continue to refer to Figure 2 , perform step S4 to simulate the multiple groups of data sets to be measured to obtain multiple corresponding write noise margins.

[0104] Specifically, the multiple groups of data sets to be measured can be respectively simulated through a simulation program. For example, SPICE simulation programs such as "Synopsys HSPICE" or "Cadence Spectre" can be used. Simulating by using the above simulation program is a known technology in the industry, and this embodiment will not elaborate on this step.

[0105] Continue to refer to Figure 2 , perform step S5 to extract the data set to be measured corresponding to the minimum value among the multiple write noise margins as the worst process angle of the write noise margin.

[0106] Each group of data sets to be measured corresponds to the electrical property data of the pull-up transistor, pull-down transistor, and transmission gate transistor in an SRAM cell device. Therefore, by extracting the data set to be measured corresponding to the minimum value among the multiple write noise margins, the electrical property data of the three transistors corresponding to the minimum value of the write noise margin can be obtained, and the electrical property data of these three transistors is the worst process angle.

[0107] Correspondingly, the present invention further provides a process corner detection system. Refer to Figure 8 , which shows a functional block diagram of an embodiment of the process corner detection system of the present invention.

[0108] The process corner detection system is used to obtain the worst process corner of the SRAM cell device, and the SRAM cell device includes a pull-up transistor, a pull-down transistor, and a transmission gate transistor.

[0109] Refer to Figure 9 , the process corner detection system includes: a test module 50, configured to obtain electrical property data of a plurality of the SRAM cell devices, and the electrical property data of the pull-up transistor, the pull-down transistor, and the transmission gate transistor in the same SRAM cell device form a set of first data groups; a modeling module 60, configured to establish a three-dimensional normal distribution model by using multiple sets of the first data groups, and the shape of the three-dimensional normal distribution model is an ellipsoid; a first data extraction module 70, configured to extract multiple sets of data groups to be measured corresponding to the surface positions of the ellipsoid from the first data groups; a simulation module 80, configured to simulate the multiple sets of data groups to be measured to obtain multiple corresponding write noise margins; a second data extraction module 90, configured to extract the data group to be measured corresponding to the minimum value among the multiple write noise margins as the worst process corner of the write noise margin.

[0110] The test module 50 is configured to obtain electrical property data of a plurality of the SRAM cell devices. After obtaining the electrical property data of the plurality of SRAM cell devices, multiple sets of first data groups are correspondingly obtained, thereby preparing for establishing a three-dimensional normal distribution model subsequently.

[0111] In this embodiment, the SRAM cell device is a 6T SRAM cell device. Combining with reference to Figure 3 , which shows a schematic circuit structure diagram of the SRAM cell device, the SRAM cell device includes 6 transistors, which are a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4 respectively.

[0112] The drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1, the gate of the first PMOS transistor P1 is connected to the gate of the first NMOS transistor N1, and the first PMOS transistor P1 and the first NMOS transistor N1 form a first CMOS transistor 101.

[0113] The drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, the gate of the second PMOS transistor P2 is connected to the gate of the second NMOS transistor N2, and the second PMOS transistor P2 and the second NMOS transistor N2 form a second CMOS transistor 102.

[0114] The input terminal of the first CMOS transistor 101 is connected to the output terminal of the second CMOS transistor 102, and the output terminal of the first CMOS transistor 101 is connected to the input terminal of the second CMOS transistor 102.

[0115] The sources of the first PMOS transistor P1 and the second PMOS transistor P2 are both connected to the power supply voltage Vdd, and the sources of the first NMOS transistor N1 and the second NMOS transistor N2 are both connected to the power supply voltage Vss.

[0116] The source of the third NMOS transistor N3 is connected to the bit line BL, the drain is connected to the drain of the first PMOS transistor P1, and the gate is connected to the word line WL; the source of the fourth NMOS transistor N4 is connected to the drain of the second PMOS transistor, the gate is connected to the word line WL, and the drain is connected to another bit line BLB.

[0117] In the SRAM cell device, the first PMOS transistor P1 and the second PMOS transistor P2 serve as pull-up transistors, the first NMOS transistor N1 and the second NMOS transistor N2 serve as pull-down transistors, and the third NMOS transistor N3 and the fourth NMOS transistor N4 serve as transmission gate transistors.

[0118] Subsequently, the electrical data of each SRAM cell device is simulated by the simulation module 80, so as to obtain the key performance of the SRAM cell device.

[0119] In this embodiment, the process corner detection method is used to detect the write noise margin of the SRAM cell device. Specifically, the process corner detection method is used to detect the worst process corner when the write noise margin of the SRAM cell device is at its minimum value.

[0120] Therefore, the test module 50 is used to test and obtain electrical data related to the write noise margin of the SRAM cell device, such as the threshold voltage, saturation current or linear region current, and the electrical data types of the pull-up transistor, pull-down transistor and transmission gate transistor are the same.

[0121] In this embodiment, the test module 50 is used to obtain the threshold voltage. By selecting the threshold voltage, it is easy to perform data calculation when establishing a three-dimensional normal distribution model.

[0122] The modeling module 60 is used to establish a three-dimensional normal distribution model by using multiple groups of the first data groups, and the shape of the three-dimensional normal distribution model is an ellipsoid.

[0123] Compared with the corner model of the traditional MOS transistor, in this embodiment, a three-dimensional normal distribution model is established to obtain more data, so as to analyze the worst process corner of the write noise margin of the SRAM cell device while taking into account the variation of the electrical property data, thereby improving the accuracy of the process corner detection.

[0124] As Figure 9 shown, Figure 9 is Figure 8 a functional block diagram of an embodiment of the modeling module 60. In this embodiment, the modeling module 60 includes: a first calculation unit 61, configured to calculate the average value and standard deviation of the electrical property data of the pull-up transistor, pull-down transistor, and transmission gate transistor for each of the multiple SRAM cell devices; a second calculation unit 62, configured to calculate, for each of the SRAM cell devices, the deviation degree values of the electrical property data of the pull-up transistor, pull-down transistor, and transmission gate transistor by using the average value and standard deviation of the electrical property data, where the deviation degree value is the ratio of the deviation amount of the electrical property data relative to the average value to the standard deviation; and a model establishment unit 63, configured to establish the three-dimensional normal distribution model by using the deviation degree values.

[0125] The first calculation unit 61 is configured to perform statistical analysis on the electrical property data and calculate the average value and standard deviation of the electrical property data corresponding to each transistor.

[0126] It should be noted that the electrical property data usually has variations, that is, the electrical property data corresponding to each transistor usually has a probability distribution approximately normal. For example, about 68.4% of the values are distributed within the range of 1 standard deviation from the average value of the electrical property data, about 95.4% of the values are distributed within the range of 2 standard deviations from the average value of the electrical property data, and about 99.7% of the values are distributed within the range of 3 standard deviations from the average value of the electrical property data, which has been widely known as the "empirical rule".

[0127] Therefore, after obtaining the average value and standard deviation of the electrical property data corresponding to each transistor, the second calculation unit 62 is used to calculate the deviation degree values of the electrical property data of the pull-up transistor, pull-down transistor, and transmission gate transistor respectively.

[0128] The offset degree value is the ratio of the offset of the electrical property data relative to the average value to the standard deviation. That is, the difference between the electrical property data of any transistor and the average value of the electrical property data is represented by the standard deviation. For example, if the offset degree value of the electrical property data of any transistor is 1 standard deviation, it means that the difference between the electrical property data of this transistor and the average value of the electrical property data is the value corresponding to 1 standard deviation.

[0129] In this embodiment, the second calculation unit 62 calculates the offset degree value by using formula (Ⅰ).

[0130]

[0131] Wherein, VT_SIGMA is the offset degree value of any type of transistor in each SRAM cell device, Vtsat is the electrical property data of any type of transistor in each SRAM cell device. is the average value of the electrical property data of the same type of transistors in the multiple SRAM cell devices, and σ is the standard deviation of the electrical property data of the same type of transistors in the multiple SRAM cell devices.

[0132] For example, for any SRAM cell device, the second calculation unit 62 uses formula (Ⅰ) to operate on the average value and the standard deviation of the electrical property data of the pull-up transistor to obtain the offset degree value of the pull-up transistor, uses formula (Ⅰ) to operate on the average value and the standard deviation of the electrical property data of the pull-down transistor to obtain the offset degree value of the pull-down transistor, and uses formula (Ⅰ) to operate on the average value and the standard deviation of the electrical property data of the transmission gate transistor to obtain the offset degree value of the transmission gate transistor.

[0133] In this embodiment, the offset degree values of the pull-up transistor, the pull-down transistor, and the transmission gate transistor in the same SRAM cell device form a second data set.

[0134] By obtaining the second data set, it is thus prepared for establishing a three-dimensional space coordinate system subsequently. Among them, the three-dimensional normal distribution model established subsequently is located in the three-dimensional space coordinate system.

[0135] For example, when establishing the three-dimensional space coordinate system corresponding to the three-dimensional normal distribution model, the offset degree value of the transmission gate transistor can be used as the X-axis, the offset degree value of the pull-down transistor can be used as the Y-axis, and the offset degree value of the pull-up transistor can be used as the Z-axis.

[0136] It should be noted that the number of the SRAM cell devices is multiple, and thus the number of the second data groups is multiple. The multiple second data groups are used to form a database, and subsequently, according to actual requirements, an offset degree value within a preset distribution range can be selected from the database as a data group for modeling to establish a three-dimensional normal distribution model.

[0137] Therefore, after the second calculation unit 62 calculates the offset degree values of the electrical property data of the pull-up transistor, pull-down transistor, and transmission gate transistor respectively, the three-dimensional normal distribution model can be established by the model establishment unit 63.

[0138] The model establishment unit 63 uses the offset degree values to establish the three-dimensional normal distribution model. Thus, according to actual requirements, by determining the preset distribution range of the offset degree values, the data included in the preset distribution range is used to establish the three-dimensional normal distribution model, thereby adjusting the amount of data included in the three-dimensional normal distribution model, which improves the detection flexibility of the detection system.

[0139] As Figure 10 shown, Figure 10 is Figure 9 a functional block diagram of an embodiment of the model establishment unit 63. In this embodiment, the model establishment unit 63 includes: an interval selection subunit 631 for determining the preset distribution range of the offset degree values; a screening subunit 632 for screening out multiple data groups for modeling from the multiple second data groups according to the preset distribution range; a matrix establishment subunit 633 for establishing a correlation coefficient matrix with the data groups for modeling of the same SRAM cell device as vectors; and a model establishment subunit 634 for establishing a three-dimensional normal distribution model using the correlation coefficient matrix.

[0140] The shape of the three-dimensional normal distribution model is an ellipsoid. The interval selection subunit 631 determines the size of the ellipsoid. Correspondingly, the preset distribution range determines the amount of data included in the three-dimensional normal distribution model. The preset distribution range is determined according to actual requirements. The larger the preset distribution range, the larger the amount of data included in the three-dimensional normal distribution model.

[0141] The multiple second data groups are complete data. The screening subunit 632 screens out multiple data groups for modeling from the multiple second data groups, thereby determining the size of the ellipsoid corresponding to the three-dimensional normal distribution model.

[0142] The data set for modeling each SRAM cell device constitutes a vector, and the number of SRAM cell devices is multiple. Therefore, the matrix includes multiple vectors. The vector corresponding to each SRAM cell device is used to determine its specific position in the three-dimensional space coordinate system, so that a three-dimensional normal distribution model of the 3D shape can be established through multiple SRAM cell devices.

[0143] In this embodiment, the model establishment subunit 634 establishes a three-dimensional normal distribution model using formula (Ⅱ).

[0144] Where f(Y) is the probability of the offset degree value of any one of the transistors of the same type among the multiple SRAM cell devices, Y is the vector coordinate of the offset degree values of the pull-up transistor, pull-down transistor, and transmission gate transistor in any one of the SRAM cell devices, S is the correlation coefficient matrix of the electrical data of any one of the SRAM cell devices, and Y' is the transpose of the vector coordinate.

[0145] As Figure 6 shown, Figure 6 is a schematic diagram of the three-dimensional normal distribution model of this embodiment. In the three-dimensional space coordinate system corresponding to the three-dimensional normal distribution model, the X-axis represents the offset degree value (PG VT_SIGMA) of the transmission gate transistor, the Y-axis represents the offset degree value (PD VT_SIGMA) of the pull-down transistor, and the Z-axis represents the offset degree value (PU VT_SIGMA) of the pull-up transistor. Among them, Figure 5 each point in corresponds to an SRAM cell device, and the darker the color area, the more data is located within the range of that area.

[0146] In this embodiment, the shape of the three-dimensional normal distribution model is an ellipsoid.

[0147] Continuing to refer to Figure 8 the first data extraction module 70 is used to extract multiple groups of data sets to be measured corresponding to the surface position of the ellipsoid from the first data set.

[0148] Generally, the greater the offset degree value of the electrical data, the smaller the write noise margin. Therefore, by extracting multiple groups of data sets to be measured corresponding to the surface position of the ellipsoid from the first data set, it prepares for obtaining the worst process corner of the write noise margin subsequently.

[0149] In this embodiment, the first data extraction module 70 determines the surface of the ellipsoid using the lower limit value and upper limit value of the preset distribution interval.

[0150] Specifically, the first data extraction module 70 determines the electrical data corresponding to the surface of the ellipsoid by using formula (Ⅲ).

[0151] Y'×S -1 ×Y=R_SIGMA 2 (Ⅲ)

[0152] Wherein, when the size R_SIGMA of the ellipsoid is determined, the electrical data corresponding to the surface of the ellipsoid can be obtained.

[0153] As Figure 7 shown Figure 7 is a schematic diagram of the surface contour of the ellipsoid in this embodiment.

[0154] Continuing to refer to Figure 8 , the simulation module 80 is used to simulate the multiple groups of data to be measured, and obtain multiple corresponding write noise margins.

[0155] Specifically, the simulation module 80 respectively simulates the multiple groups of data to be measured through a simulation program. For example, SPICE simulation programs such as "Synopsys HSPICE" or "Cadence Spectre" can be used.

[0156] Continuing to refer to Figure 8 , the second data extraction module 90 is used to extract the group of data to be measured corresponding to the minimum value among the multiple write noise margins as the worst process corner of the write noise margin.

[0157] Each group of data to be measured corresponds to the electrical data of the pull-up transistor, pull-down transistor and transmission gate transistor in an SRAM cell device. Therefore, by extracting the group of data to be measured corresponding to the minimum value among the multiple write noise margins, the electrical data of the three transistors corresponding to the minimum value of the write noise margin can be obtained, and the electrical data of these three transistors are the worst process corners.

[0158] An embodiment of the present invention further provides a device, which can implement the preprocessing method provided by the embodiment of the present invention by loading the above preprocessing method in the form of a program.

[0159] Referring to Figure 11 , a hardware structure diagram of the device provided by an embodiment of the present invention is shown. The device in this embodiment includes: at least one processor 01, at least one communication interface 02, at least one memory 03 and at least one communication bus 04.

[0160] In this embodiment, the number of the processor 01, the communication interface 02, the memory 03 and the communication bus 04 is at least one, and the processor 01, the communication interface 02 and the memory 03 complete the communication with each other through the communication bus 04.

[0161] The communication interface 02 may be an interface of a communication module for network communication, for example, an interface of a GSM module.

[0162] The processor 01 may be a central processing unit CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the process corner detection method described in this embodiment.

[0163] The memory 03 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory.

[0164] Among them, the memory 03 stores one or more computer instructions, and the one or more computer instructions are executed by the processor 01 to implement the process corner detection method provided in the foregoing embodiment.

[0165] It should be noted that the above implementation terminal device may further include other devices (not shown) that may not be necessary for the disclosure of the embodiments of the present invention; in view of the fact that these other devices may not be necessary for understanding the disclosure of the embodiments of the present invention, the embodiments of the present invention do not introduce them one by one.

[0166] The embodiment of the present invention further provides a storage medium, and the storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the process corner detection method provided in the foregoing embodiment.

[0167] In the embodiment of the present invention, the process corner detection method is performed by establishing a three-dimensional normal distribution model to obtain more data, so as to analyze the worst process corner of the write noise margin of the SRAM cell device considering the variation of the electrical data, thereby improving the accuracy of the process corner detection.

[0168] The above-described embodiments of the present invention are combinations of elements and features of the present invention. Unless otherwise mentioned, the elements or features may be considered optional. Each element or feature may be practiced without combination with other elements or features. Additionally, embodiments of the present invention may be constructed by combining some of the elements and / or features. The operation sequences described in the embodiments of the present invention may be rearranged. Some configurations of any one embodiment may be included in another embodiment and replaced with corresponding configurations of another embodiment. It is obvious to those skilled in the art that claims that do not have an explicit citation relationship with each other in the appended claims may be combined into embodiments of the present invention or included as new claims in amendments after the filing of this application.

[0169] Embodiments of the present invention can be implemented by various means such as hardware, firmware, software, or combinations thereof. In a hardware configuration, the method according to an exemplary embodiment of the present invention can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, etc.

[0170] In a firmware or software configuration, embodiments of the present invention can be implemented in the form of modules, procedures, functions, etc. The software code can be stored in a memory unit and executed by a processor. The memory unit is located inside or outside the processor and can send data to and receive data from the processor via various known means.

[0171] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

[0172] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A process angle detection method for obtaining the worst process angle of an SRAM unit device, wherein the SRAM unit device includes a pull-up transistor, a pull-down transistor and a transmission gate transistor, characterized in that: include: Acquire electrical property data of a plurality of the SRAM unit devices, wherein the electrical property data of the pull-up transistor, the pull-down transistor and the transmission gate transistor in the same SRAM unit device constitute a first data group; A three-dimensional normal distribution model is established using multiple groups of the first data groups, and the shape of the three-dimensional normal distribution model is an ellipsoid. The steps of establishing the three-dimensional normal distribution model using multiple groups of the first data groups include: for the multiple SRAM unit devices, respectively calculating the average value and standard deviation of the electrical data of the pull-up transistor, the pull-down transistor and the transfer gate transistor; for each of the SRAM unit devices, respectively calculating the offset value of the electrical data of the pull-up transistor, the pull-down transistor and the transfer gate transistor using the average value and standard deviation of the electrical data, the offset value being the ratio of the offset of the electrical data relative to the average value to the standard deviation; and establishing the three-dimensional normal distribution model using the offset value; Extracting a plurality of groups of data to be measured corresponding to the surface positions of the ellipsoid from the first data group; Simulating the plurality of groups of data to be tested to obtain a plurality of corresponding write noise tolerances; A data group to be tested corresponding to a minimum value among the multiple write noise margins is extracted as the worst process angle of the write noise margin.

2. The process angle detection method according to claim 1, characterized in that: The SRAM cell device is a 6T SRAM cell device.

3. The process angle detection method according to claim 1, characterized in that: In the step of acquiring electrical data of the plurality of SRAM cell devices, the electrical data includes threshold voltage, saturation current or linear region current, and the electrical data types of the pull-up transistor, the pull-down transistor and the transfer gate transistor are the same.

4. The process angle detection method according to claim 1, characterized in that: In the step of respectively calculating the offset values ​​of the electrical property data of the pull-up transistor, the pull-down transistor and the transfer gate transistor, the offset values ​​of the pull-up transistor, the pull-down transistor and the transfer gate transistor in the same SRAM unit device constitute a second data group; The step of establishing the three-dimensional normal distribution model by using the deviation degree value comprises: Determine a preset distribution interval of the offset degree value; According to the preset distribution interval, selecting a plurality of data groups for modeling from the plurality of second data groups; Using the modeling data set of the same SRAM unit device as a vector, a correlation coefficient matrix is ​​established; A three-dimensional normal distribution model is established using the correlation coefficient matrix.

5. The process angle detection method according to claim 3, characterized in that: For each transistor of any type in the SRAM cell device, the offset value is calculated using formula (I), Wherein, VT_SIGMA is the offset value of any type of transistor in each of the SRAM unit devices, Vtsat is the electrical property data of any type of transistor in each of the SRAM unit devices, is the average value of the electrical property data of the transistors of the same type in the plurality of SRAM unit devices, and σ is the standard deviation of the electrical property data of the transistors of the same type in the plurality of SRAM unit devices.

6. The process angle detection method according to claim 4, characterized in that: The three-dimensional normal distribution model is established using formula (II), Among them, f(Y) is the probability of any offset value of the same type of transistors in the multiple SRAM unit devices, Y is the vector coordinates of the offset values ​​of the pull-up transistor, the pull-down transistor and the transfer gate transistor in any of the SRAM unit devices, S is the correlation coefficient matrix of the electrical data of any of the SRAM unit devices, and Y' is the transpose of the vector coordinates.

7. The process angle detection method according to claim 4, characterized in that: The preset distribution interval is (-n*σ, +n*σ), the value of n is 3 to 6, and σ is the standard deviation of the electrical parameter data of transistors of the same type in the multiple SRAM unit devices.

8. The process angle detection method according to claim 4, characterized in that: The surface position of the ellipsoid is determined using the lower limit value and the upper limit value of the preset distribution interval.

9. A process angle detection system for obtaining the worst process angle of an SRAM unit device, wherein the SRAM unit device includes a pull-up transistor, a pull-down transistor and a transmission gate transistor, characterized in that: include: A test module, used for acquiring electrical data of a plurality of the SRAM unit devices, wherein the electrical data of the pull-up transistor, the pull-down transistor and the transmission gate transistor in the same SRAM unit device constitute a first data group; A modeling module, used to establish a three-dimensional normal distribution model using multiple groups of the first data groups, wherein the shape of the three-dimensional normal distribution model is an ellipsoid, and the modeling module includes: a first calculation unit, used to calculate the average value and standard deviation of the electrical data of the pull-up transistor, the pull-down transistor and the transfer gate transistor for the multiple SRAM unit devices; a second calculation unit, used to calculate the offset value of the electrical data of the pull-up transistor, the pull-down transistor and the transfer gate transistor for each of the SRAM unit devices using the average value and standard deviation of the electrical data, wherein the offset value is the ratio of the offset of the electrical data relative to the average value to the standard deviation; a model building unit, used to establish the three-dimensional normal distribution model using the offset value; A first data extraction module, used for extracting a plurality of groups of to-be-tested data groups corresponding to the surface positions of the ellipsoid from the first data group; A simulation module, used for simulating the plurality of groups of data to be tested to obtain a plurality of corresponding write noise tolerances; The second data extraction module is used to extract the test data group corresponding to the minimum value of the multiple write noise tolerances as the worst process angle of the write noise tolerance.

10. A device, characterized in that: The invention comprises at least one memory and at least one processor, wherein the memory stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the process angle detection method according to any one of claims 1 to 8.

11. A storage medium, characterized in that: The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the process angle detection method according to any one of claims 1 to 8.

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