Switch-mode power supply including three-stage LLC circuit

Abstract

The present invention relates to a switch mode power supply including a three-level LLC circuit, the switch mode power supply including: a pair of input terminals, a pair of output terminals and at least four switches, the at least four switches are connected in a three-level LLC circuit arrangement between the pair of input terminals and the pair of output terminals. The first switch and the second switch of the at least four switches define a first half bridge, and the third switch and the fourth switch of the at least four switches define a second half bridge. The switch mode power supply also includes a fifth switch and a control circuit, the fifth switch is connected across the second switch and the third switch to short-circuit the second switch and the third switch when the fifth switch is closed, the control circuit includes a voltage controlled oscillator (VCO) and a plurality of logic gates and a plurality of flip-flops, the voltage controlled oscillator (VCO) and the plurality of logic gates and the plurality of flip-flops are connected to operate the at least four switches using zero voltage switching (ZVS).

Description

Technical Field

[0001] The present invention relates to a switched mode power supply comprising a three-level LLC circuit. Background Art

[0002] This section provides background information related to the present disclosure which is not necessarily prior art.

[0003] A switch-mode power supply with a three-phase input can use a Vienna rectifier topology to implement an efficient front-end Power Factor Correction (PFC) circuit, but the output voltage of the PFC can be around 800V, which can make the design of a downstream DC-DC converter difficult. Conventional high-efficiency half-bridge LLC converters or full-bridge LLC converters typically require 1200V-rated devices for switching, but 1200V-rated Si devices may not be very efficient at medium and high switching frequencies. A three-level LLC topology can be used with 600V-650V-rated devices, using asymmetric control to achieve a high step-down ratio with a relatively low transformer primary to transformer secondary ratio.

[0004] Figure 1 An exemplary power supply 100 including a three-level LLC topology is shown. The power supply 100 receives a voltage input of 800V from an input power source 800. Switches Q2 and Q3 define a first half-bridge coupled to capacitor C6, and switches Q1 and Q4 define a second half-bridge coupled to capacitor C7. Switch Q2 is driven by control signal AA via isolation driver E9 and resistors R34 and R38, switch Q3 is driven by control signal BB2 via isolation driver E8 and resistors R27 and R28, switch Q4 is driven by control signal AA2 via isolation driver E10 and resistors R35 and R37, and switch Q1 is driven by control signal BB via isolation driver E7 and resistors R29 and R32.

[0005] The power supply further includes a transformer TX1 including a primary winding P1 and a secondary winding S1. A capacitor C1 and an inductor L5 are connected between the primary winding P1 and switches Q2 and Q3, and a capacitor C2 and an inductor L1 are connected between the primary winding P1 and switches Q1 and Q4. The power supply 100 further includes four diodes D1, D2, D9 and D10 connected to the secondary winding S1, and a capacitor C10 and a load RLOAD connected to the output terminal Vout.

[0006] Figure 21 shows exemplary current waveforms through switches Q1, Q2, Q3, and Q4 during operation of power supply 100. Figure 2 As shown, the RMS current through switch Q3 and switch Q4 is higher (e.g., about 1.732 times higher) than the RMS current through switch Q1 and switch Q2. Therefore, switch Q1 and switch Q2 require a lower on-resistance (Rdson). In addition, switch Q3 and switch Q4 are turned on at the same time, so the power loss through switch Q3 and switch Q4 is higher because the on-resistances of switch Q3 and switch Q4 are connected in series. Summary of the invention

[0007] This section provides a general summary of the invention, and is not a comprehensive disclosure of its full scope or all of its features.

[0008] According to one aspect of the present invention, a switch mode power supply includes a pair of input terminals for receiving an alternating current (AC) voltage input or a direct current (DC) voltage input from an input power source; a pair of output terminals for supplying a direct current (DC) voltage output to a load; and at least four switches, the at least four switches being connected in a three-level LLC circuit arrangement between the pair of input terminals and the pair of output terminals. A first switch and a second switch of the at least four switches define a first half-bridge, and a third switch and a fourth switch of the at least four switches define a second half-bridge. The switch mode power supply also includes a fifth switch and a control circuit, the fifth switch being connected across the second switch and the third switch to short-circuit the second switch and the third switch when the fifth switch is closed; the control circuit includes a voltage-controlled oscillator (VCO) and a plurality of logic gates and a plurality of flip-flops, the voltage-controlled oscillator and the plurality of logic gates and the plurality of flip-flops being connected to operate the at least four switches using zero-voltage switching (Zero-Voltage Switching, ZVS).

[0009] According to another aspect of the present invention, a switch mode power supply includes a pair of input terminals for receiving an alternating current (AC) voltage input or a direct current (DC) voltage input from an input power source; a pair of output terminals for supplying a direct current (DC) voltage output to a load; a circuit ground; and at least four switches, the at least four switches being connected in a three-stage LLC circuit arrangement between the pair of input terminals and the pair of output terminals. A first switch and a second switch of the at least four switches define a first half-bridge, and a third switch and a fourth switch of the at least four switches define a second half-bridge. The first half-bridge is connected between the circuit ground and the first input terminal of the pair of input terminals, and the second half-bridge is connected between the circuit ground and the second input terminal of the pair of input terminals. The switch mode power supply also includes a fifth switch, the fifth switch being connected across the second switch and the third switch to short-circuit the second switch and the third switch when the fifth switch is closed.

[0010] According to another aspect of the present invention, a switch mode power supply includes a pair of input terminals for receiving an alternating current (AC) voltage input or a direct current (DC) voltage input from an input power source; a pair of output terminals for supplying a direct current (DC) voltage output to a load; a transformer having a primary side and a secondary side; and at least four switches, the at least four switches being connected in a three-level LLC circuit arrangement between the pair of input terminals and the primary side of the transformer. A first switch and a second switch of the at least four switches define a first half-bridge, and a third switch and a fourth switch of the at least four switches define a second half-bridge. The switch mode power supply also includes a control circuit. The control circuit includes a voltage controlled oscillator (VCO) and a plurality of logic gates and a plurality of flip-flops, the voltage controlled oscillator (VCO) and the plurality of logic gates and the plurality of flip-flops being connected to operate the at least four switches using zero voltage switching (ZVS).

[0011] Concept 1: A switch mode power supply comprising:

[0012] a pair of input terminals for receiving an AC voltage input or a DC voltage input from an input power source;

[0013] a pair of output terminals, the pair of output terminals being used to supply a DC voltage output to a load;

[0014] at least four switches coupled in a three-stage LLC circuit arrangement between the pair of input terminals and the pair of output terminals, a first switch and a second switch of the at least four switches defining a first half-bridge, and a third switch and a fourth switch of the at least four switches defining a second half-bridge;

[0015] a fifth switch connected across the second switch and the third switch to short-circuit the second switch and the third switch when the fifth switch is closed; and

[0016] A control circuit includes a voltage controlled oscillator, and a plurality of logic gates and a plurality of flip-flops, the voltage controlled oscillator, and the plurality of logic gates and the plurality of flip-flops being coupled to operate the at least four switches using zero voltage switching.

[0017] Concept 2: The switch mode power supply of Concept 1 further comprising a transformer and a plurality of secondary switches, wherein said at least four switches in said three-level LLC circuit arrangement are coupled to a primary side of said transformer and said plurality of secondary switches are coupled to a secondary side of said transformer.

[0018] Concept 3: The switch mode power supply of Concept 2 further comprising:

[0019] a first capacitor and a first inductor coupled between a primary side of the transformer and the first half-bridge; and

[0020] A second capacitor and a second inductor are coupled between the primary side of the transformer and the second half-bridge.

[0021] Concept 4: The switch mode power supply of Concept 2 or 3 wherein said control circuit is coupled to operate said plurality of secondary switches utilizing zero voltage switching and zero current switching.

[0022] Concept 5: The switch mode power supply of any of Concepts 1-4 further comprising:

[0023] a circuit ground, the first half-bridge coupled between the circuit ground and a first input terminal of the pair of input terminals, and the second half-bridge coupled between the circuit ground and a second input terminal of the pair of input terminals; and

[0024] A first capacitor and a second capacitor, the first capacitor is coupled between the circuit ground and the first input terminal, and the second capacitor is coupled between the circuit ground and the second input terminal.

[0025] Concept 6: The switch mode power supply of Concept 5 wherein a capacitance value of said first capacitor and a capacitance value of said second capacitor are the same to equally divide said voltage input into said first capacitor and said second capacitor.

[0026] Concept 7: The switch mode power supply of any of Concepts 1-6 wherein said control circuit further comprises a compensator, a phase comparator and a delay circuit, said compensator, said phase comparator and said delay circuit being coupled to provide a dead time to achieve zero voltage switching of said at least four switches coupled in said three-stage LLC circuit arrangement.

[0027] Concept 8: The switch mode power supply of any of Concepts 1-7 wherein only a single said fifth switch is coupled across said second switch and said third switch.

[0028] Concept 9: The switch mode power supply of any of Concepts 1 to 8 wherein:

[0029] The plurality of flip-flops include at least two D flip-flops coupled to divide a frequency output by the voltage-controlled oscillator into halves; and

[0030] A first pair of logic gates and a second pair of logic gates of the plurality of logic gates are coupled to a first D flip-flop of the at least two D flip-flops to generate a fifty percent duty cycle for controlling the at least four switches coupled in the three-stage LLC circuit arrangement.

[0031] Concept 10: The switch mode power supply of Concept 9 wherein:

[0032] A fifth logic gate and a sixth logic gate of the plurality of logic gates are coupled to a second D flip-flop of the at least two D flip-flops to generate a twenty-five percent duty cycle; and

[0033] A seventh logic gate of the plurality of logic gates includes an OR gate coupled to receive outputs of the fifth logic gate and the sixth logic gate to control the fifth switch.

[0034] Concept 11: The switch mode power supply of any of Concepts 1 to 10 wherein said control circuit is coupled to:

[0035] Simultaneously turning on the first switch and the third switch, and simultaneously turning off the first switch and the third switch;

[0036] Simultaneously turning on the second switch and the fourth switch, and simultaneously turning off the second switch and the fourth switch;

[0037] Turning on the fifth switch while turning off the at least four switches; and

[0038] The fifth switch is turned off while the at least four switches are turned on.

[0039] Concept 12: A switch mode power supply comprising:

[0040] a pair of input terminals for receiving an AC voltage input or a DC voltage input from an input power source;

[0041] a pair of output terminals, the pair of output terminals being used to supply a DC voltage output to a load;

[0042] Circuit ground terminal;

[0043] at least four switches coupled in a three-stage LLC circuit arrangement between the pair of input terminals and the pair of output terminals, a first switch and a second switch of the at least four switches defining a first half-bridge and a third switch and a fourth switch of the at least four switches defining a second half-bridge, the first half-bridge coupled between the circuit ground and a first input terminal of the pair of input terminals, and the second half-bridge coupled between the circuit ground and a second input terminal of the pair of input terminals; and

[0044] A fifth switch is connected across the second switch and the third switch to short-circuit the second switch and the third switch when the fifth switch is closed.

[0045] Concept 13: The switch mode power supply of Concept 12 further comprising a transformer and a plurality of secondary switches, wherein said at least four switches in said three-level LLC circuit arrangement are coupled to a primary side of said transformer and said plurality of secondary switches are coupled to a secondary side of said transformer.

[0046] Concept 14: The switch mode power supply of Concept 12 or 13 further comprising:

[0047] a first capacitor and a first inductor coupled between a primary side of the transformer and the first half-bridge; and

[0048] A second capacitor and a second inductor are coupled between the primary side of the transformer and the second half-bridge.

[0049] Concept 15: The switch mode power supply of any of Concepts 12-14 further comprising:

[0050] a first capacitor and a second capacitor, the first capacitor coupled between the circuit ground and the first input terminal, and the second capacitor coupled between the circuit ground and the second input terminal; and

[0051] A first resistor and a second resistor, the first resistor being coupled between the circuit ground and the first input terminal, and the second resistor being coupled between the circuit ground and the second input terminal.

[0052] Concept 16: The switch mode power supply of any of Concepts 12-15 wherein only a single said fifth switch is coupled across said second switch and said third switch.

[0053] Concept 17: A switch mode power supply comprising:

[0054] a pair of input terminals for receiving an AC voltage input or a DC voltage input from an input power source;

[0055] a pair of output terminals, the pair of output terminals being used to supply a DC voltage output to a load;

[0056] a transformer having a primary side and a secondary side;

[0057] at least four switches coupled in a three-stage LLC circuit arrangement between the pair of input terminals and the primary side of the transformer, a fifth switch coupled across two switches of the at least four switches coupled in the three-stage LLC circuit arrangement to short-circuit the two switches when the fifth switch is closed; and

[0058] A control circuit includes a voltage controlled oscillator coupled to operate the five switches, as well as a plurality of logic gates and a plurality of flip-flops.

[0059] Concept 18: The switch mode power supply of Concept 17 wherein said control circuit further comprises a compensator, a phase comparator and a delay circuit, said compensator, said phase comparator and said delay circuit being coupled to provide a dead time to achieve zero voltage switching of said at least four switches coupled in said three-stage LLC circuit arrangement.

[0060] Concept 19: The switch mode power supply of Concept 17 or 18 wherein:

[0061] The plurality of flip-flops include at least two D flip-flops coupled to divide a frequency output by the voltage-controlled oscillator into halves; and

[0062] A first pair of logic gates and a second pair of logic gates of the plurality of logic gates are coupled to a first D flip-flop of the at least two D flip-flops to generate a fifty percent duty cycle for controlling the at least four switches coupled in the three-stage LLC circuit arrangement.

[0063] Concept 20: The switch mode power supply of Concept 19 wherein:

[0064] A fifth logic gate and a sixth logic gate of the plurality of logic gates are coupled to a second D flip-flop of the at least two D flip-flops to generate a twenty-five percent duty cycle; and

[0065] A seventh logic gate of the plurality of logic gates includes an OR gate coupled to receive outputs of the fifth logic gate and the sixth logic gate to control the fifth switch.

[0066] Concept 21: The switch mode power supply of any of Concepts 17 to 20 wherein said control circuit is coupled to:

[0067] Simultaneously turning on the first switch and the third switch, and simultaneously turning off the first switch and the third switch;

[0068] Simultaneously turning on the second switch and the fourth switch, and simultaneously turning off the second switch and the fourth switch;

[0069] turning on the fifth switch while turning off the four switches; and

[0070] The fifth switch is turned off while the four switches are turned on.

[0071] From the description provided herein, other aspects and fields of application will become apparent. It should be understood that various aspects of the present invention can be implemented separately or in combination with one or more other aspects. It should also be understood that the description and specific examples herein are only for illustrative purposes and are not intended to limit the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present invention.

[0073] Figure 1 is a circuit diagram of a power supply including a three-stage LLC circuit according to the prior art.

[0074] Figure 2 for Figure 1 Graph of an exemplary current waveform of a power supply.

[0075] Figure 3 is a circuit diagram of a power supply including a three-stage LLC circuit according to an exemplary embodiment of the present invention.

[0076] Figure 4 for Figure 3 Circuit diagram of the power supply control circuit.

[0077] Figure 5 Reason Figure 4 FIG. 1 is a graph of an exemplary control signal generated by a control circuit of FIG.

[0078] Figure 6 for Figure 3 Graph of an exemplary current waveform of a power supply.

[0079] Figure 7 for Figure 3 A graph of exemplary control signals for a switch of a power supply during a turn-on and turn-off sequence.

[0080] Figure 8 is a circuit diagram of a power supply including a three-level LLC circuit and a synchronous rectifier switch on the secondary side of a transformer.

[0081] Fig. 9 To provide Figure 8 FIG. 2 is a graph of exemplary control signals for synchronous rectifier switches of a power supply and the current generated by the synchronous rectifier.

[0082] Fig.10 To provide Figure 8 Graph of exemplary control signals for a synchronous rectifier switch and a primary switch of a power supply.

[0083] Fig.11 is a circuit diagram of a power supply including a voltage doubler PFC circuit according to another exemplary embodiment of the present invention.

[0084] Fig.12 for Fig.11 Circuit diagram of the power supply control circuit.

[0085] Fig.13 for Fig.11 Graphs of exemplary current waveforms and voltage waveforms of a power supply.

[0086] Fig.14 for Fig.11 FIG. 2 is a graph of exemplary current waveforms and voltage waveforms of a power supply during another operating mode.

[0087] Fig.15 is a circuit diagram of a power supply including a reference voltage selector according to another exemplary embodiment of the present invention.

[0088] Corresponding reference numerals indicate corresponding parts or features throughout the several views of the drawings. DETAILED DESCRIPTION

[0089] Example embodiments will now be described more fully with reference to the accompanying drawings.

[0090] Exemplary embodiments are provided so that the present invention will be thorough and will fully convey the scope to those skilled in the art. A number of specific details, such as examples of specific components, devices and methods, are presented to provide a thorough understanding of embodiments of the present invention. It will be apparent to those skilled in the art that specific details need not be employed, that exemplary embodiments may be embodied in many different forms, and that both specific details and exemplary embodiments should not be construed as limiting the scope of the present invention. In some exemplary embodiments, well-known processes, well-known equipment structures, and well-known techniques are not described in detail.

[0091] The terms used herein are only for the purpose of describing specific exemplary embodiments and are not intended to be limited. As used herein, the singular forms "one", "the", "said" may also be intended to include plural forms unless the context clearly indicates otherwise. The terms "include", "comprise" and "have" are inclusive and therefore refer to the existence of stated features, integers, steps, operations, elements, and / or parts, but do not exclude the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or their combinations. The method steps, processes and operations described herein should not be understood as necessarily requiring them to be performed in the specific order discussed or shown, unless the specific order discussed or shown is specifically identified as an execution order. It will also be understood that additional or alternative steps may be adopted.

[0092] Although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Terms such as "first", "second" and other numerical terms do not imply order or sequence when used in this article unless the context has clear instructions. Therefore, the first element, first component, first area, first layer or first part discussed below can be referred to as the second element, second component, second area, second layer or second part, without departing from the teaching of exemplary embodiments.

[0093] For ease of description, spatially relative terms such as "inside", "outside", "below", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between an element or feature as shown in the figure and one or more other elements or features. In addition to the orientations shown in the figures, spatially relative terms may also be intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, the element described as being "below" or "below" other elements or features will be oriented to be "above" the other elements or features. Thus, the exemplary term "below" may cover both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein are understood accordingly.

[0094] A switch mode power supply according to an exemplary embodiment of the present invention is Figure 3 , and generally designated by reference numeral 200. The power supply 200 includes a pair of input terminals 202 and 204 for receiving a direct current (DC) voltage input from an input power source V6, and a pair of output terminals 206 and 208 for supplying a direct current (DC) voltage output (Vout) to a load (RLOAD).

[0095] The power supply 200 also includes four switches Q1, Q2, Q3 and Q4 in a three-level LLC circuit arrangement coupled between a pair of input terminals 202, 204 and a pair of output terminals 206, 208. Switches Q2 and Q3 define a first half bridge and switches Q1 and Q4 define a second half bridge.

[0096] The power supply 200 further includes: a fifth switch Q5 connected between the switch Q3 and the switch Q4 to short-circuit the switch Q3 and the switch Q4 when the fifth switch Q5 is closed; and a control circuit 210 (in Figure 4 ). The control circuit 210 includes a voltage controlled oscillator (VCO) coupled to operate switches Q1-Q4 using zero voltage switching (ZVS), logic gates U1-U5, U7-U8, U13-U14, U17, and U30, and flip-flops U0 and U19.

[0097] Refer again Figure 3 , the power supply 200 includes a transformer Tx1 and four diodes D1, D2, D9 and D10. The transformer Tx1 includes one or more primary windings P1 and one or more secondary windings S1. Switches Q1-Q4 are connected to (one or more) primary windings P1, and diodes D1-D2 and diodes D9-D10 are connected to (one or more) secondary windings S1.

[0098] although Figure 3Four diodes D1 - D2 and D9 - D10 are shown, but other embodiments may include more or fewer diodes, diodes connected in different arrangements, secondary switches (eg, synchronous rectification switches, etc.).

[0099] For example, Figure 8 An exemplary power converter 250 is shown in which diodes D1-D2 and D9-D10 have been replaced by secondary switches Q6, Q7, Q8, and Q9. Synchronous rectification controller 252 provides control signal DH1 to switch Q6 (coupled to resistor R4), control signal DH2 to switch Q7 (coupled to resistor R3), control signal DL1 to switch Q8 (coupled to resistor R1), and control signal DL2 to switch Q9 (coupled to resistor R2).

[0100] The secondary switches Q6 - Q9 may be turned on and / or off using zero voltage switching (ZVS) and zero current switching (Zero-Current Switching, ZCS). Fig. 9 Exemplary control signals DL1 and DL2 and corresponding currents in switches Q8 and Q9 are shown. Fig. 9 As shown, when the current is approximately zero, the switch Q8 and the switch Q9 may be turned on and / or off.

[0101] Return to reference Figure 3 The power supply 200 includes a capacitor C1 and an inductor L5 connected between (one or more) primary windings P1 (e.g., primary side) of a transformer Tx1 and a half-bridge formed by switches Q2 and Q3, and a capacitor C2 and an inductor L1 connected between (one or more) primary windings P1 of a transformer Tx1 and a half-bridge defined by switches Q1 and Q4.

[0102] Capacitor C1 and capacitor C2 and inductor L5 and inductor L1 may be separate resonant components. In other embodiments, capacitor C1 and inductor L5 may be used alone, capacitor C2 and inductor L1 may be used alone, etc. For example, a single inductor having an inductance value equal to the sum of the inductances of inductor L1 and inductor L5 may be used, a single capacitor having a capacitance equal to (C1×C2 / (C1+C2)) may be used, etc.

[0103] Transformer Tx1 may be a step-down transformer, and diodes D1, D2, D9, and D10 may form a rectifier bridge. Capacitor C10 may be a filter capacitor, and RLOAD may be a load resistor. In some embodiments, the rated voltage of all switches used in the power supply may be 600V, 650V, etc.

[0104] like Figure 3As shown, the power supply 200 may include a circuit ground terminal 212, a first half bridge (i.e., switch Q2 and switch Q3) connected between the circuit ground terminal 212 and the input terminal 202, and a second half bridge (e.g., switch Q1 and switch Q4) connected between the circuit ground terminal 212 and the input terminal 204.

[0105] Capacitor C6 is coupled between circuit ground 212 and input terminal 202, and resistor R30 is coupled in parallel with capacitor C6. Capacitor C7 is coupled between circuit ground 212 and input terminal 204, and resistor R33 is coupled in parallel with capacitor C7.

[0106] In some embodiments, the capacitance values ​​of capacitor C6 and capacitor C7 can be the same (e.g., exactly equal, within one percent of each other, within five percent of each other, within manufacturing tolerance, etc.) to evenly divide the DC voltage across capacitor C6 and capacitor C7 (e.g., exactly equal, within one percent of each other, within five percent of each other, etc.).

[0107] For example, the capacitance values ​​of capacitor C6 and capacitor C7 can be the same to divide the input voltage so that each has fifty percent, and resistor R30 and resistor R33 maintain the voltage balance. As described above, switches Q2 and Q3 can form a half bridge across capacitor C6, and switches Q4 and Q1 can form another half bridge across capacitor C7.

[0108] Figure 3 The input power source V6 (e.g., voltage source) is shown when supplying a DC voltage of 800 volts (Volt). In other embodiments, the input power source may supply other suitable voltages higher or lower than 800V, and the power supply 200 may be a stage of an AC-DC converter that converts an AC input (e.g., a three-phase AC input, etc.) into a DC voltage supplied to the power supply 200 (e.g., as the power source V6, etc.). For example, the input power source V6 may be the output of a PFC converter stage of the AC-DC converter.

[0109] The switch Q5 may be the only switch connected across the switch Q3 and the switch Q4 to reduce the conduction loss when the switch Q5 is turned on. When the switch Q5 is turned on, the switch Q5 may short-circuit the switch Q3 and the switch Q4.

[0110] like Figure 3As shown, switch Q2 is driven by control signal AA via isolation driver E9 and resistors R34 and R38, switch Q3 is driven by control signal BB2 via isolation driver E8 and resistors R27 and R28, switch Q4 is driven by control signal AA2 via isolation driver E10 and resistors R35 and R37, switch Q1 is driven by control signal BB via isolation driver E7 and resistors R29 and R32, and switch Q5 is driven by control signal Com via isolation driver E1 and resistor R12. Control signals AA, BB, AA2, BB2, and control signal Com may be generated by control circuit 210 as further explained below.

[0111] Switches Q1-Q5 may include any suitable switching devices, such as bipolar-junction switches (BJT), metal-oxide semiconductor field-effect transistors (MOSFET), silicon carbide (SiC) FETs, etc. Although power supply 200 shows a specific arrangement of four switches in a three-stage LLC circuit, other embodiments may include more or fewer switches, capacitors, inductors, resistors, etc., which may be arranged in other suitable three-stage LLC circuit topologies.

[0112] Now refer to Figure 4 , the control circuit 210 includes two D flip-flops U9 and U19 connected to a voltage controlled oscillator (VCO). The D flip-flops U9 and U19 can divide the frequency output by the VCO into two halves. For example, the VCO can receive a voltage from the output terminal of the compensator and output a frequency corresponding to the voltage received from the output terminal of the compensator.

[0113] Logic gates U17 and U30 are connected to flip-flop U19 to generate a fifty percent duty cycle, while logic gates U2 and U3 are connected between flip-flop U19 and flip-flop U9 to generate a complementary fifty percent duty cycle. Logic gates U17, U30, and logic gates U2 and U3 can each be considered to form a delay circuit.

[0114] Logic gates U13 and U14 are each connected to convert the corresponding fifty percent duty cycle into a twenty-five percent duty cycle with a dead time, thereby supplying control signals AA and BB to switches Q2 and Q1, respectively. Logic gates U7, U8, and logical OR gate U1 supply control signal Com to switch Q5. Logic gates U4 and U5 supply control signals AA2 and BB2 to switches Q4 and Q3, respectively.

[0115] For example, the VCO can convert the output voltage of the compensator to a frequency, and the D flip-flops U9, U19 can divide the frequency in half. Logic gates U3, U2 and logic gates U17, U30 provide dead time between complementary pairs with a fifty percent duty cycle from flip-flop U19. Logic gates U14, U13 can convert a fifty percent duty cycle to a twenty-five percent duty cycle with dead time, and logic gates U7, U8 together with logic gate U1 provide complementary pairs for an OR-ed output (Com). Control signal AA2 and control signal BB2 are drive signals for switch Q4 and switch Q3, respectively.

[0116] Figure 5 shows exemplary waveforms of control signals AA, BB, AA2, BB2, and Com during operation of power supply 200, and Figure 6 Exemplary current waveforms through respective switches Q1 - Q4 and switch Q5 are shown.

[0117] like Figure 5 As shown, the control circuit 210 is coupled to turn on the switch Q1 and the switch Q3 at the same time, and to turn off the switch Q1 and the switch Q3 at the same time (e.g., via the control signal BB and the control signal BB2). In the opposite phase, the control circuit 210 is coupled to turn on the switch Q2 and the switch Q4 at the same time, and to turn off the switch Q2 and the switch Q4 at the same time (e.g., via the control signal AA and the control signal AA2).

[0118] While switches Q1-Q4 are turned off, switch Q5 is turned on (eg, via control signal Com), and while switches Q1-Q4 are turned on, switch Q5 is turned off. Figure 5 As shown, the switch Q5 is turned on twice as often as the switches Q1 - Q4 , and the total duration is twice as long as the duration of each individual switch in the switches Q1 - Q4 .

[0119] For example, for each turn-on of switches Q1-Q4, switch Q5 turns on twice, so switch Q5 conducts two half-cycles of current compared to switches Q1-Q4, and the RMS current of switch Q5 will be 1.414 times higher than the RMS current of any of switches Q1-Q4. Compared to an arrangement without switch Q5 and in which both switches Q3 and switch Q4 will experience conduction losses, the arrangement of switches in power supply 200 provides conduction losses through only one switch when switch Q5 is turned on. Therefore, the conduction losses with switch Q5 are lower than the conduction losses without switch Q5.

[0120] although Figure 4 Shown is the Figure 5 This is one exemplary arrangement of flip-flops and logic gates of a control signal pattern, but other implementations may include flip-flops and logic gates connected in other arrangements, control signals supplied with different timing waveforms, etc.

[0121] Compared to conventional three-level LLC circuits, power supply 200 can provide many advantages. For example, compared to conventional three-level LLC circuits, power supply 200 can provide an LLC topology suitable for 800V input (or other suitable high voltage input) with a control circuit that allows a reduced transformer ratio.

[0122] The power supply 200 can provide zero voltage switching (ZVS) operation for all primary switches, and zero voltage switching (ZVS) operation and zero current switching (ZCS) operation for all secondary switches, for example, when the operating frequency is equal to or lower than the resonant frequency. The primary-to-secondary turns ratio of the transformer can be about 50% of the turns ratio of the transformer used with the traditional three-level LLC circuit control method. This allows for improved optimization of transformer efficiency.

[0123] For example, a transformer designed for a conventional LLC topology receiving a 400V DC input can be replaced with an 800V DC input. The input of the power supply 200 can be a three-phase AC input, a single-phase AC input with an 800V PFC output using a voltage doubler boost circuit, or the like.

[0124] Figure 7 FIG. 2 shows an exemplary timing sequence of control signals AA, BB, AA2, BB2 during one turn on and turn off sequence. Figure 7 As shown, during the time period t1 - t2 , the switch Q2 and the switch Q4 are turned on and transfer power from the capacitor C6 to the output terminal.

[0125] At time t2, switch Q2 is turned off. During time period t2-t3, the output capacitance (Coss) of switch Q3 and switch Q5 will be discharged, and switch Q2 will be charged through capacitor C1, capacitor C2, inductor L1, inductor L5 and transformer Tx1.

[0126] At time t3, after switch Q2 has fully charged the voltage across capacitor C6 (ZVS), switch Q5 is turned on. The resonant capacitor will discharge through switch Q5, transferring the charge to the output, and switch Q5 is turned off at time t4.

[0127] During the time period t4-t5, the output capacitance (Coss) of switch Q5 and switch Q4 will be charged, and the output capacitance (Coss) of switch Q1 will be discharged through switch Q3, capacitor C7, resonant component and transformer Tx1. When the current flows through its body diode, switch Q1 will turn on, thus achieving ZVS. In a similar manner, ZVS is achieved for switch Q2 after switch Q5 is turned off when the current is forced to flow through its body diode, capacitor C6 and switch Q4.

[0128] Fig.10 Exemplary control signals DL1 and DL2 for secondary switches Q8 and Q9 are shown with respect to control signals Com and AA+BB. Fig.10 As shown, when the control signal Com is at a low level (e.g., based on the logic high value of the control signal AA+BB), the control signal DL1 turns on the switch Q8, and when the control signal Com is at a high level (e.g., based on the logic low value of the control signal AA+BB), the control signal DL2 turns on the switch Q9.

[0129] For example, the control signal DL1 and the control signal DH2 can be synchronized with the control signal AA+BB, and the control signal DL2 and the control signal DH1 can be synchronized with the Com drive signal. When the switching frequency is equal to or lower than the resonant frequency, the on time of the synchronous rectifier FETQ6-Q9 can be less than the resonant half period of the LLC resonant tank circuit.

[0130] When the switching frequency is higher than the resonant frequency, the on-time of the synchronous rectifier FETs Q6-Q9 may be equal to the on-time of the corresponding drive signals of the primary FETs Q1-Q4 (e.g., the on-time of the control signal DL1 and the control signal DH2 may be the same as the on-time of the control signal AA+BB, and the on-time of the control signal DL2 and the control signal DH1 may be the same as the on-time of the control signal Com). However, the turn-on of the synchronous rectifier FETs Q6-Q9 may need to be delayed compared to the corresponding primary FETs Q1-Q4 in order to avoid reverse current when the conduction mode goes deeper into the continuous mode. Smart commercial analog control integrated circuits may be used to control the synchronous rectifier FETs Q6-Q9.

[0131] According to another aspect of the present invention, a switch mode power supply includes a pair of input terminals for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source, a pair of output terminals for providing a direct current (DC) voltage output to a load, a circuit ground, and at least four switches in a three-stage LLC circuit arrangement connected between the pair of input terminals and the pair of output terminals.

[0132] The first and second switches of the at least four switches define a first half-bridge, and the third and fourth switches of the at least four switches define a second half-bridge. The first half-bridge is coupled between the circuit ground and a first input terminal of the pair of input terminals, and the second half-bridge is coupled between the circuit ground and a second input terminal of the pair of input terminals. The power supply further includes a fifth switch coupled across the second and third switches to short-circuit the second and third switches when the fifth switch is closed.

[0133] The power supply may include a transformer and a plurality of secondary switches, wherein the at least four switches are coupled to a primary side of the transformer, and the plurality of secondary switches are coupled to a secondary side of the transformer. A first capacitor and a first inductor may be coupled between the primary side of the transformer and the first half-bridge, and a second capacitor and a second inductor may be coupled between the primary side of the transformer and the second half-bridge.

[0134] A first capacitor may be coupled between circuit ground and the first input terminal, and a second capacitor may be coupled between circuit ground and the second input terminal. A first resistor may be coupled between the circuit ground and the first input terminal, and a second resistor may be coupled between the circuit ground and the second input terminal. In some embodiments, only a single fifth switch may be coupled across the second switch and the third switch.

[0135] According to another aspect of the present invention, a switch mode power supply includes a pair of input terminals for receiving an alternating current (AC) or direct current (DC) voltage input from an input power source, a pair of output terminals for providing a direct current (DC) voltage output to a load, a transformer having a primary side and a secondary side, and at least four switches in a three-level LLC circuit arrangement connected between the pair of input terminals and the primary side of the transformer.

[0136] The first and second switches of the at least four switches define a first half-bridge, and the third and fourth switches of the at least four switches define a second half-bridge. The power supply further includes a control circuit. The control circuit includes a voltage controlled oscillator (VCO) and a plurality of logic gates and a plurality of flip-flops, and the voltage controlled oscillator (VCO) and the plurality of logic gates and the plurality of flip-flops are connected to operate at least the four switches using zero voltage switching (ZVS).

[0137] The control circuit includes a compensator, a phase comparator, and a delay circuit, which are connected to provide a dead time to achieve ZVS of the at least four switches. The plurality of flip-flops may include at least two D flip-flops connected to divide the frequency of the VCO output into halves, and a first pair of logic gates and a second pair of logic gates of the plurality of logic gates may be connected to a first D flip-flop of the at least two D flip-flops to generate a fifty percent duty cycle to control the at least four switches.

[0138] In some embodiments, the fifth and sixth logic gates of the plurality of logic gates may be coupled to the second D flip-flop of the at least two D flip-flops to generate a duty cycle of 25 percent, and the seventh logic gate of the plurality of logic gates may include an OR gate coupled to receive outputs of the fifth and sixth logic gates to control the fifth switch. The control circuit may be coupled to simultaneously turn on the first and third switches and simultaneously turn off the first and third switches, simultaneously turn on the second and fourth switches and simultaneously turn off the second and fourth switches, turn on the fifth switch while turning off the four switches and turn on the four switches while turning on the fifth switch.

[0139] According to another aspect of the present invention, Fig.11 1 shows a switch mode power supply 300. The power supply 300 includes a pair of input terminals 302 and 304 for receiving an alternating current (AC) voltage input from an input power source V1, a pair of output terminals 306 and 308 for supplying a direct current (DC) voltage output (Vout) to a load (RLOAD), and four switches Q1-Q4 in a three-level LLC circuit arrangement connected between the pair of input terminals 302, 304 and the pair of output terminals 306, 308.

[0140] The power supply also includes a voltage doubler power factor correction (PFC) circuit 314 coupled between a pair of input terminals 302, 304 and the three-stage LLC circuit, and a control circuit 310 ( Fig.12 ), thereby supplying a DC voltage output (Vout) to a load (RLOAD).

[0141] The three-stage LLC circuit arrangement of power supply 300 may be similar to the three-stage LLC circuit arrangement of power supply 200 , and thus some components of power supply 300 will not be repeatedly described herein.

[0142] The voltage doubler PFC circuit 314 is configured to supply a first PFC voltage output to the three-stage LLC circuit arrangement when the AC input voltage V1 is within a specified low line voltage range, and the voltage doubler PFC circuit 314 is configured to supply a second PFC voltage output to the three-stage LLC circuit arrangement when the AC input voltage V1 is within a specified high line voltage range.

[0143] The second PFC voltage output may be greater than the first PFC voltage output. For example, the second PFC voltage output may be twice the first PFC voltage output. In some embodiments, the second PFC voltage output may be at least 800 volts (e.g., approximately 880 volts, etc.), and the first PFC voltage output may be at least 400 volts (e.g., approximately 440 volts, etc.).

[0144] The specified low line voltage range may be different than the specified high line voltage range.In some implementations, the first PFC voltage output may be greater than the specified low line voltage range, and the second PFC voltage output may be greater than the specified high line voltage range.

[0145] For example, the power supply 300 can be designed to have any suitable AC voltage input, such as an AC voltage input in the range of 85 V to 305 V. The voltage doubler PFC circuit (e.g., front-end PFC) can increase a low line input (e.g., 85 V to 140 V AC, etc.) to a first PFC voltage output (e.g., approximately 440 V DC), and can increase a high line input (e.g., 85 V to 277 V AC, 180 V to 305 V AC, etc.) to a higher PFC voltage output (e.g., approximately 880 V DC, etc.).

[0146] The power supply 300 may be used in any suitable application, such as hyperscale applications, telecommunications, server power supplies, etc. The voltage doubler PFC circuit may use any suitable voltage input range and voltage output range, including a 1:2 ratio, etc.

[0147] like Fig.11As shown, the voltage doubler PFC circuit 314 includes two PFC circuit switches Q6 and Q7. The control circuit 310 may include two reference voltages (e.g., Fig.15 The two reference voltages are different from each other (eg, 2.5 V and 5 V, etc.).

[0148] The control circuit 310 may be configured to receive a sensed AC voltage input and determine whether the sensed AC voltage input is within a specified low line voltage range or within a specified high line voltage range. Then, when the AC voltage input V1 is within the specified low line voltage range, the control circuit 310 may operate the PFC circuit switches Q6 and Q7 according to a first reference voltage (e.g., V2), and when the AC voltage input V1 is within the specified high line voltage range, the control circuit 310 may operate the PFC circuit switches Q6 and Q7 according to a second reference voltage (e.g., V3).

[0149] The voltage doubler PFC circuit 314 may include an inductor L2 , two diodes D3 and D4 , and two capacitors (eg, capacitor C6 and capacitor C7 ). The two PFC circuit switches Q6 and Q7 are coupled between the inductor L2 and the input terminal 304 .

[0150] Each of diodes D3 and D4 is coupled between inductor L2 and the three-stage LLC circuit arrangement. Each capacitor may be coupled between a corresponding one of diodes D3 and D4 and circuit ground 312. Control circuit 310 (or a separate control circuit) may be configured to control switches Q6 and Q7 via a pulse width modulation (PWM) signal.

[0151] For example, switches Q6 and Q7 conduct current during the on period of the PWM signal. During the off period, diode D4 may conduct current during the positive half-cycle of the AC input, and diode D3 may conduct current during the negative half-cycle of the AC input.

[0152] During low line voltage (e.g., 85V-140V AC, etc.), the output of the PFC circuit can be at a first value (e.g., 440V DC). When the input AC line voltage is within a high line voltage input range (e.g., 180V-305V AC), the output of the PFC circuit can be at a higher value (e.g., 880V DC).

[0153] For example, during a positive half cycle of the line voltage, switch Q6 and switch Q7 will be turned on during the on time period of the PWM control signal, and current will flow from input terminal 302 through inductor L2, then through switch Q6 and switch Q7 to input terminal 304, which can be connected to circuit ground 312 or the midpoint of the two capacitors C6 and C7.

[0154] During the off period of the PWM control signal, the current flowing through inductor L2 will continue to flow through diode D4, through capacitor C6 and back to input terminal 304 connected to circuit ground 312. Therefore, capacitor C6 will be charged through D4 during the entire positive half cycle of the line voltage.

[0155] During the negative half cycle of the line voltage, switches Q6 and Q7 will be turned on during the on time period of the PWM control signal, and current will flow from circuit ground 312 connected to input terminal 304 through switches Q6 and Q7, and then through inductor L2 to input terminal 302.

[0156] During the off period of the PWM control signal, the current flowing through the inductor L2 will continue to flow through the input power source V1, capacitor C7 and diode D3, back to the input terminal 302. Therefore, during the entire negative half cycle, the capacitor C7 will be charged through the diode D3.

[0157] although Fig.11 One particular arrangement of components in a voltage doubler PFC circuit 314 is shown (which may have lower conduction losses than other circuits), but other circuits may include more or fewer switches, inductors, diodes or capacitors, components arranged in other suitable circuit topologies, etc.

[0158] In some embodiments, the control circuit 310 can be configured to operate the switches Q1-Q4 in the three-level LLC circuit arrangement in a first operation mode when the AC voltage input V1 is within a specified low line voltage range, and to operate the switches Q1-Q4 in the three-level LLC circuit arrangement in a second operation mode when the AC voltage input V1 is within a specified high line voltage range. The first operation mode can be a symmetrical half-bridge (SHB) operation, and the second operation mode can be an asymmetrical half-bridge (AHB) operation.

[0159] like Fig.11As shown, switch Q2 and switch Q3 form a first half bridge, and switch Q1 and switch Q4 form a second half bridge. Power supply 300 includes switch Q5 connected across switch Q3 and switch Q4 to short-circuit switch Q3 and switch Q4 when switch Q5 is closed. Fig.11 A switch Q5 is shown, but in some implementations, the power supply may not include the switch Q5.

[0160] Fig.12 2 shows a control circuit 310 of the power supply 300. Fig.12 As shown, the control circuit 310 includes a voltage controlled oscillator (VCO) and a plurality of logic gates and flip-flops, which are coupled to operate at least four switches according to a frequency output by the VCO.

[0161] Except for control signal AA1 and control signal BB1, control circuit 310 of power supply 300 may be similar to control circuit 210 of power supply 200, and thus descriptions of some components of control circuit 310 will not be repeated herein. As further described below, control circuit 310 may selectively provide different control signals according to the SHB operation mode or AHB operation mode of power supply 300.

[0162] For example, the control circuit 310 may be configured to supply the first control signal AA to the switch Q1 and the switch Q2 , supply the second control signal BB to the switch Q3 and the switch Q4 , and turn off the switch Q5 when operating in the SHB operation mode.

[0163] Fig.13 Exemplary waveforms of control signals AA and BB supplied by control circuit 310 during the SHB mode of operation are shown. Fig.13 Also shown are exemplary waveforms of currents flowing through switches Q2 and Q3 during the SHB mode of operation and the relationship between nodes A and B (eg, Fig.11 The voltage between

[0164] The control circuit 310 may be configured to supply control signals AA and AA2 to simultaneously turn on the switches Q2 and Q4, and to supply control signals BB and BB2 to simultaneously turn on the switches Q1 and Q3 when operating in the AHB operation mode. Figure 5 The control circuit 310 may turn on the switch Q2 and the switch Q4 in a phase opposite to the phase in which the switch Q1 and the switch Q3 are turned on, and turn on the switch Q5 when the switches Q1 - Q4 are turned off.

[0165] Alternatively, the control signal BB may be supplied to the switch Q5 instead of the switches Q3 and Q4, wherein the switches Q3 and Q4 are in an off state (AA2=BB2=0). This may allow energy to be transferred from the resonant capacitors C1 and C2 to the output, and may reduce conduction losses to approximately fifty percent, since only a single switch Q5 conducts current instead of the two switches Q3 and Q4.

[0166] Fig.14 Exemplary waveforms of control signals AA1 and BB1 that may be supplied by control circuit 310 during the SHB mode of operation are shown. Fig.14 Also shown are exemplary waveforms of currents flowing through switch Q1, switch Q2, and switch Q5. Fig.14 As shown, the control signal BB1 turns on the switch Q5 and turns off the switch Q1 and the switch Q2 , which can reduce conduction loss because only the single switch Q5 conducts current.

[0167] In view of the above, during SHB mode, the control circuit 310 can select AA1 and BB1 while Com is zero, or set AA1=AA=BB and Com=BB1. During AHB mode, the control circuit 310 can select AA, BB, AA2, BB2, and Com.

[0168] Refer again Fig.11 In some embodiments, the control circuit 310 is configured to operate switches Q1-Q4 to maintain the voltage between node A (e.g., the output of the first half-bridge) and node B (e.g., the output of the second half-bridge) the same when operating in the SHB operating mode and when operating in the AHB operating mode.

[0169] For example, for a low line voltage input range (eg, approximately 440 V), the voltage maintained between nodes A and B may be the same as the output of the voltage doubler PFC circuit 314 regardless of whether the AC voltage input is within the low line voltage input range or the high line voltage input range.

[0170] For example, Figure 6 An exemplary current waveform for switches Q1-Q5 during AHB operation mode is shown. In AHB mode, switches Q1-Q4 can obtain fifty percent of the input voltage. Since the voltage doubler PFC circuit output voltage is, for example, a high line voltage of 880V, the voltage across nodes A and B of power supply 300 will be, for example, 440V.

[0171] Fig.13 2 shows exemplary control signals and currents for switches Q2 and Q3 for low line input voltages during the SHB mode of operation. Fig.13As shown, switches Q1 and Q2 receive the same drive signal AA, while switches Q3 and Q4 receive the same drive signal BB. The current flowing through switches Q1 and Q2 will be the same as I(Q2-D), while the current flowing through switches Q3 and Q4 will be the same as I(Q3-D). Therefore, in a low line voltage state (e.g., 440V), the voltage across nodes A and B of the power supply 300 will be equal to the PFC output voltage.

[0172] Therefore, the asymmetric half-bridge mode may allow only half (e.g., 440 V) of the PFC output voltage (e.g., 880 V) for a high line voltage input to be applied to the LLC components of the three-stage LLC circuit. During a low line voltage input, the three-stage LLC circuit operates in a symmetric half-bridge mode such that the voltage between node A and node B (e.g., 440 V) is equal to the output voltage of the PFC (e.g., 440 V).

[0173] The two operating modes may be based on a mode change scheme in which the input voltage of the voltage doubler PFC circuit 314 is sensed between a low line voltage input (e.g., 85V to 140V AC, etc.) and a high line voltage input (e.g., 85V to 277V, 180V to 305V, etc.), and the output voltage of the PFC circuit is set to a corresponding low value (e.g., 440V) or high value (e.g., 880V). Thus, the PFC circuit 314 may operate as a voltage doubler in both a low line voltage input range and a high line voltage input range.

[0174] Therefore, during the low line voltage PFC circuit operation and the high line voltage PFC circuit operation, the node voltage between the node A and the node B is maintained at, for example, 440 V. Therefore, the same LLC resonant components, main transformer, and output rectifier components can be used even if the LLC is operated from, for example, 440 V at a low line voltage to, for example, 880 V at a high line voltage.

[0175] The power supply 300 can provide one or more advantages, such as, compared with the traditional three-stage LLC circuit, reduced conduction loss and improved efficiency; in the low line voltage input range, the boost voltage of each capacitor is lower (for example, 200V), thereby improving the low line voltage efficiency with a smaller boost ratio; the LLC operating range is wider because only the control mode needs to be changed for different voltages without changing the power components; large-capacity capacitors can be used in parallel in the high line voltage asymmetric mode, etc.

[0176] Fig.15 An exemplary power supply 400 according to another aspect of the invention is shown. The power supply 400 includes a three-stage LLC circuit arrangement, which may be similar to the three-stage LLC circuit arrangements of the power supplies 200 and 300.

[0177] The power supply 400 also includes a voltage doubler PFC circuit 414 and a control circuit. The control circuit includes a PFC controller 416, a reference voltage selector 418, and an LLC controller 420. If the AC voltage input V1 is within the low line voltage range, the reference voltage selector 418 can select the reference voltage V2, and if the AC voltage input V1 is within the high line voltage range, the reference voltage selector 418 can select the reference voltage V3.

[0178] PFC controller 416 receives the selected reference voltage from reference voltage selector 418 and operates the voltage doubler PFC circuit to output the appropriate low voltage or high voltage to the three-stage LLC circuit. LLC controller 420 receives the selected reference voltage from reference voltage selector 418 and controls switches Q1-Q4 to operate in the appropriate AHB mode or SHB mode.

[0179] As described herein, the exemplary power supply and control circuitry may include a microprocessor, a microcontroller, an integrated circuit, a digital signal processor, etc., which may include a memory. The power supply and control circuitry may be configured to perform (e.g., be operable to perform, etc.) any of the example processes described herein using any suitable hardware and / or software implementation. For example, the power supply and controller may execute computer-executable instructions stored in a memory, may include one or more logic gates, control circuits, etc. The PFC voltage doubler circuit may include any suitable circuit arrangement for boosting an input voltage as described above.

[0180] According to another aspect of the present invention, a method of operating a switch mode power supply is disclosed. The power supply includes a pair of input terminals, a pair of output terminals, at least four switches in a three-stage LLC circuit arrangement coupled between the pair of input terminals and the pair of output terminals, and at least two PFC circuit switches coupled in a voltage doubler power factor correction (PFC) circuit, the voltage doubler power factor correction (PFC) circuit coupled between the pair of input terminals and the three-stage LLC circuit.

[0181] The method includes operating at least two PFC switches in a voltage doubler power factor correction circuit to increase an AC voltage input received at the pair of input terminals and supplying the increased voltage to a three-stage LLC circuit, and operating at least four switches of the three-stage LLC circuit to supply a DC voltage output to the pair of output terminals.

[0182] In some embodiments, operating at least two PFC switches includes supplying a first PFC voltage output to a three-stage LLC circuit arrangement when the AC voltage input is within a specified low line voltage range, and supplying a second PFC voltage output to the three-stage LLC circuit arrangement when the AC voltage input is within a specified high line voltage range. The second PFC voltage output is greater than the first PFC voltage output, and the specified low line voltage range is different from the specified high line voltage range.

[0183] The power supply may include a first reference voltage and a second reference voltage, and the method may further include sensing an AC voltage input and determining whether the sensed AC voltage input is within a specified low line voltage range or within a specified high line voltage range.

[0184] Operating the at least two PFC circuit switches may include operating the at least two PFC circuit switches according to a first reference voltage when the AC voltage input is within a specified low line voltage range, and operating the at least two PFC circuit switches according to a second reference voltage when the AC voltage input is within a specified high line voltage range.

[0185] In some embodiments, operating at least four switches of the three-level LLC circuit may include: operating the at least four switches of the three-level LLC circuit arrangement in a first operating mode when the AC voltage input is within a specified low line voltage range, and operating the at least four switches of the three-level LLC circuit arrangement in a second operating mode when the AC voltage input is within a specified high line voltage range. The first operating mode may include symmetric half bridge (SHB) operation, and the second operating mode may include asymmetric half bridge (AHB) operation.

[0186] The first and second switches of the at least four switches of the three-level LLC circuit arrangement may define a first half-bridge, and the third and fourth switches of the at least four switches of the three-level LLC circuit arrangement may define a second half-bridge. The power supply further includes a fifth switch coupled across the second and third switches to short-circuit the second and third switches when the fifth switch is closed.

[0187] Operating at least four switches of the three-level LLC circuit may include supplying a first control signal to the first switch and the second switch, supplying a second control signal to the third switch and the fourth switch, and opening the fifth switch when operating in the SHB operation mode.

[0188] Operating at least four switches of the three-level LLC circuit may include supplying a first control signal to the first switch and the second switch and supplying a second control signal to the fifth switch while opening the third switch and the fourth switch when operating in the SHB operation mode.

[0189] In some embodiments, operating at least four switches of the three-stage LLC circuit may include: when operating in an AHB operation mode, supplying a control signal to simultaneously turn on a first switch and a third switch, turning on a second switch and a fourth switch in a phase opposite to the first switch and the third switch, and turning on a fifth switch while turning off at least four switches of the three-stage LLC circuit arrangement.

[0190] For the purpose of illustration and description, the foregoing description of the embodiment has been provided. This is not intended to be exhaustive or limit the present invention. Each element or feature of a particular embodiment is generally not limited to the particular embodiment, but when applicable, can be interchangeable and can be used in a selected embodiment, even if not specifically shown or described. Each element or feature of a particular embodiment can also be changed in a variety of ways. These changes should not be considered as departing from the present invention, and all these modifications are intended to be included within the scope of the present invention.

Claims

1. A switch mode power supply comprising: a pair of input terminals for receiving an AC voltage input or a DC voltage input from an input power source; a pair of output terminals, the pair of output terminals being used to supply a DC voltage output to a load; at least four switches coupled in a three-stage LLC circuit arrangement between the pair of input terminals and the pair of output terminals, a first switch and a second switch of the at least four switches defining a first half-bridge, and a third switch and a fourth switch of the at least four switches defining a second half-bridge; a circuit ground, the first half-bridge coupled between the circuit ground and a first input terminal of the pair of input terminals, and the second half-bridge coupled between the circuit ground and a second input terminal of the pair of input terminals; a fifth switch, the fifth switch being connected to both ends of the second switch and the third switch so as to short-circuit the second switch and the third switch when the fifth switch is closed; as well as a control circuit, the control circuit comprising a voltage controlled oscillator, and a plurality of logic gates and a plurality of flip-flops, the voltage controlled oscillator, and the plurality of logic gates and the plurality of flip-flops being coupled to operate the at least four switches using zero voltage switching, Wherein, the three-stage LLC circuit arrangement has three voltage levels, and the three voltage levels include: a first voltage level at the first input terminal of the pair of input terminals; a second voltage level at said circuit ground; and A third voltage level at the second input terminal of the pair of input terminals.

2. The switch mode power supply according to claim 1, further comprising a transformer and a plurality of secondary switches, wherein: The at least four switches in the three-level LLC circuit arrangement are coupled to a primary side of the transformer and the plurality of secondary switches are coupled to a secondary side of the transformer.

3. The switch mode power supply according to claim 2, further comprising: a first capacitor and a first inductor, the first capacitor and the first inductor being coupled between the primary side of the transformer and the first half-bridge; as well as A second capacitor and a second inductor are coupled between the primary side of the transformer and the second half-bridge.

4. A switched mode power supply according to claim 2 or 3, wherein: The control circuit is coupled to operate the plurality of secondary switches utilizing zero voltage switching and zero current switching.

5. The switch mode power supply according to any one of claims 1 to 3, further comprising: A first capacitor and a second capacitor, the first capacitor is coupled between the circuit ground and the first input terminal, and the second capacitor is coupled between the circuit ground and the second input terminal.

6. A switch mode power supply according to claim 5, wherein: A capacitance value of the first capacitor and a capacitance value of the second capacitor are the same so as to evenly divide the voltage input into the first capacitor and the second capacitor.

7. A switched mode power supply according to any one of claims 1 to 3, wherein: The control circuit also includes a compensator, a phase comparator, and a delay circuit, which are coupled to provide a dead time to achieve zero voltage switching of the at least four switches coupled in the three-stage LLC circuit arrangement.

8. A switched mode power supply according to any one of claims 1 to 3, wherein: Only a single fifth switch is coupled across the second switch and the third switch.

9. A switched mode power supply according to any one of claims 1 to 3, wherein: The plurality of flip-flops include at least two D flip-flops, the at least two D flip-flops being coupled to divide the frequency output by the voltage-controlled oscillator into halves; as well as A first pair of logic gates and a second pair of logic gates of the plurality of logic gates are coupled to a first D flip-flop of the at least two D flip-flops to generate a fifty percent duty cycle for controlling the at least four switches coupled in the three-stage LLC circuit arrangement.

10. A switch mode power supply according to claim 9, wherein: A fifth logic gate and a sixth logic gate of the plurality of logic gates are coupled to a second D flip-flop of the at least two D flip-flops to generate a twenty-five percent duty cycle; as well as A seventh logic gate of the plurality of logic gates includes an OR gate coupled to receive outputs of the fifth logic gate and the sixth logic gate to control the fifth switch.

11. A switched mode power supply according to any one of claims 1 to 3, wherein: The control circuit is connected as follows: Simultaneously turning on the first switch and the third switch, and simultaneously turning off the first switch and the third switch; Simultaneously turning on the second switch and the fourth switch, and simultaneously turning off the second switch and the fourth switch; Turning on the fifth switch while turning off the at least four switches; as well as The fifth switch is turned off while the at least four switches are turned on.

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