Storage Devices

Abstract

A novel storage device is provided. N (N is a natural number greater than 2) storage layers including a plurality of storage cells arranged in a matrix are stacked on a driving circuit layer. The storage cell includes two transistors and a capacitor. An oxide semiconductor is used as a semiconductor constituting the transistor. The storage cell is electrically connected to a write word line, a select line, a capacitor line, a write bit line, and a read bit line. By extending the write bit line and the read bit line in the stacking direction, the signal transmission distance between the storage cell and the driving circuit layer is shortened.

Description

Technical Field

[0001] One embodiment of the present invention relates to a storage device, a semiconductor device, or an electronic device using the same.

[0002] However, one embodiment of the present invention is not limited to the above-mentioned technical field. One embodiment of the invention disclosed in this specification, etc., relates to an object, method, or manufacturing method. In addition, one embodiment of the invention disclosed in this specification, etc., relates to a process, machine, product, or composition of matter.

[0003] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. Transistors and semiconductor circuits are one form of semiconductor devices. In addition, display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices are sometimes said to be semiconductor devices. Or, sometimes, it can be said that they include semiconductor devices. Background Art

[0004] In recent years, as the amount of data used increases, semiconductor devices with larger storage capacity are needed. In order to increase the storage capacity per unit area, stacking memory cells is effective (see Patent Document 1 and Patent Document 2). By stacking memory cells, the storage capacity per unit area can be increased according to the number of stacked memory cells.

[0005] [Prior technical literature]

[0006] [Patent Document]

[0007] [Non-patent literature]

[0008] [Patent Document 1] U.S. Patent Application Publication No. 2011 / 0065270A1

[0009] [Patent Document 2] U.S. Patent No. 9634097B2 Summary of the invention

[0010] Technical problem to be solved by the invention

[0011] In Patent Documents 1 and 2, a plurality of memory elements (also referred to as memory cells) are stacked and connected in series to form a memory cell array (also referred to as a memory string) of a three-dimensional structure. On the other hand, in such a memory cell array of a three-dimensional structure, the more stacked memory elements there are, the higher the series resistance between the memory cells, and the higher the resistance of the memory cell array. When the resistance of the memory cell array becomes higher, there are problems such as loss of current flowing through the memory cell array and heat generation of the memory cell array.

[0012] In addition, in Patent Document 1, a semiconductor pattern formed in a columnar shape is in contact with an insulator including a charge accumulation layer. In addition, in Patent Document 2, a semiconductor pattern formed in a columnar shape is in contact with an insulator used as a tunneling medium. When a semiconductor contacts an insulator, a trap center is sometimes formed at their interface. The trap center formed at the interface between the semiconductor and the insulator captures electrons, causing the threshold voltage of the transistor to drift in the positive direction, and thus may have a negative impact on the current driving force of the transistor in the on-state state, that is, the on-state current, field effect mobility or reliability.

[0013] One of the purposes of one embodiment of the present invention is to provide a highly integrated storage device. Another purpose of the present invention is to provide a highly reliable storage device. Another purpose of the present invention is to provide a low power consumption storage device. Another purpose of the present invention is to provide a novel storage device. Another purpose of the present invention is to provide a novel semiconductor device.

[0014] Solutions to technical problems

[0015] Note that the recording of these purposes does not prevent the existence of other purposes. Note that one mode of the present invention does not need to achieve all of the above purposes. Purposes other than the above purposes are obvious from the description of the specification, drawings, claims, etc., and can be extracted from the description.

[0016] N (N is a natural number greater than 2) storage layers including a plurality of storage cells arranged in a matrix are stacked on the driving circuit layer. The storage cell includes two transistors and a capacitor. An oxide semiconductor is used for a semiconductor constituting the transistor. The storage cell is electrically connected to a write word line, a select line, a capacitor line, a write bit line, and a read bit line. By extending the write bit line and the read bit line in the stacking direction, the signal transmission distance between the storage cell and the driving circuit layer is shortened.

[0017] One embodiment of the present invention is a storage device, which includes N (N is a natural number greater than 2) storage layers, a drive circuit layer, a plurality of first wirings, and a plurality of second wirings. The N storage layers are stacked on the drive circuit layer. The drive circuit layer includes a plurality of first circuits. The plurality of first wirings extend in the stacking direction of the N storage layers and are arranged in a matrix of P rows and R columns (P and R are natural numbers greater than 1). The plurality of second wirings extend in the stacking direction and are arranged in a matrix of P rows and Q columns (P and Q are natural numbers greater than 2). Each of the N storage layers includes a plurality of storage cells arranged in a matrix of P rows and Q columns, a third wiring of the Q column, a fourth wiring of the Q column, and a fifth wiring of the Q column. In the kth storage layer, the memory cell in the i-th row and the 2×s-1 column and the memory cell in the i-th row and the 2×s column are electrically connected to the first wiring in the i-th row and the s-th column, and the memory cell in the i-th row and the 2×s-1 column is electrically connected to the second wiring in the i-th row and the 2×s-1 column, the third wiring in the 2×s-1 column, the fourth wiring in the 2×s-1 column, and the fifth wiring in the 2×s-1 column. The first wiring and the second wiring are electrically connected to any one of the plurality of first circuits.

[0018] In addition, as another embodiment of the present invention, in the above-mentioned storage device, the storage unit in the i-th row and the 2×s-1th column includes a first transistor, a second transistor, and a capacitor. One of the source and the drain of the first transistor is electrically connected to the gate of the second transistor and one electrode of the capacitor. The other of the source and the drain of the first transistor is electrically connected to the first wiring. The gate of the first transistor is electrically connected to the third wiring. One of the source and the drain of the first transistor is electrically connected to the fourth wiring. The other of the source and the drain of the first transistor is electrically connected to the second wiring. The other electrode of the capacitor is electrically connected to the fifth wiring.

[0019] In addition, in the above structure, it is preferred that a functional layer is further included between the driving circuit layer and the plurality of storage cells. The functional layer includes a plurality of second circuits. The first wiring and the second wiring may also be electrically connected to the first circuit via any one of the plurality of second circuits.

[0020] At least one of the first transistor and the second transistor preferably includes an oxide in the semiconductor. In addition, the oxide preferably includes any one or both of In and Zn. Alternatively, the oxide preferably includes In, Ga, and Zn.

[0021] In addition, it is preferable that the above-mentioned circuit includes a plurality of transistors, and the plurality of transistors include silicon in a semiconductor.

[0022] Effects of the Invention

[0023] According to one embodiment of the present invention, a highly integrated storage device can be provided. In addition, a highly reliable storage device can be provided. In addition, a low power consumption storage device can be provided. In addition, a novel storage device can be provided. In addition, a novel semiconductor device can be provided.

[0024] Note that the description of these effects does not prevent the existence of other effects. In addition, one mode of the present invention does not need to have all of the above effects. In addition, the description of the specification, drawings, and claims clearly has effects other than the above effects, and effects other than the above effects can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] [Figure 1] Figure 1A and Figure 1B is a diagram showing a configuration example of a storage device.

[0026] [ Figure 2 ] Figure 2 A diagram illustrating a structural example of a driving circuit layer.

[0027] [ Figure 3 ] Figure 3 A diagram illustrating a structural example of a storage layer.

[0028] [ Figure 4 ] Figure 4 The diagram shows a portion of the memory layer and a portion of the driver circuit layer.

[0029] [ Figure 5 ] Figure 5 is a diagram showing a portion of a storage layer.

[0030] [ Figure 6 ] Figure 6 A diagram showing a connection example of a bit line, a memory cell, and an RW circuit.

[0031] [Figure 7] Fig. 7A and Figure 7B is a diagram showing a structural example of a storage unit.

[0032] [Figure 8] Fig. 8A and Figure 8B is a diagram showing a structural example of a storage unit.

[0033] [Figure 9] Fig.9A and Fig. 9B is a diagram showing a multi-gate transistor.

[0034] [ Fig.10 ] Fig.10 It is a timing diagram used to illustrate the operation of a memory cell.

[0035] [Figure 11] Fig.11A and Fig. 11B A diagram for explaining the operation of a memory cell.

[0036] [Figure 12] Fig. 12A and Fig. 12B A diagram for explaining the operation of a memory cell.

[0037] [ Fig.13 ] Fig.13 It is a diagram illustrating a configuration example of a read / write circuit.

[0038] [Figure 14] FIG. 14A to FIG. 14C is a diagram showing a configuration example of a storage device.

[0039] [Figure 15] Fig.15A and Fig. 15B is a diagram showing a configuration example of a storage device.

[0040] [ Fig.16 ] Fig.16 The diagram shows a portion of the memory layer and a portion of the driver circuit layer.

[0041] [ Fig.17 ] Fig.17 2 is a diagram showing a connection example between a bit line and an RW circuit.

[0042] [Figure 18] Fig.18A and Fig.18B is a diagram showing a configuration example of a storage device.

[0043] [ Fig.19 ] Fig.19 The diagram shows a portion of the memory layer, a portion of the functional layer, and a portion of the drive circuit layer.

[0044] [ Fig. 20 ] Fig. 20 A diagram showing a connection example of a bit line, a selection circuit, and an RW circuit.

[0045] [ Fig.21 ] Fig.21 It is a diagram for explaining a configuration example of a selection circuit.

[0046] [Figure 22] Fig.22A and Fig. 22B 1 and 2 are a plan view and a cross-sectional view of a storage device according to one embodiment of the present invention.

[0047] [Figure 23] Fig.23A and Fig. 23B 1 and 2 are a plan view and a cross-sectional view of a storage device according to one embodiment of the present invention.

[0048] [ Fig.24 ] Fig.24This is a top view of a storage device according to one embodiment of the present invention.

[0049] [ Fig.25 ] Fig.25 is a cross-sectional view of a storage device according to one embodiment of the present invention.

[0050] [ Fig.26 ] Fig.26 is a cross-sectional view of a storage device according to one embodiment of the present invention.

[0051] [ Fig. 27 ] Fig. 27 is a cross-sectional view of a storage device according to one embodiment of the present invention.

[0052] [Figure 28] Fig.28A This is a diagram illustrating the classification of the crystal structure of IGZO. Fig.28B is a diagram illustrating the XRD spectrum of quartz glass. Fig.28C This is a diagram illustrating the XRD spectrum of crystalline IGZO.

[0053] [Figure 29] Fig.29A and Fig.29B This is a diagram for explaining an example of an electronic component.

[0054] [ Fig.30 ] Fig.30 It is a diagram for explaining an example of an electronic device.

[0055] [ Fig.31 ] Fig.31 It is a diagram showing various storage devices in a hierarchical manner.

[0056] [Figure 32] FIG. 32A to FIG. 32E A diagram illustrating an application example of a storage device.

[0057] [ Fig.33 ] Fig.33 This is a diagram showing the hierarchical structure of an IoT network and the tendency of requirement specifications.

[0058] [ Fig.34 ] Fig.34 This is a conceptual diagram of factory automation. DETAILED DESCRIPTION

[0059] The embodiments are described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description, and a person skilled in the art can easily understand that the method and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below. Note that in the structure of the invention described below, the same figure mark is used in different drawings to represent the same part or the part with the same function, and its repeated description is omitted.

[0060] In addition, in order to facilitate understanding of the invention, the position, size, range, etc. of each structure shown in the drawings and the like may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like. For example, in an actual manufacturing process, a resist mask and the like may be unintentionally etched due to etching and the like, but for ease of understanding, the illustration is sometimes omitted.

[0061] In addition, in particular, in a top view (also called a plan view) or a perspective view, some components may be omitted for easy understanding of the drawings.

[0062] In addition, in this specification, etc., "electrode" or "wiring" does not limit its constituent elements in terms of function. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" or "wiring" also includes a case where a plurality of "electrodes" or "wiring" are formed as one.

[0063] In this specification, a "terminal" in an electronic circuit refers to a portion that inputs or outputs a current, inputs or outputs a voltage, and / or receives or transmits a signal. Therefore, a portion of a wiring or an electrode may be used as a terminal.

[0064] In addition, in this specification, etc., "above" or "below" is not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, "electrode B on insulating layer A" does not need to form electrode B on insulating layer A in direct contact, and may also include the case where other components are included between insulating layer A and electrode B.

[0065] In addition, since the functions of the "source" and "drain" are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, it is difficult to define which is the "source" and which is the "drain". Therefore, in this specification, the "source" and "drain" can be interchangeable.

[0066] In this specification and the like, when it is clearly stated that “X and Y are connected”, the case disclosed in this specification and the like includes a case where X and Y are electrically connected and a case where X and Y are directly connected.

[0067] Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films and layers, etc.).

[0068] As an example of a case where X and Y are directly connected, there can be cited a case where X and Y are not connected via an element that can electrically connect X and Y (for example, a switch, transistor, capacitor, inductor, resistor, diode, display element, light emitting element, load, etc.).

[0069] As an example of a case where X and Y are electrically connected, for example, one or more elements capable of electrically connecting X and Y (such as switches, transistors, capacitors, inductors, resistors, diodes, display elements, light-emitting elements, and loads, etc.) may be connected between X and Y. In addition, the switch has a function of controlling whether to allow current to flow by controlling to be in a conducting state (on state) or a non-conducting state (off state). Alternatively, the switch has a function of selecting and switching a current path. In addition, the case where X and Y are electrically connected includes the case where X and Y are directly connected.

[0070] In addition, in this specification, "parallel" refers to, for example, a state in which two straight lines are arranged in an angle range of not less than -10° and not more than 10°. Therefore, the case where the angle is not less than -5° and not more than 5° is also included. In addition, "perpendicular" or "orthogonal" refers to, for example, a state in which two straight lines are arranged in an angle range of not less than 80° and not more than 100°. Therefore, the case where the angle is not less than 85° and not more than 95° is also included.

[0071] In addition, in this specification, unless otherwise stated, when "same", "identical", "equal", or "uniform" is mentioned about count values ​​or measured values, a variation of ±20% is included as an error.

[0072] In addition, voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential or source potential, etc.). Therefore, the terms "voltage" and "potential" may sometimes be interchanged. In this specification, unless otherwise specified, voltage and potential are interchangeable.

[0073] Note that, for example, when the conductivity is sufficiently low, even if it is expressed as a "semiconductor", it has the characteristics of an "insulator". Therefore, "insulator" can also be used instead of "semiconductor". In this case, the boundary between "semiconductor" and "insulator" is blurred, so it is difficult to distinguish accurately. Therefore, sometimes the "semiconductor" recorded in this specification can be replaced by "insulator".

[0074] In addition, for example, when the conductivity is sufficiently high, even if it is expressed as a "semiconductor", it has the characteristics of a "conductor". Therefore, "conductor" can also be used instead of "semiconductor". In this case, the boundary between "semiconductor" and "conductor" is blurred, so it is difficult to distinguish accurately. Therefore, sometimes the "semiconductor" recorded in this specification can be replaced by "conductor".

[0075] Ordinal numbers such as "first" and "second" in this specification are used to avoid confusion between constituent elements, and do not indicate an order or sequence such as a process sequence or a stacking sequence. In addition, with respect to words that are not accompanied by ordinal numbers in this specification, ordinal numbers are sometimes added to these words in the claims to avoid confusion between constituent elements. Note that with respect to words that are accompanied by ordinal numbers in this specification, ordinal numbers are sometimes omitted in the claims.

[0076] In addition, in this specification, etc., the "on state" (sometimes abbreviated as "on") of a transistor refers to a state that can be regarded as a state where the source and drain of the transistor are electrically short-circuited (also referred to as "conduction state"). Alternatively, unless otherwise specified, in an n-channel transistor, the "on state" refers to a state where the voltage between the gate and the source (also referred to as "gate voltage" or "Vg") is greater than a threshold voltage (also referred to as "Vth"), and in a p-channel transistor, the "on state" refers to a state where Vg is less than Vth.

[0077] In addition, the "off state" (sometimes abbreviated as "off") of a transistor refers to a state that can be regarded as the source and drain of the transistor being electrically disconnected (also called a "non-conducting state"). Alternatively, unless otherwise specified, in an n-channel transistor, the off state refers to a state in which Vg is lower than Vth, and in a p-channel transistor, the off state refers to a state in which Vg is higher than Vth.

[0078] In this specification, the term "on-state current" sometimes refers to the current flowing between the source and the drain when the transistor is in the on state. In addition, the term "off-state current" sometimes refers to the current flowing between the source and the drain when the transistor is in the off state.

[0079] In addition, in this specification, etc., a high power supply potential VDD (also referred to as "VDD" or "H potential") refers to a power supply potential of a potential higher than a low power supply potential VSS. In addition, a low power supply potential VSS (also referred to as "VSS" or "L potential") refers to a power supply potential of a potential lower than a high power supply potential VDD. In addition, a ground potential may be used as VDD or VSS. For example, when VDD is a ground potential, VSS is a potential lower than the ground potential, and when VSS is a ground potential, VDD is a potential higher than the ground potential.

[0080] In this specification, the term "gate" refers to a part or all of a gate electrode and a gate wiring. A gate wiring refers to a wiring for electrically connecting a gate electrode of at least one transistor to another electrode or another wiring.

[0081] In addition, in this specification, etc., the source refers to a part or all of the source region, source electrode, and source wiring. The source region refers to a region in the semiconductor layer whose resistivity is less than a certain value. The source electrode refers to a portion of the conductive layer connected to the source region. The source wiring refers to wiring for electrically connecting the source electrode of at least one transistor to other electrodes or other wiring.

[0082] In addition, in this specification, etc., the drain refers to a part or all of the drain region, drain electrode, and drain wiring. The drain region refers to a region in the semiconductor layer whose resistivity is less than a certain value. The drain electrode refers to a portion of the conductive layer connected to the drain region. The drain wiring refers to a wiring used to electrically connect the drain electrode of at least one transistor to other electrodes or other wiring.

[0083] (Implementation Method 1)

[0084] A storage device according to one embodiment of the present invention will be described using the drawings. Note that in some drawings, arrows indicating the X direction, the Y direction, and the Z direction are provided. The X direction, the Y direction, and the Z direction are directions that are orthogonal to or intersect with each other.

[0085] Figure 1A and Figure 1B A perspective view of a storage device 100 according to one embodiment of the present invention is shown. The storage device 100 includes a drive circuit layer 110 and N (N is a natural number greater than or equal to 2) storage layers 120. The drive circuit layer 110 includes a plurality of circuits such as a plurality of RW arrays 127. In addition, each storage layer 120 includes a plurality of storage cells 10. Note that Figure 1B In FIG. 1 , the storage layer 120 is represented by a dotted line.

[0086] N memory layers 120 are provided on the driving circuit layer 110. By providing N memory layers 120 on the driving circuit layer 110, the occupied area of ​​the memory device 100 can be reduced. In addition, the storage capacity per unit area can be increased.

[0087] exist Figure 1A , the first storage layer 120 is described as storage layer 120_1, the second storage layer 120 is described as storage layer 120_2, and the third storage layer 120 is described as storage layer 120_3. Similarly, the k-th (k is a natural number greater than or equal to 1) storage layer 120 is described as storage layer 120_k, and the N-th storage layer 120 is described as storage layer 120_N. Note that in this specification, when describing the contents of the N storage layers 120 as a whole or showing the contents common to each layer of the N storage layers 120, sometimes it is simply described as "storage layer 120".

[0088] <Structural Example of Driving Circuit Layer 110>

[0089] An example of the structure of the driving circuit layer 110 will be described. Figure 2 1 is a block diagram illustrating a configuration example of the drive circuit layer 110. The drive circuit layer 110 includes a PSW 141 (power switch), a PSW 142, a peripheral circuit 115, and an RW array 127. The peripheral circuit 115 includes a peripheral circuit 111, a control circuit 112, and a voltage generation circuit 128.

[0090] In the driving circuit layer 110, each circuit, each signal and each voltage can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0091] In addition, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. In addition, signals PON1 and PON2 can also be generated in the control circuit 112.

[0092] The control circuit 112 is a logic circuit that has the function of controlling the overall operation of the driving circuit layer 110. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 100. Alternatively, the control circuit 112 generates a control signal for the peripheral circuit 111 to execute the above operation mode.

[0093] The voltage generating circuit 128 generates a negative voltage (V BG) function. WAKE has a function of controlling the input CLK to the voltage generating circuit 128. For example, when WAKE is supplied with an H level signal, the signal CLK is input to the voltage generating circuit 128, and the voltage generating circuit 128 generates V BG .

[0094] The peripheral circuit 111 is a circuit for writing and reading data from the memory cell 10 , and includes a row decoder 121 , a column decoder 122 , a row driver 123 , a column driver 124 , an input circuit 125 , an output circuit 126 , and an RW array 127 .

[0095] The row decoder 121 and the column decoder 122 have the function of decoding the signal ADDR. The row decoder 121 is a circuit for specifying the row to be accessed by the storage layer 120, and the column decoder 122 is a circuit for specifying the column to be accessed by the storage layer 120. The row driver 123 has the function of selecting the word line of the storage cell 10 connected to the row specified by the row decoder 121 for the storage layer 120 by layer. The column driver 124 has the following functions: the function of writing data into the storage cell 10 of the storage layer 120 through the RW circuit 129 described later; the function of reading data from the storage cell 10 of the storage layer 120 through the RW circuit 129 described later; the function of holding the read data, etc.

[0096] The input circuit 125 has a function of holding a signal WDA. The data held in the input circuit 125 is output to the column driver 124. The output data of the input circuit 125 is data (Din) written to the storage layer 120. The data (Dout) read out from the storage layer 120 by the column driver 124 is output to the output circuit 126. The output circuit 126 has a function of holding Dout. In addition, the output circuit 126 has a function of outputting Dout to the outside of the storage device 100. The data signal output from the output circuit 126 is a signal RDA.

[0097] PSW141 has a function of controlling the supply of VDD to the peripheral circuit 115. PSW142 has a function of controlling the supply of VHM to the row driver 123. Here, the high power supply voltage of the memory device 100 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage used in the memory layer 120, and is sometimes higher than VDD. The on / off of PSW141 is controlled by the signal PON1, and the on / off of PSW142 is controlled by the signal PON2. Figure 2 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 115 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0098] The RW array 127 includes a plurality of read / write circuits (RW circuits 129) arranged in a matrix of P rows and R columns (P and R are natural numbers greater than or equal to 2). Figure 2 In the example above, the RW circuit 129 disposed in the first row and the first column is recorded as RW circuit 129[1,1]. In addition, the RW circuit 129 disposed in the i-th row and the s-th column (i is a natural number greater than 1 and less than P, and s is a natural number greater than 1 and less than R) is recorded as RW circuit 129[i,s]. In addition, the RW circuit 129 disposed in the P-th row and the R-th column is recorded as RW circuit 129[P,R].

[0099] Note that in this specification and the like, when describing the contents of the entire RW circuit 129 or showing the contents common to the RW circuits 129 , the circuit may be simply described as “RW circuit 129 ”.

[0100] The RW circuit 129 is electrically connected to a bit line described later, and has a function of writing data into the memory cell 10 of the memory layer 120 and a function of reading data held in the memory cell 10 .

[0101] <Structural Example of the Storage Layer 120>

[0102] A description will be given of a structural example of N memory layers 120. Each memory layer 120 includes a plurality of memory cells 10 arranged in a matrix of P rows and Q columns (Q is a natural number greater than or equal to 2). Figure 3 This is a block diagram when the k-th memory layer 120 (memory layer 120_k) is viewed from the Z direction. In this specification, the X direction corresponds to the row direction, the Y direction corresponds to the column direction, and the Z direction corresponds to the stacking direction of the memory layer 120 .

[0103] exist Figure 3 In the above, the memory cell 10 disposed in the first row and first column of the k-th memory layer 120 is recorded as the memory cell 10[1,1]_k. In addition, the memory cell 10 disposed in the i-th row and j-th column (j is a natural number greater than 1 and less than Q) of the k-th memory layer 120 is recorded as the memory cell 10[i,j]_k. In addition, the memory cell 10 disposed in the P-th row and Q-th column of the k-th memory layer 120 is recorded as the memory cell 10[P,Q]_k.

[0104] Note that in this specification and the like, when describing the contents of the entire storage unit 10 or showing the contents common to the storage units 10 , the storage unit 10 may be simply described as “the storage unit 10 ”.

[0105] In addition, each layer of the memory layer 120 includes Q word lines WWL, Q capacitor lines CL, and Q selection lines SL. The Q word lines WWL, Q capacitor lines CL, and Q selection lines SL have regions extending in the column direction (Y direction).

[0106] exist Figure 3 In the above description, the word line WWL of the first column in the k-th storage layer 120 is recorded as word line WWL[1]_k. In addition, the word line WWL of the j-th column in the k-th storage layer 120 is recorded as word line WWL[j]_k. In addition, the word line WWL of the Q-th column in the k-th storage layer 120 is recorded as word line WWL[Q]_k. The description of the capacitor line CL and the selection line SL is also the same as that of the word line WWL.

[0107] Note that in this specification, when describing the entire word line WWL or showing the common content between word lines WWL, it may be simply described as “word line WWL.” Other wirings and electrodes other than word line WWL are described similarly.

[0108] In the memory layer 120 — k , the word line WWL arranged in the j-th column, the capacitance line CL arranged in the j-th column, and the selection line SL arranged in the j-th column are electrically connected to the memory cell 10 arranged in the j-th column.

[0109] In addition, generally, a fixed potential is supplied to the capacitor line CL. In the case where a fixed potential is supplied to the capacitor line CL, the capacitor line CL may not extend in the column direction. For example, the capacitor line CL may extend in the row direction. In addition, any plurality of capacitor lines CL may be electrically connected to each other.

[0110] The memory device 100 includes bit lines WBL extending in the Z direction and arranged in a matrix of P rows and R columns, and bit lines RBL extending in the Z direction and arranged in a matrix of P rows and Q columns (see FIG. Figure 3 and Figure 4 ).

[0111] When Q is an odd number, the relationship between R and Q indicating the column position can be expressed using Formula 1 or Formula 2.

[0112] R=(Q+1) / 2···(Formula 1)

[0113] Q=2×R-1···(Formula 2)

[0114] When Q is an even number, the relationship between R and Q indicating the column position can be expressed using Formula 3 or Formula 4.

[0115] R=Q / 2···(Formula 3)

[0116] Q=2×R···(Formula 4)

[0117] The bit line WBL has a region overlapping with the memory layer 120 — k. The bit line RBL has a region overlapping with the memory layer 120 — k.

[0118] exist Figure 3 In the examples, the bit line WBL provided in the i-th row and the s-th column is referred to as the bit line WBL[i,s]. Figure 3 In the above description, the bit line WRBL provided in the i-th row and the j-th column is referred to as the bit line RBL[i,j].

[0119] In the memory layer 120_k, one bit line WBL is electrically connected to two memory cells 10. Specifically, the bit line WBL[i,s] is electrically connected to the memory cell 10[i,2×s-1]_k and the memory cell 10[i,2×s]_k. Figure 3 etc. show the case where j is 2×s-1.

[0120] In addition, in the memory layer 120 — k, the bit line RBL[i,j] is electrically connected to the memory cell 10 [i,j]_k.

[0121] Figure 4 1 is a perspective view showing a portion of the N memory layers 120 and a portion of the driving circuit layer 110 . Figure 5 is a perspective view showing a portion of the N storage layers 120 . Figure 5 An example of the structure of a portion of the storage layer 120_k and a portion of the storage layer 120_k-1 is shown. Figure 6 1 is a diagram showing a connection example of the bit line WBL, the bit line RBL, the memory cell 10 , and the RW circuit 129 .

[0122] The bit line WBL[i,s], the bit line RBL[i,j] and the bit line RBL[i,j+1] are electrically connected to the RW circuit 129[i,s] (see Figure 4 and Figure 6 ). Figure 4 and Figure 6 etc. show the case where j is 2×s-1 and j+1 is 2×s.

[0123] When j is an odd number, the relationship between s and j indicating the column position can be expressed using Formula 5 or Formula 6.

[0124] s=(j+1) / 2···(Formula 5)

[0125] j=2×s-1···(Formula 6)

[0126] When j is an even number, the relationship between s and j indicating the column position can be expressed using Formula 7 or Formula 8.

[0127] s=j / 2···(Formula 7)

[0128] j=2×s···(Formula 8)

[0129] <Configuration Example of Memory Cell 10>

[0130] Next, a configuration example of the memory cell 10 is described. The memory cell 10 includes a transistor 11A, a transistor 11B, and a capacitor 12 (see Fig. 7A ). One of the source and drain of transistor 11A is electrically connected to node FN, the other of the source and drain of transistor 11A is electrically connected to bit line WBL, and the gate of transistor 11A is electrically connected to word line WWL. One of the source and drain of transistor 11B is electrically connected to selection line SL, the other of the source and drain of transistor 11B is electrically connected to bit line RBL, and the gate of transistor 11B is electrically connected to node FN.

[0131] The capacitor 12 is provided between the node FN and the capacitance line CL. Specifically, one electrode of the capacitor 12 is electrically connected to the node FN, and the other electrode of the capacitor 12 is electrically connected to the capacitance line CL.

[0132] As the transistor 11A and the transistor 11B, it is preferable to use a transistor in which an oxide semiconductor, which is one of metal oxides, is used in a semiconductor layer forming a channel (also referred to as an “OS transistor”).

[0133] The off-state current of the OS transistor can be extremely small. Specifically, the off-state current per channel width of 1 μm at room temperature can be less than 1×10 -20 A, preferably less than 1×10 -22 A, more preferably less than 1×10 -24 A.

[0134] In addition, even in a high temperature environment, the off-state current of the OS transistor hardly increases. Specifically, even in an ambient temperature above room temperature and below 200°C, the off-state current hardly increases. By using the OS transistor as a transistor constituting a semiconductor device, a storage device that operates stably and has high reliability even in a high temperature environment can be realized.

[0135] By using an OS transistor as the transistor 11A, the capacitor 12 can be made smaller. Alternatively, a parasitic capacitance of a transistor or the like can be used instead of the capacitor 12, and the capacitor 12 is not provided. As a result, the occupied area of ​​the memory device can be reduced. Note that a memory element formed by using an OS transistor as a transistor constituting a memory cell is sometimes referred to as an "OS memory".

[0136] Since oxide semiconductors can be formed by sputtering or the like, OS transistors can be manufactured by modifying a portion of existing production equipment. Therefore, equipment investment can be suppressed. In addition, in the manufacturing process of the OS transistor, there is no need for an impurity introduction process or the like that is performed in the manufacturing process of transistors that use silicon to form a semiconductor layer of a channel (also referred to as Si transistors). By using OS transistors as transistors constituting the storage layer 120, it is possible to facilitate the realization of multilayering of the storage layer 120.

[0137] In addition, a transistor including a back gate may be used as at least one of the transistor 11A and the transistor 11B. Figure 7B , an example is shown in which both transistors 11A and 11B use transistors including back gates. Figure 7B , an example in which the gate and the back gate of each of the transistor 11A and the transistor 11B are electrically connected is shown.

[0138] The back gate is configured so as to sandwich the channel formation region of the semiconductor layer with the gate. The back gate can play the same role as the gate. In addition, by changing the potential of the back gate, the threshold voltage of the transistor can be changed.

[0139] Since the gate and the back gate are formed by a conductive layer or a semiconductor layer with a low resistivity, they have the function of preventing the electric field generated outside the transistor from affecting the semiconductor layer forming the channel (especially the static electricity shielding function). That is, it is possible to prevent the electrical characteristics of the transistor from changing due to the influence of external electric fields such as static electricity. In addition, by providing a back gate, the change in the threshold voltage of the transistor before and after the BT test can be reduced.

[0140] In addition, if Fig. 8A As shown, the back gate of transistor 11A may be electrically connected to wiring BGL1, and the back gate of transistor 11B may be electrically connected to wiring BGL2. The potential of the back gate may be equal to that of the gate, or may be a ground potential (GND potential) or any other potential.

[0141] In addition, if Figure 8B As shown, the back gate of the transistor 11A and the back gate of the transistor 11B can be electrically connected to the wiring BGL.

[0142] Alternatively, the transistor 11A and the transistor 11B may be dual-gate transistors. Fig.9A An example of a circuit diagram symbol of the dual-gate transistor 21 is shown.

[0143] The transistor 21 has a structure in which a transistor Tr1 and a transistor Tr2 are connected in series. Fig.9AIn FIG. 1 , the following state is shown: one of the source and drain of transistor Tr1 is electrically connected to terminal S, the other of the source and drain of transistor Tr1 is electrically connected to one of the source and drain of transistor Tr2, and the other of the source and drain of transistor Tr2 is electrically connected to terminal D. In addition, in Fig.9A , a state in which the gates of the transistor Tr1 and the transistor Tr2 are electrically connected to each other and to the terminal G is shown.

[0144] Fig.9A The transistor 21 shown has a function of switching the conductive state or non-conductive state between the terminal S and the terminal D by changing the potential of the terminal G. Therefore, although the transistor 21 of the dual-gate transistor includes the transistor Tr1 and the transistor Tr2, it is actually used as one transistor. That is, it can be said that in Fig.9A In the embodiment, one of the source and the drain of the transistor 21 is electrically connected to the terminal S, the other of the source and the drain of the transistor 21 is electrically connected to the terminal D, and the gate of the transistor 21 is electrically connected to the terminal G.

[0145] Alternatively, the transistor 11A and the transistor 11B may be tri-gate transistors. Fig. 9B An example of a circuit diagram symbol of the tri-gate transistor 22 is shown.

[0146] The transistor 22 has a structure in which a transistor Tr1, a transistor Tr2, and a transistor Tr3 are connected in series. Fig. 9B In FIG. 1 , the following state is shown: one of the source and drain of transistor Tr1 is electrically connected to terminal S, the other of the source and drain of transistor Tr1 is electrically connected to one of the source and drain of transistor Tr2, the other of the source and drain of transistor Tr2 is electrically connected to one of the source and drain of transistor Tr3, and the other of the source and drain of transistor Tr3 is electrically connected to terminal D. In addition, in Fig. 9B , a state in which the gates of the transistor Tr1, the transistor Tr2, and the transistor Tr3 are electrically connected to each other and to the terminal G is shown.

[0147] Fig. 9B The transistor 22 shown has a function of switching the conduction state or non-conduction state between the terminal S and the terminal D by changing the potential of the terminal G. Therefore, although the transistor 22 of the three-gate transistor includes the transistor Tr1, the transistor Tr2 and the transistor Tr3, it is actually used as one transistor. That is, it can be said that in Fig. 9B In the embodiment, one of the source and the drain of the transistor 22 is electrically connected to the terminal S, the other of the source and the drain of the transistor 22 is electrically connected to the terminal D, and the gate of the transistor 22 is electrically connected to the terminal G.

[0148] A transistor including a plurality of gates electrically connected to each other, such as the transistor 21 and the transistor 22 , is sometimes referred to as a “multi-gate transistor” or a “multi-gate transistor”.

[0149] <Working Example of Memory Cell 10>

[0150] Next, a description will be given of an example of a data writing operation and a data reading operation of the memory cell 10. In this embodiment, n-channel transistors are used as the transistor 11A and the transistor 11B. Fig.10 It is a timing chart for explaining an example of the operation of the memory cell 10. Fig.11A , Fig. 11B , Fig. 12A and Fig. 12B 1 is a circuit diagram for explaining an operation example of the memory cell 10 .

[0151] In addition, in the drawings, in order to indicate the potential of wiring and electrodes, "H" indicating H potential or "L" indicating L potential is sometimes added to the position adjacent to the wiring and electrode. In addition, "H" or "L" is sometimes added to the wiring and electrode whose potential changes in the form of a frame. In addition, when a transistor is in the off state, the symbol "×" is sometimes added to the transistor in an overlapping manner.

[0152] First, in period T0, word line WWL, bit line WBL and node FN are at L potential, bit line RBL and select line SL are at H potential (see Fig.10 ).

[0153] [Data writing work]

[0154] In period T1, H potential is supplied to word line WWL and bit line WBL (see Fig.10 and Fig.11A ). At this time, the transistor 11A is turned on, and an H potential is written to the node FN as data indicating "1". More specifically, a charge of an amount that makes the potential of the node FN become an H potential is supplied to the node FN.

[0155] The gate, source, and drain of the transistor 11B are all at H potential, and the transistor 11B is in an off state.

[0156] [Keep working]

[0157] In period T2, the word line WWL is supplied with an L potential. At this time, the transistor 11A is turned off, and the data written to the node FN is retained (see Fig.10 and Fig. 11B ).

[0158] As described above, the OS transistor is a transistor with an extremely small off-state current. By using the OS transistor as the transistor 11A, the data written to the node FN can be retained for a long period of time. Therefore, the potential of the node FN does not need to be refreshed, and the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the memory device 100 can be reduced.

[0159] Furthermore, the drain withstand voltage of the OS transistor is higher than that of the Si transistor. Therefore, by using the OS transistor as the transistor 11A, the range of the potential held at the node FN can be expanded. Therefore, the amount of information held at the node FN can be increased.

[0160] [Reading work]

[0161] In period T3, the bit line RBL is precharged to an H potential. That is, the bit line RBL is placed in a floating state while maintaining the H potential (see Fig.10 and Fig. 12A ).

[0162] Next, in period T4, the selection line SL is supplied with an L potential (see Fig.10 and Fig. 12B ). At this time, when the node FN maintains the H potential, the transistor 11B becomes turned on, and the bit line RBL and the selection line SL become conductive. As a result, the potential of the bit line RBL changes from the H potential to the L potential.

[0163] On the other hand, when an L potential is written to the node FN as data indicating "0", the transistor 11B is not turned on even if an L potential is supplied to the selection line SL. Therefore, by detecting a potential change of the bit line RBL when an L potential is supplied to the selection line SL, the data written to the memory cell 10 can be read.

[0164] In the memory cell 10 using the OS transistor, the charge is written to the node FN through the OS transistor, so the high voltage required by the existing flash memory is not required, and high-speed writing operation can be achieved. In addition, charge injection into the floating gate or the charge trapping layer and charge extraction from the floating gate or the charge trapping layer are not performed, so the memory cell 10 using the OS transistor can write and read data indefinitely in essence. Unlike the flash memory, even in the repeated rewriting operation, the instability caused by the increase of the electron capture center in the memory cell 10 using the OS transistor is not observed. Compared with the existing flash memory, the memory cell 10 using the OS transistor has less degradation and can obtain higher reliability.

[0165] In the memory cell 10 using an OS transistor, there is no atomic-level structural change such as in a magnetic memory or a resistive memory. Therefore, the memory cell 10 using an OS transistor has better rewrite endurance than magnetic memories and resistive memories.

[0166] In addition, in the storage device 100 according to one embodiment of the present invention, the memory cell 10 and the RW circuit 129 are electrically connected through bit lines WBL and RBL having regions extending in the Z direction. Therefore, the routing distance of the bit lines WBL and RBL is short, and the wiring resistance and parasitic capacitance are small.

[0167] <Structural example of RW circuit 129>

[0168] In the column driver 124, the RW circuit 129 shown is provided for each column. Fig.13 The RW circuit 129 shown is provided for each column. Fig.13 It is a circuit diagram showing a structural example of the RW circuit 129.

[0169] The RW circuit 129 includes transistors M21 to M26, a sense amplifier circuit 31, an AND circuit 32, analog switches 33 and 34. The RW circuit 129 operates according to signals SEN, SEP, PRE, RSEL, WSEL, GRSEL, and GWSEL.

[0170] Data DIN supplied from the column driver 124 to the RW circuit 129 is written into the memory cell 10 through the bit line WBL electrically connected to the node NW. In addition, data read from the memory cell 10 through the bit line RBL electrically connected to the node NR is output from the RW circuit 129 to the column driver 124 as data DOUT.

[0171] Data DIN and data DOUT are internal signals, corresponding to data signal WDA and data signal RDA, respectively.

[0172] [Precharge circuit]

[0173] The transistor M21 is used as a precharge circuit. The bit line RBL is precharged to the potential VDD by the transistor M21. The signal PRE is a precharge signal, and the on / off state of the transistor M21 is controlled by the signal PRE.

[0174] [Sense amplifier circuit]

[0175] The sense amplifier circuit 31 determines whether the data input to the bit line RBL is high level or low level during the read operation. In addition, the sense amplifier circuit 31 is used as a latch circuit for temporarily holding the input data DIN during the write operation.

[0176] Fig.13The sense amplifier circuit 31 shown is a latch-type sense amplifier. The sense amplifier circuit 31 includes two inverter circuits, and the input node of one inverter circuit is connected to the output node of the other inverter circuit. The input node and the output node of one inverter circuit are respectively referred to as a node NS and a node NSB, and complementary data is held in the node NS and the node NSB.

[0177] Signals SEN and SEP are sense amplifier enable signals for activating sense amplifier circuit 31, and reference potential Vref is a read determination potential. Sense amplifier circuit 31 determines whether the potential of node NSB is high or low when activated based on reference potential Vref.

[0178] AND circuit 32 controls the conduction state between node NS and bit line WBL. In addition, analog switch 33 controls the conduction state between node NSB and bit line RBL, and analog switch 34 controls the conduction state between node NS and a wiring supplying a reference potential Vref.

[0179] The signal WSEL is a write selection signal and controls the AND circuit 32. The signal RSEL is a read selection signal and controls the analog switch 33 and the analog switch 34.

[0180] [Output MUX circuit]

[0181] The transistor M22 and the transistor M23 constitute an output MUX (multiplexer) circuit. The signal GRSEL is a global readout selection signal and controls the output MUX circuit.

[0182] The output MUX circuit has a function of outputting the data DOUT read out from the sense amplifier circuit 31 .

[0183] [Write drive circuit]

[0184] The transistors M24 to M26 constitute a write driver circuit. The signal GWSEL is a global write selection signal and controls the write driver circuit. The write driver circuit has a function of writing input data DIN to the sense amplifier circuit 31.

[0185] The write driver circuit has a function of selecting a column into which data DIN is to be written. The write driver circuit writes data in byte units, half-word units, or one-word units according to a signal GWSEL.

[0186] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0187] (Implementation Method 2)

[0188] In this embodiment, a modified example of the storage device 100 is described. As a modified example of the storage device 100, Fig.14A A storage device 100A is shown. In this embodiment, differences between the storage device 100A and the storage device 100 are described. For matters not described in this embodiment, other embodiments and the like can be referred to.

[0189] <Storage Device 100A>

[0190] The memory device 100A has a structure in which M memory blocks 130 are stacked on a driving circuit layer 110. Fig.14A In the above, the first storage block 130 is recorded as storage block 130_1, the Mth (M is a natural number greater than or equal to 2) storage block 130 is recorded as storage block 130_M, and the tth (t is a natural number greater than or equal to 1 and less than or equal to M) storage block 130 is recorded as storage block 130_t.

[0191] One memory block 130 (for example, memory block 130_t) includes a functional layer 160 having an RW array 127 and R (R is a natural number greater than or equal to 1) memory layers 120. The functional layer 160 can be formed using OS transistors, for example. Fig.14A In the above description, the functional layer 160 included in the memory block 130_1 is referred to as the functional layer 160_1, the functional layer 160 included in the Mth memory block 130 is referred to as the functional layer 160_M, and the functional layer 160 included in the tth memory block 130 is referred to as the functional layer 160_t.

[0192] Fig. 14B 130_t shows an example of the structure of the storage block 130_t. Fig. 14B In the illustrated memory block 130_t, R memory layers 120 are stacked on the functional layer 160. The memory cells 10 included in the R memory layers 120 are electrically connected to the RW array 127 included in the functional layer 160_t through the bit lines WBL and RBL included in the R memory layers 120.

[0193] The N storage layers 120 are divided into a plurality of blocks, and the RW array 127 is set in each block, thereby shortening the bit lines WBL and RBL. By shortening the bit lines WBL and RBL, the signal transmission distance from the storage cell 10 to the RW array 127 becomes shorter, so the operating speed of the storage device can be improved. In addition, the parasitic capacitance of the bit lines WBL and RBL is reduced, so the power consumption can be reduced. In addition, multi-value storage using one storage cell for multi-bit storage can be easily realized. In addition, the RW array 127 has the function of reading the data held by the storage cell 10 or writing the data to the storage cell 10. Note that the circuit included in the functional layer 160 is not limited to the RW array 127, and circuits with various functions can also be set. Therefore, the RW array 127 is sometimes referred to as a functional circuit.

[0194] R, which indicates the number of storage layers 120 included in the storage block 130_t, is preferably a divisor of M, which indicates the total number of storage blocks 130 .

[0195] In addition, if Fig. 14C As shown, the storage layer 120 may be disposed above and below the functional layer 160 . Fig. 14C The example in which two storage layers 120 are provided above and below the functional layer 160 is shown. By configuring a plurality of storage layers 120 in a manner of sandwiching the functional layer 160, the signal transmission distance can be further shortened. Note that the storage layer 120 stacked on the functional layer 160 and the storage layer 120 stacked under the functional layer 160 may be at least one. Fig. 14C Two shown.

[0196] The number of storage layers 120 stacked on the functional layer 160 is preferably equal to the number of storage layers 120 stacked under the functional layer 160. Fig. 14C In the illustrated memory block 130_t, R representing the total number of memory layers 120 is preferably an even number.

[0197] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0198] (Implementation method 3)

[0199] In this embodiment, a modified example of the storage device 100 is described. As a modified example of the storage device 100, Fig.15A The storage device 100B is shown. In this embodiment, differences between the storage device 100B and the storage device 100 are described. For matters not described in this embodiment, other embodiments and the like can be referred to.

[0200] <Storage Device 100B>

[0201] The memory device 100B includes a driving circuit layer 110A instead of the driving circuit layer 110 of the memory device 100 . Fig. 15B 1 is a block diagram illustrating a structural example of the driving circuit layer 110A. The driving circuit layer 110A includes an RW array 127A instead of the RW array 127 of the driving circuit layer 110. The structure of the driving circuit layer 110A other than the RW array 127A is the same as that of the driving circuit layer 110, so detailed description is omitted in this embodiment.

[0202] The RW array 127A includes one RW circuit 129 for each row of memory cells 10. Fig. 15B In the above, the RW circuit 129 in the first row is referred to as RW circuit 129 [1], the RW circuit 129 in the i-th row is referred to as RW circuit 129 [i], and the RW circuit 129 in the P-th row is referred to as RW circuit 129 [P].

[0203] Fig.16 1 is a perspective view showing a portion of the N storage layers 120 and a portion of the drive circuit layer 110A. Fig.17 The diagram shows an example of connection between the RW circuit 129 (RW circuit 129[i]) in the i-th row, the bit line WBL (bit line WBL[i,1] to bit line WBL[i,R]) in the i-th row, and the bit line RBL (bit line RBL[i,1] to bit line RBL[i,Q]) in the i-th row.

[0204] The RW circuit 129 [i] is electrically connected to the bit lines WBL [i, 1] to WBL [i, R] and the bit lines RBL [i, 1] to RBL [i, Q].

[0205] When the structure of the RW array 127A is adopted, the design freedom of the RW circuit 129 can be higher than that of the case where the RW circuit 129 is arranged in a matrix of P rows and Q columns. In addition, since the occupied area of ​​the RW array 127A can be reduced, the design freedom of all circuits included in the driving circuit layer 110A can be improved.

[0206] <Storage Device 100C>

[0207] In the above-mentioned memory device 100B, all the bit lines included in one row are connected to one RW circuit 129, so the load such as wiring capacitance applied to the RW circuit 129 tends to increase. In particular, when the storage capacity of the memory device increases and the number of bit lines included in one row increases, the influence becomes greater, and the data read / write speed or accuracy tends to decrease.

[0208] Therefore, by providing the selection circuit 153 between the memory cell 10 and the RW circuit 129, the number of bit lines WBL and bit lines RBL electrically connected to the RW circuit 129 during the read / write operation is reduced, thereby reducing the load applied to the RW circuit 129.

[0209] Fig.18A A storage device 100C is shown. The storage device 100C is a modified example of the storage device 100B. Therefore, in order to reduce repeated descriptions, the differences between the storage device 100C and the storage device 100B will be described.

[0210] The memory device 100C includes a functional layer 150 between the memory layer 120 and the driving circuit layer 110A. Fig.18B 1 is a block diagram illustrating a configuration example of the functional layer 150. The functional layer 150 includes a control circuit 151 and a selection circuit group 152.

[0211] The selection circuit group 152 includes one selection circuit 153 for each row of memory cells 10. Fig.18B In the above description, the selection circuit 153 in the first row is referred to as the selection circuit 153 [1], the selection circuit 153 in the i-th row is referred to as the selection circuit 153 [i], and the selection circuit 153 in the p-th row is referred to as the selection circuit 153 [P].

[0212] Fig.19 1 is a perspective view showing a portion of the storage layer 120, a portion of the functional layer 150, and a portion of the drive circuit layer 110A. Fig. 20 The diagram shows the RW circuit 129 (RW circuit 129[i]) of the i-th row, the selection circuit 153 (selection circuit 153[i]) of the i-th row, and the bit line WBL ( Fig. 20 The bit lines WBL[i,1] to WBL[i,6] in the i-th row and the bit line RBL( Fig. 20 A diagram of a connection example of bit line RBL[i,1] to bit line RBL[i,12]) in FIG.

[0213] The bit line WBL of the i-th row and the bit line RBL of the i-th row are electrically connected to the selection circuit 153[i]. The selection circuit 153[i] is electrically connected to the RW circuit 129[i] via the wiring 154W[i] and the wiring 154R[i]. The wiring 154W[i] is electrically connected to the node NW of the RW circuit 129[i]. The wiring 154R[i] is electrically connected to the node NR of the RW circuit 129[i] (see Fig.19 ).

[0214] The selection circuit 153 includes G (G is a natural number greater than or equal to 2) switch groups 155. In the present embodiment, the first switch group 155 is referred to as switch group 155[1]. Fig. 20 , switch group 155[2] of the second switch group 155 and switch group 155[3] of the third switch group 155 are shown.

[0215] use Fig.21 The configuration example of the selection circuit 153[i] is described in more detail. As described above, the selection circuit 153[i] includes a plurality of switch groups 155. Fig.21 Two switch groups 155 (switch group 155 [ 1 ] and switch group 155 [ 2 ]) are shown. One switch group 155 includes a plurality of switches 156 . Fig.21 The example in which the switch group 155[1] includes switches 156

[11] to 156

[19] is shown. Similarly, the example in which the switch group 155[2] includes switches 156

[21] to 156

[29] is shown.

[0216] The switch 156

[11] is provided between the bit line WBL[i,1] and the wiring 154W[i]. The switch 156

[12] is provided between the bit line RBL[i,1] and the wiring 154R[i]. The switch 156

[13] is provided between the bit line RBL[i,2] and the wiring 154R[i]. The switch 156

[14] is provided between the bit line WBL[i,2] and the wiring 154W[i]. The switch 156

[15] is provided between the bit line RBL[i,3] and the wiring 154R[i]. The switch 156

[16] is provided between the bit line RBL[i,4] and the wiring 154R[i]. The switch 156

[17] is provided between the bit line WBL[i,3] and the wiring 154W[i]. The switch 156

[18] is provided between the bit line RBL[i,5] and the wiring 154R[i]. The switch 156

[19] is provided between the bit line RBL[i,6] and the wiring 154R[i].

[0217] The control circuit 151 is electrically connected to the peripheral circuit 115. In addition, the control circuit 151 has a function of controlling the operation of the switch group 155[1] through the wiring 157[1]. In other words, the conduction state (on state) and the non-conduction state (off state) of the switches 156

[11] to 156

[19] are controlled according to a signal supplied from the control circuit 151 through the wiring 157[1].

[0218] When a signal for turning on switches 156

[11] to 156

[19] is supplied from control circuit 151 via wiring 157[1], bit lines WBL[i,1] to WBL[i,3] and wiring 154W[i] are turned on. Also, bit lines RBL[i,1] to RBL[i,6] and wiring 154R[i] are turned on.

[0219] The switch 156

[21] is provided between the bit line WBL[i,4] and the wiring 154W[i]. The switch 156

[22] is provided between the bit line RBL[i,7] and the wiring 154R[i]. The switch 156

[23] is provided between the bit line RBL[i,8] and the wiring 154R[i]. The switch 156

[24] is provided between the bit line WBL[i,5] and the wiring 154W[i]. The switch 156

[25] is provided between the bit line RBL[i,9] and the wiring 154R[i]. The switch 156

[26] is provided between the bit line RBL[i,10] and the wiring 154R[i]. The switch 156

[27] is provided between the bit line WBL[i,6] and the wiring 154W[i]. The switch 156

[28] is provided between the bit line RBL[i,11] and the wiring 154R[i]. The switch 156

[29] is provided between the bit line RBL[i,12] and the wiring 154R[i].

[0220] The control circuit 151 has a function of controlling the operation of the switch group 155[2] through the wiring 157[2]. In other words, the conduction state and non-conduction state of the switches 156

[21] to 156

[29] are controlled according to a signal supplied from the control circuit 151 through the wiring 157[2].

[0221] When a signal for turning on switches 156

[21] to 156

[29] is supplied from control circuit 151 via wiring 157[2], bit lines WBL[i,4] to WBL[i,6] and wiring 154W[i] are turned on. Also, bit lines RBL[i,7] to RBL[i,12] and wiring 154R[i] are turned on.

[0222] In addition, the wiring 157 [ 3 ] has a function of transmitting a control signal to a plurality of switches 156 included in a switch group 155 [ 3 ] (not shown).

[0223] The control circuit 151 selects the switch group 155 to be turned on according to the bit line used. For example, when performing a read / write operation of data of the memory cell 10 connected to the bit line RBL[i,7], the control circuit 151 turns on the switch group 155[2] and turns off the other switch groups 155.

[0224] By selecting the switch group 155 to be turned on, the number of bit lines WBL and bit lines RBL electrically connected to the RW circuit 129 in the read / write operation can be reduced. Therefore, the load such as wiring capacitance applied to the RW circuit 129 can be reduced.

[0225] In this embodiment, a structure in which three bit lines WBL and six bit lines RBL are connected to one switch group 155 is shown, but the number of bit lines WBL and bit lines RBL connected to one switch group 155 is not limited thereto. Alternatively, one of the bit lines WBL and bit lines RBL may be electrically connected to the switch group 155 and the other of the bit lines WBL and bit lines RBL may be electrically connected to the RW circuit 129.

[0226] In addition, the number G of the switch groups 155 is preferably a submultiple of the number R of the bit lines WBL included in one row. Alternatively, the number G of the switch groups 155 is preferably a submultiple of the number Q of the bit lines RBL included in one row.

[0227] A switch element such as a MEMS (Micro Electro Mechanical Systems) element or a transistor can be used as the switch 156. When a transistor is used as the switch 156, an OS transistor is preferably used.

[0228] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0229] (Implementation 4)

[0230] Below, using Figures 22 to Fig. 27 An example of the storage device according to the above embodiment will be described. First, a configuration example of a storage cell constituting the storage device will be described.

[0231] <Structure example of storage unit>

[0232] Fig.22A and Fig. 22B The structure of a storage unit 860 constituting a storage device according to one embodiment of the present invention is shown. Fig.22A 8 is a top view of the storage unit 860 and its vicinity. Fig. 22B is a cross-sectional view of a storage unit 860, Fig. 22B Corresponding to Fig.22A The portion indicated by the dot-dash line A1-A2. Fig. 22B 1 and 2 show a cross section of the channel length direction of the transistor 600 and a cross section of the channel width direction of the transistor 700. Fig.22A In the top view, some components are omitted for clarity. Fig.22A The X direction, Y direction and Z direction in the diagram refer to directions that are orthogonal or intersecting with each other. Here, preferably, the X direction and the Y direction are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially perpendicular to the substrate surface.

[0233] The memory cell 860 described in this embodiment includes a transistor 600, a transistor 700, and a capacitor 655. The memory cell 860 corresponds to the memory cell 10 in the above embodiment, and the transistor 600, the transistor 700, and the capacitor 655 correspond to the transistor 11A, the transistor 11B, and the capacitor 12 in the above embodiment, respectively. Therefore, one of the source and the drain of the transistor 600, the gate of the transistor 700, and one electrode of the capacitor 655 are electrically connected.

[0234] like Fig.22A and Fig. 22B As shown, in the memory cell 860, the transistor 600 and the transistor 700 are arranged on the insulator 614, the insulator 680 is arranged on a part of the transistor 600 and the transistor 700, the insulator 682 is arranged on the transistor 600, the transistor 700, and the insulator 680, the insulator 685 is arranged on the insulator 682, the capacitor 655 is arranged on the insulator 685, and the insulator 688 is arranged on the capacitor 655. The insulator 614, the insulator 680, the insulator 682, the insulator 685, and the insulator 688 are used as interlayer films.

[0235] Here, the transistor 600 includes: an insulator 616 on an insulator 614; a conductor 605 (conductor 605a and conductor 605b) arranged in a manner of being buried in the insulator 616; an insulator 622 on the insulator 616 and the conductor 605; an insulator 624 on the insulator 622; an oxide 630a on the insulator 624; an oxide 630b on the oxide 630a; an oxide 643a and an oxide 643b on the oxide 630b; a conductor 642a on the oxide 643a; and a conductor 642b on the oxide 643b. Insulator 672 in contact with a portion of body 624, the side surface of oxide 630a, the side surface of oxide 630b, the side surface of oxide 643a, the side surface of conductor 642a, the top surface of conductor 642a, the side surface of oxide 643b, the side surface of conductor 642b, and the top surface of conductor 642b; insulator 673 on insulator 672; oxide 630c on oxide 630b; insulator 650 on oxide 630c; and conductor 660 (conductor 660a and conductor 660b) on insulator 650 and overlapping with oxide 630c. In addition, oxide 630c is in contact with the side surface of oxide 643a, the side surface of oxide 643b, the side surface of conductor 642a, and the side surface of conductor 642b. Fig. 22B As shown, the top surface of the conductor 660 is arranged to be substantially aligned with the top surfaces of the insulator 650, the oxide 630c, and the insulator 680. In addition, the insulator 682 is in contact with the top surfaces of the conductor 660, the insulator 650, the oxide 630c, and the insulator 680.

[0236] Note that hereinafter, the oxide 630a, the oxide 630b, and the oxide 630c may be collectively referred to as an oxide 630. Also, the oxide 643a and the oxide 643b may be collectively referred to as an oxide 643. Also, the conductor 642a and the conductor 642b may be collectively referred to as a conductor 642.

[0237] In transistor 600, conductor 660 is used as a gate, and conductor 642a and conductor 642b are used as a source or a drain, respectively. In addition, conductor 605 is used as a back gate. In transistor 600, conductor 660 used as a gate is formed in a self-aligned manner to fill an opening formed in insulator 680 or the like. In this way, in the memory device according to this embodiment, conductor 660 can be accurately arranged in the region between conductor 642a and conductor 642b without alignment.

[0238] In addition, the transistor 700 includes: an insulator 616 on the insulator 614; a conductor 705 (conductor 705a and conductor 705b) arranged in a manner buried in the insulator 616; an insulator 622 on the insulator 616 and the conductor 705; an insulator 624 on the insulator 622; an oxide 730a on the insulator 624; an oxide 730b on the oxide 730a; an oxide 743a and an oxide 743b on the oxide 730b; a conductor 742a on the oxide 743a; a conductor 742b on the oxide 743b; and an insulator 624 on the insulator 624. Insulator 672 in contact with a portion of body 624, the side surface of oxide 730a, the side surface of oxide 730b, the side surface of oxide 743a, the side surface of conductor 742a, the top surface of conductor 742a, the side surface of oxide 743b, the side surface of conductor 742b, and the top surface of conductor 742b; insulator 673 on insulator 672; oxide 730c on oxide 730b; insulator 750 on oxide 730c; and conductor 760 (conductor 760a and conductor 760b) on insulator 750 and overlapping with oxide 730c. In addition, oxide 730c is in contact with the side surface of oxide 743a, the side surface of oxide 743b, the side surface of conductor 742a, and the side surface of conductor 742b. Here, as Fig. 22B As shown, the top surface of the conductor 760 is arranged to be substantially aligned with the top surface of the insulator 750, the top surface of the oxide 730c, and the top surface of the insulator 680. In addition, the insulator 682 is in contact with the top surfaces of the conductor 760, the insulator 750, the oxide 730c, and the insulator 680.

[0239] Note that hereinafter, the oxide 730a, the oxide 730b, and the oxide 730c may be collectively referred to as an oxide 730. Also, the oxide 743a and the oxide 743b may be collectively referred to as an oxide 743. Also, the conductor 742a and the conductor 742b may be collectively referred to as a conductor 742.

[0240] In transistor 700, conductor 760 is used as a gate, and conductor 742a and conductor 742b are used as a source or a drain, respectively. In addition, conductor 705 is used as a back gate. In transistor 700, conductor 760 used as a gate is formed in a self-aligned manner to fill an opening formed in insulator 680 or the like. In this way, in the memory device according to this embodiment, conductor 760 can be accurately arranged in the region between conductor 742a and conductor 742b without alignment.

[0241] Here, transistor 700 is formed in the same layer as transistor 600 and has the same structure as transistor 600. Therefore, although not shown in the figure, the cross section of transistor 700 in the channel length direction has the same structure as transistor 600. Fig. 22B The structure of the transistor 600 in the channel length direction is the same as that of the cross section shown in FIG. That is, the oxide 743 and the conductor 742 not shown in the cross section also have the same structure as that of the transistor 600 in the channel length direction. Fig. 22B The oxide 643 and the conductor 642 shown in the figure have the same structure. Although not shown in the figure, the cross section of the transistor 600 in the channel width direction has the same Fig. 22B The cross-section of the transistor 700 shown in the channel width direction has the same structure.

[0242] Therefore, oxide 730 has the same structure as oxide 630, and the description of oxide 630 can be referred to. Conductor 705 has the same structure as conductor 605, and the description of conductor 605 can be referred to. Oxide 743 has the same structure as oxide 643, and the description of oxide 643 can be referred to. Conductor 742 has the same structure as conductor 642, and the description of conductor 642 can be referred to. Insulator 750 has the same structure as insulator 650, and the description of insulator 650 can be referred to. Conductor 760 has the same structure as conductor 660, and the description of conductor 660 can be referred to. Hereinafter, unless otherwise specified, as described above, the structure of transistor 700 can refer to the description of the structure of transistor 600.

[0243] In the transistor 600 and the transistor 700 , a metal oxide used as an oxide semiconductor (hereinafter, sometimes referred to as an oxide semiconductor) is preferably used for the oxide 630 and the oxide 730 including a region where a channel is formed (hereinafter, also referred to as a channel formation region).

[0244] For example, the energy gap of a metal oxide used as an oxide semiconductor is 2 eV or more, preferably 2.5 eV or more. By using a metal oxide having a wide energy gap, leakage current (off-state current) of the transistor 600 in a non-conducting state can be minimized.

[0245] As an oxide semiconductor, for example, a metal oxide such as In-M-Zn oxide (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium) is preferably used. In particular, aluminum, gallium, yttrium or tin is preferably used as the element M. In addition, In-M oxide, In-Zn oxide or M-Zn oxide may also be used as an oxide semiconductor.

[0246] Since the transistor 600 and the transistor 700 using an oxide semiconductor in the channel formation region have an extremely small off-state current, a semiconductor device with low power consumption can be provided. In addition, even in a high temperature environment, the off-state current of the transistor 600 and the transistor 700 hardly increases. Specifically, even at an ambient temperature above room temperature and below 200° C., the off-state current hardly increases. Therefore, a storage device that operates stably and has high reliability even in a high temperature environment can be realized.

[0247] Since the off-state current of the transistor 600 is extremely small, the capacitance value of the capacitor 655 can be set small. As a result, the occupied area of ​​the memory cell 860 can be reduced, and the memory device can be integrated.

[0248] like Fig.22A As shown, the conductor 742a, the conductor 660, the conductor 605, and the conductor 705 preferably extend in the Y direction. By adopting such a structure, the conductor 742a is used as the selection line SL in the above embodiment. In addition, the conductor 660 is used as the word line WWL in the above embodiment. In addition, the conductor 605 is used as the wiring BGL1 in the above embodiment. In addition, the conductor 705 is used as the wiring BGL2 in the above embodiment.

[0249] The capacitor 655 includes a conductor 646a on an insulator 685, an insulator 686 covering the conductor 646a, and a conductor 656 disposed on the insulator 686 so as to overlap at least a portion of the conductor 656. Here, the conductor 646a is used as one electrode of the capacitor 655, and the conductor 646b is used as the other electrode of the capacitor 655. In addition, the insulator 686 is used as a dielectric of the capacitor 655.

[0250] In addition, it is preferable that the conductor 656 is extended in the Y direction and used as the capacitor line CL in the above embodiment.

[0251] In addition, openings are formed in the insulators 622, 624, 672, 673, 680, 682, and 685, and the conductors 640 (conductors 640a, 640b, 640c, and 640d) used as plugs are provided so as to fill the openings. In addition, the insulators 685 and the conductors 640 are provided so that their top surfaces are aligned.

[0252] The bottom surface of the conductor 640a is in contact with the conductor 642a, and the top surface of the conductor 640a is in contact with the conductor 646a. The bottom surface of the conductor 640c is in contact with the conductor 760, and the top surface of the conductor 640c is in contact with the conductor 646a. In this way, one of the source and drain of the transistor 600, the gate of the transistor 700, and one electrode of the capacitor 655 are electrically connected.

[0253] Conductor 640b is provided in contact with the side surface of conductor 642b. Conductor 615 and conductor 607 are provided below conductor 640b, and conductor 646b and conductor 657 are provided above conductor 640b. Conductor 607 is provided in an opening formed in insulator 614. Here, conductor 615 is formed in the same layer as conductor 605 and has the same structure as conductor 605. In addition, conductor 646b is formed in the same layer as conductor 646a and has the same structure as conductor 646a. In addition, conductor 657 is provided in openings formed in insulator 686 and insulator 688.

[0254] The conductor 640b is electrically connected to the conductor 640b of the memory cell 860 in the lower layer through the conductor 607 and the conductor 615. In addition, the conductor 640b is electrically connected to the conductor 640b of the memory cell 860 in the upper layer through the conductor 646b and the conductor 657. In this way, the conductor 607, the conductor 615, the conductor 640b, the conductor 646b, and the conductor 657 extend in the Z direction and are used as the bit line WBL in the above embodiment.

[0255] Although not shown in the cross-sectional view, the conductor 640d is provided in contact with the side surface of the conductor 742b. In addition, the conductor 715 is provided below the conductor 640d. The conductor 640d is electrically connected to the conductors 640d of the upper layer and the lower layer. In this way, the conductor 715 and the conductor 640d extend in the Z direction and are used as the bit line RBL in the above embodiment.

[0256] like Fig. 22BAs shown, by forming the transistor 600 and the transistor 700 in the same layer, the transistor 600 and the transistor 700 can be formed in the same process. Therefore, the manufacturing process of the memory device can be shortened and productivity can be improved.

[0257] Note that in the memory cell 860, the transistor 600, the transistor 700, and the capacitor 655 are arranged so that the channel length direction of the transistor 600 is parallel to the channel length direction of the transistor 700, but the memory device described in this embodiment is not limited to this. The memory cell 860 shown in FIG. 22 and the like is only an example of the structure of the memory device, and a transistor or capacitor having an appropriate structure can be used according to the circuit structure or the driving method.

[0258] [Detailed structure of storage unit]

[0259] Hereinafter, a detailed structure of the memory cell 860 according to one embodiment of the present invention will be described. Hereinafter, the components of the transistor 700 may refer to the description of the components of the transistor 600 .

[0260] As shown in Fig. 22, the oxide 630 preferably includes an oxide 630a on the insulator 624, an oxide 630b on the oxide 630a, and an oxide 630c disposed on the oxide 630b and at least a portion of which is in contact with the top surface of the oxide 630b. Here, the oxide 630c is preferably provided so that its side surface is in contact with the oxide 643a, the oxide 643b, the conductor 642a, the conductor 642b, the insulator 672, the insulator 673, and the insulator 680.

[0261] That is, the oxide 630 includes an oxide 630a, an oxide 630b on the oxide 630a, and an oxide 630c on the oxide 630b. When the oxide 630a is provided under the oxide 630b, it is possible to suppress the diffusion of impurities from the structure formed under the oxide 630a to the oxide 630b. When the oxide 630c is provided on the oxide 630b, it is possible to suppress the diffusion of impurities from the structure formed above the oxide 630c to the oxide 630b.

[0262] Note that in the transistor 600, three layers of oxide 630a, oxide 630b, and oxide 630c are stacked in the channel formation region and its vicinity, but the present invention is not limited to this. For example, a single layer of oxide 630b, a two-layer structure of oxide 630b and oxide 630a, a two-layer structure of oxide 630b and oxide 630c, or a stacked structure of four or more layers may be provided. For example, oxide 630c may also have a two-layer structure to form a four-layer stacked structure.

[0263] In addition, the oxide 630 preferably has a stacked structure composed of oxides having different atomic number ratios of each metal atom. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 630a is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 630b. In addition, the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 630a is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 630b. In addition, the atomic number ratio of In relative to the element M in the metal oxide used for the oxide 630b is preferably greater than the atomic number ratio of In relative to the element M in the metal oxide used for the oxide 630a. In addition, the metal oxide that can be used for the oxide 630a or the oxide 630b can be used for the oxide 630c. In addition, the atomic number ratio of In relative to the element M in the metal oxide used for the oxide 630c is preferably greater than the atomic number ratio of In relative to the element M in the metal oxide used for the oxide 630b.

[0264] Specifically, as the oxide 630 a , a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of 1:1:0.5 [atomic ratio] or a composition close thereto.

[0265] In addition, as the oxide 630b, a metal oxide having a composition of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of 1:1:1 [atomic ratio] or a composition close thereto. In addition, as the oxide 630b, a metal oxide having a composition of In:Ga:Zn=5:1:3 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Ga:Zn=10:1:3 [atomic ratio] or a composition close thereto may be used. In addition, as the oxide 630b, an In-Zn oxide (for example, a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto, In:Zn=5:1 [atomic ratio] or a composition close thereto, or In:Zn=10:1 [atomic ratio] or a composition close thereto) may be used. In oxide may also be used as the oxide 630b.

[0266] In addition, as the oxide 630c, a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio or a composition close thereto], Ga:Zn=2:1 [atomic ratio] or a composition close thereto, or Ga:Zn=2:5 [atomic ratio] or a composition close thereto may be used. In addition, as the oxide 630c, a material that can be used for the oxide 630b may be used, and the oxide 630c may be provided in a single layer or in a stacked layer. For example, as specific examples when the oxide 630c has a stacked structure, there can be cited a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto and In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto, a stacked structure of Ga:Zn=2:1 [atomic ratio] or a composition close thereto and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, a stacked structure of Ga:Zn=2:5 [atomic ratio] or a composition close thereto and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, and a stacked structure of gallium oxide and In:Ga:Zn=4:2:3 [atomic ratio] or a composition close thereto, and the like.

[0267] In addition, in oxide 630b and oxide 630c, increasing the ratio of indium in the film is preferred because the on-state current and field effect mobility of the transistor can be increased. The composition in the vicinity described above includes a range of ±30% of the desired atomic number ratio.

[0268] In addition, the composition of the elements contained in the metal oxide can be changed according to the operating frequency required of the transistor, etc. For example, the composition of the metal oxide of the transistor included in the memory cell can be set to In:Ga:Zn=4:2:3 [atomic ratio] or thereabouts, and the composition of the metal oxide of the transistor included in the driving circuit layer 110 can be set to In:Ga:Zn=5:1:3 [atomic ratio] or thereabouts. Note that the composition of the metal oxide of the transistor included in the driving circuit layer 110 can also be set to In:Ga:Zn=10:1:3 [atomic ratio] or thereabouts or In:Zn=2:1 [atomic ratio] or thereabouts.

[0269] In addition, the oxide 630b may also be crystalline. For example, it is preferable to use the following CAAC-OS (c-axis aligned crystalline oxide semiconductor). Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (oxygen vacancies, etc.). Therefore, it is possible to suppress the source electrode or the drain electrode from extracting oxygen from the oxide 630b. In addition, even if heat treatment is performed, the oxygen extracted from the oxide 630b can be reduced, so the transistor 600 is stable even at high temperatures (so-called thermal budget) in the manufacturing process.

[0270] It is preferable to provide oxide 630c in the opening provided in the interlayer film including insulator 680. Therefore, insulator 650 and conductor 660 include a region overlapping with the stacked structure of oxide 630b and oxide 630a via oxide 630c. By adopting this structure, oxide 630c and insulator 650 can be continuously formed, so that the interface between oxide 630 and insulator 650 can be kept clean. Therefore, the influence of interface scattering on carrier conduction is reduced, so that transistor 600 can obtain large on-state current and high frequency characteristics.

[0271] In addition, it is preferred to use an oxide semiconductor with a low carrier concentration as oxide 630 (for example, oxide 630b). When the purpose is to reduce the carrier concentration of the oxide semiconductor, the impurity concentration in the oxide semiconductor can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, as impurities in the oxide semiconductor, for example, there are hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0272] In particular, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to generate water, thereby sometimes forming an oxygen vacancy (also referred to as V O Furthermore, hydrogen sometimes enters the defect in the oxygen vacancy (hereinafter, sometimes referred to as V O H) is used as a donor to generate electrons as carriers. Sometimes, electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have a normally-on characteristic. In addition, since the hydrogen in the oxide semiconductor is easily moved due to pressure such as heat and electric fields, when the oxide semiconductor contains a large amount of hydrogen, there is also a concern that the reliability of the transistor will decrease.

[0273] V OH will be used as a donor of the oxide semiconductor. However, it is difficult to quantitatively evaluate this defect. Therefore, in oxide semiconductors, sometimes the evaluation is not based on the donor concentration but on the carrier concentration. Therefore, in this specification, etc., sometimes as a parameter of the oxide semiconductor, instead of the donor concentration, the carrier concentration assumed to be in a state where no electric field is applied is used. That is to say, sometimes the "carrier concentration" recorded in this specification, etc. can be replaced by "donor concentration".

[0274] As described above, when an oxide semiconductor is used as the oxide 630, it is preferable to minimize the V O H to make the oxide 630 high purity intrinsic or substantially high purity intrinsic. O To prepare an oxide semiconductor with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen in the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment); and supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxidation treatment). O An oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, and can provide stable electrical characteristics.

[0275] In the oxide 630b, the hydrogen concentration measured by secondary ion mass spectrometry (SIMS) can be less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 By using the oxide 630 in which impurities such as hydrogen are sufficiently reduced in the channel formation region of the transistor 600, a normally-off characteristic can be realized, and stable electrical characteristics and improved reliability can be achieved.

[0276] When an oxide semiconductor is used as the oxide 630, the carrier concentration of the oxide semiconductor in a region used as a channel formation region is preferably 1×10 18 cm -3 Below, more preferably below 1×10 17 cm -3 , and more preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , and more preferably less than 1×1012 cm -3 The lower limit of the carrier concentration of the oxide semiconductor in the region serving as the channel formation region is not particularly limited, and can be set to 1×10 -9 cm -3 .

[0277] Therefore, it is preferable to use a material that suppresses the diffusion of impurities (hereinafter, also referred to as a barrier material to impurities) as the insulator 614, the insulator 622, the insulator 672, the insulator 673, and the insulator 682 to reduce the diffusion of impurities such as hydrogen into the oxide 630. Note that in this specification, etc., barrier property refers to a function of suppressing the diffusion of the corresponding substance (it can also be said that the permeability is low). Alternatively, it refers to a function of capturing and fixing the corresponding substance (also referred to as impurity absorption). In addition, in this specification, etc., an insulating film having a barrier property is sometimes referred to as a blocking insulating film.

[0278] For example, materials having the function of inhibiting the diffusion of hydrogen and oxygen include aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, silicon oxynitride, etc. In particular, silicon nitride or silicon oxynitride has a high barrier property against hydrogen and is therefore preferably used as a sealing material.

[0279] For example, as a material having the function of capturing and fixing hydrogen, there are metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide.

[0280] For example, aluminum oxide or hafnium oxide is preferably used as the insulator 614. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 600 side. Alternatively, diffusion of oxygen included in the insulator 624 or the like to the substrate side can be suppressed.

[0281] The conductor 605 is arranged so as to overlap with the oxide 630 and the conductor 660. In addition, the conductor 605 is preferably provided so as to be embedded in the insulator 616.

[0282] In the case where the conductor 605 is used as a back gate, the threshold voltage (Vth) of the transistor 600 can be controlled by independently changing the potential supplied to the conductor 605 without linking it with the potential applied to the conductor 660. In particular, by applying a negative potential to the conductor 605, the Vth of the transistor 600 can be made larger and the off-state current can be reduced. Therefore, compared with the case where the negative potential is not applied to the conductor 605, when the negative potential is applied to the conductor 605, the drain current when the potential applied to the conductor 660 is 0V can be reduced.

[0283] In addition, if Fig.22AAs shown, the conductor 605 is preferably larger than the area of ​​the oxide 630 that does not overlap with the conductor 642a and the conductor 642b. In particular, the conductor 605 preferably extends to the area outside the end that intersects the channel width direction of the oxide 630. That is, it is preferred that the conductor 605 and the conductor 660 overlap with the insulator on the outside of the side surface in the channel width direction of the oxide 630. Alternatively, by setting the conductor 605 large, local charging (also called charge up) can sometimes be alleviated during the treatment using plasma in the manufacturing process after the conductor 605 is formed. However, one embodiment of the present invention is not limited to this. The conductor 605 at least overlaps with the oxide 630 located between the conductor 642a and the conductor 642b.

[0284] Furthermore, with the bottom surface of the insulator 624 as a reference, the bottom surface of the conductor 660 in the region where the oxide 630 a and the oxide 630 b do not overlap with the conductor 660 is preferably located at a position lower than the bottom surface of the oxide 630 b .

[0285] As shown in the drawings, by making the conductor 660 used as the gate have a structure in which the side and top surfaces of the oxide 630b of the channel formation region are covered via the oxide 630c and the insulator 650, it is easy for the electric field generated from the conductor 660 to act on the entire channel formation region generated in the oxide 630b. Therefore, the on-state current of the transistor 600 can be increased to improve the frequency characteristics. In this specification, the transistor structure in which the channel formation region is electrically surrounded by the electric field of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0286] The conductor 605a is preferably a conductor that inhibits the permeation of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum or tantalum nitride can be used. In addition, the conductor 605b is preferably a conductive material with tungsten, copper or aluminum as a main component. In addition, in the drawings, the conductor 605 is a two-layer structure, but a multilayer structure with three or more layers can also be used.

[0287] In addition, the dielectric constants of the insulators 616, 680, 685, and 688 are preferably lower than the dielectric constant of the insulator 614. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulators 616, 680, 685, and 688, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having pores can be used appropriately.

[0288] For example, the insulator 616, the insulator 680, the insulator 685, and the insulator 688 can be formed by a CVD method or an ALD method using a compound gas containing no hydrogen atoms or containing a small amount of hydrogen atoms.

[0289] For example, when forming the above-mentioned insulating film, a gas containing molecules including silicon atoms is mainly used as a deposition gas. When reducing the hydrogen contained in the above-mentioned insulating film, the hydrogen atoms contained in the molecules containing silicon atoms are preferably small, and more preferably, the molecules containing silicon atoms do not contain hydrogen atoms. Of course, the hydrogen atoms contained in the deposition gas other than the gas containing molecules containing silicon atoms are also preferably small, and more preferably, the film-forming gas does not contain hydrogen atoms.

[0290] In Si x -R y When representing the above-mentioned silicon atom-containing molecule, for example, as the functional group R, an isocyanate group (-N=C=O), a cyanate group (-OC≡N), a cyano group (-C≡N), a diazo group (=N 2 ), azido (-N 3 ), nitroso (-NO) and nitro (-NO 2 ). For example, 1≤x≤3, 1≤y≤8 are satisfied. As such a molecule containing a silicon atom, for example, tetraisocyanatosilane, tetracyanatosilane, tetracyanosilane, hexaisocyanatosilane, octaisocyanatosilane, etc. can be used. Here, a molecule in which a silicon atom is bonded to a functional group of the same type is shown, but the present embodiment is not limited thereto. A structure in which a silicon atom is also bonded to a functional group of a different type may be used.

[0291] In addition, for example, halogen (Cl, Br, I or F) can also be used as the functional group R. For example, 1≤x≤2, 1≤y≤6 can be satisfied. As such a molecule containing silicon atoms, for example, tetrachlorosilane (SiCl 4 ), hexachlorodisilane (Si 2 Cl 6 ) etc. An example using chlorine as a functional group is shown, but halogens such as bromine, iodine, and fluorine other than chlorine may also be used as functional groups. In addition, a structure in which a silicon atom is bonded to a different type of halogen may also be used.

[0292] The insulator 622 and the insulator 624 function as gate insulators.

[0293] Here, in the insulator 624 in contact with the oxide 630, oxygen is preferably removed by heating. In this specification, oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulator 624. By providing an insulator containing excess oxygen in contact with the oxide 630, oxygen vacancies in the oxide 630 can be reduced, thereby improving the reliability of the transistor 600.

[0294] Specifically, an oxide material from which some oxygen is released by heating is preferably used as the insulator 624. An oxide from which oxygen is released by heating means that the amount of oxygen molecules released in thermal desorption spectroscopy (TDS) analysis is 1.0×10 18 molecules / cm 3 Above, preferably 1.0×10 19 molecules / cm 3 More preferably, 2.0×10 19 molecules / cm 3 Above, or 3.0×10 20 molecules / cm 3 In addition, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0295] The insulator 622 is preferably used as a blocking insulating film for suppressing impurities such as water and hydrogen from being mixed into the transistor 600 from the substrate side. For example, the hydrogen permeability of the insulator 622 is preferably lower than that of the insulator 624. By surrounding the insulator 624 and the oxide 630 with the insulator 622 and the insulator 683, impurities such as water and hydrogen can be suppressed from entering the transistor 600 from the outside.

[0296] Furthermore, the insulator 622 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (does not easily allow the above oxygen to pass through). For example, the oxygen permeability of the insulator 622 is preferably lower than that of the insulator 624. By making the insulator 622 have a function of suppressing the diffusion of oxygen or impurities, it is preferable because the diffusion of oxygen contained in the oxide 630 to the bottom of the insulator 622 can be reduced. In addition, the conductor 605 can be suppressed from reacting with oxygen contained in the insulator 624 and the oxide 630.

[0297] The insulator 622 preferably uses an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 622 is formed using such a material, the insulator 622 is used as a layer that suppresses the release of oxygen from the oxide 630 or the entry of impurities such as hydrogen into the oxide 630 from the surrounding part of the transistor 600.

[0298] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, the insulator may be nitrided. Alternatively, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator for use.

[0299] In addition, as the insulator 622, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba,Sr)TiO 3 (BST) and other so-called high-k insulators. When miniaturization and high integration of transistors are carried out, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material as an insulator used as a gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0300] In addition, the insulator 622 and the insulator 624 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure composed of the same material, and a stacked structure composed of different materials may be used.

[0301] In addition, oxide 643 (oxide 643a and oxide 643b) may be arranged between oxide 630b and conductor 642 (conductor 642a and conductor 642b) used as a source electrode or a drain electrode. In this case, conductor 642 and oxide 630 are not in contact, so it is possible to suppress conductor 642 from absorbing oxygen of oxide 630. That is, by preventing oxidation of conductor 642, it is possible to suppress a decrease in the conductivity of conductor 642. Therefore, oxide 643 preferably has a function of suppressing oxidation of conductor 642.

[0302] Therefore, the oxide 643 preferably has a function of suppressing the transmission of oxygen. When the oxide 643 having the function of suppressing the transmission of oxygen is arranged between the conductor 642 used as the source electrode or the drain electrode and the oxide 630b, the resistance between the conductor 642 and the oxide 630b is reduced, so it is preferable. By adopting such a structure, the electrical characteristics of the transistor 600 and the reliability of the transistor 600 can be improved.

[0303] As oxide 643, a metal oxide containing element M can also be used. In particular, aluminum, gallium, yttrium or tin is preferably used as element M. The concentration of element M in oxide 643 is preferably higher than that of oxide 630b. In addition, gallium oxide can also be used as oxide 643. In addition, as oxide 643, metal oxides such as In-M-Zn oxide can also be used. Specifically, the atomic number ratio of element M relative to In in the metal oxide used for oxide 643 is preferably greater than the atomic number ratio of element M relative to In in the metal oxide used for oxide 630b. In addition, the thickness of oxide 643 is preferably greater than 0.5nm and less than 5nm, preferably greater than 1nm and less than 3nm. In addition, oxide 643 preferably has crystallinity. When oxide 643 has crystallinity, the release of oxygen from oxide 630 can be appropriately suppressed. For example, as long as oxide 643 has a crystalline structure such as hexagonal crystal, the release of oxygen from oxide 630 can sometimes be suppressed.

[0304] In addition, the oxide 643 is not necessarily provided. In this case, the conductor 642 (conductor 642a and conductor 642b) is in contact with the oxide 630, and oxygen in the oxide 630 diffuses into the conductor 642, thereby oxidizing the conductor 642. It is highly likely that the conductivity of the conductor 642 decreases due to oxidation. Note that the case where oxygen in the oxide 630 diffuses into the conductor 642 can be replaced by the case where the conductor 642 absorbs oxygen in the oxide 630.

[0305] In addition, when oxygen in the oxide 630 diffuses into the conductor 642 (conductor 642a and conductor 642b), an unnecessary layer may be formed between the conductor 642a and the oxide 630b and between the conductor 642b and the oxide 630b. Since the unnecessary layer contains more oxygen than the conductor 642, it is presumed that the unnecessary layer has insulating properties. At this time, the three-layer structure of the conductor 642, the unnecessary layer and the oxide 630b can be regarded as a three-layer structure composed of metal-insulator-semiconductor, and it is sometimes called a MIS (Metal-Insulator-Semiconductor) structure or a diode junction structure based on the MIS structure.

[0306] Note that the unnecessary layer is not limited to being formed between the conductor 642 and the oxide 630b. For example, the unnecessary layer may be formed between the conductor 642 and the oxide 630c or between the conductor 642 and the oxide 630b and between the conductor 642 and the oxide 630c.

[0307] The conductor 642 (conductor 642a and conductor 642b) used as a source electrode and a drain electrode is provided on the oxide 643. The thickness of the conductor 642 is, for example, not less than 1 nm and not more than 50 nm, and preferably not less than 2 nm and not more than 25 nm.

[0308] As the conductor 642, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferable.

[0309] The insulator 672 is preferably provided in contact with the top surface of the conductor 642 and is used as a blocking insulating film. In addition, an insulator 673 used as a blocking insulating film is preferably provided on the insulator 672. By adopting this structure, it is possible to suppress the conductor 642 from absorbing excess oxygen contained in the insulator 680. In addition, by suppressing the oxidation of the conductor 642, it is possible to suppress the increase in the contact resistance between the transistor 600 and the wiring. Thus, it is possible to give the transistor 600 good electrical characteristics and reliability.

[0310] Therefore, the insulator 672 and the insulator 673 preferably have a function of suppressing the diffusion of oxygen. For example, the insulator 672 preferably has a function of suppressing the diffusion of oxygen more than the insulator 680. As the insulator 672, for example, an insulator containing an oxide of one or both of aluminum and hafnium is preferably formed. In addition, as the insulator 673, for example, silicon nitride or silicon nitride oxide may be used.

[0311] Furthermore, it is possible to suppress the diffusion of impurities such as water and hydrogen from the insulator 680 or the like disposed via the insulator 672 and the insulator 673 toward the transistor 600. In this manner, it is preferable to adopt a structure in which the transistor 600 is surrounded by the insulator 672 and the insulator 673 having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0312] The insulator 650 is used as a gate insulator. The insulator 650 is preferably arranged in contact with the top surface of the oxide 630c. The insulator 650 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide with pores. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0313] As with the insulator 624, the insulator 650 is preferably formed using an insulator that releases oxygen when heated. By providing the insulator 650 as a contact with the top surface of the oxide 630c, oxygen can be effectively supplied to the channel formation region of the oxide 630b. As with the insulator 624, it is preferable to reduce the concentration of impurities such as water or hydrogen in the insulator 650. The thickness of the insulator 650 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

[0314] In addition, a metal oxide may be provided between the insulator 650 and the conductor 660. The metal oxide preferably suppresses diffusion of oxygen from the insulator 650 to the conductor 660. By providing a metal oxide that suppresses diffusion of oxygen, diffusion of oxygen from the insulator 650 to the conductor 660 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 630 can be suppressed. In addition, oxidation of the conductor 660 due to oxygen in the insulator 650 can be suppressed.

[0315] In addition, the metal oxide is sometimes used as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 650, it is preferable to use a metal oxide that is a high-k material with a high relative dielectric constant as the metal oxide. By making the gate insulator have a stacked structure of the insulator 650 and the metal oxide, a stacked structure with thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0316] Specifically, metal oxides containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate), which are insulators containing one or both of aluminum and hafnium oxides, are preferably used.

[0317] Alternatively, the metal oxide is sometimes used as a part of the gate. In this case, it is preferred to arrange the conductive material containing oxygen on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0318] In particular, as a conductor used as a gate, it is preferable to use a conductive material containing a metal element and oxygen contained in a metal oxide forming a channel. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen mixed from an external insulator or the like can sometimes be captured.

[0319] The conductor 660 is arranged so that its bottom surface and side surfaces are in contact with the insulator 650. Although the conductor 660 has a two-layer structure in FIG22 , it may have a single-layer structure or a stacked-layer structure of three or more layers.

[0320] As the conductor 660a, it is preferable to use a conductor having a property of suppressing hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 It is also preferable to use a conductive material having a function of inhibiting the diffusion of impurities such as copper atoms, etc. In addition, it is preferable to use a conductive material having a function of inhibiting the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0321] In addition, when the conductor 660a has a function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 660b by oxygen contained in the insulator 650. As a conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

[0322] In addition, as the conductor 660b, it is preferable to use a conductive material with tungsten, copper or aluminum as a main component. In addition, since the conductor 660 is also used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material with tungsten, copper or aluminum as a main component can be used. In addition, the conductor 660b can have a laminated structure, for example, it can have a laminated structure of titanium or titanium nitride and the above conductive materials.

[0323] For example, the insulator 680 preferably uses silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide with pores. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, materials such as silicon oxide, silicon oxynitride, and silicon oxide with pores are preferred because they easily form regions containing oxygen that is released by heating. In addition, the insulator 680 may also have a structure in which the above materials are stacked, for example, a stacked structure of silicon oxide formed by a sputtering method and silicon oxynitride formed by a CVD method stacked thereon may be used. In addition, silicon nitride may also be stacked thereon.

[0324] Here, the insulator 680 preferably contains excess oxygen. For example, silicon oxide or silicon oxynitride can be appropriately used as the insulator 680. By providing the insulator 680 containing excess oxygen in contact with the oxide 630, oxygen vacancies in the oxide 630 can be reduced, thereby improving the reliability of the transistor 600. In order to make the insulator 680 contain excess oxygen, for example, the insulator 682 can be formed by sputtering in an atmosphere containing oxygen. By forming the insulator 682 by sputtering in an atmosphere containing oxygen, oxygen can be added to the insulator 680 while the film is formed.

[0325] In addition, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 680. In addition, the top surface of the insulator 680 may be planarized.

[0326] The insulator 682 is preferably used as a blocking insulating film for suppressing impurities such as water or hydrogen from being mixed into the insulator 680 from above. In addition, the insulator 682 is preferably used as a blocking insulating film for suppressing the permeation of oxygen. As the insulator 682, for example, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide can be used. For example, as the insulator 682, aluminum oxide having a high barrier property against oxygen can be used.

[0327] like Fig. 22B As shown, the insulator 682 has a structure in direct contact with the oxide 630c. By adopting this structure, it is possible to suppress the diffusion of oxygen contained in the insulator 680 to the conductor 660. Therefore, the oxygen contained in the insulator 680 can be efficiently supplied to the oxide 630a and the oxide 630b through the oxide 630c, thereby reducing oxygen vacancies in the oxide 630a and the oxide 630b to improve the electrical characteristics and reliability of the transistor 600.

[0328] In addition, an insulator 685 used as an interlayer film is preferably provided over the insulator 682. As in the insulator 624 and the like, the concentration of impurities such as water and hydrogen in the insulator 685 is preferably reduced.

[0329] The conductor 640 is preferably a conductive material mainly composed of tungsten, copper or aluminum. In addition, the conductor 640 may also have a laminated structure. Fig.22A In the top view, the conductor 640 has a circular shape, but is not limited to this. For example, in the top view, the conductor 640 may have a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved.

[0330] When the conductor 640 adopts a laminated structure, it is preferable to use a conductive material having a function of inhibiting the permeation of impurities such as water or hydrogen and oxygen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium or ruthenium oxide is preferably used. A conductive material having a function of inhibiting the permeation of impurities such as water or hydrogen and oxygen can be used in a single layer or a laminated layer. By using this conductive material, it is possible to further reduce impurities such as water or hydrogen diffused from the insulator 680 and the like and mixed into the oxide 630 through the conductor 640. In addition, it is possible to prevent oxygen added to the insulator 680 from being absorbed by the conductor 640.

[0331] In addition, the conductor 646a is arranged in contact with the top surface of the conductor 640a and the top surface of the conductor 640c, and the conductor 646b is arranged in contact with the top surface of the conductor 640b. The conductor 646a and the conductor 646b preferably use a conductive material containing tungsten, copper or aluminum as a main component. In addition, the conductor 646a and the conductor 646b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material. In addition, the conductor may be formed in a manner embedded in an opening provided in the insulator.

[0332] The insulator 686 is provided to cover the insulator 685, the conductor 646a, and the conductor 646b. The insulator 686 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or zirconium oxide, and can be provided in a stacked layer or a single layer.

[0333] For example, the insulator 686 may use a laminated structure of a material with a high dielectric withstand voltage such as silicon oxynitride and a high dielectric constant (high-k) material. By adopting this structure, the capacitor 655 may include an insulator with a high dielectric constant (high-k) to ensure sufficient capacitance, and may include an insulator with a high dielectric withstand voltage to improve the dielectric withstand voltage, thereby suppressing electrostatic damage to the capacitor 655.

[0334] Note that insulators that are high dielectric constant (high-k) materials (materials with a relatively high dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0335] Alternatively, as the insulator 686, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba,Sr)TiO 3 (BST) and other high-k materials insulators. For example, when the insulator 686 has a stacked structure, the following structure can be adopted: a three-layer stacked structure in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence; a four-layer structure in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence; etc. In addition, compounds containing hafnium and zirconium can also be used as the insulator 686. With the miniaturization and high integration of semiconductor devices, problems such as leakage current of transistors or capacitors sometimes occur due to the thin filmization of dielectrics used for gate insulators and capacitors. By using a high-k material as an insulator used as a dielectric for a gate insulator and a capacitor, the gate potential when the transistor is working can be reduced while maintaining the physical thickness and ensuring the capacitance of the capacitor.

[0336] On the other hand, materials with high insulating withstand voltage (materials with low relative dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, silicon oxide with pores, or resin.

[0337] The conductor 656 is arranged so as to overlap at least a portion of the conductor 646a via the insulator 686. The conductor 656 that can be used as the conductor 646 can be used.

[0338] In addition, an insulator 688 serving as an interlayer film is preferably provided over the insulator 686 and the conductor 646b. As in the insulator 624 and the like, the concentration of impurities such as water and hydrogen in the insulator 688 is preferably reduced.

[0339] <<Deformation example of storage unit>>

[0340] Hereinafter, a modified example of the memory cell will be described using FIG. 23 . Fig.23A 8 is a top view of the storage unit 860 and its vicinity. Fig. 23B is a cross-sectional view of a storage unit 860, Fig. 23B Corresponding to Fig.23A The portion indicated by the dot-dash line A1-A2. Fig. 23B 1 and 2 show a cross section of the channel length direction of the transistor 600 and a cross section of the channel width direction of the transistor 700. Fig.23A In the top view, some components are omitted for clarity. Fig.23AThe X direction, Y direction and Z direction in the diagram refer to directions that are orthogonal or intersecting with each other. Here, preferably, the X direction and the Y direction are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially perpendicular to the substrate surface.

[0341] Fig.23A and Fig. 23B The storage unit 860 shown is Fig.22A and Fig. 22B The memory cell 860 is different in that transistors 690 and 790 are used instead of transistors 600 and 700. Here, transistor 790 is formed in the same layer as transistor 690 and has the same structure as transistor 690. Hereinafter, the components of transistor 790 may refer to the description of the components of transistor 690.

[0342] The transistor 690 is different from the transistor 600 in that the oxide 630 c is formed in a U-shape along openings formed in the insulator 680 , the insulator 672 , the insulator 673 , the conductor 642 (the conductor 642 a and the conductor 642 b ), and the oxide 630 b .

[0343] For example, when the channel length of the transistor is miniaturized (typically 5 nm or more and less than 60 nm, preferably 10 nm or more and 30 nm or less), the effective L length can be extended by adopting the above structure as the structure of the transistor 600. As an example, when the distance between the conductor 642a and the conductor 642b is 20 nm, the effective L length can be set to 40 nm or more and 60 nm or less, which is the distance between the conductor 642a and the conductor 642b, that is, about twice or more and three times or less of the minimum processing size. Therefore, Fig.23A and Fig. 23B The memory cell 860 shown has a structure including a transistor 690, a transistor 790, and a capacitor 655 which are excellent in miniaturization.

[0344] <<Metal Oxides>>

[0345] As the oxide 630, a metal oxide used as an oxide semiconductor is preferably used. Hereinafter, a metal oxide that can be used for the oxide 630 according to the present invention will be described.

[0346] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it preferably contains gallium, yttrium, tin, etc. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0347] Here, the case where the metal oxide is an In-M-Zn oxide containing indium, element M and zinc is considered. Note that element M is aluminum, gallium, yttrium or tin, etc. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. Note that as element M, a plurality of the above elements may be combined.

[0348] Note that in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide. Alternatively, a metal oxide containing nitrogen may also be referred to as a metal oxynitride.

[0349] [Composition of Metal Oxides]

[0350] Here, CAC-OS (Cloud-Aligned Composite Oxide Semiconductor) or CAC-metal oxide will be described as an example of the configuration of metal oxide.

[0351] CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in another part of the material, and has a semiconductor function as a whole. In addition, when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is to allow electrons (or holes) used as carriers to flow through, and the insulating function is to prevent electrons used as carriers from flowing through. Through the complementary effects of the conductive function and the insulating function, CAC-OS or CAC-metal oxide can have a switching function (a function of controlling on / off). By separating each function in CAC-OS or CAC-metal oxide, each function can be maximized.

[0352] In addition, CAC-OS or CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the function of the above-mentioned conductivity, and the insulating region has the function of the above-mentioned insulation. In addition, in the material, the conductive region and the insulating region are sometimes separated with a nanoparticle level. In addition, the conductive region and the insulating region are sometimes distributed unevenly in the material. In addition, sometimes the conductive region whose edge is fuzzy and connected with a cloud shape is observed.

[0353] In CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm.

[0354] In addition, CAC-OS or CAC-metal oxide is composed of components with different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, when carriers are allowed to flow through, the carriers mainly flow through the component with the narrow gap. In addition, the component with the narrow gap interacts with the component with the narrow gap through the complementary effect with the component with the wide gap, so that the carriers flow through the component with the wide gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current and a high field effect mobility can be obtained in the on-state of the transistor.

[0355] That is, CAC-OS or CAC-metal oxide may also be referred to as a matrix composite material (matrix composite) or a metal matrix composite material (metal matrix composite).

[0356] [Structure of Metal Oxide]

[0357] Oxide semiconductors (metal oxides) are classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0358] When focusing on the crystal structure, oxide semiconductors are sometimes classified into categories different from those described above. Fig.28A The classification of crystal structures in oxide semiconductors will be described. Fig.28A The diagram explains the classification of the crystal structure of an oxide semiconductor, typically IGZO (metal oxide containing In, Ga, and Zn).

[0359] like Fig.28A As shown, IGZO is roughly classified into Amorphous, Crystalline, and Crystal. In addition, completely amorphous is included in Amorphous. In addition, CAAC, nc, and CAC are included in Crystalline. In addition, single crystal and poly crystal are included in Crystal.

[0360] Notice, Fig.28AThe structure in the thick frame is a structure belonging to the New crystalline phase. This structure exists in the boundary region between Amorphous and Crystal. In other words, Amorphous and Crystalline, which are energetically unstable, can be said to be completely different structures.

[0361] Note that the crystal structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) image. Fig.28B and Fig.28C The following shows XRD spectra of quartz glass and IGZO (also referred to as Crystalline IGZO) having a crystal structure classified as Crystalline. Fig.28B and Fig.28C In the figure, the horizontal axis represents 2θ [deg.] and the vertical axis represents intensity [au]. Fig.28B is the XRD spectrum of quartz glass, Fig.28C This is the XRD spectrum of crystalline IGZO. Note that Fig.28C The crystalline IGZO shown has a composition of In:Ga:Zn=4:2:3 [atomic ratio]. Fig.28C The thickness of the crystalline IGZO shown is 500 nm.

[0362] like Fig.28B As shown by the arrows, quartz glass has roughly symmetrical XRD peaks. Fig.28C As shown by the arrow, crystalline IGZO has an asymmetric XRD peak. The asymmetric XRD peak clearly indicates the presence of crystals. In other words, an XRD peak that is not bilaterally symmetric cannot be called amorphous.

[0363] CAAC-OS has c-axis orientation, and its multiple nanocrystals are connected in the ab plane direction and the crystal structure has distortion. Note that distortion refers to the part where the lattice arrangement direction changes between the region where the multiple nanocrystals are connected and the region where the lattice arrangement is consistent.

[0364] Although nanocrystals are basically hexagonal, they are not limited to regular hexagons, and there are cases where they are not regular hexagons. In addition, in the distortion, there is sometimes a lattice arrangement such as a pentagon or a heptagon. In addition, in CAAC-OS, it is difficult to observe a clear grain boundary (also called a grain boundary) even near the distortion. That is, it can be seen that the formation of grain boundaries is suppressed due to the distortion of the lattice arrangement. This is because CAAC-OS can accommodate distortion due to the low density of oxygen atoms arranged in the ab plane direction or the change in the bonding distance between atoms caused by the substitution of metal elements.

[0365] In addition, a crystalline structure in which clear grain boundaries are confirmed is called a so-called polycrystalline (polycrystal). Grain boundaries become recombination centers and carriers are captured, which may lead to a decrease in the on-state current of the transistor, a decrease in field effect mobility, etc. Therefore, CAAC-OS, in which no clear grain boundaries are confirmed, is one of the crystalline oxides that gives the semiconductor layer of the transistor an excellent crystalline structure. Note that in order to form CAAC-OS, a structure containing Zn is preferably used. For example, compared with In oxide, In-Zn oxide and In-Ga-Zn oxide can further suppress the occurrence of grain boundaries, so they are preferred.

[0366] In addition, CAAC-OS tends to have a layered crystalline structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M can replace each other. When indium replaces element M in the (M, Zn) layer, the layer can also be represented as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0367] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is not easy to observe clear grain boundaries in CAAC-OS, so it can be said that the decrease in electron mobility caused by grain boundaries is not easy to occur. In addition, the crystallinity of metal oxides is sometimes reduced due to the entry of impurities or the generation of defects, so it can be said that CAAC-OS is a metal oxide with few impurities or defects (oxygen vacancies, etc.). Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide containing CAAC-OS has high heat resistance and high reliability.

[0368] In nc-OS, the atomic arrangement in a tiny region (e.g., a region between 1 nm and 10 nm, especially a region between 1 nm and 3 nm) is periodic. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductors in some analysis methods.

[0369] In addition, when In-Ga-Zn oxide (hereinafter, IGZO), which is a metal oxide containing indium, gallium and zinc, is the above-mentioned nanocrystal, it may have a stable structure. In particular, since IGZO has a tendency that crystal growth is not easy in the atmosphere, when IGZO is a small crystal (for example, the above-mentioned nanocrystal) than when IGZO is a large crystal (here, a crystal of several mm or a crystal of several cm), it may be structurally stable.

[0370] a-like OS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductor. a-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS.

[0371] Oxide semiconductors (metal oxides) have various structures and various characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0372] [Impurities]

[0373] Here, the influence of each impurity in the metal oxide is described.

[0374] When impurities are mixed into an oxide semiconductor, defect levels or oxygen vacancies are sometimes formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, the electrical characteristics of the transistor using the oxide semiconductor are easily changed and reliability is sometimes reduced. In addition, when the channel formation region includes oxygen vacancies, the transistor is likely to have a normally-on characteristic.

[0375] In addition, the above-mentioned defect energy levels sometimes include trap energy levels. It takes a long time for the charges captured by the trap energy levels of the metal oxide to disappear, and sometimes they behave like fixed charges. Therefore, the electrical characteristics of transistors having metal oxides with high trap state density in the channel formation region are sometimes unstable.

[0376] In addition, when impurities are present in the channel formation region of the oxide semiconductor, the crystallinity of the channel formation region is sometimes reduced, or the crystallinity of the oxide provided in contact with the channel formation region is sometimes reduced. When the crystallinity of the channel formation region is low, there is a tendency for the stability or reliability of the transistor to decrease. In addition, when the crystallinity of the oxide provided in contact with the channel formation region is low, an interface energy level is sometimes formed to reduce the stability or reliability of the transistor.

[0377] Therefore, in order to improve the stability or reliability of the transistor, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity. Examples of the impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0378] Specifically, the concentration of the impurity in the channel formation region of the oxide semiconductor and its vicinity obtained by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably set to 2×10 16 atoms / cm 3Or, the concentration of the impurities in the channel forming region of the oxide semiconductor and its vicinity obtained by elemental analysis using EDX is set to 1.0 atomic% or less. In addition, when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurities in the channel forming region of the oxide semiconductor and its vicinity relative to element M is set to less than 0.10, preferably less than 0.05. Here, the concentration of element M used to calculate the above concentration ratio may be the concentration in the same region as the region where the concentration of the impurities is calculated, or the concentration in the oxide semiconductor.

[0379] Since the defect state density of the metal oxide whose impurity concentration is reduced is low, its trap state density may also be low.

[0380] When hydrogen enters the oxygen vacancy of the metal oxide, the oxygen vacancy and hydrogen sometimes bond to form V O H. Sometimes V O H is used as a donor to generate electrons as carriers. In addition, electrons as carriers may be generated by bonding a part of hydrogen to oxygen bonded to a metal atom.

[0381] Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have a normally-on characteristic. In addition, since hydrogen in an oxide semiconductor easily moves due to pressure such as heat or an electric field, when the oxide semiconductor contains a large amount of hydrogen, there is also a concern that the reliability of the transistor may decrease.

[0382] That is, it is preferred to minimize the amount of V in the metal oxide. O H to make the metal oxide high-purity intrinsic or substantially high-purity intrinsic. O To prepare an oxide semiconductor with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen in the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment); and supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxidation treatment). O An oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, and can provide stable electrical characteristics.

[0383] In addition, it is preferred to use an oxide semiconductor with a low carrier concentration for a transistor. When the purpose is to reduce the carrier concentration of the oxide semiconductor, the impurity concentration in the oxide semiconductor is reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, as impurities in the oxide semiconductor, for example, there are hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc.

[0384] In particular, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, and thus oxygen vacancies are sometimes formed in the oxide semiconductor. In the case where the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor tends to have a normally-on characteristic. Furthermore, sometimes defects in which hydrogen enters the oxygen vacancies are used as donors to generate electrons as carriers. Sometimes, electrons as carriers are generated because a portion of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have normally-on characteristics.

[0385] Hydrogen enters the defect in the oxygen vacancy (V O H) will be used as a donor of the oxide semiconductor. However, it is difficult to quantitatively evaluate this defect. Therefore, in oxide semiconductors, sometimes the evaluation is not based on the donor concentration but on the carrier concentration. Therefore, in this specification, etc., sometimes as a parameter of the oxide semiconductor, instead of the donor concentration, the carrier concentration assumed to be in a state where no electric field is applied is used. In other words, sometimes the "carrier concentration" recorded in this specification, etc. can be replaced by "donor concentration".

[0386] Therefore, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, in the oxide semiconductor film, the hydrogen concentration measured by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , and more preferably less than 1×10 18 atoms / cm 3 By using an oxide semiconductor in which impurities such as hydrogen have been sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be imparted.

[0387] The carrier concentration of the oxide semiconductor in the channel formation region is preferably 1×10 18 cm -3 Below, more preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , more preferably less than 1×10 12 cm -3 In addition, there is no particular limitation on the lower limit of the carrier concentration of the oxide semiconductor in the channel formation region, and it can be, for example, 1×10 -9 cm -3.

[0388] According to one embodiment of the present invention, a semiconductor device with good reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0389] <<Other semiconductor materials>>

[0390] The semiconductor material that can be used for the oxide 630 is not limited to the above-mentioned metal oxides. As the oxide 630, a semiconductor material having a band gap (a semiconductor material that is not a zero-band gap semiconductor) can also be used. For example, semiconductors of a single element such as silicon, compound semiconductors such as gallium arsenide, layered materials used as semiconductors (also referred to as atomic layer materials, two-dimensional materials, etc.), etc. are preferably used as semiconductor materials. In particular, layered materials used as semiconductors are preferably used as semiconductor materials.

[0391] Here, in this specification, etc., a layered material is a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals forces that are weaker than covalent bonds or ionic bonds. A layered material has high conductivity per unit layer, that is, has high two-dimensional conductivity. By using a material that is used as a semiconductor and has high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0392] As layered substances, there are graphene, silicene, chalcogenides, etc. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and lead. In addition, as chalcogenides, transition metal chalcogenides, Group 13 chalcogenides, etc. can be cited.

[0393] As the oxide 630, for example, a transition metal chalcogenide used as a semiconductor is preferably used. Specific examples of the transition metal chalcogenide that can be used as the oxide 630 include molybdenum sulfide (typically MoS 2 ), Molybdenum selenide (typically MoSe 2 ), molybdenum telluride (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten telluride (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2), zirconium sulfide (typically ZrS 2 ), zirconium selenide (typically ZrSe 2 )wait.

[0394] <Structural example of storage unit configuration>

[0395] Next, use Fig.24 and Fig.25 An example of the configuration of the above-mentioned storage unit 860 is described. Fig.24 and Fig.25 A memory cell block including 2×2×2 memory cells 860 is shown. Fig.24 is a top view of the storage unit block. In addition, Fig.25 is a cross-sectional view of a memory cell block, Fig.25 Corresponding to Fig.24 The portion indicated by the dot-dash line B1-B2. Fig.25 1 and 2 show a cross section of the channel length direction of the transistor 600 and a cross section of the channel width direction of the transistor 700. Fig.24 In the top view, some components are omitted for clarity. Fig.24 The X direction, Y direction and Z direction in the diagram refer to directions that are orthogonal or intersecting with each other. Here, preferably, the X direction and the Y direction are parallel or substantially parallel to the substrate surface, and the Z direction is perpendicular or substantially perpendicular to the substrate surface.

[0396] exist Fig.24 and Fig.25 In the illustrated memory cell block, memory cell 860_2 is arranged adjacent to memory cell 860_1 in the X direction. In addition, memory cell 860_3 and memory cell 860_4 are arranged adjacent to memory cell 860_1 and memory cell 860_2 in the Y direction, respectively. In addition, memory cell 860_5 and memory cell 860_6 are arranged adjacent to memory cell 860_1 and memory cell 860_2 in the Z direction, respectively.

[0397] like Fig.24 and Fig.25As shown, the components of the memory cell 860_1 and the memory cell 860_2 can be arranged axially symmetrically. At this time, the side surface of the conductor 640b is preferably in contact with the conductor 642b of the memory cell 860_1 and the conductor 642b of the memory cell 860_2. That is, the conductor 607, the conductor 615, the conductor 640b, the conductor 646b and the conductor 657 used as the bit line WBL are preferably electrically connected to one of the source and drain of the transistor 600 of the memory cell 860_1 and one of the source and drain of the transistor 600 of the memory cell 860_2. In this way, by making the wiring connected to the memory cell 860_1 and the memory cell 860_2 common, the occupied area of ​​the memory cell can be further reduced.

[0398] In addition, if Fig.25 As shown, the conductors 607, 615, 640b, 646b, and 657 used as the bit line WBL are also electrically connected to the transistors 600 arranged in the upper layer, the memory cells 860_5, and the memory cells 860_6. Fig.25 As shown, the conductor 657 of the memory cell 860_1 and the memory cell 860_2 is equivalent to the conductor 607 of the memory cell 860_5 and the memory cell 860_6. In this way, the bit line WBL can be extended in the Z direction. In addition, although not shown in the cross-sectional view, the bit line RBL including the conductor 640d and the like can also be extended in the Z direction.

[0399] In addition, if Fig.24 As shown in FIG. 8 , the conductor 660 of the memory cell 860_1 extends to the memory cell 860_3. In this way, the word line WWL can be extended in the Y direction. Fig.24 As shown in FIG. 8 , the conductor 742 a of the memory cell 860_1 extends to the memory cell 860_3. In this way, the selection line SL can be extended in the Y direction. In addition, the memory cells 860 adjacent to each other in the X direction can also use the selection line SL in common. Fig.24 As shown in FIG. 8 , the conductor 605 of the memory cell 860_1 extends to the memory cell 860_3. In this way, the wiring BGL1 can be extended in the Y direction. Fig.24 As shown, the conductor 705 of the memory cell 860_1 extends to the memory cell 860_3. In this way, the wiring BGL1 can be extended in the Y direction.

[0400] Note that Fig.24In the embodiment, the structure in which the oxide 630c is extended so as to overlap with the conductor 660 is adopted, but the memory device described in this embodiment is not limited to this. For example, a structure in which the oxide 630c is patterned for each memory cell 860 and the oxide 630c is separately provided for each transistor 600 may be adopted. In addition, for example, in the case where the oxide 630c has a two-layer stacked structure, either the upper layer or the lower layer of the oxide 630c may be separately provided for each transistor 600.

[0401] <Configuration Example of Storage Device>

[0402] Next, use Fig.26 An example of a storage device in which the above-described storage unit 860 is stacked will be described. Fig.26 FIG. 8 is a cross-sectional view of a memory device in which a plurality of memory cell layers 870 including memory cells 860 are stacked on a silicon layer 871 . Fig.26 The memory device shown is equivalent to the memory device 100 shown in FIG. 1 and the like, the silicon layer 871 is equivalent to the driving circuit layer 110 , and the memory cell layer 870 is equivalent to the memory layer 120 .

[0403] First, the silicon layer 871 is described. The silicon layer 871 is provided with a plurality of transistors 800, forming Figure 2 The peripheral circuit 115, RW circuit 129, etc. are shown.

[0404] The transistor 800 is disposed on a substrate 811 and includes: a conductor 816 used as a gate, an insulator 815 used as a gate insulator, a semiconductor region 813 formed by a portion of the substrate 811; and a low resistance region 814a and a low resistance region 814b used as a source region or a drain region. The transistor 800 can be a p-channel type or an n-channel type.

[0405] Here, in Fig.26 In the transistor 800 shown, the semiconductor region 813 (a part of the substrate 811) forming the channel has a convex shape. In addition, a conductor 816 is provided in a manner that covers the side and top surfaces of the semiconductor region 813 via an insulator 815. In addition, the conductor 816 can use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 800 is also referred to as a FIN-type transistor. In addition, an insulator having a mask for forming a convex portion in a manner that contacts the upper surface of the convex portion may also be provided. In addition, although a portion of the semiconductor substrate is shown here to be processed to form a convex portion, an SOI substrate may also be processed to form a semiconductor film having a convex shape.

[0406] Notice, Fig.26The structure of the transistor 800 shown is only an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or driving method.

[0407] A wiring layer including an interlayer film, wiring, and plugs may also be provided between each structure. In addition, multiple wiring layers may be provided according to the design. Here, in a conductor having the function of a plug or wiring, the same reference numeral is sometimes used to represent multiple structures. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be a component. That is, a part of the conductor is sometimes used as wiring, and a part of the conductor is sometimes used as a plug.

[0408] For example, an insulator 820, an insulator 822, an insulator 824, and an insulator 826 are sequentially stacked as interlayer films on the transistor 800. In addition, a conductor 828 and a conductor 830 used as a plug or wiring are embedded in the insulator 820, the insulator 822, the insulator 824, and the insulator 826.

[0409] In addition, the insulator used as the interlayer film can be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 822, planarization can also be achieved by planarization treatment using a chemical mechanical polishing (CMP) method or the like.

[0410] A wiring layer may be provided on the insulator 826 and the conductor 830. Fig.26 In the embodiment, an insulator 850, an insulator 852, and an insulator 854 are stacked in this order. In addition, a conductor 856 is formed in the insulator 850, the insulator 852, and the insulator 854. The conductor 856 is used as a plug or wiring.

[0411] Examples of insulators that can be used as the interlayer film include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides that have insulating properties.

[0412] For example, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator.

[0413] For example, an insulator with a low relative dielectric constant is preferably used for insulator 820, insulator 822, insulator 826, insulator 852, and insulator 854. For example, the insulator preferably contains silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide with pores and resin. Since silicon oxide and silicon oxynitride have thermal stability, by combining them with resin, a laminated structure with thermal stability and low relative dielectric constant can be achieved. As resins, for example, polyesters, polyolefins, polyamides (nylon, aromatic polyamide, etc.), polyimides, polycarbonates, or acrylic resins can be cited.

[0414] In addition, by surrounding a transistor using an oxide semiconductor with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, as the insulator 824 and the insulator 850, an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen can be used.

[0415] As an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide, silicon oxynitride or silicon nitride can be used.

[0416] As the conductor that can be used for wiring and plugs, it is preferable to use a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium and ruthenium. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0417] For example, as the conductor 828, the conductor 830, and the conductor 856, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above materials can be used in a single layer or a laminated layer. It is preferred to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferred. Alternatively, it is preferred to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0418] The silicon layer 871 is provided with an insulator 611 and an insulator 612, and the memory cell layers 870_1 to 870_n (n is a natural number greater than 2) are stacked on the insulator 611 and the insulator 612. Although there is no particular limitation, the above n value is greater than 2 and less than 200, preferably greater than 2 and less than 100, and more preferably greater than 2 and less than 10. For example, it may be 1≤n≤10, preferably 1≤n≤50, and more preferably 1≤n≤100.

[0419] In each memory cell layer 870, Fig.24 Likewise, the storage unit 860 and various wiring arrangements are arranged in a matrix. Fig.25 As shown, the memory cell layers 870 adjacent to each other in the stacking direction are electrically connected to each other through wiring such as bit lines WBL and bit lines RBL.

[0420] In addition, if Fig.26 As shown, in the memory cell layer 870_1 at the bottom, the conductor 607 is arranged in a manner embedded in the insulator 611 and the insulator 612. The conductor 607 is in contact with the conductor 857 provided in the same layer as the conductor 856. In this way, the bit line WBL connected to the memory cell 860 is connected to the RW circuit 129 through the conductor 857.

[0421] In addition, the memory cell layers 870_1 to 870_n preferably have a structure sealed by an insulator 611, an insulator 612, an insulator 687, an insulator 683, and an insulator 684. Here, the insulator 611 is arranged on the silicon layer 871, and the insulator 612 is arranged on the insulator 611. The memory cell layers 870_1 to 870_n are arranged on the insulator 612, and the insulator 612 is formed in the same pattern as the memory cell layers 870_1 to 870_n when viewed from above. The insulator 687 is arranged in contact with the top surface of the insulator 611, the side surface of the insulator 612, and the side surface of the memory cell layers 870_1 to 870_n. That is, the insulator 687 is formed in the shape of the side walls of the memory cell layers 870_1 to 870_n. The insulator 683 is disposed so as to cover the insulator 611 , the insulator 687 , and the memory cell layers 870_1 to 870 — n . Furthermore, the insulator 684 is disposed so as to cover the insulator 683 .

[0422] As with the insulator 682 and the like, the insulator 611 , the insulator 612 , the insulator 687 , the insulator 683 , and the insulator 684 are preferably made of a barrier material.

[0423] Here, each memory cell layer 870 is sealed by the insulator 614, the insulator 687, and the insulator 682. Here, the insulator 614, the insulator 687, and the insulator 682 are preferably made of the same material. In addition, the insulator 614, the insulator 687, and the insulator 682 are preferably formed under the same conditions. By making the insulator 614, the insulator 687, and the insulator 682 with equal film properties contact each other, a sealing structure with high sealing performance can be achieved.

[0424] Note that a material having a function of capturing and fixing hydrogen is preferably used for the insulator 614, the insulator 687, and the insulator 682. Specifically, a metal oxide such as aluminum oxide, hafnium oxide, gallium oxide, or indium gallium zinc oxide can be used.

[0425] The insulator 614, the insulator 687, and the insulator 682 forming the sealing structure are provided in contact with the insulator 680. Therefore, by capturing and fixing hydrogen mixed in the insulator 680, the hydrogen concentration of the oxide semiconductor included in the memory cell 860 can be reduced.

[0426] In addition, the insulators 614, 687, and 682 that seal the components of the memory cell layer 870 are also covered by the insulators 611, 612, and 683. For example, Fig.26 As shown, the insulator 611 outside the memory cell layer 870_1 to the memory cell layer 870_n is in contact with the insulator 683 to form a second sealing structure.

[0427] Here, a material having a function of suppressing the diffusion of hydrogen and oxygen is preferably used for the insulators 611, 612, and 683. In particular, silicon nitride or silicon nitride oxide is preferably used as a sealing material because it has a high barrier property against hydrogen.

[0428] In addition, an insulator 684 having high coverage is preferably provided over the insulator 683 covering the upper portion of the transistor 600. In addition, the insulator 684 is preferably made of the same material as the insulator 612 and the insulator 683.

[0429] For example, when the insulator 612 and the insulator 683 are formed by a sputtering method, a sealing structure formed of a film having a low hydrogen concentration can be achieved.

[0430] On the other hand, the coverage of a film formed by a sputtering method is low. Therefore, by forming the insulator 611 and the insulator 684 by a CVD method or the like having high coverage, the sealing property can be further improved.

[0431] Therefore, the hydrogen concentration of the insulator 612 and the insulator 683 is preferably lower than that of the insulator 611 and the insulator 684 .

[0432] Through the above steps, the memory cell layers 870_1 to 870_n are sealed using a barrier insulating film, and hydrogen diffused into the oxide semiconductor in each memory cell 860 can be reduced, so that a memory device with high reliability can be provided.

[0433] Alternatively, a material having a barrier property to oxygen may be used for the insulators 611, 612, 614, 682, 687, 683, and 684. When the sealing structure has a barrier property to oxygen, it is possible to suppress the diffusion of excess oxygen in the insulator 680 to the outside, and to efficiently supply the excess oxygen to the transistor 600.

[0434] In addition, the insulator 674 is preferably configured so as to be embedded in the memory cell layers 870_1 to 870_n and the insulator 684. The insulator 674 can use an insulator that can be used as the insulator 680. Fig.26 As shown, the top surface height of the insulator 674 is preferably substantially consistent with the top surface height of the insulator 684.

[0435] In addition, if Fig.26 As shown, an opening may be formed in the insulator 674, the insulator 684, the insulator 683, and the insulator 611, and a conductor 876 may be arranged in the opening. The bottom surface of the conductor 876 is in contact with the conductor 856. A conductor 878 used as a wiring may be provided in contact with the top surface of the conductor 876. In addition, an insulator 689 used as an interlayer film is provided in a manner covering the memory cell layer 870_n, the insulator 674, and the conductor 878. By adopting such a structure, the upper layer wiring (conductor 878) and the circuit of the silicon layer 871 can be electrically connected without passing through the memory cell layer 870.

[0436] Notice, Fig.26 The structure in which the memory cell layers 870_1 to 870_n are sealed by the insulators 611, 612, 687, 683, and 684 is shown, but the memory device according to this embodiment is not limited thereto. Fig. 27 As shown, a structure may be adopted in which each memory cell layer 870 is sealed by the insulator 611, the insulator 612, the insulator 687, the insulator 683, and the insulator 684. Here, the insulator 612 and the insulator 611 are arranged under the insulator 614.

[0437] Insulator 687 is disposed in contact with the side surfaces of insulator 680, insulator 673, insulator 672, insulator 624, insulator 622, insulator 616, and insulator 614. Insulator 683 is disposed so as to cover insulator 680 and insulator 687, and insulator 684 is disposed on insulator 683. At this time, capacitor 655 and insulator 688 disposed above insulator 682 can be disposed on insulator 684.

[0438] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0439] (Implementation method 5)

[0440] This embodiment mode describes an example of an electronic component and an electronic device in which the storage device or the like described in the above embodiment modes is mounted.

[0441] <Electronic components>

[0442] First, refer to Fig.29A and Fig.29B An example of an electronic component in which the storage device 100 is incorporated will be described.

[0443] Fig.29A The electronic component 710 and a substrate (mounting substrate 704 ) on which the electronic component 710 is mounted are shown in a perspective view. Fig.29A The electronic component 710 shown includes the storage device 100 in a mold 711. Fig.29A 710, a part of the electronic component 710 is omitted in order to show the inside of the electronic component 710. The electronic component 710 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the storage device 100 through a wire 714. The electronic component 710 is mounted on a printed circuit board 702, for example. By combining a plurality of such electronic components and electrically connecting them on the printed circuit board 702, the mounting substrate 704 is completed.

[0444] Fig.29B A perspective view of an electronic component 720 is shown. The electronic component 720 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 720, an interposer 721 is provided on a package substrate 722 (printed circuit board), and a semiconductor device 725 and a plurality of storage devices 100 are provided on the interposer 721.

[0445] An example in which the storage device 100 is used as a high bandwidth memory (HBM) is shown in the electronic component 720. In addition, as the semiconductor device 725, an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used.

[0446] The package substrate 722 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 721 may be a silicon interposer, a resin interposer, or the like.

[0447] The plug board 721 includes a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 721 has the function of electrically connecting the integrated circuit disposed on the plug board 721 to the electrode disposed on the package substrate 722. Therefore, the plug board is sometimes referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 721, and the integrated circuit is electrically connected to the package substrate 722 through the through electrode. In addition, when a silicon plug board is used, TSV (Through Silicon Via: silicon through hole) can also be used as a through electrode.

[0448] A silicon interposer is preferably used as the interposer 721. Since a silicon interposer does not need to be provided with active elements, it can be manufactured at a lower cost than an integrated circuit. On the other hand, the wiring formation of the silicon interposer can be performed in a semiconductor process, so it is easy to form fine wiring that is difficult to form when using a resin interposer.

[0449] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0450] In addition, in SiP or MCM using a silicon interposer, the reliability is not easily reduced due to the difference in expansion coefficient between the integrated circuit and the interposer. In addition, since the surface flatness of the silicon interposer is high, poor connection is not easily generated between the integrated circuit disposed on the silicon interposer and the silicon interposer. In particular, the silicon interposer is preferably used for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged side by side on the interposer.

[0451] Alternatively, a heat sink (heat sink plate) may be provided so as to overlap the electronic component 720. When a heat sink is provided, it is preferable to make the height of the integrated circuits provided on the interposer 721 consistent. For example, in the electronic component 720 shown in this embodiment, it is preferable to make the height of the storage device 100 and the semiconductor device 725 consistent.

[0452] In order to mount the electronic component 720 on another substrate, an electrode 723 may be provided on the bottom of the package substrate 722 . Fig.29B An example of forming the electrode 723 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 722, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 723 can also be formed using conductive pins. By arranging conductive pins in a matrix on the bottom of the package substrate 722, PGA (Pin Grid Array) mounting can be achieved.

[0453] The electronic component 720 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. For example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package) or QFN (Quad Flat Non-leaded package) can be used.

[0454] <Electronic equipment>

[0455] Next, refer to Fig.30 An example of an electronic device in which the above-mentioned electronic components are mounted will be described.

[0456] The robot 7100 includes an illumination sensor, a microphone, a camera, a speaker, a display, various sensors (infrared sensor, ultrasonic sensor, acceleration sensor, piezoelectric sensor, optical sensor, gyro sensor, etc.), a moving mechanism, etc. The electronic component 720 includes a processor, etc. and has a function of controlling these peripheral devices. For example, the electronic component 710 has a function of storing data measured by the sensor.

[0457] The microphone has the function of detecting audio signals such as the user's voice and surrounding sounds. In addition, the speaker has the function of emitting audio signals such as sounds and warning sounds. The robot 7100 can analyze the audio signals input through the microphone and emit the required audio signals from the speaker. The robot 7100 can communicate with the user by using the microphone and the speaker.

[0458] The camera has a function of capturing images of the surroundings of the robot 7100. In addition, the robot 7100 has a function of moving using a moving mechanism. The robot 7100 can capture images of the surroundings using the camera and analyze the images to determine the presence or absence of obstacles during movement.

[0459] The flying object 7120 includes propellers, a camera, a battery, etc., and has an autonomous flight function. The electronic component 720 has a function of controlling these peripheral devices.

[0460] For example, image data captured by a camera is stored in the electronic component 710. The electronic component 720 can analyze the image data to determine the presence or absence of obstacles during movement, etc. In addition, the electronic component 720 can estimate the remaining power of the battery by the change in the battery storage capacity.

[0461] The sweeping robot 7140 includes a display configured on the top surface, multiple cameras configured on the side, a brush, operation buttons, and various sensors, etc. Although not shown in the figure, the sweeping robot 7140 is equipped with tires, a suction port, etc. The sweeping robot 7140 can walk automatically, detect garbage, and suck garbage from the suction port on the bottom surface.

[0462] For example, the electronic component 720 can determine the presence or absence of obstacles such as walls, furniture or steps by analyzing the images taken by the camera. In addition, when objects such as wiring that may be entangled in the brush are detected through image analysis, the rotation of the brush can be stopped.

[0463] The automobile 7160 includes an engine, tires, brakes, a steering device, a camera, etc. For example, the electronic component 720 performs control to optimize the driving state of the automobile 7160 based on data such as navigation information, speed, engine status, gear selection status, brake usage frequency, etc. For example, image data captured by the camera is stored in the electronic component 710.

[0464] The electronic component 710 and / or the electronic component 720 may be installed in a television receiver (TV) device 7200 , a smartphone 7210 , a PC 7220 (personal computer), a PC 7230 , a game console 7240 , a game console 7260 , or the like.

[0465] For example, the electronic component 720 provided in the TV set 7200 may be used as an image engine. For example, the electronic component 720 may perform image processing such as noise removal and up-conversion of resolution.

[0466] The smartphone 7210 is an example of a portable information terminal. The smartphone 7210 includes a microphone, a camera, a speaker, various sensors, and a display portion. The electronic component 720 controls these peripheral devices.

[0467] PC 7220 and PC 7230 are examples of a notebook PC and a desktop PC, respectively. Keyboard 7232 and display device 7233 can be connected to PC 7230 wirelessly or by wire. Game console 7240 is an example of a portable game console. Game console 7260 is an example of a fixed game console. Game console 7260 is connected to controller 7262 wirelessly or by wire. Electronic component 710 and / or electronic component 720 can be installed in controller 7262.

[0468] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0469] (Implementation 6)

[0470] In this embodiment, an application example of a storage device using the storage device described in the above embodiment will be described.

[0471] Generally speaking, in semiconductor devices such as computers, various storage devices are used depending on the application. Fig.31 The hierarchy of various storage devices is shown. The higher the storage device, the faster the access speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density is required. Fig.31 , the memory installed together as registers in a CPU or other arithmetic processing device, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory are shown in order from the top layer.

[0472] Since the memory installed together with the register in the CPU and other processing devices is used for temporary storage of the calculation results, the access frequency from the processing devices is high. Therefore, the operation speed is required to be faster than the storage capacity. In addition, the register has the function of holding the setting information of the processing device.

[0473] SRAM is used for cache, for example. Cache has the function of copying and holding a part of the information held in the main memory. By copying frequently used data to the cache, the speed of accessing the data can be increased.

[0474] DRAM is used for main memory, for example. The main memory has the function of holding programs or data read from storage. The recording density of DRAM is about 0.1 to 0.3 Gbit / mm 2 .

[0475] 3D NAND memory is used for storage, for example. Storage has the function of maintaining data that needs to be stored for a long time and various programs used by the operation processing device. Therefore, compared with a faster working speed, storage requires a larger storage capacity and a higher recording density. The recording density of the storage device used for storage is about 0.6 to 6.0 Gbit / mm 2 .

[0476] The storage device of one embodiment of the present invention has a high operating speed and can retain data for a long period of time. The storage device of one embodiment of the present invention can be used as a storage device located in a boundary area 901 between a layer including a cache and a layer including a main memory. In addition, the storage device of one embodiment of the present invention can be used as a storage device located in a boundary area 902 between a layer including a main memory and a layer including a storage.

[0477] The storage device described in the above embodiment can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smart phones, e-book reader terminals, digital cameras, video playback devices, navigation systems, game consoles, etc.). In addition, it can be used for image sensors, IoT (Internet of Things), medical treatment, etc. Note that here, the computer includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0478] Alternatively, the storage device described in the above embodiment is applied to various removable storage devices such as a memory card (eg, an SD card), a USB memory, and an SSD (solid state drive). FIG. 32A to FIG. 32E Several structural examples of the removable storage device are schematically shown. For example, the storage device shown in the above embodiment is processed into a packaged memory chip and used in various storage devices or removable memories.

[0479] Fig.32A 11 is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is accommodated in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. The semiconductor device described in the above embodiment can be assembled with the memory chip 1105 on the substrate 1104.

[0480] Fig.32B This is a schematic diagram of the appearance of an SD card. Fig.32C11 is a schematic diagram of the internal structure of the SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is accommodated in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. In addition, a wireless chip with a wireless communication function can also be provided on the substrate 1113. Thus, data of the memory chip 1114 can be read and written through wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be assembled on the memory chip 1114 on the substrate 1113, etc.

[0481] Fig.32D This is a schematic diagram of the appearance of SSD. Fig.32E 1150 is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is accommodated in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 is a working memory of the controller chip 1156, and a DOSRAM chip can be used, for example. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the above embodiment can be assembled with the memory chip 1154 on the substrate 1153, etc.

[0482] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0483] [Example]

[0484] By using the memory cell or memory device described in this specification, etc., a normally-off CPU (also referred to as "Noff-CPU") can be realized. A Noff-CPU refers to an integrated circuit including a normally-off transistor that is in a non-conductive state (also referred to as an off state) even when the gate voltage is 0 V. The normally-off transistor can be realized by using an OS transistor.

[0485] In Noff-CPU, it is possible to stop supplying power to a circuit that does not need to work in Noff-CPU, and put the circuit in standby mode. In a circuit in standby mode when power is stopped, no power is consumed. Therefore, Noff-CPU can minimize power consumption. In addition, even if power is stopped, Noff-CPU can maintain information required for work such as setting conditions for a long time. When recovering from standby mode, it is sufficient to start supplying power to the circuit again without having to rewrite setting conditions. In other words, it is possible to recover from standby mode at high speed. In this way, Noff-CPU can reduce power consumption without significantly reducing operating speed.

[0486] Noff-CPU can be used in small-scale systems such as IoT terminal devices ("also called endpoint microcomputers") 803 in the IoT field. Fig.33 The hierarchical structure of the IoT network and the trend of the requirements specification are shown. Fig.33 , power consumption 804 and processing performance 805 are shown as required specifications. The hierarchical structure of the IoT network is roughly divided into an upper cloud domain 801 and a lower embedded domain 802. For example, servers are included in the cloud domain 801. For example, machinery, industrial robots, vehicle-mounted equipment, home appliances, etc. are included in the embedded domain 802.

[0487] The higher the level, the higher the requirement for high processing performance than for low power consumption. Therefore, in the cloud domain 801, high-performance CPUs, high-performance GPUs, and large-scale SoCs (System on a Chip) are used. In addition, the lower the level, the higher the requirement for low power consumption than for high processing performance, and the number of devices increases dramatically.

[0488] In addition, "endpoint" refers to a terminal area of ​​the embedded field 802. For example, a microcomputer used in factories, home appliances, infrastructure, agriculture, etc. corresponds to a device used in an endpoint.

[0489] exist Fig.34 In the figure, a schematic diagram of factory automation is shown as an application example of an endpoint microcomputer. Factory 884 is connected to cloud 883 via an Internet cable. In addition, cloud 883 is connected to home 881 and company 882 via an Internet cable. The Internet cable can be either a wired communication method or a wireless communication method. For example, in the case of a wireless communication method, a fourth generation mobile communication system (4G) or a fifth generation mobile communication system (5G) can be used. Factory 884 can be connected to factory 885 and factory 886 via an Internet cable.

[0490] The factory 884 includes a main device (control device) 831. The main device 831 has a function of connecting to the cloud 883 to send and receive information. In addition, the main device 831 is connected to a plurality of industrial robots 842 included in the IoT terminal device 841 via an M2M (machine to machine) interface 832. As the M2M interface 832, for example, industrial Ethernet, which is one of the wired communication methods, or local 5G (Local5G), which is one of the wireless communication methods, can be used.

[0491] The manager of the factory can connect to the factory 884 via the cloud 883 at home 881 or at work 882 to check the working status, etc. In addition, it is possible to check for errors and shortages of products, indicate where to place them, and measure takt time, etc.

[0492] In recent years, IoT has been introduced into factories around the world under the impetus of "smart factories". As an example of smart factories, there are known cases where endpoint microcomputers are used not only for inspection and monitoring, but also for fault detection and abnormality prediction.

[0493] In small-scale systems such as endpoint microcomputers, the overall power consumption of the system is often low when operating, so the power reduction effect of the Noff-CPU in the standby state becomes greater. On the other hand, the embedded field of IoT sometimes requires fast response capabilities, and the use of Noff-CPU can quickly recover from the standby state.

[0494] [Explanation of symbols]

[0495] 10: memory cell, 11A: transistor, 11B: transistor, 12: capacitor, 21: transistor, 22: transistor, 31: sense amplifier circuit, 32: AND circuit, 33: analog switch, 34: analog switch, 100: memory device, 110: drive circuit layer, 111: peripheral circuit, 112: control circuit, 115: peripheral circuit, 120: memory layer, 121: row decoder, 122: column decoder, 123: row driver, 124: column driver, 125: input circuit, 126: output circuit, 127: RW array, 128: voltage generation circuit, 129: RW circuit, 141: PSW, 142: PSW

Claims

1. A storage device, include: N storage layers; Driving circuit layer; a plurality of first wirings; as well as a plurality of second wirings, Where N is a natural number greater than 2. The N storage layers are stacked on the driving circuit layer, The driving circuit layer includes a plurality of first circuits. The plurality of first wirings extend in the stacking direction of the N memory layers and are arranged in a matrix of P rows and R columns, where P and R are each a natural number greater than 2. The plurality of second wirings extend in the stacking direction and are arranged in a matrix of P rows and Q columns, where Q is a natural number greater than or equal to 2. Each of the N storage layers includes: A plurality of storage units arranged in a matrix of P rows and Q columns; The third wiring of the Q column; A fourth wiring of the Q column; and The fifth wiring of the Q column, In the storage layer at the kth layer, The memory cell at the i-th row and the 2×s-1-th column and the memory cell at the i-th row and the 2×s-th column are electrically connected to the first wiring at the i-th row and the s-th column. The memory cell in the i-th row and the 2×s-1-th column is electrically connected to the second wiring in the i-th row and the 2×s-1-th column, the third wiring in the 2×s-1-th column, the fourth wiring in the 2×s-1-th column, and the fifth wiring in the 2×s-1-th column, Furthermore, the first wiring at the i-th row and the s-th column and the second wiring at the i-th row and the 2×s-1-th column are electrically connected to one of the plurality of first circuits.

2. The storage device according to claim 1, The storage unit at the i-th row and the 2×s-1-th column comprises a first transistor, a second transistor and a capacitor. One of the source and the drain of the first transistor is electrically connected to the gate of the second transistor and one electrode of the capacitor, The other of the source and the drain of the first transistor is electrically connected to the first wiring, The gate of the first transistor is electrically connected to the third wiring, One of a source and a drain of the second transistor is electrically connected to the fourth wiring, The other of the source and the drain of the second transistor is electrically connected to the second wiring, and the other electrode of the capacitor is electrically connected to the fifth wiring.

3. The storage device according to claim 1 or 2, A functional layer is further included between the driving circuit layer and the plurality of storage units.

4. The storage device according to claim 3, wherein the functional layer comprises a plurality of second circuits, And the first wiring and the second wiring are electrically connected to the one of the plurality of first circuits through one of the plurality of second circuits.

5. The storage device according to claim 2, At least one of the first transistor and the second transistor includes an oxide in a semiconductor.

6. The storage device according to claim 5, The oxide contains one or both of In and Zn.

7. The storage device according to claim 5, The oxide includes In, Ga and Zn.

8. The storage device according to any one of claims 1, 2, 4, 5, 6 and 7, wherein said one of said plurality of first circuits comprises a plurality of transistors, Furthermore, each of the plurality of transistors includes silicon in a semiconductor.

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