Display device and method of manufacturing the same

Abstract

A display device according to an embodiment of the present invention includes pixels arranged in a display area. Each of the pixels includes: a first sub-area and a second sub-area, arranged sequentially along a first direction; a first electrode and a second electrode of a first level, spaced apart from each other in the first sub-area; a first light-emitting element, arranged in parallel between the first electrode and the second electrode of the first level; a first contact electrode and a second contact electrode of the first level, respectively arranged on the first electrode and the second electrode of the first level, and electrically connecting the first light-emitting element between the first electrode and the second electrode of the first level; a first electrode and a second electrode of the second level, spaced apart from each other in the second sub-area; a second light-emitting element, arranged in parallel between the first electrode and the second electrode of the second level; a first contact electrode and a second contact electrode of the second level, respectively arranged on the first electrode and the second electrode of the second level, and electrically connecting the second light-emitting element between the first electrode and the second electrode of the second level; and a connecting electrode, connecting the second contact electrode of the first level with the first contact electrode of the second level.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display device and a method of manufacturing the same. Background Art

[0002] Recently, a technology for manufacturing ultra-small light-emitting elements using materials having a reliable inorganic crystal structure and manufacturing light-emitting devices using the light-emitting elements has been developed. For example, a technology for manufacturing a plurality of ultra-small light-emitting elements having a small size corresponding to a range from nanometers to micrometers and forming a light source of various light-emitting devices (e.g., pixels of a display device) using the ultra-small light-emitting elements has been developed. Summary of the invention

[0003] Technical issues

[0004] Embodiments of the present disclosure relate to a display device including a light emitting element and a method of manufacturing the display device.

[0005] Technical Solution

[0006] A display device according to an embodiment of the present disclosure includes a pixel arranged in a display area. The pixel includes: a first sub-area and a second sub-area, which are sequentially arranged in a first direction; a first electrode and a second electrode of a first level, which are arranged to be spaced apart from each other in the first sub-area; a first light-emitting element, which is arranged in parallel between the first electrode and the second electrode of the first level; a first contact electrode and a second contact electrode of the first level, which are respectively arranged on the first electrode and the second electrode of the first level, and are configured to electrically connect the first light-emitting element between the first electrode and the second electrode of the first level; the first electrode and the second electrode of the second level, which are arranged to be spaced apart from each other in the second sub-area; a second light-emitting element, which is arranged in parallel between the first electrode and the second electrode of the second level; the first contact electrode and the second contact electrode of the second level, which are respectively arranged on the first electrode and the second electrode of the second level, and are configured to electrically connect the second light-emitting element between the first electrode and the second electrode of the second level; and a connecting electrode, which is configured to connect the second contact electrode of the first level with the first contact electrode of the second level.

[0007] In an embodiment, the first contact electrode and the second contact electrode of the first level and the first contact electrode and the second contact electrode of the second level may be sequentially or alternately arranged in the first sub-region and the second sub-region, respectively, in a second direction intersecting the first direction. The connecting electrode may extend in a boundary region between the first sub-region and the second sub-region in a third direction intersecting the first direction and the second direction, and may connect the second contact electrode of the first level with the first contact electrode of the second level.

[0008] In an embodiment, the display device may further include: a Kth (K is a natural number of 3 or greater) sub-region, arranged behind the first sub-region and the second sub-region in the first direction; a first electrode and a second electrode of the Kth level, arranged to be spaced apart from each other in the K sub-region; a Kth light-emitting element, arranged in parallel between the first electrode and the second electrode of the Kth level; a first contact electrode and a second contact electrode of the Kth level, respectively arranged on the first electrode and the second electrode of the Kth level, and configured to electrically connect the Kth light-emitting element between the first electrode and the second electrode of the Kth level; and another connecting electrode, configured to connect the first contact electrode of the Kth level to the second contact electrode of the previous level.

[0009] In an embodiment, the display device may further include: a first line connected to the first electrode of the first stage and configured to be provided with a first power supply voltage or a first driving signal; and a second line connected to the second electrode of the Kth stage or the second electrode of the last stage and configured to be provided with a second power supply voltage or a second driving signal.

[0010] In an implementation, the second electrode of the first stage, the first and second electrodes of the intermediate stages including the second stage, and the first electrode of the Kth stage or the first electrode of the last stage may each have separate individual pattern shapes.

[0011] In an embodiment, the display device may further include: a first line connected to the first electrode of the first level and configured to be provided with a first power supply voltage or a first driving signal; and a second line connected to the second electrode of the second level and configured to be provided with a second power supply voltage or a second driving signal.

[0012] In an implementation, the second electrode of the first stage and the first electrode of the second stage may each have separate individual pattern shapes.

[0013] In an implementation, the second contact electrode of the first stage, the connection electrode, and the first contact electrode of the second stage may be integrally connected to each other.

[0014] In an embodiment, the pixel may further include at least one reverse light emitting element connected between the first and second electrodes of the first stage or between the first and second electrodes of the second stage in a direction opposite to the first and second light emitting elements.

[0015] In an embodiment, the number of the first light emitting elements and the second light emitting elements may be greater than the number of the reverse light emitting elements.

[0016] In an embodiment, a pixel may include: a plurality of first electrodes and a plurality of second electrodes of a first level, arranged in a first sub-region; a plurality of first contact electrodes and a plurality of second contact electrodes of a first level, arranged in the first sub-region and respectively arranged on the first electrode and the second electrode of the first level; a plurality of first electrodes and a plurality of second electrodes of a second level, arranged in the second sub-region; and a plurality of first contact electrodes and a plurality of second contact electrodes of a second level, arranged in the second sub-region and respectively arranged on the first electrode and the second electrode of the second level.

[0017] In an embodiment, the pixel may further include at least one defective light emitting element having opposite ends short-circuited between any pair of the first and second electrodes of the first stage and between any pair of the first and second electrodes of the second stage. The first contact electrode or the second contact electrode directly connected to the defective light emitting element may be separated from the remaining first contact electrodes and second contact electrodes.

[0018] In an embodiment, the display device may further include: a first line connected to at least one of the first electrodes of the first stage and configured to be provided with a first power supply voltage or a first drive signal; a second line connected to at least one of the second electrodes of the second stage or at least one of the second electrodes of the last stage and configured to be provided with a second power supply voltage or a second drive signal; and at least one defective light emitting element connected to any first electrode or any second electrode of the first electrode of the first stage and the second electrode of the second stage or the second electrode of the last stage and having a short-circuited opposite end, and any first electrode or any second electrode may be separated from the first line or the second line.

[0019] In an embodiment, the pixel may include: first partition walls, which are respectively disposed under the first electrode of the first level and the first electrode of the second level and each has a separate individual pattern; and second partition walls, which are respectively disposed under the second electrode of the first level and the second electrode of the second level and each has a separate individual pattern.

[0020] A method for manufacturing a display device according to an embodiment of the present disclosure includes: forming first and second alignment electrodes spaced apart from each other and each extending in a first direction and first and second lines connected to the first and second alignment electrodes, respectively, in an emission region of each pixel; providing a plurality of light emitting elements to the emission region, and arranging the light emitting elements between the first and second alignment electrodes; forming a plurality of first contact electrodes and a plurality of second contact electrodes, the plurality of first contact electrodes being arranged on different regions of the first alignment electrode in the first direction and configured to connect a first end of the light emitting element to the first alignment electrode, the plurality of second contact electrodes being arranged on different regions of the second alignment electrode in the first direction and configured to electrically connect a second end of the light emitting element to the second alignment electrode; and dividing the first alignment electrode into a plurality of first electrodes arranged in the first direction, and dividing the second alignment electrode into a plurality of second electrodes arranged in the first direction. Forming the first and second contact electrodes includes connecting the second contact electrode arranged in the first level of the emission region to the first contact electrode arranged in the second level of the emission region.

[0021] In an embodiment, forming the first contact electrode and the second contact electrode may include forming a connection electrode configured to integrally connect the second contact electrode disposed in the first level of the emission region to the first contact electrode disposed in the second level of the emission region.

[0022] In an embodiment, forming a first contact electrode and a second contact electrode may sequentially include: forming a second contact electrode disposed in a first level of the emission region and a first contact electrode disposed in a second level of the emission region; and forming a first contact electrode disposed in the first level of the emission region and a second contact electrode disposed in the second level of the emission region.

[0023] In an embodiment, forming the first alignment electrode and the second alignment electrode may include forming a plurality of first alignment electrodes and a plurality of second alignment electrodes to be alternately arranged in the second direction in the emission region. Forming the first contact electrode and the second contact electrode may include forming a plurality of connecting electrodes configured to connect the second contact electrode arranged in any one level of the emission region to the first contact electrode arranged in a subsequent level of the emission region.

[0024] In an embodiment, the method may further include: checking whether there is a short circuit defect in the light emitting element; and in a case where it is determined that at least one of the light emitting elements is a defective light emitting element, disconnecting a connection electrode connected to a first contact electrode or a second contact electrode connected to the defective light emitting element.

[0025] In an embodiment, the method may further include: checking whether there is a short circuit defect in the light emitting element; and when it is determined that at least one of the light emitting elements is a defective light emitting element, separating the first electrode or the second electrode connected to the defective light emitting element from the first line or the second line.

[0026] Beneficial Effects

[0027] In a display device including pixels and a method of manufacturing the display device according to an embodiment of the present disclosure, a light emitting element provided to an emission area of ​​each pixel can be efficiently used to form each light source unit, and a driving current flowing through a display panel can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1a and Figure 1b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0029] Figure 2a and Figure 2b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0030] Figure 3a and Figure 3b They are respectively a perspective view and a cross-sectional view showing a light emitting element according to an embodiment of the present disclosure.

[0031] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure.

[0032] Figure 5a to Figure 5e are circuit diagrams each showing a pixel according to an embodiment of the present disclosure.

[0033] Figure 6 and Figure 7 are plan views each showing a pixel according to an embodiment of the present disclosure.

[0034] Figures 8 to 11 are cross-sectional views each showing a pixel according to an embodiment of the present disclosure, and for example, show a pixel corresponding to Figure 7 Different implementations of a cross section of a pixel along line II'.

[0035] Fig.12 is a cross-sectional view showing a pixel according to an embodiment of the present disclosure, and for example shows a pixel corresponding to Figure 7 Implementation of a cross section of a pixel along line II-II'.

[0036] Fig.13 is a plan view showing a driving current flowing through a pixel according to an embodiment of the present disclosure, and for example shows a driving current flowing through Figure 7The driving current of the pixel flows.

[0037] Figures 14a to 14e are plan views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Figure 7 Embodiments of the present invention provide a method for displaying a pixel of a display device.

[0038] Figures 15a to 15e are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing Figures 14a to 14e Implementation of the cross section corresponding to line III-III'.

[0039] Fig.16a and Fig.16b is a plan view illustrating a method of manufacturing a display device according to an embodiment of the present disclosure, and illustrates an embodiment related to a method of forming a first contact electrode and a second contact electrode, for example.

[0040] Figures 17 to 20 1 and 2 are plan views each showing a pixel according to an embodiment of the present disclosure, and show, for example, different embodiments related to a pixel in which a defect has been repaired.

[0041] Fig.21 and Fig. 22 are plan views each showing a pixel according to an embodiment of the present disclosure, and for example, Figure 7 Different modified implementations related to the implementations of the present invention. DETAILED DESCRIPTION

[0042] Reference will now be made in detail to various embodiments of the present disclosure, specific examples of which are shown in the accompanying drawings and described below, and which may be variously modified in many different forms. However, the present disclosure is not limited to the following embodiments and may be modified in various forms.

[0043] In order to clearly explain the present disclosure, some elements that are not directly related to the features of the present disclosure in the drawings may be omitted. In addition, the sizes, proportions, etc. of some elements in the drawings may be slightly exaggerated. It should be noted that in all the drawings, the same reference numerals are used to represent the same or similar elements, and repeated explanations will be omitted.

[0044] It should be understood that although the terms "first", "second", etc. can be used in this document to describe various elements, these elements should not be limited by these terms. It should also be understood that when used in this specification, the terms "comprise", "include", "have", etc. specify the presence of the features, wholes, steps, operations, elements, components and / or their combinations, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations. In addition, when the first component or the first part is arranged on the second component or the second part, the first component or the first part can not only be directly on the second component or the second part, but also a third component or the third part can be interposed between them. In addition, the terms "position", "direction", etc. used in the following description are defined in relative terms, and it should be noted that they can be changed to opposite positions or directions according to the viewing angle or direction. In addition, the singular form can include the plural form as long as it is not specifically mentioned in the sentence.

[0045] Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b 1 is a perspective view and a cross-sectional view showing a light emitting element LD according to an embodiment of the present disclosure. Figures 1a to 3b A cylindrical rod-type light emitting element LD is illustrated, but the type and / or shape of the light emitting element LD according to the present disclosure is not limited thereto.

[0046] Reference Figure 1a and Figure 1b , the light emitting element LD according to the embodiment of the present disclosure may include a first conductive type semiconductor layer 11 (also referred to as a "first semiconductor layer"), a second conductive type semiconductor layer 13 (also referred to as a "second semiconductor layer"), and an active layer 12 interposed between the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. For example, the light emitting element LD may be configured by a stacked body formed by continuously stacking the first conductive type semiconductor layer 11, the active layer 12, and the second conductive type semiconductor layer 13 in a longitudinal direction.

[0047] In an embodiment, the light emitting element LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end with respect to the longitudinal direction.

[0048] In an embodiment, one of the first and second conductive type semiconductor layers 11 and 13 may be disposed on a first end of the light emitting element LD. The other of the first and second conductive type semiconductor layers 11 and 13 may be disposed on a second end of the light emitting element LD.

[0049] In an embodiment, the light emitting element LD may be a rod-type light emitting diode manufactured in the form of a rod. In this specification, the term "rod-type" includes a rod-like shape and a bar-like shape, such as a cylindrical shape and a prism shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1), and its cross-sectional shape is not limited to a specific shape. For example, the length L of the light emitting element LD may be greater than its diameter D (or the width of its cross section).

[0050] In an embodiment, the light emitting element LD may have a small size in the range from nanometer level to micrometer level. For example, each light emitting element LD may have a diameter D and / or a length L in the range from nanometer level to micrometer level. However, in the present disclosure, the size of the light emitting element LD is not limited thereto. For example, the size of the light emitting element LD may be changed in various ways according to the design conditions of various devices (e.g., display devices), and various devices use light emitting devices using the light emitting element LD as light sources.

[0051] The first conductive type semiconductor layer 11 may include, for example, at least one N-type semiconductor layer. For example, the first conductive type semiconductor layer 11 may include an N-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material used to form the first conductive type semiconductor layer 11 is not limited thereto, and the first conductive type semiconductor layer 11 may be formed of various other materials.

[0052] The active layer 12 may be disposed on the first conductive type semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. In an embodiment, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or below the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and various other materials may be used to form the active layer 12.

[0053] If a voltage equal to or greater than a threshold voltage is applied to each of the opposite ends of the light emitting element LD, the light emitting element LD may emit light by recombination of electron-hole pairs in the active layer 12. Since the light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for various light emitting devices and pixels of a display device.

[0054] The second conductive type semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer of a type different from that of the first conductive type semiconductor layer 11. For example, the second conductive type semiconductor layer 13 may include at least one P-type semiconductor layer. For example, the second conductive type semiconductor layer 13 may include a P-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials and doped with a second conductive dopant such as Mg. However, the material used to form the second conductive type semiconductor layer 13 is not limited thereto, and the second conductive type semiconductor layer 13 may be formed of various other materials.

[0055] In an embodiment, the light emitting element LD may further include an insulating film INF disposed on the surface of the light emitting element LD. The insulating film INF may be formed on the surface of the light emitting element LD to surround at least the outer circumferential surface of the active layer 12, and may also surround predetermined regions of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13. Here, the insulating film INF may allow opposite ends of the light emitting element LD having different polarities to be exposed to the outside. For example, the insulating film INF may expose one end of each of the first conductive type semiconductor layer 11 and the second conductive type semiconductor layer 13 disposed on the corresponding opposite ends of the light emitting element LD with respect to the longitudinal direction, for example, may expose both base sides of the cylinder (at Figure 1a and Figure 1b , the top surface and the bottom surface of the light emitting element LD), rather than covering both substrate sides.

[0056] In an embodiment, the insulating film INF may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ) and titanium oxide (TiO 2 ) at least one insulating material, but is not limited thereto. In other words, the material forming the insulating film INF is not limited to a specific material, and the insulating film INF can be formed of various well-known insulating materials.

[0057] In an embodiment, in addition to the first conductive type semiconductor layer 11, the active layer 12, the second conductive type semiconductor layer 13 and / or the insulating film INF, the light emitting element LD may further include additional other components. For example, the light emitting element LD may further include one or more fluorescent layers, one or more active layers, one or more semiconductor layers and / or one or more electrode layers disposed on one end of the first conductive type semiconductor layer 11, the active layer 12 and / or the second conductive type semiconductor layer 13.

[0058] For example, Figure 2a and Figure 2b As shown in , the light emitting element LD may further include at least one electrode layer 14 disposed on one end of the second conductive type semiconductor layer 13. In an embodiment, as Figure 3a and Figure 3b As shown in , the light emitting element LD may further include at least one electrode layer 15 disposed on one end of the first conductive type semiconductor layer 11 .

[0059] Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but is not limited thereto. Each of the electrode layers 14 and 15 may include a metal or a metal oxide. For example, each of the electrode layers 14 and 15 may be formed of a transparent electrode material such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO) or a combination thereof. In an embodiment, the electrode layers 14 and 15 may be substantially transparent or translucent. Thus, the light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layers 14 and 15.

[0060] In an embodiment, the insulating film INF may at least partially surround the outer circumferential surface of the electrode layers 14 and 15, or may not surround the outer circumferential surface thereof. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15. In addition, the insulating film INF may be formed to expose opposite ends of the light emitting element LD having different polarities, for example, at least one region of each of the electrode layers 14 and 15 may be exposed. Alternatively, in an embodiment, the insulating film INF may not be provided.

[0061] If the insulating film INF is provided on the surface of the light emitting element LD, specifically, on the surface of the active layer 12, the active layer 12 can be prevented from being short-circuited with at least one electrode not shown (for example, at least one of the contact electrodes connected to the opposite ends of the light emitting element LD). Therefore, the electrical stability of the light emitting element LD can be ensured. In the description of each embodiment of the present disclosure, the term "connection (or coupling)" may comprehensively refer to physical connection (or coupling) and / or electrical connection (or coupling). In addition, this may comprehensively refer to direct connection (or coupling) and / or indirect connection (or coupling).

[0062] In addition, due to the insulating film INF formed on the surface of the light emitting element LD, defects occurring on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In addition, if the insulating film INF is formed on each light emitting element LD, even when a plurality of light emitting elements LD are disposed adjacent to each other, the light emitting element LD can be prevented from being unexpectedly short-circuited.

[0063] In an embodiment of the present disclosure, a surface treatment process may be performed to manufacture the light emitting element LD. For example, each light emitting element LD may be surface treated so that when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each emission region (e.g., the emission region of each pixel), the light emitting element LD may be uniformly dispersed in the solution instead of being unevenly aggregated.

[0064] In an embodiment not limited thereto, the insulating film INF itself may be formed of a hydrophobic film using a hydrophobic material, or an additional hydrophobic film formed of a hydrophobic material may be formed on the insulating film INF. In an embodiment, the hydrophobic material may be a fluorine-containing material to exhibit hydrophobicity. In an embodiment, the hydrophobic material may be applied to the light emitting element LD in the form of a self-assembled monolayer (SAM). In this case, the hydrophobic material may include octadecyltrichlorosilane, fluoroalkyltrichlorosilane, perfluoroalkyltriethoxysilane, etc. In addition, the hydrophobic material may be a commercially available fluorine-containing material such as Teflon. TM or Cytop TM or corresponding materials.

[0065] The light-emitting device including the above-mentioned light-emitting element LD can be used not only in display devices, but also in various devices that require light sources. For example, at least one ultra-small light-emitting element LD (for example, a plurality of ultra-small light-emitting elements LD each having a size ranging from nanometers to micrometers) can be arranged in each pixel area of ​​the display panel to form a light source (or light source unit) of the corresponding pixel using the ultra-small light-emitting element LD. In addition, the application field of the light-emitting element LD according to the present disclosure is not limited to display devices. For example, the light-emitting element LD can also be used in other types of devices (such as lighting devices) that require light sources.

[0066] Figure 4 is a plan view showing a display device according to an embodiment of the present disclosure. In the embodiment, Figure 4 A display device is shown, and in particular, a display panel PNL provided in the display device is shown as a reference. Figures 1a to 3b The light emitting element LD is described as an example of a device of a light source. For example, each of the pixels PXL of the display panel PNL may have at least one light emitting element LD.

[0067] For the sake of explanation, Figure 4 The structure of the display panel PNL according to the embodiment is simply shown focusing on the display area DA. In some embodiments, although not shown, at least one driving circuit (eg, at least one of a scan driver and a data driver) and / or a plurality of lines may be further provided in the display panel PNL.

[0068] Reference Figure 4 , the display panel PNL according to an embodiment of the present disclosure may include a base layer BSL and a plurality of pixels PXL disposed on the base layer BSL. In detail, the display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image and a non-display area NDA formed in a predetermined area other than the display area DA. The pixels PXL may be disposed in the display area DA on the base layer BSL.

[0069] In an embodiment, the display area DA may be disposed in a central area of ​​the display panel PNL, and the non-display area NDA may be disposed in a peripheral area of ​​the display panel PNL so as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed. The display area DA may form a screen on which an image is displayed.

[0070] The base layer BSL may form a substrate of the display panel PNL. In an embodiment, the base layer BSL may be a rigid substrate or a rigid film or a flexible substrate or a flexible film, and its material or properties are not particularly limited. For example, the base layer BSL may be a rigid substrate made of glass or reinforced glass, a flexible substrate (or film) formed of plastic or metal, or at least one insulating layer, and its material and / or properties are not particularly limited.

[0071] In addition, the base layer BSL may be transparent, but the present disclosure is not limited thereto. For example, the base layer BSL may be a transparent, translucent, opaque or reflective substrate.

[0072] One area on the base layer BSL may be defined as a display area DA in which the pixels PXL are disposed, and another area thereof may be defined as a non-display area NDA. For example, the base layer BSL may include a display area DA including a plurality of pixel areas in which corresponding pixels PXL are formed, and a non-display area NDA disposed around the display area DA. Various lines and / or internal circuits connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA.

[0073] In an embodiment, the pixel PXL may be disposed in each pixel region of the display area DA. In an embodiment, the pixel PXL may be arranged in the display area DA in a stripe arrangement or a PenTile arrangement, but the present disclosure is not limited thereto. For example, the pixel PXL may be arranged in the display area DA in various known arrangements.

[0074] Each pixel PXL may include at least one light source driven by a predetermined control signal (eg, a scan signal and a data signal) and / or a predetermined power source (eg, a first power source and a second power source). Figures 1a to 3b The light-emitting element LD of any one of the embodiments, for example, has at least one ultra-small rod-type light-emitting element LD having a small size corresponding to the nanometer level or the micrometer level. However, in the embodiments of the present disclosure, the type of light-emitting element LD that can be used as the light source of the pixel PXL is not limited thereto. For example, in an embodiment, each pixel PXL may include a light-emitting element having a core-shell structure and manufactured by a growth method. In an embodiment, the light-emitting element having a core-shell structure may be an ultra-small core-shell light-emitting element having a small size corresponding to the nanometer level or the micrometer level, but the size of the light-emitting element having a core-shell structure is not limited.

[0075] In an embodiment, each pixel PXL may be formed by an active pixel. However, the type, structure and / or driving scheme of the pixel PXL that can be applied to the display device according to the present disclosure is not particularly limited. For example, each pixel PXL may have the same structure as a pixel for a passive light-emitting display device or an active light-emitting display device, and the passive light-emitting display device or the active light-emitting display device has various known structures and / or can operate with various known driving schemes.

[0076] Figure 5a to Figure 5e are circuit diagrams each showing a pixel PXL according to an embodiment of the present disclosure. For example, Figure 5a to Figure 5e 1 and 2 show different embodiments of the pixel PXL applicable to an active display device. However, the types of the pixel PXL and the display device to which the embodiments of the present disclosure can be applied are not limited thereto. Figure 5a to Figure 5e Each pixel PXL shown in FIG. 1 may be set to Figure 4 The pixels PXL may have substantially the same or similar structures.

[0077] Reference Figure 5a The pixel PXL according to the embodiment of the present disclosure may include a light source unit LSU configured to generate light having brightness corresponding to a data signal. The pixel PXL may further include a pixel circuit PXC configured to drive the light source unit LSU.

[0078] In an embodiment, the light source unit LSU may include a plurality of light emitting elements LD electrically connected to each other between a first power source VDD and a second power source VSS. For example, the light source unit LSU may include a first electrode ET1 connected to the first power source VDD, a second electrode ET2 connected to the second power source VSS, and a plurality of light emitting elements LD connected in parallel to each other between the first electrode ET1 and the second electrode ET2 in the same direction. In an embodiment, the first electrode ET1 may be an anode electrode, and the second electrode ET2 may be a cathode electrode.

[0079] In an embodiment, each of the light emitting elements LD may include a P-type terminal connected to a first power source VDD through a first electrode ET1 and an N-type terminal connected to a second power source VSS through a second electrode ET2. In an embodiment, the light emitting elements LD may be connected in parallel between the first electrode ET1 and the second electrode ET2 in a forward direction. In this way, each of the light emitting elements LD connected between the first power source VDD and the second power source VSS in the forward direction may form an effective light source. A group of effective light sources may form a light source unit LSU of a pixel PXL.

[0080] In an embodiment, the first power supply VDD and the second power supply VSS may have different potentials so that the light emitting element LD can emit light. For example, the first power supply VDD may be set as a high potential power supply, and the second power supply VSS may be set as a low potential power supply. Here, during at least one emission cycle of the pixel PXL, the potential difference between the first power supply VDD and the second power supply VSS may be set to a threshold voltage of the light emitting element LD or a voltage greater than that.

[0081] In an embodiment, a first end (e.g., a P-type end) of the light emitting element LD forming each light source unit LSU may be commonly connected to the pixel circuit PXC through a first electrode of the light source unit LSU (e.g., a first electrode ET1 (also referred to as a “first pixel electrode”) of each light source unit LSU), and connected to a first power source VDD through the pixel circuit PXC and a first power line PL1. A second end (e.g., an N-type end) of the light emitting element LD may be commonly connected to a second power source VSS through another electrode of the light source unit LSU (e.g., a second electrode ET2 (also referred to as a “second pixel electrode”) of each light source unit LSU) and a second power line PL2.

[0082] The light emitting element LD of the light source unit LSU may emit light having a brightness corresponding to the driving current supplied thereto by the pixel circuit PXC. For example, during each frame period, the pixel circuit PXC may supply the light source unit LSU with a driving current corresponding to the grayscale value of the data of the corresponding frame. The driving current supplied to the light source unit LSU may be divided into a portion flowing to the light emitting element LD connected in the forward direction. Therefore, each of the light emitting elements LD may emit light having a brightness corresponding to the current applied thereto, so that the light source unit LSU may emit light having a brightness corresponding to the driving current.

[0083] In an embodiment, the light source unit LSU may further include at least one ineffective light source in addition to the light emitting elements LD forming each effective light source. For example, at least one reverse light emitting element LDrv may be further connected between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0084] Each reverse light-emitting element LDrv, together with the light-emitting element LD forming an effective light source, can be connected in parallel with each other between the first electrode ET1 and the second electrode ET2, and can be connected between the first electrode ET1 and the second electrode ET2 in a direction opposite to the direction of the light-emitting element LD. For example, the N-type end of the reverse light-emitting element LDrv can be connected to the first power supply VDD via the first electrode ET1. The P-type end of the reverse light-emitting element LDrv can be connected to the second power supply VSS via the second electrode ET2. Even when a predetermined driving voltage (e.g., a normal direction driving voltage) is applied between the first electrode ET1 and the second electrode ET2, the reverse light-emitting element LDrv remains deactivated. Therefore, current does not substantially flow through the reverse light-emitting element LDrv.

[0085] The pixel circuit PXC may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, if the pixel PXL is disposed on the i-th row (i is a natural number) and the j-th column (j is a natural number) of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, the pixel circuit PXC may include a first transistor T1 and a second transistor T2 and a storage capacitor Cst.

[0086] The first transistor (also referred to as a "driving transistor") T1 is connected between the first power source VDD and the light source unit LSU. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control a driving current to be supplied to the light source unit LSU in response to a voltage of the first node N1.

[0087] The second transistor (also referred to as a "switching transistor") T2 may be connected between the data line Dj and the first node N1. The gate electrode of the second transistor T2 is connected to the scan line Si. When a scan signal having a gate-on voltage (e.g., a low-level voltage) is provided from the scan line Si, the second transistor T2 is turned on to electrically connect the first node N1 to the data line Dj.

[0088] During each frame period, a data signal of a corresponding frame is supplied to the data line Dj. The data signal is transmitted to the first node N1 via the second transistor T2. Thus, a voltage corresponding to the data signal is charged to the storage capacitor Cst.

[0089] One electrode of the storage capacitor Cst is connected to the first power source VDD, and the other electrode thereof is connected to the first node N1. The storage capacitor Cst may charge a voltage corresponding to a data signal to be supplied to the first node N1 during each frame period.

[0090] Despite Figure 5a In the embodiment, the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit PXC are shown to be formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 may be changed to an N-type transistor.

[0091] For example, Figure 5b As shown in FIG. 1 , both the first transistor T1 and the second transistor T2 may be formed of N-type transistors. In this case, the gate-on voltage of the scanning signal for writing the data signal supplied to the data line Dj to the pixel PXL in each frame period may be a high-level voltage. Similarly, the voltage of the data signal for turning on the first transistor T1 may be a voltage having a voltage with a value similar to that of the gate-on voltage. Figure 5a The voltage level of the embodiment is opposite to the level of the voltage level. For example, in Figure 5b In an embodiment, as the grayscale value to be represented increases, a data signal having a higher voltage may be provided.

[0092] In addition to the connection positions of some circuit elements and the voltage levels of control signals (e.g., scan signals and data signals) that vary according to the transistor types, Figure 5b The pixel PXL shown in FIG. 1 is similar in configuration and operation to the Figure 5a The pixels PXL are basically similar. Therefore, Figure 5b The pixel PXL is described in detail.

[0093] The structure of the pixel circuit PXC is not limited to Figure 5a and Figure 5bIn other words, the pixel circuit PXC may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. For example, the pixel circuit PXC may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. Figure 5c The embodiment shown in FIG. 1 is configured in the same manner.

[0094] Reference Figure 5c , the pixel circuit PXC can be connected not only to the scan line Si of the corresponding horizontal line, but also to at least one other scan line (or control line). For example, the pixel circuit PXC of the pixel PXL arranged on the i-th row of the display area DA can also be connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit PXC can be connected not only to the first power supply VDD and the second power supply VSS, but also to the third power supply. For example, the pixel circuit PXC can also be connected to the initialization power supply Vint. In an embodiment, the pixel circuit PXC may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0095] The first transistor T1 may be connected between the first power source VDD and the light source unit LSU. For example, the first electrode (e.g., source electrode) of the first transistor T1 may be connected to the first power source VDD through the fifth transistor T5 and the first power line PL1, and the second electrode (e.g., drain electrode) of the first transistor T1 may be connected to an electrode of the light source unit LSU (e.g., a first contact electrode and / or a first pixel electrode of the corresponding pixel PXL) through the sixth transistor T6. The gate electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 may control a driving current to be provided to the light source unit LSU in response to a voltage of the first node N1.

[0096] The second transistor T2 is connected between the data line Dj and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the corresponding scan line Si. When a scan signal having a gate-on voltage is provided from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj to the first electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal provided from the data line Dj may be transmitted to the first transistor T1.

[0097] The third transistor T3 is connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 is connected to the corresponding scan line Si. When a scan signal having a gate-on voltage is provided from the scan line Si, the third transistor T3 can be turned on to electrically connect the first transistor T1 in a diode form.

[0098] The fourth transistor T4 may be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the previous scan line, for example, the i-1th scan line Si-1. When a scan signal of a gate-on voltage is provided to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N1. In an embodiment, when the first transistor T1 is a P-type transistor, the voltage of the initialization power supply Vint for initializing the gate voltage of the first transistor T1 may be less than or equal to the lowest voltage of the data signal.

[0099] The fifth transistor T5 is connected between the first power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal having a gate cut-off voltage (for example, a high level voltage) is provided to the emission control line Ei, the fifth transistor T5 can be turned off, and the fifth transistor T5 can be turned on in other cases.

[0100] The sixth transistor T6 is connected between the first transistor T1 and the light source unit LSU. The gate electrode of the sixth transistor T6 is connected to the corresponding emission control line, for example, the i-th emission control line Ei. When the emission control signal having the gate-off voltage is provided to the emission control line Ei, the sixth transistor T6 may be turned off, and the sixth transistor T6 may be turned on in other cases.

[0101] The seventh transistor T7 is connected between an electrode of the light source unit LSU (e.g., a first pixel electrode of a corresponding pixel PXL) and an initialization power supply Vint. The gate electrode of the seventh transistor T7 is connected to any one of the scan lines of the subsequent stage (subsequent horizontal pixel row), for example, to the i+1th scan line Si+1. When a scan signal of a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU. In this case, during each initialization period in which the voltage of the initialization power supply Vint is transmitted to the light source unit LSU, the voltage of the electrode of the light source unit LSU may be initialized. The control signal for controlling the operation of the seventh transistor T7 may be changed in various ways. For example, in an embodiment, the gate electrode of the seventh transistor T7 may be connected to the scan line of the corresponding horizontal line, i.e., the i-th scan line Si. In this case, when a scan signal having a gate-on voltage is supplied to the i-th scan line Si, the seventh transistor T7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU.

[0102] The storage capacitor Cst may be connected between the first power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 during each frame period and the threshold voltage of the first transistor T1.

[0103] Despite Figure 5c The transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit PXC are shown to be formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0104] although Figure 5a to Figure 5c 1 shows an embodiment in which all effective light sources (ie, light emitting elements LD) constituting each light source unit LSU are connected in parallel to each other, but the present disclosure is not limited thereto. Figure 5d and Figure 5e As shown in , the light source unit LSU of each pixel PXL may be configured to include a series structure. Figure 5d and Figure 5e In the following description of the implementation method of Figure 5a to Figure 5c Detailed explanation of components similar or equivalent to components of the embodiments (e.g., pixel circuit PXC).

[0105] Reference Figure 5d , the light source unit LSU may include a plurality of light emitting elements connected in series with each other. For example, the light source unit LSU may include a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3, which are connected in series between a first power supply VDD and a second power supply VSS in a forward direction and constitute each effective light source. Hereinafter, when a specific light emitting element among the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 is specified, the corresponding light emitting element will be referred to as the first light emitting element LD1, the second light emitting element LD2, or the third light emitting element LD3. The term "light emitting element (light emitting element) LD" or "light emitting elements (light emitting elements) LD" will be used to arbitrarily specify at least one light emitting element among the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3, or to inclusively specify the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3.

[0106] The P-type end of the first light emitting element LD1 may be connected to the first power source VDD through the first electrode ET1 of the light source unit LSU. The N-type end of the first light emitting element LD1 may be connected to the P-type end of the second light emitting element LD2. The P-type end of the second light emitting element LD2 may be connected to the N-type end of the first light emitting element LD1. The N-type end of the second light emitting element LD2 may be connected to the P-type end of the third light emitting element LD3. The P-type end of the third light emitting element LD3 may be connected to the N-type end of the second light emitting element LD2. The N-type end of the third light emitting element LD3 may be connected to the second power source VSS through the second electrode ET2 of the light source unit LSU. In this way, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 may be connected in series between the first electrode ET1 and the second electrode ET2 of the light source unit LSU.

[0107] Despite Figure 5d , the light emitting elements LD are connected to form a three-stage series structure, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, two light emitting elements LD may be connected to form a two-stage series structure, or four or more light emitting elements LD may be connected to form a four-stage or more series structure.

[0108] When it is assumed that the same brightness is represented by light emitting elements LD having the same conditions (e.g., the same size and / or number), in the light source unit LSU having a structure in which the light emitting elements LD are connected in series, the voltage applied between the first electrode ET1 and the second electrode ET2 can be increased, and the amount of driving current flowing to the light source unit LSU can be reduced, compared to the light source unit LSU having a structure in which the light emitting elements LD are connected in parallel. Therefore, in the case where the light source unit LSU of each pixel PXL is formed by a series structure, when the display device is driven, the panel current flowing through the display panel PNL can be reduced. Therefore, power consumption can be reduced. The above-mentioned series connection structure can be effectively used to reduce the panel current in a large display panel PNL in which the panel current is relatively large.

[0109] In an embodiment, at least one series stage may include a plurality of light emitting elements LD connected in parallel to each other. In this case, the light source unit LSU may be formed by a series / parallel combination structure. For example, the light source unit LSU may be as follows: Figure 5e Configured as shown in the embodiment.

[0110] Reference Figure 5e, each series stage of the light source unit LSU may include a plurality of light emitting elements LD connected in parallel to each other. For example, the light source unit LSU may include a plurality of first light emitting elements LD1 disposed in a first stage (also referred to as a "first series stage" or a "first row") and a plurality of second light emitting elements LD2 disposed in a second stage (also referred to as a "second series stage" or a "second row") after the first stage. In addition, the light source unit LSU may also selectively include at least one series stage after the second stage. For example, the light source unit LSU may also include a plurality of third light emitting elements LD3 disposed in a third stage (referred to as a "third series stage" or a "third row") after the second stage. In addition, in an embodiment, at least one series stage may further include at least one reverse light emitting element LDrv, but the present disclosure is not limited thereto.

[0111] The first light emitting element LD1 may be connected in parallel with each other between the first electrode ET11 and the second electrode ET21 of the first stage. The second light emitting element LD2 may be connected in parallel with each other between the first electrode ET12 and the second electrode ET22 of the second stage. The third light emitting element LD3 may be connected in parallel with each other between the first electrode ET13 and the second electrode ET23 of the third stage.

[0112] In an embodiment, the first electrodes ET11 to ET13 and the second electrodes ET21 to ET23 provided in each series stage may form separate electrodes dispersed and provided in the light source unit LSU. Hereinafter, the term "first electrode ET1" (also referred to as "first separate electrode") will be used to arbitrarily specify at least one first electrode among the first electrodes ET11 to ET13 (also referred to as "first separate electrodes") provided in each series stage, or to inclusively specify the first electrodes ET11 to ET13 provided in each series stage. Similarly, the term "second electrode ET2" (also referred to as "second separate electrode") will be used to arbitrarily specify at least one second electrode among the second electrodes ET21 to ET23 (also referred to as "second separate electrodes") provided in each series stage, or to inclusively specify the second electrodes ET21 to ET23 provided in each series stage.

[0113] In this way, in the case of configuring the light source unit LSU of each pixel PXL by connecting a plurality of light emitting elements LD in a series / parallel combination structure, the driving current / voltage conditions can be easily controlled corresponding to the specifications of the desired product. For example, when it is assumed that light emitting elements LD having the same conditions (e.g., the same size and / or number) are used and represent the same brightness, as in Figure 5a to Figure 5c Compared with the driving current of the light source unit LSU having a structure in which all the light emitting elements LD are connected in parallel to each other as shown in the embodiment of FIG. 1 , the light source unit LSU in which the light emitting elements LD are connected in a series / parallel combination structure can reduce the driving current, and Figure 5d Compared to the driving voltage of the light source unit LSU having a structure in which all the light emitting elements LD are connected in series as shown in the embodiment of the present invention, the light source unit LSU in which the light emitting elements LD are connected in a series / parallel combination structure can reduce the driving voltage applied to the opposite end of the light source unit LSU. In the case where all the light emitting elements LD are connected in series, if at least one of the light emitting elements LD connected in series to each other is not effectively connected in the forward direction, the path along which the driving current of the pixel PXL can flow is blocked, thereby causing a black spot defect. On the other hand, in the case where the light emitting elements LD are connected to each other in a series / parallel combination structure, even if some of the light emitting elements LD in each series stage are not completely connected in the forward direction or defects occur in some of the light emitting elements LD, the driving current is allowed to flow through the other light emitting elements LD of the corresponding series stage. Therefore, defects of the pixel PXL can be prevented or reduced.

[0114] As shown in the foregoing embodiments, the pixel PXL according to the embodiments of the present disclosure may include a pixel circuit PXC and / or a light source unit LSU which may have various structures. The structure of the pixel PXL applicable to the present disclosure is not limited to Figure 5a to Figure 5e , and each pixel PXL may have various known structures. For example, the pixel circuit PXC included in each pixel PXL may be formed by a known pixel circuit that may have various structures and / or be operated by various driving schemes. In an embodiment of the present disclosure, each pixel PXL may be configured in a passive light emitting display device or the like. In this case, the pixel circuit PXC may be omitted, and each of the first electrode ET1 and the second electrode ET2 of the light source unit LSU may be directly connected to the scan line Si, the data line Dj, the power line and / or the control line.

[0115] Figure 6 and Figure 7 are plan views each showing a pixel PXL according to an embodiment of the present disclosure. Figure 6 and Figure 7 Each pixel PXL shown in FIG. 1 may be Figures 4 to 5e Any one of the pixels PXL shown in . For example, Figure 6 and Figure 7 Each pixel PXL shown in FIG. 1 may be Figure 5e In the embodiment, the pixel PXL is arranged in the display area ( Figure 4 The pixels PXL in DA) may have substantially the same or similar structure.

[0116] In an embodiment, Figure 6 and Figure 7The structure of the pixel PXL according to each embodiment is shown in FIG. 1 . Here, the pixel PXL may further include a circuit element (eg, a circuit element forming a circuit element) for controlling each light source unit LSU. Figure 5a to Figure 5e At least one circuit element of the pixel circuit PXC of the base layer BSL). In an embodiment, the circuit element may be disposed on a layer different from the layer of the light source unit LSU. For example, the circuit element may be disposed in a pixel circuit layer located on one surface of the base layer BSL, and the light source unit LSU may be disposed in a display element layer, and the display element layer is disposed on the pixel circuit layer.

[0117] Furthermore, in an embodiment, Figure 6 and Figure 7 An embodiment in which each light source unit LSU is connected to a predetermined power line (e.g., a first power line PL1 and / or a second power line PL2), a circuit element (e.g., at least one circuit element forming a pixel circuit PXC), and / or a signal line (e.g., a scan line Si and / or a data line Dj) through a first contact hole CH1 and a second contact hole CH2 is shown, but the present disclosure is not limited thereto. For example, in an embodiment of the present disclosure, at least one of the first electrode ET1 and the second electrode ET2 of each pixel PXL may be directly connected to a predetermined power line and / or a signal line without using, for example, a contact hole and / or an intermediate line.

[0118] Reference Figure 6 , the pixel PXL according to an embodiment of the present disclosure may include a plurality of first electrodes ET1 and a plurality of second electrodes ET2 separated from each other and dispersed in an emission area EMA, and a plurality of light emitting elements LD connected between the first electrodes ET1 and the second electrodes ET2 in a series / parallel combination structure. In an embodiment, the emission area EMA of each pixel PXL may refer to a region in which the light emitting element LD of the light source unit LSU forming the pixel PXL is disposed. In addition to the light emitting element LD, the first electrode ET1 and the second electrode ET2 connected to the light emitting element LD may also be disposed in the emission area EMA.

[0119] In an embodiment, the emission area EMA may be surrounded by a light shielding bank and / or a reflective bank (also referred to as a “pixel defining layer”) BNK. For example, the emission area EMA of each pixel PXL may be defined and / or divided by the bank BNK.

[0120] In an embodiment, the bank BNK may be disposed to surround each emission area EMA. For example, the bank BNK may be disposed between the emission areas EMA of the pixels PXL so that the bank BNK is disposed in a peripheral area of ​​each pixel PXL and / or an area between adjacent pixels PXL.

[0121] In an embodiment, the first electrode ET1 and the second electrode ET2 may be dispersed in the emission area EMA in a first direction (e.g., a column direction or a vertical direction) DR1 and a second direction (e.g., a row direction or a horizontal direction) DR2 in the form of a matrix. In the following description, an area in which the first electrode ET1 and the second electrode ET2 of each series stage and the light emitting element LD are arranged with respect to the first direction DR1 may be defined as a sub-area. For example, if the light source unit LSU includes a plurality of light emitting elements LD dispersed and arranged in three series stages, the emission area EMA in which the light source unit LSU is arranged may be divided into three sub-areas with respect to the first direction DR1. For example, the emission area EMA may include a first sub-area SAR1, a second sub-area SAR2, and a third sub-area SAR3 that are continuously arranged in the first direction DR1.

[0122] At least one pair of first-level first electrodes ET11 and first-level second electrodes ET21 and a plurality of first light emitting elements LD1 connected therebetween may be disposed in the first sub-region SAR1. For example, a plurality of first-level first electrodes ET11 and a plurality of first-level second electrodes ET21 may be disposed in the first sub-region SAR1. In addition, at least one pair of first-level first contact electrodes CE11 and first-level second contact electrodes CE21 corresponding to the first-level first electrodes ET11 and the second electrodes ET21, respectively, may be selectively disposed in the first sub-region SAR1.

[0123] The first and second electrodes ET11 and ET21 of the first stage may be disposed at positions spaced apart from each other in the first sub-region SAR1. In an embodiment, the first and second electrodes ET11 and ET21 of the first stage may be regularly arranged in the first sub-region SAR1, but the present disclosure is not limited thereto.

[0124] In an embodiment, the first electrode ET11 and the second electrode ET21 of the first level may each have a rod shape extending in one direction in the first sub-region SAR1. For example, the first electrode ET11 and the second electrode ET21 of the first level may each have a rod shape extending in the first direction DR1, and the first electrode ET11 and the second electrode ET21 of the first level may be continuously or alternately arranged at positions spaced apart from each other in the second direction DR2 intersecting the first direction DR1. However, the shape, orientation and / or relative arrangement structure of the first electrode ET11 and the second electrode ET21 of the first level are not limited thereto, and may be changed in various ways. For example, in an embodiment, the first electrode ET11 and the second electrode ET21 of the first level may be arranged at positions spaced apart from each other in a double helix structure, etc.

[0125] In an embodiment, each first-level first electrode ET11 may be connected to a first line (also referred to as a "first connection line" or a "first connection pattern") LI1 in an integral or non-integrated manner. For example, each pixel PXL may further include a first line LI1 connected to at least one first-level first electrode ET11. For example, each pixel PXL may further include a first line LI1 integrally connected to a plurality of first-level first electrodes ET11. In this case, the first-level first electrode ET11 and the first line LI1 may be considered as different regions of one electrode, one line, or one pattern.

[0126] In an embodiment, in the area between the first-level first electrode ET11 and the first line LI1, the width of the conductive pattern forming the first-level first electrode ET11 and the first line LI1 may be locally reduced. If the above structure is used, any one of the first-level first electrodes ET11 may be easily separated from the first line LI1 as needed. For example, in the event of a short circuit defect in at least one first light-emitting element LD1 connected to any one of the first-level first electrodes ET11, any one of the first-level first electrodes ET11 may be separated from the first line LI1 to allow the defect of the pixel PXL caused by the short circuit defect to be repaired. However, the present disclosure is not limited thereto. For example, in an embodiment, the width of each first-level first electrode ET11 may be kept constant to the area where the first-level first electrode ET11 is connected to the first line LI1.

[0127] In an embodiment, during a cycle of operating the display device, a voltage of a first power source VDD (first power source voltage) or a first drive signal (e.g., a scan signal, a data signal, or a predetermined other control signal) may be provided to the first line LI1. In an embodiment, the first line LI1 may be electrically connected to a first contact hole CH1, a predetermined circuit element (e.g., at least one transistor forming a pixel circuit PXC), a power line (e.g., a first power line PL1), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). For example, the first line LI1 may be electrically connected to a predetermined circuit element disposed thereunder through the first contact hole CH1, and connected to the first power line PL1 through the circuit element. In an embodiment, the first line LI1 may be connected to a signal line provided with a predetermined first drive signal via the first contact hole CH1, etc. In an embodiment, the first line LI1 may be directly connected to the first power line PL1 or a predetermined signal line without using the first contact hole CH1 and / or the circuit element. In this case, the first line LI1 may be connected to the first power line PL1 or the predetermined signal line integrally or non-integrally.

[0128] In an embodiment, the first line LI1 connected to the first-stage first electrode ET11 of each of the pixels PXL may first be manufactured to be commonly connected to the plurality of pixels PXL, and provided with a first alignment signal (or a first alignment voltage) in the step of aligning the light emitting element LD. Thereafter, the first line LI1 between the pixels PXL may be disconnected (disconnected) so that the pixels PXL may be manufactured to be capable of being individually operated.

[0129] In an embodiment, each first-level second electrode ET21 may have a separate independent pattern shape. Each first-level second electrode ET21 may be electrically connected to at least one electrode of a subsequent level. For example, each first-level second electrode ET21 may be electrically connected to any second-level first electrode ET12 and / or any second-level first contact electrode CE12 through a corresponding first-level second contact electrode CE21 or without using the first-level second contact electrode CE21.

[0130] The plurality of first light emitting elements LD1 may be disposed between the first-stage first electrode ET11 and the second electrode ET21. For example, the plurality of first light emitting elements LD1 may be arranged in parallel with each other between each first-stage first electrode ET11 and the corresponding first-stage second electrode ET21.

[0131] Each first light emitting element LD1 may include a first end EP1 connected to any one of the first-stage first electrodes ET11 and a second end EP2 connected to any one of the first-stage second electrodes ET21. In an embodiment, the first end EP1 may be a P-type end, and the second end EP2 may be an N-type end.

[0132] In an embodiment, each first light emitting element LD1 may be connected between the first electrode ET11 and the second electrode ET21 of the first stage in the forward direction. For example, the first end EP1 of each of the first light emitting elements LD1 may be directly connected to any one of the first-stage first electrodes ET11, or may be connected to any one of the first-stage first contact electrodes CE11. Similarly, the second end EP2 of each of the first light emitting elements LD1 may be directly connected to any one of the first-stage second electrodes ET21, or may be connected to any one of the first-stage second contact electrodes CE21. The first light emitting element LD1 may form an effective light source of the first stage.

[0133] In an embodiment, at least one reverse light emitting element LDrv connected in a direction opposite to that of the first light emitting element LD1 may be further connected between the first electrode ET11 and the second electrode ET21 of the first stage. The at least one reverse light emitting element LDrv may remain disabled in the pixel PXL.

[0134] In an embodiment, each first-level first contact electrode CE11 may be disposed on each corresponding first-level first electrode ET11. Each first-level second contact electrode CE21 may be disposed on each corresponding first-level second electrode ET21. For example, in the case where a plurality of first-level first electrodes ET11 and a plurality of first-level second electrodes ET21 are disposed in the first sub-region SAR1, a plurality of first-level first contact electrodes CE11 disposed on each first-level first electrode ET11 and a plurality of first-level second contact electrodes CE21 disposed on each first-level second electrode ET21 may be disposed in the first sub-region SAR1. In an embodiment, the first-level first contact electrodes CE11 and the second contact electrodes CE21 may be disposed continuously or alternately at positions spaced apart from each other in the second direction DR2 in the first sub-region SAR1.

[0135] Each first-level first contact electrode CE11 may be disposed on each corresponding first-level first electrode ET11 and a first end EP1 of at least one first light emitting element LD1 adjacent to the first-level first electrode ET11, and electrically connect the first end EP1 to the corresponding first-level first electrode ET11. Similarly, each first-level second contact electrode CE21 may be disposed on each corresponding first-level second electrode ET21 and a second end EP2 of at least one first light emitting element LD1 adjacent to the first-level second electrode ET21, and electrically connect the second end EP2 to the corresponding first-level second electrode ET21. For example, the first-level first contact electrode CE11 and the second contact electrode CE21 may electrically connect the first light emitting element LD1 between the first-level first electrode ET11 and the second electrode ET21.

[0136] In an embodiment, each first-level first contact electrode CE11 may have a separate individual pattern shape. Each first-level second contact electrode CE21 may be integrally or non-integrally connected to at least one second-level first contact electrode CE12. For example, at least one 1-2 level connection electrode SCE1-2 configured to connect each first-level second contact electrode CE21 to at least one second-level first contact electrode CE12 of a subsequent level may be disposed in a boundary region between the first sub-region SAR1 and the second sub-region SAR2.

[0137] In an embodiment, the 1-2 level connection electrode SCE1-2 may extend in a third direction DR3 (e.g., a diagonal direction) intersecting the first direction DR1 and the second direction DR2 in a boundary region between the first sub-region SAR1 and the second sub-region SAR2, and connect each first-level second contact electrode CE21 with at least one second-level first contact electrode CE12. For example, the 1-2 level connection electrode SCE1-2 may extend in a diagonal direction in a boundary region between the first sub-region SAR1 and the second sub-region SAR2, and connect each first-level second contact electrode CE21 to at least one second-level first contact electrode CE12.

[0138] In an embodiment, the 1-2 level connection electrode SCE1-2 may be integrally connected to at least one first level second contact electrode CE21 and at least one second level first contact electrode CE12. In this case, in the step of forming the first contact electrode CE1 and the second contact electrode CE2 of each level, at least one connection electrode (also referred to as a "connector", "bridge" or "bridge pattern") SCE for connecting the light emitting element LD of each level in series may be formed simultaneously therewith. Therefore, the process of manufacturing the pixel PXL and the display device including the pixel PXL may be simplified, and its efficiency may be improved. In the case where a plurality of contact electrodes arranged in two consecutive series stages and at least one connection electrode SCE connecting the plurality of contact electrodes (e.g., at least one first level second contact electrode CE21, at least one second level first contact electrode CE12 and the 1-2 level connection electrode SCE1-2) are integrally connected to each other, they may be considered as different predetermined regions of one contact electrode.

[0139] At least one pair of second-level first electrodes ET12 and second-level second electrodes ET22 and a plurality of second light emitting elements LD2 connected therebetween may be disposed in the second sub-region SAR2. For example, a plurality of second-level first electrodes ET12 and a plurality of second-level second electrodes ET22 may be disposed in the second sub-region SAR2. In addition, at least one pair of second-level first contact electrodes CE12 and second-level second contact electrodes CE22 corresponding to the second-level first electrodes ET12 and second electrodes ET22, respectively, may be selectively disposed in the second sub-region SAR2.

[0140] The first and second electrodes ET12 and ET22 of the second stage may be disposed at positions spaced apart from each other in the second sub-region SAR2. In an embodiment, the first and second electrodes ET12 and ET22 of the second stage may be regularly arranged in the second sub-region SAR2, but the present disclosure is not limited thereto.

[0141] In an embodiment, the first electrode ET12 and the second electrode ET22 of the second level may each have a rod shape extending in one direction in the second sub-region SAR2. For example, the first electrode ET12 and the second electrode ET22 of the second level may each have a rod shape extending in the first direction DR1, and are continuously and / or alternately arranged at positions spaced apart from each other in the second direction DR2 intersecting the first direction DR1. However, the shape, orientation and / or relative arrangement structure of the first electrode ET12 and the second electrode ET22 of the second level may be changed in various ways.

[0142] In an embodiment, each of the first electrode ET12 and the second electrode ET22 of the second level as the intermediate level of the series structure may have a separate individual pattern shape. Each of the first electrode ET12 and the second electrode ET22 of the second level may be connected to at least one electrode of the previous level (i.e., the first level) or the next level (i.e., the third level). For example, each second-level first electrode ET12 may be electrically connected to any first-level (i.e., the previous level) second electrode ET21 and / or any first-level second contact electrode CE21 through a corresponding second-level first contact electrode CE12 or without using the second-level first contact electrode CE12. Each second-level second electrode ET22 may be electrically connected to any third-level (i.e., the next level) first electrode ET13 and / or any third-level first contact electrode CE13 through a corresponding second-level second contact electrode CE22 or without using the second-level second contact electrode CE22.

[0143] In an embodiment, in the case where the light source unit LSU has only a two-stage series structure, each second-stage first electrode ET12 may have a separate individual pattern shape, and each second-stage second electrode ET22 may be directly connected to the second line LI2 provided with a power supply voltage (e.g., a voltage of a second power supply VSS (second power supply voltage)) and / or a signal (e.g., a second drive signal) different from the power supply voltage or signal of the first line LI1.

[0144] The plurality of second light emitting elements LD2 may be disposed between the second-stage first electrode ET12 and the second electrode ET22. For example, the plurality of second light emitting elements LD2 may be arranged in parallel with each other between each second-stage first electrode ET12 and the corresponding second-stage second electrode ET22.

[0145] Each second light emitting element LD2 may include a first end EP1 connected to any second-stage first electrode ET12 and a second end EP2 connected to any second-stage second electrode ET22. In an embodiment, the first end EP1 may be a P-type end, and the second end EP2 may be an N-type end.

[0146] In an embodiment, each second light emitting element LD2 may be connected between the first electrode ET12 and the second electrode ET22 of the second stage in the forward direction. For example, the first end EP1 of each of the second light emitting elements LD2 may be directly connected to any second-stage first electrode ET12, or may be connected to any second-stage first electrode ET12 through any second-stage first contact electrode CE12. Similarly, the second end EP2 of each of the second light emitting elements LD2 may be directly connected to any second-stage second electrode ET22, or may be connected to any second-stage second electrode ET22 through any second-stage second contact electrode CE22. The second light emitting element LD2 may form an effective light source of the second stage.

[0147] In an embodiment, at least one reverse light emitting element LDrv connected in a direction opposite to that of the second light emitting element LD2 may be further connected between the first electrode ET12 and the second electrode ET22 of the second stage. The at least one reverse light emitting element LDrv may remain disabled in the pixel PXL.

[0148] In an embodiment, each second-level first contact electrode CE12 may be disposed on each corresponding second-level first electrode ET12. Each second-level second contact electrode CE22 may be disposed on each corresponding second-level second electrode ET22. For example, in the case where a plurality of second-level first electrodes ET12 and a plurality of second-level second electrodes ET22 are disposed in the second sub-region SAR2, a plurality of second-level first contact electrodes CE12 disposed on each second-level first electrode ET12 and a plurality of second-level second contact electrodes CE22 disposed on each second-level second electrode ET22 may be disposed in the second sub-region SAR2. In an embodiment, the second-level first contact electrodes CE12 and the second contact electrodes CE22 may be disposed continuously or alternately at positions spaced apart from each other in the second direction DR2 in the second sub-region SAR2.

[0149] Each second-level first contact electrode CE12 may be disposed on each corresponding second-level first electrode ET12 and the first end EP1 of at least one second light emitting element LD2 adjacent to the second-level first electrode ET12, and electrically connect the first end EP1 to the corresponding second-level first electrode ET12. Likewise, each second-level second contact electrode CE22 may be disposed on each corresponding second-level second electrode ET22 and the second end EP2 of at least one second light emitting element LD2 adjacent to the second-level second electrode ET22, and electrically connect the second end EP2 to the corresponding second-level second electrode ET22. For example, the second-level first contact electrode CE12 and the second contact electrode CE22 may electrically connect the second light emitting element LD2 between the second-level first electrode ET12 and the second electrode ET22.

[0150] In an embodiment, each second-level first contact electrode CE12 may be connected integrally or non-integrally with at least one first-level (i.e., previous-level) second contact electrode CE21. Each second-level second contact electrode CE22 may be connected integrally or non-integrally with at least one third-level (i.e., next-level) first contact electrode CE13. For example, at least one 1-2 level connection electrode SCE1-2 configured to connect at least one first-level second contact electrode CE21 and at least one second-level first contact electrode CE12 may be disposed in a boundary region between the first sub-region SAR1 and the second sub-region SAR2. For example, at least one 2-3 level connection electrode SCE2-3 configured to connect at least one second-level second contact electrode CE22 and at least one third-level first contact electrode CE13 may be disposed in a boundary region between the second sub-region SAR2 and the third sub-region SAR3.

[0151] In an embodiment, the 2-3 level connection electrode SCE2-3 may extend in a third direction DR3 intersecting the first direction DR1 and the second direction DR2 in a boundary region between the second sub-region SAR2 and the third sub-region SAR3, and connect each second-level second contact electrode CE22 with at least one third-level first contact electrode CE13. For example, the 2-3 level connection electrode SCE2-3 may extend in a diagonal direction in a boundary region between the second sub-region SAR2 and the third sub-region SAR3, and connect each second-level second contact electrode CE22 to at least one third-level first contact electrode CE13. In an embodiment, the 2-3 level connection electrode SCE2-3 may be integrally connected with at least one second-level second contact electrode CE22 and at least one third-level first contact electrode CE13.

[0152] In an embodiment, if the light source unit LSU has only a two-stage series structure, each second-stage second contact electrode CE22 may have a separate individual pattern shape. In this case, each second-stage second contact electrode CE22 may be connected to the second line LI2 through the second-stage second electrode ET22.

[0153] At least one pair of third-level first electrodes ET13 and third-level second electrodes ET23 and a plurality of third light emitting elements LD3 connected therebetween may be disposed in the third sub-region SAR3. For example, a plurality of third-level first electrodes ET13 and a plurality of third-level second electrodes ET23 may be disposed in the third sub-region SAR3. In addition, at least one pair of third-level first contact electrodes CE13 and third-level second contact electrodes CE23 corresponding to the third-level first electrodes ET13 and the second electrodes ET23, respectively, may be selectively disposed in the third sub-region SAR3.

[0154] The first and second electrodes ET13 and ET23 of the third level may be disposed at positions spaced apart from each other in the third sub-region SAR3. In an embodiment, the first and second electrodes ET13 and ET23 of the third level may be regularly arranged in the third sub-region SAR3, but the present disclosure is not limited thereto.

[0155] In an embodiment, the first electrode ET13 and the second electrode ET23 of the third level may each have a rod shape extending in one direction in the third sub-region SAR3. For example, the first electrode ET13 and the second electrode ET23 of the third level may each have a rod shape extending in the first direction DR1, and are continuously or alternately arranged at positions spaced apart from each other in the second direction DR2 intersecting the first direction DR1. However, the shape, orientation and / or relative arrangement structure of the first electrode ET13 and the second electrode ET23 of the third level may be changed in various ways.

[0156] In an embodiment, each third-level first electrode ET13 may have a separate individual pattern shape. Each third-level first electrode ET13 may be electrically connected to at least one electrode of the previous level. For example, each third-level first electrode ET13 may be electrically connected to any second-level second electrode ET22 and / or any second-level second contact electrode CE22 through a corresponding third-level first contact electrode CE13 or without using the third-level first contact electrode CE13.

[0157] In an embodiment, each third-level second electrode ET23 may be connected to a second line (also referred to as a "second connection line" or a "second connection pattern") LI2 in an integral or non-integrated manner. For example, each pixel PXL may also include a second line LI2 connected to at least one third-level second electrode ET23. For example, each pixel PXL may also include a second line LI2 integrally connected to a plurality of third-level second electrodes ET23. In this case, the third-level second electrode ET23 and the second line LI2 may be considered as different regions of one electrode, one line, or one pattern.

[0158] In an embodiment, in the area between the third-level second electrode ET23 and the second line LI2, the width of the conductive pattern forming the third-level second electrode ET23 and the second line LI2 may be locally reduced. If the above structure is used, any third-level second electrode ET23 may be easily separated from the second line LI2 as needed. For example, in the event of a short circuit defect in at least one third light-emitting element LD3 connected to any third-level second electrode ET23, any third-level second electrode ET23 may be separated from the second line LI2 to allow the defect of the pixel PXL caused by the short circuit defect to be repaired. However, the present disclosure is not limited thereto. For example, in an embodiment, the width of each third-level second electrode ET23 may be kept constant to the area where the third-level second electrode ET23 is connected to the second line LI2.

[0159] In an embodiment, during a cycle in which the display device is operating, a voltage of a second power source VSS or a second drive signal (e.g., a scan signal, a data signal, or a predetermined other control signal) may be provided to the second line LI2. In an embodiment, the second line LI2 may be electrically connected to a second contact hole CH2, a predetermined circuit element (e.g., at least one transistor forming a pixel circuit PXC), a power line (e.g., a second power line PL2), and / or a signal line (e.g., a scan line Si, a data line Dj, or a predetermined control line). For example, the second line LI2 may be connected to a second power line PL2 disposed thereunder through a second contact hole CH2. In an embodiment, the second line LI2 may be directly connected to the second power line PL2 or a predetermined signal line without using, for example, a second contact hole CH2 and / or a circuit element. In this case, the second line LI2 may be connected to the second power line PL2 or a predetermined signal line integrally or non-integrally.

[0160] In an embodiment, the second line LI2 connected to the second electrode ET23 of the last stage (e.g., the third stage) of each of the pixels PXL may be commonly connected to the plurality of pixels PXL. In the step of aligning the light emitting element LD, a predetermined second alignment signal (or second alignment voltage) may be provided to the second line LI2. During a period of actually driving the display device, a voltage of the second power source VSS or a predetermined second driving signal may be provided to the second line LI2.

[0161] The plurality of third light emitting elements LD3 may be disposed between the third-stage first electrode ET13 and the second electrode ET23. For example, the plurality of third light emitting elements LD3 may be arranged in parallel with each other between each third-stage first electrode ET13 and the corresponding third-stage second electrode ET23.

[0162] Each third light emitting element LD3 may include a first end EP1 connected to any third-stage first electrode ET13 and a second end EP2 connected to any third-stage second electrode ET23. In an embodiment, the first end EP1 may be a P-type end, and the second end EP2 may be an N-type end.

[0163] In an embodiment, each third light emitting element LD3 may be connected between the first electrode ET13 and the second electrode ET23 of the third stage in the forward direction. For example, the first end EP1 of each of the third light emitting elements LD3 may be directly connected to any one of the third-stage first electrodes ET13, or may be connected to any one of the third-stage first contact electrodes CE13. Similarly, the second end EP2 of each of the third light emitting elements LD3 may be directly connected to any one of the third-stage second electrodes ET23, or may be connected to any one of the third-stage second contact electrodes CE23. The third light emitting element LD3 may form an effective light source of the third stage.

[0164] In an embodiment, at least one reverse light emitting element LDrv connected in a direction opposite to that of the third light emitting element LD3 may be further connected between the first electrode ET13 and the second electrode ET23 of the third stage. At least one reverse light emitting element LDrv may remain disabled in the pixel PXL. For example, in addition to including a plurality of light emitting elements LD (e.g., the first light emitting element LD1, the second light emitting element LD2, and / or the third light emitting element LD3) disposed in the emission area EMA to form an effective light source, the pixel PXL may further include at least one reverse light emitting element LDrv disposed in the emission area EMA.

[0165] In an embodiment, the number of light emitting elements LD disposed in the emission area EMA may be greater than the number of reverse light emitting elements LDrv. For example, each of the first sub-area SAR1, the second sub-area SAR2, and the third sub-area SAR3 may include a first light emitting element LD1, a second light emitting element LD2, and a third light emitting element LD3, and the number of the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 is greater than the number of the reverse light emitting elements LDrv.

[0166] In an embodiment, in the step of aligning the light-emitting element LD, the alignment and bias of the light-emitting element LD provided to the emission area EMA in any direction (for example, the forward direction) can be controlled by adjusting the alignment signal (or alignment voltage) applied to each alignment electrode or forming a magnetic field. For example, in the step of aligning the light-emitting element LD, when the waveform of the alignment signal is adjusted or the magnetic field is formed in each emission area EMA, the number of light-emitting elements LD oriented in the forward direction so that each of its first ends EP1 is oriented toward the first alignment electrode and each of its second ends EP2 is oriented toward the second alignment electrode can be controlled to be greater than the number of reverse light-emitting elements LDrv oriented so that each of its first ends EP1 is oriented toward the second alignment electrode and each of its second ends EP2 is oriented toward the first alignment electrode. For example, the light-emitting element LD can be aligned by controlling the process conditions so that the ratio of the number of light-emitting elements LD oriented in the forward direction to the number of reverse light-emitting elements LDrv becomes about 80:20.

[0167] In an embodiment, each of the light emitting elements LD disposed in the emission area EMA may be a light emitting element made of a material having an inorganic crystal structure and having an ultra-small size, for example, in the range of nanometer to micrometer. For example, each light emitting element LD may be an ultra-small rod-type light emitting element (e.g., Figures 1a to 3b ). The size, type, shape, etc. of the light emitting element LD may be changed in various ways.

[0168] although Figure 6 1 and 2. In the embodiment shown in FIG. 1 , in a region where a pair of first electrodes ET1 and second electrodes ET2 are arranged to face each other, each light emitting element LD is uniformly and horizontally arranged between the first electrode ET1 and the second electrode ET2 in the first direction DR1, but the present disclosure is not limited thereto. For example, at least one of the light emitting elements LD may be arranged and / or connected between the first electrode ET1 and the second electrode ET2 in a diagonal direction. Alternatively, although not in FIG. Figure 6 As shown in the figure, at least one light emitting element (eg, an ineffective light source other than the reverse light emitting element LDrv) that is not completely connected between the first electrode ET1 and the second electrode ET2 may also be provided in each pixel region and / or in a region provided around the pixel region.

[0169] In an embodiment, the light emitting element LD may be prepared in the form of being dispersed in a predetermined solution, and then provided to the emission area EMA of each pixel PXL by an inkjet scheme or the like. For example, the light emitting element LD may be mixed with a volatile solvent and provided to each emission area EMA. Here, if a predetermined alignment signal (or alignment voltage) is applied to the first electrode ET1 and the second electrode ET2 (or the first alignment electrode and the second alignment electrode corresponding to the corresponding state of the first electrode ET1 and the second electrode ET2 before the first electrode ET1 and the second electrode ET2 are divided by the boundary of the corresponding sub-region), an electric field is formed between the first electrode ET1 and the second electrode ET2, whereby the light emitting element LD may be aligned between the first electrode ET1 and the second electrode ET2 (or the first alignment electrode and the second alignment electrode). After the light emitting element LD has been aligned, the solvent may be removed by a volatilization scheme or other schemes. In this way, the light emitting element LD may be reliably disposed between the first electrode ET1 and the second electrode ET2. Thereafter, since the first and second contact electrodes CE1 and CE2 are formed on opposite ends of the light emitting element LD, for example, on the first and second ends EP1 and EP2, the light emitting element LD may be more reliably connected between the first and second electrodes ET1 and ET2.

[0170] In an embodiment, each third-level first contact electrode CE13 may be disposed on each corresponding third-level first electrode ET13. Each third-level second contact electrode CE23 may be disposed on each corresponding third-level second electrode ET23. For example, in the case where a plurality of third-level first electrodes ET13 and a plurality of third-level second electrodes ET23 are disposed in the third sub-region SAR3, a plurality of third-level first contact electrodes CE13 disposed on each third-level first electrode ET13 and a plurality of third-level second contact electrodes CE23 disposed on each third-level second electrode ET23 may be disposed in the third sub-region SAR3. In an embodiment, the third-level first contact electrodes CE13 and the second contact electrodes CE23 may be disposed continuously or alternately at positions spaced apart from each other in the second direction DR2 in the third sub-region SAR3.

[0171] Each third-level first contact electrode CE13 may be disposed on each corresponding third-level first electrode ET13 and a first end EP1 of at least one third light emitting element LD3 adjacent to the third-level first electrode ET13, and electrically connects the first end EP1 to the corresponding third-level first electrode ET13. Similarly, each third-level second contact electrode CE23 may be disposed on each corresponding third-level second electrode ET23 and a second end EP2 of at least one third light emitting element LD3 adjacent to the third-level second electrode ET23, and electrically connects the second end EP2 to the corresponding third-level second electrode ET23. For example, the third-level first contact electrode CE13 and the second contact electrode CE23 may electrically connect the third light emitting element LD3 between the third-level first electrode ET13 and the second electrode ET23.

[0172] In an embodiment, each third-level first contact electrode CE13 may be integrally or non-integrally connected to at least one second-level (i.e., previous-level) second contact electrode CE22. For example, each third-level first contact electrode CE13 may be integrally connected to at least one 2-3 level connection electrode SCE2-3 and at least one second-level second contact electrode CE22 disposed in a boundary region between the second sub-region SAR2 and the third sub-region SAR3. Each third-level second contact electrode CE23 may have a separate individual pattern shape.

[0173] In the case where the emission area EMA includes at least three sub-areas as described above, in the Kth sub-area (K is a natural number of 3 or greater) of the emission area EMA, the first electrode and the second electrode of the Kth stage set at positions spaced apart from each other, the Kth light-emitting element arranged in parallel with each other between the first electrode and the second electrode of the Kth stage, and the first contact electrode and the second contact electrode of the Kth stage respectively set on the first electrode and the second electrode of the Kth stage and configured to electrically connect the Kth light-emitting element between the first electrode and the second electrode of the Kth stage may be provided. In the boundary area between the Kth sub-area and the sub-area of ​​the previous stage (i.e., the [K-1]th sub-area), at least one [K-1]-Kth stage connection electrode may be provided, and the [K-1]-Kth stage connection electrode is configured to connect the first contact electrode of the Kth stage to the second contact electrode of the previous stage (i.e., the [K-1]th stage). In the aforementioned embodiment, the first electrode ET11 of the first stage may be connected to the first line LI1, and the second electrode of the Kth or last stage may be connected to the second line LI2. In addition, each of the second electrode ET21 of the first stage, the first and second electrodes of the intermediate stages including the second stage, and the first electrode of the Kth or final stage may have separate individual pattern shapes.

[0174] Reference Figure 7The pixel PXL may further include a plurality of first partition walls PW1 (also referred to as "first walls" or "first banks") overlapping each first electrode ET1 and a plurality of second partition walls PW2 (also referred to as "second walls" or "second banks") overlapping each second electrode ET2. In an embodiment, the first partition walls PW1 and the second partition walls PW2 may each have a separate individual pattern.

[0175] In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be disposed under the first electrode ET1 and the second electrode ET2, respectively. For example, each first partition wall PW1 may be disposed under any first electrode ET1 disposed in any one of the first sub-region SAR1, the second sub-region SAR2, and the third sub-region SAR3. Each second partition wall PW2 may be disposed under any second electrode ET2 disposed in any one of the first sub-region SAR1, the second sub-region SAR2, and the third sub-region SAR3.

[0176] In an embodiment, each first partition wall PW1 may have a width smaller than that of each first electrode ET1 and be disposed under the first electrode ET1. For example, in a plan view, each first partition wall PW1 may have a shape corresponding to the first electrode ET1 and be disposed inside the first electrode ET1.

[0177] When the first partition wall PW1 is disposed under the first electrode ET1, the first electrode ET1 may protrude upward in the region where the first partition wall PW1 is disposed. Therefore, light emitted from the first end EP1 of the light emitting element LD facing the first electrode ET1 may be controlled to travel more efficiently in the forward direction of the display device.

[0178] In an embodiment, each second partition wall PW2 may have a width smaller than that of each second electrode ET2 and be disposed under the second electrode ET2. For example, in a plan view, each second partition wall PW2 may have a shape corresponding to each second electrode ET2 and be disposed inside the second electrode ET2.

[0179] When the second partition wall PW2 is disposed under the second electrode ET2, the second electrode ET2 may protrude upward in the region where the second partition wall PW2 is disposed. Therefore, light emitted from the second end EP2 of the light emitting element LD facing the second electrode ET2 may be controlled to travel more efficiently in the forward direction of the display device.

[0180] according to Figure 6 and Figure 7In an embodiment, the emission area EMA of each pixel PXL is divided into a plurality of sub-areas in any one direction (e.g., the first direction DR1), and the first electrode ET1 and the second electrode ET2, the light emitting element LD, and the first contact electrode CE1 and the second contact electrode CE2 are arranged in each sub-area. The second contact electrode CE2 of any level can be connected to the first contact electrode CE1 of the subsequent level between adjacent sub-areas through the connection electrode SCE passing through the boundary area between the sub-areas. In this way, the light emitting element LD provided to each emission area EMA can be connected in a series / parallel combination structure to form each light source unit LSU.

[0181] According to the aforementioned embodiment, since the light source unit LSU has a series / parallel combination structure, each pixel PXL can be reliably driven, and the driving current flowing through the display panel PNL can be reduced. Therefore, the power consumption efficiency can be improved. In addition, the light emitting element LD is biased and aligned, and a plurality of first electrodes ET1 and second electrodes ET2 are respectively arranged in a plurality of sub-regions, and the first contact electrode CE1 and the second contact electrode CE2 are alternately connected between adjacent sub-regions. Therefore, the main alignment direction of the biased aligned light emitting element LD can match the forward direction of each series stage. Therefore, the number of light emitting elements LD that can be used as an effective light source to form each light source unit LSU can be increased among the light emitting elements LD provided to the emission area EMA of each pixel PXL. That is, according to the aforementioned embodiment, the application efficiency of the light emitting element LD can be improved.

[0182] Figures 8 to 11 are cross-sectional views each showing a pixel PXL according to an embodiment of the present disclosure, and for example, showing a pixel PXL corresponding to Figure 7 Different implementations of a cross section of the pixel PXL along line II'. Fig.12 is a cross-sectional view showing a pixel PXL according to an embodiment of the present disclosure, and for example shows a pixel PXL corresponding to Figure 7 Implementation of the cross section of the pixel PXL along the line II-II'. Figures 4 to 7 refer to Figures 8 to 12 An embodiment of a cross-sectional structure of each pixel PXL is described.

[0183] Reference Figures 4 to 12 According to an embodiment of the present disclosure, the pixel PXL may include a display element layer DPL disposed on one surface of the base layer BSL and including a plurality of light emitting elements LD. In addition, the pixel PXL may selectively include a pixel circuit layer PCL. For example, the pixel PXL may further include a pixel circuit layer PCL disposed between the base layer BSL and the display element layer DPL.

[0184] In an embodiment, the pixel circuit layer PCL may include at least one circuit element electrically connected to the light emitting element LD. For example, the pixel circuit layer PCL may include at least one circuit element forming the pixel circuit PXC of each pixel PXL.

[0185] For example, the pixel circuit layer PCL may include a plurality of transistors T and a storage capacitor Cst disposed in each pixel region and forming a corresponding pixel circuit PXC, and the pixel circuit layer PCL may also include at least one power line and / or signal line connected to the pixel circuit PXC and / or the light source unit LSU. Here, in the case where the pixel circuit PXC is omitted and each light source unit LSU is directly connected to the first power line PL1 and the second power line PL2 (or a predetermined signal line), the pixel circuit layer PCL may be omitted. For the purpose of explanation, Figures 8 to 11 Only one transistor T among the circuit elements and lines provided in the pixel circuit layer PCL is representatively shown, and Fig.12 The storage capacitor Cst disposed in the pixel circuit layer PCL is shown. Here, the plane / cross-sectional structure of the pixel circuit layer PCL may be changed in various ways. The position and cross-sectional structure of each transistor T and the storage capacitor Cst may be changed in various ways according to the embodiment.

[0186] In addition, the pixel circuit layer PCL may include a plurality of insulating layers disposed between the respective electrodes and / or lines. In an embodiment, the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV sequentially stacked on one surface of the base layer BSL. In some embodiments, the pixel circuit layer PCL may further include at least one light shielding pattern (not shown) disposed under at least some of the transistors T.

[0187] The buffer layer BFL may prevent impurities from diffusing into each circuit element. The buffer layer BFL may be formed of a single layer, or may be formed of a multilayer having at least two or more layers. In the case where the buffer layer BFL has a multilayer structure, each layer may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.

[0188] In an implementation, each transistor T may include a semiconductor layer SCL, a gate electrode GE, and first and second transistor electrodes TE1 and TE2. Figures 8 to 11 An embodiment in which each transistor T includes a first transistor electrode TE1 and a second transistor electrode TE2 formed separately from the semiconductor layer SCL is shown, but the present disclosure is not limited thereto. For example, in an embodiment, the first transistor electrode TE1 and / or the second transistor electrode TE2 provided in at least one transistor T provided in each pixel region may be formed integrally with the corresponding semiconductor layer SCL.

[0189] The semiconductor layer SCL may be disposed on the buffer layer BFL. For example, the semiconductor layer SCL may be disposed between the gate insulating layer GI and the base layer BSL on which the buffer layer BFL is formed. The semiconductor layer SCL may include a first region in contact with each first transistor electrode TE1, a second region in contact with each second transistor electrode TE2, and a channel region disposed between the first region and the second region. In an embodiment, one of the first region and the second region may be a source region, and the other may be a drain region.

[0190] In an embodiment, the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region of the semiconductor layer SCL may be an intrinsic semiconductor, which is an undoped semiconductor pattern. Each of the first region and the second region of the semiconductor layer SCL may be a semiconductor pattern doped with predetermined impurities.

[0191] The gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween. For example, the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap at least one region of the semiconductor layer SCL.

[0192] The first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on each semiconductor layer SCL, with at least one interlayer insulating layer ILD and a gate insulating layer GI interposed therebetween. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on respective different ends of the semiconductor layer SCL, with the gate insulating layer GI and the interlayer insulating layer ILD interposed therebetween. The first transistor electrode TE1 and the second transistor electrode TE2 may be electrically connected to each semiconductor layer SCL. For example, the first transistor electrode TE1 and the second transistor electrode TE2 may be connected to the first region and the second region of the semiconductor layer SCL through respective contact holes passing through the gate insulating layer GI and the interlayer insulating layer ILD. In an embodiment, either one of the first transistor electrode TE1 and the second transistor electrode TE2 may be a source electrode, and the other may be a drain electrode.

[0193] At least one transistor T provided in the pixel circuit PXC may be connected to at least one pixel electrode. Figure 5e Any one of the first transistor electrode TE1 and the second transistor electrode TE2 of the first transistor T1 shown in FIG. 1 (e.g., the drain electrode) can be electrically connected to the first-level first electrode ET11 of the corresponding pixel PXL through a contact hole (e.g., the first contact hole CH1) passing through the passivation layer PSV and through a first line LI1 disposed above the passivation layer PSV.

[0194] The storage capacitor Cst may include a first capacitor electrode CET1 and a second capacitor electrode CET2 that are disposed on different layers and overlap each other. In an embodiment, the first capacitor electrode CET1 may be disposed on the same layer as the layer of the gate electrode GE of the transistor T. The second capacitor electrode CET2 may be disposed on the same layer as the layer of the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T. Here, the present disclosure is not limited thereto. The position of the first capacitor electrode CET1 and / or the second capacitor electrode CET2 may be changed in various ways. For example, in an embodiment, the interlayer insulating layer ILD may be formed of a plurality of insulating layers, and the first capacitor electrode CET1 or the second capacitor electrode CET2 may be disposed between the plurality of insulating layers. In an embodiment, at least one of the first capacitor electrode CET1 and the second capacitor electrode CET2 may be formed of a plurality of conductive layers.

[0195] In an embodiment, at least one signal line and / or power line connected to each pixel PXL may be provided on the same layer as the layer of one electrode of the transistor T in the circuit element forming the pixel circuit PXC. For example, the scan line Si of each pixel PXL may be provided on the same layer as the layer of the gate electrode GE. The data line Dj of each pixel PXL may be provided on the same layer as the layer of the first transistor electrode TE1 and the second transistor electrode TE2 of the transistor T. In addition, the first power line PL1 and / or the second power line PL2 may be provided on the same layer as the gate electrode GE of the transistor T or the first transistor electrode TE1 and the second transistor electrode TE2.

[0196] In an embodiment, the display element layer DPL may include a light source unit LSU for each of the pixels PXL. For example, the display element layer DPL may include a plurality of first electrodes ET1 and second electrodes ET2 disposed in the emission area EMA of each pixel PXL, a plurality of light emitting elements LD disposed between the first electrodes ET1 and the second electrodes ET2, and a plurality of first contact electrodes CE1 and second contact electrodes CE2 disposed to electrically connect the light emitting elements LD between the first electrodes ET1 and the second electrodes ET2. In addition, the display element layer DPL may further include, for example, at least one conductive layer and / or an insulating layer.

[0197] In an embodiment, the display element layer DPL may include first and second partition walls PW1 and PW2, first and second electrodes ET1 and ET2, a first insulating layer INS1, a light emitting element LD, an insulating pattern INP, first and second contact electrodes CE1 and CE2, and a second insulating layer INS2, which are sequentially arranged and / or formed on the base layer BSL and / or the pixel circuit layer PCL.

[0198] The first partition wall PW1 and the second partition wall PW2 may be disposed at positions spaced apart from each other in the emission area EMA of each pixel PXL. The first partition wall PW1 and the second partition wall PW2 may protrude from the base layer BSL and / or the pixel circuit layer PCL in a height direction of the base layer BSL. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may have substantially the same height, but the present disclosure is not limited thereto.

[0199] In an embodiment, the first partition wall PW1 may be disposed between the base layer BSL and / or the pixel circuit layer PCL and each first electrode ET1. The first partition wall PW1 may be disposed adjacent to the first end EP1 of the light emitting element LD. For example, one side surface of each of the first partition walls PW1 may be positioned adjacent to the first end EP1 of the light emitting element LD and disposed facing the first end EP1. In an embodiment, in the case where at least one reverse light emitting element LDrv is disposed around at least one first partition wall PW1, one side surface of the first partition wall PW1 may be disposed facing the second end EP2 of the reverse light emitting element LDrv.

[0200] In an embodiment, the second partition wall PW2 may be disposed between the base layer BSL and / or the pixel circuit layer PCL and the second electrode ET2. The second partition wall PW2 may be disposed adjacent to the second end EP2 of the light emitting element LD. For example, one side surface of the second partition wall PW2 may be positioned adjacent to the second end EP2 of the light emitting element LD and disposed facing the second end EP2. In an embodiment, in the case where at least one reverse light emitting element LDrv is disposed around at least one second partition wall PW2, one side surface of the second partition wall PW2 may be disposed facing the first end EP1 of the reverse light emitting element LDrv.

[0201] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may have various shapes. Figure 8 and Fig.10 As shown in , the first partition wall PW1 and the second partition wall PW2 may have a trapezoidal cross-section whose width gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have an inclined surface on at least one side. In an embodiment, as Fig. 9 and Fig.11As shown in , the first partition wall PW1 and the second partition wall PW2 may have a semicircular or semi-elliptical cross-section, the width of which gradually decreases upward. In this case, each of the first partition wall PW1 and the second partition wall PW2 may have a curved surface on at least one side surface. At least one electrode and / or an insulating layer disposed on the first partition wall PW1 and the second partition wall PW2 may have a curved surface in a region corresponding to the first partition wall PW1 and the second partition wall PW2.

[0202] In other words, the shape of each of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways without being particularly limited. In an embodiment, at least one of the first partition wall PW1 and the second partition wall PW2 may be omitted or changed in position.

[0203] Each of the first partition wall PW1 and the second partition wall PW2 may include an insulating material including at least one inorganic material and / or an organic material. For example, the first partition wall PW1 and the second partition wall PW2 may include at least one inorganic layer including various known inorganic insulating materials such as silicon nitride (SiN x ) or silicon oxide (SiO x ). Alternatively, the first partition wall PW1 and the second partition wall PW2 may include at least one organic layer and / or a photoresist layer including various known organic insulating materials, or may form a single-layer or multi-layer insulator including a combination of organic / inorganic materials. In the embodiment of the present disclosure, the constituent materials of the first partition wall PW1 and the second partition wall PW2 may be changed in various ways.

[0204] In an embodiment, each of the first partition wall PW1 and the second partition wall PW2 may be used as a reflector. For example, the first partition wall PW1 and the second partition wall PW2 together with the first electrode ET1 and the second electrode ET2 disposed on the first partition wall PW1 and the second partition wall PW2 may be used as a reflector to guide light emitted from each light emitting element LD in a desired direction, thereby enhancing the light efficiency of the pixel PXL.

[0205] The first and second electrodes ET1 and ET2 may be disposed on the first and second partition walls PW1 and PW2, respectively. The first and second electrodes ET1 and ET2 may be disposed at positions spaced apart from each other in each pixel region (specifically, each emission area EMA).

[0206] In an embodiment, the first electrode ET1 and the second electrode ET2 respectively disposed on the first partition wall PW1 and the second partition wall PW2 may have shapes corresponding to the respective shapes of the first partition wall PW1 and the second partition wall PW2. For example, the first electrode ET1 and the second electrode ET2 may have inclined surfaces or curved surfaces corresponding to the first partition wall PW1 and the second partition wall PW2, respectively, and protrude in the height direction of the base layer BSL.

[0207] Each of the first electrode ET1 and the second electrode ET2 may include at least one conductive material. For example, each of the first electrode ET1 and the second electrode ET2 may include at least one metal or its alloy among various metal materials, at least one material among conductive oxides and conductive polymers, and the various metal materials include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc., and the conductive oxides include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), antimony zinc oxide (AZO), indium tin zinc oxide (ITZO), tin oxide (SnO 2 ), a conductive polymer such as PEDOT, but the present disclosure is not limited thereto. For example, each of the first electrode ET1 and the second electrode ET2 may include other conductive materials such as carbon nanotubes and graphene. In other words, each of the first electrode ET1 and the second electrode ET2 may include at least one of various conductive materials to have conductivity, and its constituent materials are not particularly limited. In addition, each of the first electrode ET1 and the second electrode ET2 may have the same conductive material, or have at least one different conductive material.

[0208] Each of the first electrode ET1 and the second electrode ET2 may have a single-layer or multi-layer structure. For example, each of the first electrode ET1 and the second electrode ET2 may include at least one reflective electrode layer. Each of the first electrode ET1 and the second electrode ET2 may also selectively include at least one transparent electrode layer disposed above and / or below the reflective electrode layer and at least one conductive capping layer covering the upper portion of the reflective electrode layer and / or the transparent electrode layer.

[0209] In an embodiment, the reflective electrode layer of each of the first electrode ET1 and the second electrode ET2 may be formed of a conductive material having a uniform reflectivity. For example, the reflective electrode layer may include at least one of various metal materials or alloys thereof, and the various metal materials include silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc., but the present disclosure is not limited thereto. In other words, the reflective electrode layer may be formed of various reflective conductive materials. Each of the first electrode ET1 and the second electrode ET2 including the reflective electrode layer may allow the light emitted from the opposite ends (i.e., the first end EP1 and the second end EP2) of each of the light emitting elements LD to travel in the direction of displaying the image (e.g., in the forward direction). Specifically, if the first electrode ET1 and the second electrode ET2 have inclined surfaces or curved surfaces corresponding to the shapes of the first partition wall PW1 and the second partition wall PW2, respectively, and are disposed to face the first end EP1 and the second end EP2 of the light emitting element LD, respectively, light emitted from the first end EP1 and the second end EP2 of each light emitting element LD may be reflected by the first electrode ET1 and the second electrode ET2, and thus more reliably travel in the forward direction of the display panel PNL (e.g., in the upward direction of the base layer BSL). Thus, the efficiency of light emitted from the light emitting element LD may be improved.

[0210] In addition, the transparent electrode layer of each of the first electrode ET1 and the second electrode ET2 can be formed by various transparent conductive materials. For example, the transparent electrode layer may include ITO, IZO or ITZO, but the present disclosure is not limited thereto. In an embodiment, each of the first electrode ET1 and the second electrode ET2 may have a three-layer structure having a stacked structure of ITO / Ag / ITO. In this way, if the first electrode ET1 and the second electrode ET2 are each formed by a multilayer structure including at least two or more layers, the voltage drop caused by the signal delay (RC delay) can be minimized. Therefore, the desired voltage can be efficiently transmitted to the light emitting element LD.

[0211] In addition, if each of the first electrode ET1 and the second electrode ET2 includes a conductive capping layer covering the reflective electrode layer and / or the transparent electrode layer, the reflective electrode layer of the first electrode ET1 and the second electrode ET2 can be prevented from being damaged due to defects caused in the manufacturing process of the pixel PXL. However, the conductive capping layer may be selectively included in the first electrode ET1 and the second electrode ET2, and may be omitted according to the embodiment. In addition, the conductive capping layer may be considered as a component of each of the first electrode ET1 and the second electrode ET2, or as a separate component disposed on the first electrode ET1 and the second electrode ET2.

[0212] The first insulating layer INS1 may be disposed on a predetermined region of the first electrode ET1 and the second electrode ET2. For example, the first insulating layer INS1 may be formed to cover a predetermined region of the first electrode ET1 and the second electrode ET2, and may include an opening to expose another predetermined region of the first electrode ET1 and the second electrode ET2. For example, the first insulating layer INS1 may expose the first electrode ET1 and the second electrode ET2 in a predetermined first contact portion CNT1 and a second contact portion CNT2. In some embodiments, the first insulating layer INS1 may be omitted. In this case, the light emitting element LD may be directly disposed on one end of each of the passivation layer PSV and / or the first electrode ET1 and the second electrode ET2.

[0213] In an embodiment, the first insulating layer INS1 may be initially formed to cover the entire surface of the first electrode ET1 and the second electrode ET2. After providing the light emitting element LD and aligning the light emitting element LD on the first insulating layer INS1, the first insulating layer INS1 may be partially opened to expose the first electrode ET1 and the second electrode ET2 in corresponding predetermined regions (e.g., corresponding first contact portions CNT1 and second contact portions CNT2) on the first partition wall PW1 and the second partition wall PW2. In an embodiment, after completing the provision and alignment of the light emitting element LD, the first insulating layer INS1 may be patterned in the form of separate patterns, which are segmentedly disposed under the light emitting element LD.

[0214] In other words, the first insulating layer INS1 may be interposed between the first and second electrodes ET1 and ET2 and the light emitting element LD, and may expose at least one region of each of the first and second electrodes ET1 and ET2. After forming the first and second electrodes ET1 and ET2, the first insulating layer INS1 may be formed to cover the first and second electrodes ET1 and ET2, thereby preventing the first and second electrodes ET1 and ET2 from being damaged or metal from being precipitated in subsequent processes. In addition, the first insulating layer INS1 may stably support each light emitting element LD.

[0215] The first insulating layer INS1 may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or an organic insulating material. For example, the first insulating layer INS1 may include various organic / inorganic insulating materials, including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al 2 O 3 ) etc. The constituent material of the first insulating layer INS1 is not particularly limited.

[0216] A plurality of light emitting elements LD may be provided to each pixel region (specifically, an emission region EMA of each pixel PXL in which the first insulating layer INS1 is formed) and aligned in each pixel region. For example, a plurality of light emitting elements LD may be provided to each emission region EMA by an inkjet method or the like, and the light emitting element LD may be aligned between the first electrode ET1 and the second electrode ET2 with a certain directionality by a predetermined alignment voltage (or alignment signal) applied to the first electrode ET1 and the second electrode ET2.

[0217] In an embodiment, at least some of the light emitting elements LD may be disposed between a pair of first and second electrodes ET1 and ET2 in a horizontal direction so that opposite ends (i.e., first and second ends EP1 and EP2) of each light emitting element LD with respect to a longitudinal direction thereof overlap with the pair of first and second electrodes ET1 and ET2. In addition, in an embodiment, other some of the light emitting elements LD may be disposed between the pair of first and second electrodes ET1 and ET2 in a diagonal direction. In an embodiment, at least some of the light emitting elements LD may be disposed between a pair of first and second electrodes ET1 and ET2 so that at least some of the light emitting elements LD do not overlap with the first and second electrodes ET1 and ET2, and may be connected to the first and second electrodes ET1 and ET2 through the first and second contact electrodes CE1 and CE2, respectively.

[0218] The insulating pattern INP may be disposed on a predetermined region of the light emitting element LD. For example, the insulating pattern INP may expose the first end EP1 and the second end EP2 of the light emitting element LD, and may be disposed only partially on a predetermined region of the light emitting element LD, the predetermined region including a corresponding central region of the light emitting element LD. The insulating pattern INP may be formed in each emission region EMA in an independent pattern, but the present disclosure is not limited thereto. According to an embodiment, the insulating pattern INP may be omitted. In this case, the opposite ends of the first contact electrode CE1 and the second contact electrode CE2 may be disposed directly on the light emitting element LD.

[0219] The insulating pattern INP may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or an organic insulating material. For example, the insulating pattern INP may include various organic / inorganic insulating materials including silicon nitride (SiN x ), silicon oxide (SiO x ), aluminum oxide (Al 2 O 3 ), photoresist (PR) material, etc. The constituent material of the insulating pattern INP is not particularly limited.

[0220] After the alignment of the light emitting element LD is completed, an insulating pattern INP is formed on the light emitting element LD, so that the light emitting element LD can be prevented from moving from the alignment position. In addition, in the case where there is a space between the first insulating layer INS1 and the light emitting element LD, the space can be filled with an insulating material introduced therein in the process of forming the insulating pattern INP. Therefore, the light emitting element LD can be supported more stably.

[0221] The opposite ends (i.e., the first end EP1 and the second end EP2) of the light emitting element LD that are not covered by the insulating pattern INP may be covered by the first contact electrode CE1 and the second contact electrode CE2, respectively. For example, the respective ends of the first contact electrode CE1 and the second contact electrode CE2 may be disposed on the first end EP1 and the second end EP2 of the light emitting element LD at positions spaced apart from each other, with the insulating pattern INP interposed therebetween.

[0222] In an embodiment, if Figure 8 and Fig. 9 As shown in , the first contact electrode CE1 and the second contact electrode CE2 can be simultaneously formed on the same layer on one surface of the base layer BSL. Therefore, the process of manufacturing the pixel PXL and the display device including the pixel PXL can be simplified. For example, compared with the case where the first contact electrode CE1 and the second contact electrode CE2 are formed by corresponding mask processes, the number of mask processes required to form the pixel PXL can be reduced, and the first contact electrode CE1 and the second contact electrode CE2 can be more easily formed.

[0223] In an embodiment, if Fig.10 and Fig.11 As shown in , the first contact electrode CE1 and the second contact electrode CE2 may be sequentially formed on different layers on one surface of the base layer BSL. An additional third insulating layer INS3 may be disposed between the first contact electrode CE1 and the second contact electrode CE2. In other words, the positions and relative arrangement relationship of the first contact electrode CE1 and the second contact electrode CE2 may be changed in various ways.

[0224] In addition, the first contact electrode CE1 and the second contact electrode CE2 may be disposed on the first electrode ET1 and the second electrode ET2 to cover the exposed regions (e.g., the first contact portion CNT1 and the second contact portion CNT2) of the first electrode ET1 and the second electrode ET2. For example, the first contact electrode CE1 and the second contact electrode CE2 may be disposed on at least predetermined regions of the first electrode ET1 and the second electrode ET2 to contact the first electrode ET1 and the second electrode ET2 in the first contact portion CNT1 and the second contact portion CNT2. Therefore, the first contact electrode CE1 and the second contact electrode CE2 may be electrically connected to the first electrode ET1 and the second electrode ET2, respectively. The first electrode ET1 and the second electrode ET2 may be electrically connected to the first end EP1 and the second end EP2 of the light emitting element LD, respectively, through the first contact electrode CE1 and the second contact electrode CE2.

[0225] In an embodiment, at least one of the first contact electrode CE1 and the second contact electrode CE2 may be integrally or non-integrally connected to at least one contact electrode disposed in a previous stage or a subsequent stage. Fig.12 As shown in FIG. 1 , each first-level second contact electrode CE21 may be integrally connected to at least one 1-2 level connection electrode SCE1-2 and at least one second-level first contact electrode CE12.

[0226] The first contact electrode CE1 and the second contact electrode CE2 may be formed of various transparent conductive materials. For example, the first contact electrode CE1 and the second contact electrode CE2 may include at least one of various transparent conductive materials including ITO, IZO, and ITZO, and the first contact electrode CE1 and the second contact electrode CE2 may be substantially transparent or translucent to satisfy a predetermined transmittance. Therefore, light emitted from the light emitting element LD through the first end EP1 and the second end EP2 may be emitted out of the display device through the first contact electrode CE1 and the second contact electrode CE2.

[0227] The second insulating layer INS2 may be disposed on the first contact electrode CE1 and the second contact electrode CE2. For example, the second insulating layer INS2 may be formed and / or disposed on the entire surface of the display area DA of the base layer BSL on which the first partition wall PW1 and the second partition wall PW2, the first electrode ET1 and the second electrode ET2, the light emitting element LD, the insulating pattern INP, and the first contact electrode CE1 and the second contact electrode CE2 are formed, so that the second insulating layer INS2 may cover the first partition wall PW1 and the second partition wall PW2, the first electrode ET1 and the second electrode ET2, the light emitting element LD, the insulating pattern INP, and the first contact electrode CE1 and the second contact electrode CE2. The second insulating layer INS2 may include at least one inorganic layer and / or an organic layer.

[0228] In an embodiment, the second insulating layer INS2 may include a thin film encapsulation layer having a multi-layer structure, but the present disclosure is not limited thereto. In some embodiments, at least one overcoat layer and / or an encapsulation substrate, etc. may be further disposed on the second insulating layer INS2.

[0229] In an embodiment, the second insulating layer INS2 may be formed of a single layer or multiple layers and include at least one inorganic insulating material and / or an organic insulating material. For example, the second insulating layer INS2 may include various known organic / inorganic insulating materials, including silicon nitride (SiN x ), silicon oxide (SiO x ) etc. The constituent material of the second insulating layer INS2 is not particularly limited.

[0230] Fig.13 is a plan view showing a driving current flowing through a pixel PXL according to an embodiment of the present disclosure, and for example shows a driving current flowing through Figure 7 For example, in Fig.13 When the pixel PXL is driven to emit light in response to a data signal having a predetermined gray level, the current flowing through Figure 7 The flow of the driving current of the pixel PXL is indicated by a dotted arrow.

[0231] Reference Figures 4 to 13 , if the driving current passes through the driving transistor of each pixel PXL (eg, Figure 5e The first transistor T1 of the first stage) flows from the first power line PL1 to the second power line PL2 via the pixel PXL, then the driving current can be introduced into the light source unit LSU through the first contact hole CH1. For example, the driving current can be provided to the first electrode ET11 of the first stage through the first contact hole CH1. The driving current can flow to the second electrode ET21 of the first stage via the first light emitting element LD1 connected between the first electrode ET11 and the second electrode ET21 of the first stage in the forward direction. Therefore, each of the first light emitting elements LD1 can emit light at a brightness corresponding to the associated distributed current.

[0232] The driving current flowing through the second electrode ET21 of the first stage may be introduced to the first electrode ET12 of the second stage through the 1-2 stage connecting electrode SCE1-2. The driving current may flow to the second electrode ET22 of the second stage via the second light emitting element LD2 connected between the first electrode ET12 and the second electrode ET22 of the second stage in the forward direction. Therefore, each of the second light emitting elements LD2 may emit light at a brightness corresponding to the associated distributed current.

[0233] The driving current flowing through the second electrode ET22 of the second stage may be introduced to the first electrode ET13 of the third stage through the 2-3 stage connecting electrode SCE2-3. The driving current may flow to the second electrode ET23 of the third stage via the third light emitting element LD3 connected between the first electrode ET13 and the second electrode ET23 of the third stage in the forward direction. Therefore, each of the third light emitting elements LD3 may emit light at a brightness corresponding to the associated distributed current.

[0234] The driving current flowing through the second electrode ET23 of the third stage can be introduced into the second power line PL2 via the second contact hole CH2. In this way, the driving current of each pixel PXL can flow through the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 in succession. Therefore, the pixel PXL can emit light with a brightness corresponding to the data signal provided during each frame period.

[0235] Figures 14a to 14e are plan views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing a method of manufacturing a display device including Figure 7 An embodiment of the method of a display device of a pixel PXL. Figures 15a to 15e are cross-sectional views sequentially showing a method of manufacturing a display device according to an embodiment of the present disclosure, and for example, showing Figures 14a to 14e The embodiment of the cross section corresponding to the line III-III'. Figures 8 to 12 The embodiment of the present invention discloses in detail a cross section of a connection structure of the light emitting element LD connected between the first electrode ET1 and the second electrode ET2 in the forward direction, so that Figures 15a to 15e In FIG. 1 , a cross section of a connection structure of the reverse light emitting element LDrv will be shown.

[0236] Reference Fig.14a and Fig.15a The first partition wall PW1 and the second partition wall PW2 are formed at positions spaced apart from each other in the emission area EMA of each pixel PXL. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be formed in each pixel area (specifically, the emission area EMA of the corresponding pixel PXL) on the base layer BSL and / or the pixel circuit layer PCL.

[0237] In an embodiment, in the case where the emission area EMA includes a plurality of sub-areas (e.g., a first sub-area SAR1, a second sub-area SAR2, and a third sub-area SAR3), at least one pair of first partition walls PW1 and second partition walls PW2 may be formed in each of the first sub-area SAR1, the second sub-area SAR2, and the third sub-area SAR3. For example, in the case where the emission area EMA is divided into the first sub-area SAR1, the second sub-area SAR2, and the third sub-area SAR3 in the first direction DR1, at least one first partition wall PW1 and at least one second partition wall PW2 may be continuously or alternately arranged in the second direction DR2 in each of the first sub-area SAR1, the second sub-area SAR2, and the third sub-area SAR3. The first partition wall PW1 and the second partition wall PW2 may be selectively formed. In some embodiments, the step of forming the first partition wall PW1 and / or the second partition wall PW2 is omitted.

[0238] In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be formed by a process of forming an insulating layer including an inorganic material and / or an organic material and / or a patterning process (e.g., a mask process), and may be formed by various types of known processes. In an embodiment, the first partition wall PW1 and the second partition wall PW2 may be simultaneously formed on the same layer (or the same plane) on the base layer BSL using the same material, but the present disclosure is not limited thereto.

[0239] Reference Fig.14b and Fig.15b , at least one first alignment electrode ALE1 and at least one second alignment electrode ALE2 may be formed in the emission area EMA of each pixel PXL in which the first partition wall PW1 and the second partition wall PW2 are selectively formed. For example, a plurality of first alignment electrodes ALE1 and a plurality of second alignment electrodes ALE2 may be formed in the emission area EMA of each pixel PXL. In an embodiment, the first alignment electrode ALE1 and the second alignment electrode ALE2 may each extend in the first direction DR1 and be spaced apart from each other with respect to the second direction DR2. For example, a plurality of first alignment electrodes ALE1 and second alignment electrodes ALE2 may be formed in each emission area EMA and alternately arranged in the second direction DR2.

[0240] In an embodiment, each first alignment electrode ALE1 may include a plurality of first pad electrodes PAD1 and at least one first connector CP1, the first pad electrodes PAD1 being arranged in a line along the first direction DR1 in each emission area EMA and formed to cover each first partition wall PW1, the first connector CP1 being arranged between the first pad electrodes PAD1 and being integrally connected to the first pad electrode PAD1. In an embodiment, each first connector CP1 may be disconnected in a subsequent process. Therefore, each of the first pad electrodes PAD1 separated from each other may form a first electrode ET1. In an embodiment, each first connector CP1 may be formed to have a width smaller than the width of each first pad electrode PAD1. In this case, in a subsequent process, the first connector CP1 may be more easily disconnected or removed. However, the present disclosure is not limited thereto. For example, in an embodiment, each first connector CP1 may have the same width as the width of the first pad electrode PAD1.

[0241] Likewise, each second alignment electrode ALE2 may include a plurality of second pad electrodes PAD2 and at least one second connector CP2, the plurality of second pad electrodes PAD2 being arranged in a line along the first direction DR1 in each emission area EMA and being formed to cover each second partition wall PW2, at least one second connector CP2 being arranged between the second pad electrodes PAD2 and being integrally connected to the second pad electrodes PAD2. In an embodiment, each second connector CP2 may be disconnected in a subsequent process. Therefore, each of the second pad electrodes PAD2 separated from each other may form a second electrode ET2. In an embodiment, each second connector CP2 may be formed to have a width smaller than the width of each second pad electrode PAD2. Therefore, in a subsequent process, the second connector CP2 may be more easily disconnected or removed. However, the present disclosure is not limited thereto. For example, in an embodiment, each second connector CP2 may have the same width as the width of the second pad electrode PAD2.

[0242] In an embodiment, the first and second alignment electrodes ALE1 and ALE2 may be formed by a process of forming a conductive layer including at least one conductive material and / or a patterning process, and may be formed by various types of known processes.

[0243] Each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may be formed of a single layer or multiple layers. For example, each of the first alignment electrode ALE1 and the second alignment electrode ALE2 may have a multilayer structure including a reflective electrode layer, a conductive capping layer, etc. In this case, the step of forming the first alignment electrode ALE1 and the second alignment electrode ALE2 may include the step of forming a corresponding reflective electrode layer on the first partition wall PW1 and the second partition wall PW2 and the step of forming a corresponding conductive capping layer on the reflective electrode layer.

[0244] In addition, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be simultaneously formed on the same layer on the base layer BSL, but the present disclosure is not limited thereto. In the case where the first alignment electrode ALE1 and the second alignment electrode ALE2 are simultaneously formed, the number of mask processes for manufacturing a display device may be reduced or minimized.

[0245] In an embodiment, in the step of forming the first alignment electrode ALE1 and the second alignment electrode ALE2, a first line LI1 connected to the first alignment electrode ALE1 and a second line LI2 connected to the second alignment electrode ALE2 may be formed together. For example, at least one first line LI1 may be formed integrally with the first alignment electrode ALE1 so that at least one first line LI1 is commonly connected to the first alignment electrode ALE1 disposed in a plurality of pixels PXL disposed in the display area DA. At least one second line LI2 may be formed integrally with the second alignment electrode ALE2 so that at least one second line LI2 is commonly connected to the second alignment electrode ALE2 disposed in the plurality of pixels PXL.

[0246] In an embodiment, after forming the first alignment electrode ALE1 and the second alignment electrode ALE2, the first insulating layer INS1 may be formed to cover at least the first alignment electrode ALE1 and the second alignment electrode ALE2. For example, after forming the first alignment electrode ALE1 and the second alignment electrode ALE2 and the first line LI1 and the second line LI2, the first insulating layer INS1 may be formed to cover the first alignment electrode ALE1 and the second alignment electrode ALE2 and the first line LI1 and the second line LI2. The first insulating layer INS1 may be selectively formed. In some embodiments, the process of forming the first insulating layer INS1 may be omitted.

[0247] In an embodiment, the first insulating layer INS1 may be formed by a deposition process of an insulating layer including an inorganic insulating material and / or an organic insulating material, and may be formed by various types of known processes. For example, the first insulating layer INS1 may be formed by a deposition process of an insulating layer including at least one inorganic insulating material.

[0248] The first insulating layer INS1 may be formed of a single layer or a plurality of layers. In the case where the first insulating layer INS1 is formed of a plurality of layers, insulating material layers constituting the first insulating layer INS1 may be continuously formed.

[0249] Reference Fig.14c and Fig.15c , a plurality of light emitting elements LD are provided to each emission area EMA in which the first alignment electrode ALE1 and the second alignment electrode ALE2, the first insulating layer INS1, etc. are formed. The light emitting element LD is arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2. In an embodiment, the light emitting element LD may be provided to each emission area EMA by various schemes including an inkjet scheme. If a predetermined alignment signal (or alignment voltage) is applied to the first alignment electrode ALE1 and the second alignment electrode ALE2 through the first line LI1 and the second line LI2 while the light emitting element LD is provided or after the light emitting element LD is provided, the light emitting element LD is aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. For example, the light emitting element LD may be arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2 in the forward direction so that each of the first end EP1 and the second end EP2 of each light emitting element LD faces any corresponding alignment electrode in the first alignment electrode ALE1 and the second alignment electrode ALE2. In the above process, at least one reverse light emitting element LDrv may be provided between at least one pair of the first alignment electrode ALE1 and the second alignment electrode ALE2 in the direction opposite to the direction of the light emitting element LD. The reverse light emitting element LDrv can be provided to each pixel area (for example, the emission area EMA of each pixel PXL) together with the light emitting element LD through an inkjet printing scheme, etc., and the reverse light emitting element LDrv is arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2 in opposite directions so that its first end EP1 faces any one of the second alignment electrodes ALE2, and its second end EP2 faces any one of the first alignment electrodes ALE1.

[0250] In an embodiment, the ratio of the number of light emitting elements LD arranged in the forward direction to the number of reverse light emitting elements LDrv may be adjusted by various schemes (e.g., by applying a magnetic field or adjusting the waveform of an alignment signal to be applied in the step of aligning the light emitting elements LD). For example, the alignment light emitting elements LD may be biased by controlling process conditions so that the number of light emitting elements LD arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2 in the forward direction is approximately two times or more the number of reverse light emitting elements LDrv. In this case, the number of light emitting elements LD arranged between the first alignment electrode ALE1 and the second alignment electrode ALE2 in the forward direction and used as an effective light source may be increased, so that the light emitting elements LD may be used more efficiently.

[0251] In an embodiment, after aligning the light emitting element LD between the alignment electrodes ALE1 and ALE2, an insulating pattern INP may be formed on the light emitting element LD and / or the reverse light emitting element LDrv. The insulating pattern INP may be selectively formed. In some embodiments, the process of forming the insulating pattern INP may be omitted.

[0252] In addition, the first insulating layer INS1 may be etched by a process of patterning an insulating material layer for forming the insulating pattern INP or an etching process performed before or after the patterning process, thereby exposing one region of each of the first alignment electrode ALE1 and the second alignment electrode ALE2. For example, the first insulating layer INS1 may be etched so that the first alignment electrode ALE1 and the second alignment electrode ALE2 are exposed in regions corresponding to the predetermined first contact portion CNT1 and the second contact portion CNT2.

[0253] Reference Fig.14d and Fig.15d A first contact electrode CE1 and a second contact electrode CE2 are formed in each emission area EMA in which the light emitting element LD and / or at least one reverse light emitting element LDrv are arranged. Thus, the light emitting element LD and / or at least one reverse light emitting element LDrv can be electrically connected between the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0254] In an embodiment, in each emission region EMA, a plurality of first contact electrodes CE1 may be formed on different predetermined regions of each first alignment electrode ALE1 in the first direction DR1. For example, a first-level first contact electrode CE11, a second-level first contact electrode CE12, and a third-level first contact electrode CE13 may be formed on both the first pad electrode PAD1 in the first sub-region SAR1, the second sub-region SAR2, and the third sub-region SAR3 that are continuously arranged in the first direction DR1 and the first end EP1 of the light emitting element LD adjacent to the first pad electrode PAD1. Therefore, the first end EP1 of the light emitting element LD may be connected to the adjacent first alignment electrode ALE1 through the first contact electrode CE1. In addition, during the aforementioned process, the second end EP2 of at least one reverse light emitting element LDrv may be connected to the adjacent first alignment electrode ALE1.

[0255] Likewise, in each emission region EMA, a plurality of second contact electrodes CE2 may be formed on different predetermined regions of each second alignment electrode ALE2 in the first direction DR1. For example, a first-level second contact electrode CE21, a second-level second contact electrode CE22, and a third-level second contact electrode CE23 may be formed on the second pad electrodes PAD2 in the first sub-region SAR1, the second sub-region SAR2, and the third sub-region SAR3 that are consecutively arranged in the first direction DR1, and the second end EP2 of the light-emitting element LD adjacent to the second pad electrode PAD2. Therefore, the second end EP2 of the light-emitting element LD may be connected to the adjacent second alignment electrode ALE2 through the second contact electrode CE2. In addition, during the aforementioned process, the first end EP1 of at least one reverse light-emitting element LDrv may be connected to the adjacent second alignment electrode ALE2.

[0256] In an embodiment, the first contact electrode CE1 and the second contact electrode CE2 may be simultaneously formed in the same process step. For example, the first contact electrode CE1 and the second contact electrode CE2 may be simultaneously formed by applying a transparent conductive material to the base layer BSL on which the light emitting element LD and the like are arranged and patterning the conductive layer.

[0257] In an embodiment, in the step of forming the first contact electrode CE1 and the second contact electrode CE2, at least one connection electrode SCE may be further formed to cross-connect the first contact electrode CE1 and the second contact electrode CE2 in two consecutive stages (e.g., two consecutive series stages) disposed in the first direction DR1 of the emission area EMA. For example, during the process of patterning the first contact electrode CE1 and the second contact electrode CE2, at least one connection electrode SCE that connects the second contact electrode CE2 disposed in any one stage of the emission area EMA to at least one first contact electrode CE1 disposed in a subsequent stage may be formed integrally with the second contact electrode CE2 of any one stage and the first contact electrode CE1 of the subsequent stage. For example, at least one 1-2 level connection electrode SCE1-2 that connects each first-level second contact electrode CE21 to at least one second-level first contact electrode CE12 in the boundary region of the first sub-region SAR1 and the second sub-region SAR2 and at least one 2-3 level connection electrode SCE2-3 that connects each second-level second contact electrode CE22 to at least one third-level first contact electrode CE13 in the boundary region of the second sub-region SAR2 and the third sub-region SAR3 may be formed.

[0258] Reference Fig.14e and Fig.15eIn the embodiment, the first alignment electrode ALE1 and the second alignment electrode ALE2 may be divided into a plurality of first electrodes ET1 and a plurality of second electrodes ET2, respectively, in each emission area EMA in which the first contact electrode CE1 and the second contact electrode CE2 are formed. For example, since the first connectors CP1 and the second connectors CP2 of the first alignment electrode ALE1 and the second alignment electrode ALE2 are disconnected or removed using a laser cutting scheme or the like for disconnecting a predetermined conductive pattern, line, etc. by applying a laser beam, each first alignment electrode ALE1 may be divided into a plurality of first electrodes ET1, and each second alignment electrode ALE2 may be divided into a plurality of second electrodes ET2.

[0259] In addition, during the process of forming the first electrode ET1 and the second electrode ET2 by dividing the first alignment electrode ALE1 and the second alignment electrode ALE2, the first line LI1 that has been connected between the pixels PXL may be disconnected so that the first line LI1 may be individually separated by the corresponding pixels PXL. Therefore, the pixels PXL may be independently driven.

[0260] A second insulating layer INS2 may be formed over the first and second contact electrodes CE1 and CE2. In an embodiment, before or after the first and second alignment electrodes ALE1 and ALE2 are divided into the first and second electrodes ET1 and ET2, the second insulating layer INS2 may be formed to cover the entire surface of the display area DA.

[0261] In addition, the method of manufacturing a display device according to an embodiment of the present disclosure may further include the steps of inspecting whether the light emitting element LD is defective and repairing the defective pixel PXL when necessary. This will be described in detail later herein.

[0262] Fig.16a and Fig.16b is a plan view showing a method of manufacturing a display device according to an embodiment of the present disclosure, and shows, for example, an embodiment related to a method of forming a first contact electrode CE1 and a second contact electrode CE2. Fig.16a and Fig.16b In the following description of the method for manufacturing a display device according to the embodiment of the present invention, the details related to the method will be omitted. Figures 14a to 15e A detailed description of an embodiment of the invention with a configuration similar to or identical to the configuration.

[0263] Reference Fig.16a and Fig.16b, the first contact electrodes CE1 and the second contact electrodes CE2 may be divided into a plurality of groups formed continuously. In other words, in an embodiment, some of the first contact electrodes CE1 and the second contact electrodes CE2 disposed in each emission region EMA and other contact electrodes may be formed continuously. For example, after forming at least one second contact electrode CE2 disposed in an odd-numbered stage of the emission region EMA and at least one first contact electrode CE1 disposed in an even-numbered stage of the emission region EMA, at least one first contact electrode CE1 disposed in an odd-numbered stage of the emission region EMA and at least one second contact electrode CE2 disposed in an even-numbered stage of the emission region EMA may be formed.

[0264] For example, at least one first-level second contact electrode CE21 may be formed in the first sub-region SAR1 and at least one third-level second contact electrode CE23 may be formed in the third sub-region SAR3 while at least one second-level first contact electrode CE12 may be formed in the second sub-region SAR2. In an embodiment, at least one first-level second contact electrode CE21 and at least one second-level first contact electrode CE12 may be integrally formed.

[0265] Thereafter, at least one first-level first contact electrode CE11 may be formed in the first sub-region SAR1 and at least one third-level first contact electrode CE13 may be formed in the second sub-region SAR2 while at least one second-level second contact electrode CE22 is formed in the third sub-region SAR3. In an embodiment, at least one second-level second contact electrode CE22 and at least one third-level first contact electrode CE13 may be formed integrally. In other words, the first contact electrode CE1 and the second contact electrode CE2 may be formed simultaneously or sequentially, and the method of forming the first contact electrode CE1 and the second contact electrode CE2 may be changed in various ways.

[0266] Figures 17 to 20 are plan views each showing a pixel PXL according to an embodiment of the present disclosure, and show, for example, different embodiments related to a pixel PXL in which a defect has been repaired. Figure 7 In the pixel PXL of the embodiment of the present invention, a driving defect due to a defective light emitting element LDd has occurred at various positions. Figures 17 to 20 A repaired pixel PXL according to each embodiment is each shown.

[0267] Reference Fig.17 and Fig.18In the event of a short-circuit defect (wherein the first end EP1 and the second end EP2 of at least one light-emitting element (hereinafter, referred to as a "defective light-emitting element LDd") connected between the first electrode ET1 and the second electrode ET2 in the forward direction are short-circuited), most of the driving current flows through the defective light-emitting element LDd at least in the corresponding series stage, whereby the pixel PXL may not be able to express the desired brightness. In this case, in an embodiment of the present disclosure, at least one of the first contact electrode CE1 and the second contact electrode CE2 directly connected to the defective light-emitting element LDd may be separated (or isolated) from the other of the first contact electrode CE1 and the second contact electrode CE2 to allow the defect of the pixel PXL to be repaired.

[0268] In an embodiment, if Fig.17 As shown in, in the case where there are electrodes having a separate pattern shape in the first electrode ET1 and the second electrode ET2 connected to the first end EP1 and the second end EP2 of the defective light emitting element LDd, the corresponding contact electrode connected to the electrode having the separate pattern can be separated from the other contact electrodes. For example, in the case where the first-stage first electrode ET11 connected to the defective light emitting element LDd provided in the first stage is connected to the first line LI1 and the second electrode ETd of the first stage connected to the defective light emitting element LDd has a separate pattern shape, the connection electrode SCE for connecting the second electrode ETd of the first stage to the first contact electrode CE12 of the second stage can be disconnected by a laser cutting scheme or the like. Therefore, the second electrode ETd and the second contact electrode CEd can be electrically insulated so that current cannot flow through the second electrode ETd and the second contact electrode CEd connected to the defective light emitting element LDd. In this case, the driving current flows through the light emitting element LD connected between the other first electrode ET11 and the second electrode ET21 of the corresponding series stage (e.g., the first stage), so that the pixel PXL can express the desired brightness.

[0269] In an embodiment, if Fig.18 As shown in , in the case where at least two defective light emitting elements LDd are commonly connected to the first electrode or the second electrode ETd and any corresponding contact electrode CEd, any contact electrode CEd can be separated from the other first contact electrode CE1 and the second contact electrode CE2. For example, when the connection electrode SCE connecting any contact electrode CEd to the first contact electrode CE1 or the second contact electrode CE2 of the previous stage or the next stage is disconnected, the first electrode or the second electrode ETd and the contact electrode CEd connected to the defective light emitting element LDd can be electrically insulated. Therefore, the defect of the pixel PXL can be repaired.

[0270] The method for manufacturing a display device including a pixel PXL according to the aforementioned embodiment may include a step of checking whether the light emitting element LD arranged in each pixel PXL has been short-circuited. In addition, in the case where it is determined that at least one of the light emitting elements LD is a defective light emitting element LDd, the method for manufacturing a display device may further include a step of disconnecting a connection electrode SCE that connects the first contact electrode or the second contact electrode CEd connected to the defective light emitting element LDd to the first contact electrode CE1 or the second contact electrode CE2 of another series stage (e.g., the previous stage or the next stage).

[0271] Reference Fig.19 and Fig. 20 , when the first electrode ET1 or the second electrode ET2 connected to at least one defective light emitting element LDd is separated from the first line LI1 or the second line LI2, the defect of the pixel PXL caused by the defective light emitting element LDd can be repaired. For example, in the case where a plurality of first electrodes ET1 and second electrodes ET2 are provided in each series stage and the defective light emitting element LDd is connected between a pair of first electrodes ET1 and second electrodes ET2 provided in the first series stage or the last series stage, any one electrode of the pair of first electrodes ET1 and second electrodes ET2 can be separated from the first line LI1 or the second line LI2.

[0272] For example, in the case where the light source unit LSU includes three series stages and at least one defective light emitting element LDd is connected between at least one pair of third-stage first electrodes ET13 and third-stage second electrodes ET23, at least one third-stage second electrode ETd connected to the defective light emitting element LDd may be separated from the second line LI2 by a laser cutting scheme, etc. Likewise, in the case where at least one defective light emitting element LDd is connected between at least one pair of first-stage first electrodes ET11 and first-stage second electrodes ET21, at least one first-stage first electrode ET11 connected to the defective light emitting element LDd may be separated from the first line LI1 by a laser cutting scheme, etc.

[0273] The method of manufacturing a display device including a pixel PXL according to the aforementioned embodiment may include the step of checking whether the light emitting element LD arranged in each pixel PXL has been short-circuited. In addition, in the case where it is determined that at least one of the light emitting elements LD is a defective light emitting element LDd, the method of manufacturing a display device may further include the step of separating the first electrode or the second electrode ETd connected to the defective light emitting element LDd from the first line LI1 or the second line LI2.

[0274] As described above, when a defect caused by a defective light emitting element LDd is detected in at least one pixel PXL, the effect of the pixel PXL can be easily repaired by isolating the first electrode or the second electrode ETd and the first contact electrode or the second contact electrode CEd connected to the defective light emitting element LDd. Therefore, the yield of the display device can be increased.

[0275] Figure 21 to Figure 22 are plan views each showing a pixel PXL according to an embodiment of the present disclosure, and for example, Figure 7 Different modified implementations related to the implementations of the present invention.

[0276] Reference Fig.21 and Fig. 22 , the number of series stages constituting each light source unit LSU may be varied in various ways. Fig.21 As shown in , the light source unit LSU may be formed by two series stages. In this case, each emission area EMA may be divided into a first sub-area SAR1 and a second sub-area SAR2 in a first direction DR1, and a first electrode ET1 and a second electrode ET2 and a light emitting element LD may be disposed in each sub-area. For example, at least one fourth light emitting element LD4, at least one fourth-level first electrode ET14, at least one fourth-level second electrode ET24, at least one fourth-level first contact electrode CE14, and at least one fourth-level second contact electrode CE24 may be disposed in the fourth sub-area SAR4. In the aforementioned embodiment, the first-level first electrode ET11 disposed in the first sub-area SAR1 may be directly connected to the first line LI1, and the second-level second electrode ET22 disposed in the second sub-area SAR2 may be directly connected to the second line LI2. In addition, the first-level second electrode ET21 and the second-level first electrode ET12 may be connected to each other through the first-level second contact electrode CE21, the 1-2-level connecting electrode SCE1-2, and the second-level first contact electrode CE12.

[0277] In an embodiment, the light source unit LSU may be formed of four or more series connected stages. Fig. 22As shown in , the light source unit LSU may be formed of four series stages. In this case, each emission area EMA may be divided into first to fourth sub-areas SAR1 to SAR4 in the first direction DR1, and the first electrode ET1 and the second electrode ET2 and the light emitting element LD may be disposed in each sub-area. In the aforementioned embodiment, the first electrode ET11 of the first stage disposed in the first sub-area SAR1 may be directly connected to the first line LI1, and the second electrode ET24 of the fourth stage disposed in the fourth sub-area SAR4 may be directly connected to the second line LI2. In addition, the second electrode ET21 of the first stage, the first electrode ET12 and the second electrode ET22 of the second stage, the first electrode ET13 and the second electrode ET23 of the third stage, and the first electrode ET14 of the fourth stage may be cross-connected to each other between the corresponding series stages through respective first contact electrodes CE1 and second contact electrodes CE2, 1-2 stage connection electrodes SCE1-2, 2-3 stage connection electrodes SCE2-3, and 3-4 stage connection electrodes SCE3-4.

[0278] As described in the foregoing embodiments, the structure of the light source unit LSU may be changed in various ways. For example, the series / parallel combination structure of the light emitting elements LD constituting the light source unit LSU may have various types.

[0279] Although the technical concept of the present disclosure is described through detailed embodiments, it should be noted that the above embodiments are merely illustrative and should not be considered as limiting. It should be understood by those skilled in the art that various changes, substitutions, replacements, variations and modifications may be made herein without departing from the scope of the present disclosure as defined by the appended claims.

[0280] The scope of the present disclosure is not limited by the detailed description of this specification, and should be defined by the appended claims. In addition, all changes or modifications of the present disclosure derived from the meaning and scope of the claims and their equivalents should be interpreted as being included in the scope of the present disclosure.

Claims

1. Display equipment, including: A pixel is arranged in a display area, and the pixel includes: The first sub-region and the second sub-region are sequentially arranged in a first direction; a first electrode and a second electrode of a first stage, arranged to be spaced apart from each other in the first sub-region; a first light emitting element, arranged in parallel between the first electrode and the second electrode of the first stage; The first contact electrode and the second contact electrode of the first stage are respectively disposed on the first electrode and the second electrode of the first stage and are configured to electrically connect the first light emitting element between the first electrode and the second electrode of the first stage; a first electrode and a second electrode of a second stage, arranged to be spaced apart from each other in the second sub-region; a second light emitting element, arranged in parallel between the first electrode and the second electrode of the second stage; The first contact electrode and the second contact electrode of the second stage are respectively disposed on the first electrode and the second electrode of the second stage and are configured to electrically connect the second light emitting element between the first electrode and the second electrode of the second stage; and a connecting electrode configured to connect the second contact electrode of the first level with the first contact electrode of the second level, wherein the first contact electrode and the second contact electrode of the first level and the first contact electrode and the second contact electrode of the second level are respectively arranged sequentially or alternately in the first sub-region and the second sub-region in a second direction intersecting the first direction, and The connection electrode extends in a boundary region between the first subregion and the second subregion in a third direction intersecting the first direction and the second direction, and connects the second contact electrode of the first level with the first contact electrode of the second level.

2. The display device according to claim 1, further comprising: A Kth sub-region, arranged after the first sub-region and the second sub-region in the first direction, K being a natural number of 3 or greater; a first electrode and a second electrode of a Kth stage, arranged to be spaced apart from each other in the Kth sub-region; A Kth light emitting element, arranged in parallel between the first electrode and the second electrode of the Kth stage; The first contact electrode and the second contact electrode of the Kth stage are respectively disposed on the first electrode and the second electrode of the Kth stage, and are configured to electrically connect the Kth light emitting element between the first electrode and the second electrode of the Kth stage; as well as Another connecting electrode is configured to connect the first contact electrode of the Kth stage to the second contact electrode of the previous stage.

3. The display device according to claim 2, further comprising: a first line connected to the first electrode of the first stage and configured to be provided with a first power supply voltage or a first driving signal; as well as A second line is connected to the second electrode of the Kth stage or the second electrode of the last stage and is configured to be provided with a second power supply voltage or a second driving signal.

4. The display device according to claim 3, wherein: The second electrode of the first stage, the first electrode and the second electrode of the intermediate stages including the second stage, and the first electrode of the Kth stage or the first electrode of the final stage each have a separate individual pattern shape.

5. The display device according to claim 1, further comprising: a first line connected to the first electrode of the first stage and configured to be supplied with a first power supply voltage or a first driving signal; as well as A second line is connected to the second electrode of the second stage and is configured to be supplied with a second power supply voltage or a second driving signal.

6. The display device according to claim 5, wherein: The second electrode of the first stage and the first electrode of the second stage each have a separate individual pattern shape.

7. The display device according to claim 1, wherein: The second contact electrode of the first stage, the connection electrode, and the first contact electrode of the second stage are integrally connected to each other.

8. The display device according to claim 1, wherein: The pixel further includes at least one reverse light emitting element connected between the first electrode and the second electrode of the first stage or between the first electrode and the second electrode of the second stage in a direction opposite to the first light emitting element and the second light emitting element.

9. The display device according to claim 8, wherein: The number of the first light emitting elements and the second light emitting elements is greater than the number of the at least one reverse light emitting element.

10. The display device according to claim 1, wherein: The pixels include: The plurality of first electrodes and the plurality of second electrodes of the first stage are arranged in the first sub-region; The plurality of first contact electrodes and the plurality of second contact electrodes of the first level are arranged in the first sub-region and respectively arranged on the first electrodes and the second electrodes of the first level; The plurality of first electrodes and the plurality of second electrodes of the second stage are arranged in the second sub-region; and The plurality of first contact electrodes and the plurality of second contact electrodes of the second level are disposed in the second sub-region and are respectively disposed on the first electrodes and the second electrodes of the second level.

11. The display device according to claim 10, in, The pixel further includes at least one defective light emitting element having opposite ends short-circuited between any pair of the first electrode and the second electrode of the first stage and between any pair of the first electrode and the second electrode of the second stage, and The first contact electrode or the second contact electrode directly connected to the defective light emitting element is separated from the remaining first contact electrodes and the second contact electrodes.

12. The display device according to claim 10, further comprising: a first line connected to at least one of the first electrodes of the first stage and configured to be supplied with a first power supply voltage or a first driving signal; a second line connected to at least one of the second electrodes of the second stage or at least one of the second electrodes of the last stage and configured to be supplied with a second power supply voltage or a second driving signal; as well as at least one defective light emitting element connected to any one of the first electrode of the first stage and the second electrode of the second stage or the second electrode of the final stage and having opposite ends short-circuited, Wherein, any one of the first electrodes or any one of the second electrodes is separated from the first line or the second line.

13. The display device according to claim 1, wherein: The pixels include: first partition walls disposed under the first electrode of the first stage and the first electrode of the second stage, respectively, and each having a separate individual pattern; and The second partition walls are respectively disposed under the second electrode of the first stage and the second electrode of the second stage and each has a separate individual pattern.

14. Display equipment, including: A pixel is arranged in a display area, and the pixel includes: The first sub-region and the second sub-region are sequentially arranged in a first direction; a first electrode and a second electrode of a first stage, arranged to be spaced apart from each other in the first sub-region; a first light emitting element, arranged in parallel between the first electrode and the second electrode of the first stage; The first contact electrode and the second contact electrode of the first stage are respectively disposed on the first electrode and the second electrode of the first stage and are configured to electrically connect the first light emitting element between the first electrode and the second electrode of the first stage; a first electrode and a second electrode of a second stage, arranged to be spaced apart from each other in the second sub-region; a second light emitting element, arranged in parallel between the first electrode and the second electrode of the second stage; The first contact electrode and the second contact electrode of the second stage are respectively disposed on the first electrode and the second electrode of the second stage and are configured to electrically connect the second light emitting element between the first electrode and the second electrode of the second stage; and a connecting electrode configured to connect the second contact electrode of the first level with the first contact electrode of the second level, Wherein, the pixels include: The plurality of first electrodes and the plurality of second electrodes of the first stage are arranged in the first sub-region; The plurality of first contact electrodes and the plurality of second contact electrodes of the first level are arranged in the first sub-region and respectively arranged on the first electrodes and the second electrodes of the first level; The plurality of first electrodes and the plurality of second electrodes of the second stage are arranged in the second sub-region; and The plurality of first contact electrodes and the plurality of second contact electrodes of the second level are disposed in the second sub-region and are respectively disposed on the first electrodes and the second electrodes of the second level.

15. The display device according to claim 14, further comprising: A Kth sub-region, arranged after the first sub-region and the second sub-region in the first direction, K being a natural number of 3 or greater; a first electrode and a second electrode of a Kth stage, arranged to be spaced apart from each other in the Kth sub-region; A Kth light emitting element, arranged in parallel between the first electrode and the second electrode of the Kth stage; The first contact electrode and the second contact electrode of the Kth stage are respectively disposed on the first electrode and the second electrode of the Kth stage, and are configured to electrically connect the Kth light emitting element between the first electrode and the second electrode of the Kth stage; as well as Another connecting electrode is configured to connect the first contact electrode of the Kth stage to the second contact electrode of the previous stage.

16. The display device according to claim 15, further comprising: a first line connected to the first electrode of the first stage and configured to be provided with a first power supply voltage or a first driving signal; as well as A second line is connected to the second electrode of the Kth stage or the second electrode of the last stage and is configured to be provided with a second power supply voltage or a second driving signal.

17. The display device according to claim 16, wherein: The second electrode of the first stage, the first electrode and the second electrode of the intermediate stages including the second stage, and the first electrode of the Kth stage or the first electrode of the final stage each have a separate individual pattern shape.

18. The display device according to claim 14, further comprising: a first line connected to the first electrode of the first stage and configured to be supplied with a first power supply voltage or a first driving signal; as well as A second line is connected to the second electrode of the second stage and is configured to be supplied with a second power supply voltage or a second driving signal.

19. The display device according to claim 18, wherein: The second electrode of the first stage and the first electrode of the second stage each have a separate individual pattern shape.

20. The display device according to claim 14, wherein: The second contact electrode of the first stage, the connection electrode, and the first contact electrode of the second stage are integrally connected to each other.

21. The display device according to claim 14, wherein: The pixel further includes at least one reverse light emitting element connected between the first electrode and the second electrode of the first stage or between the first electrode and the second electrode of the second stage in a direction opposite to the first light emitting element and the second light emitting element.

22. The display device according to claim 21, wherein: The number of the first light emitting elements and the second light emitting elements is greater than the number of the at least one reverse light emitting element.

23. The display device according to claim 14, in, The pixel further includes at least one defective light emitting element having opposite ends short-circuited between any pair of the first electrode and the second electrode of the first stage and between any pair of the first electrode and the second electrode of the second stage, and The first contact electrode or the second contact electrode directly connected to the defective light emitting element is separated from the remaining first contact electrodes and the second contact electrodes.

24. The display device according to claim 14, further comprising: a first line connected to at least one of the first electrodes of the first stage and configured to be supplied with a first power supply voltage or a first driving signal; a second line connected to at least one of the second electrodes of the second stage or at least one of the second electrodes of the last stage and configured to be supplied with a second power supply voltage or a second driving signal; as well as at least one defective light emitting element connected to any one of the first electrode of the first stage and the second electrode of the second stage or the second electrode of the final stage and having opposite ends short-circuited, Wherein, any one of the first electrodes or any one of the second electrodes is separated from the first line or the second line.

25. The display device according to claim 14, wherein: The pixels include: first partition walls disposed under the first electrode of the first stage and the first electrode of the second stage, respectively, and each having a separate individual pattern; and The second partition walls are respectively disposed under the second electrode of the first stage and the second electrode of the second stage and each has a separate individual pattern.

26. A method for manufacturing a display device, comprising: forming first and second alignment electrodes spaced apart from each other and each extending in a first direction and first and second lines respectively connected to the first and second alignment electrodes in an emission region of each pixel; providing a plurality of light emitting elements to the emission region and arranging the light emitting elements between the first alignment electrode and the second alignment electrode; forming a plurality of first contact electrodes and a plurality of second contact electrodes, wherein the plurality of first contact electrodes are disposed on different regions of the first alignment electrode in the first direction and are configured to connect the first end of the light emitting element to the first alignment electrode, and the plurality of second contact electrodes are disposed on different regions of the second alignment electrode in the first direction and are configured to electrically connect the second end of the light emitting element to the second alignment electrode; as well as dividing the first alignment electrode into a plurality of first electrodes arranged in the first direction, and dividing the second alignment electrode into a plurality of second electrodes arranged in the first direction, wherein forming the first contact electrode and the second contact electrode comprises connecting the second contact electrode disposed in the first level of the emission region to the first contact electrode disposed in the second level of the emission region, wherein forming the first contact electrode and the second contact electrode comprises forming a connecting electrode configured to integrally connect the second contact electrode disposed in the first level of the emission region to the first contact electrode disposed in the second level of the emission region, wherein forming the first alignment electrode and the second alignment electrode comprises forming a plurality of the first alignment electrodes and a plurality of the second alignment electrodes to be alternately arranged in the emission region in a second direction, and The connection electrode extends in a third direction intersecting the first direction and the second direction in a boundary region between the first level and the second level.

27. The method according to claim 26, wherein: Forming the first contact electrode and the second contact electrode sequentially includes: forming the second contact electrode disposed in the first level of the emission region and the first contact electrode disposed in the second level of the emission region; and The first contact electrode disposed in the first level of the emission region and the second contact electrode disposed in the second level of the emission region are formed.

28. The method according to claim 26, in, Forming the first contact electrode and the second contact electrode includes forming a plurality of connection electrodes configured to connect the second contact electrode disposed in any one stage of the emission region to the first contact electrode disposed in a subsequent stage of the emission region.

29. The method according to claim 28, further comprising: Checking whether there is a short circuit defect in the light emitting element; as well as In a case where it is determined that at least one of the light emitting elements is a defective light emitting element, the connection electrode connected to the first contact electrode or the second contact electrode connected to the defective light emitting element is disconnected.

30. The method of claim 28, further comprising: Checking whether there is a short circuit defect in the light emitting element; as well as In a case where it is determined that at least one of the light emitting elements is a defective light emitting element, the first electrode or the second electrode connected to the defective light emitting element is separated from the first line or the second line.

31. A method for manufacturing a display device, comprising: forming first and second alignment electrodes spaced apart from each other and each extending in a first direction and first and second lines respectively connected to the first and second alignment electrodes in an emission region of each pixel; providing a plurality of light emitting elements to the emission region and arranging the light emitting elements between the first alignment electrode and the second alignment electrode; forming a plurality of first contact electrodes and a plurality of second contact electrodes, wherein the plurality of first contact electrodes are disposed on different regions of the first alignment electrode in the first direction and are configured to connect the first end of the light emitting element to the first alignment electrode, and the plurality of second contact electrodes are disposed on different regions of the second alignment electrode in the first direction and are configured to electrically connect the second end of the light emitting element to the second alignment electrode; as well as dividing the first alignment electrode into a plurality of first electrodes arranged in the first direction, and dividing the second alignment electrode into a plurality of second electrodes arranged in the first direction, wherein forming the first contact electrode and the second contact electrode comprises connecting the second contact electrode disposed in the first level of the emission region to the first contact electrode disposed in the second level of the emission region, wherein forming the first alignment electrode and the second alignment electrode comprises forming a plurality of the first alignment electrodes and a plurality of the second alignment electrodes to be alternately arranged in the emission region in a second direction, and Wherein, forming the first contact electrode and the second contact electrode includes forming a plurality of connection electrodes, wherein the connection electrodes are configured to connect the second contact electrode disposed in any one level of the emission region to the first contact electrode disposed in a subsequent level of the emission region.

32. The method according to claim 31, wherein: Forming the first contact electrode and the second contact electrode includes forming a connection electrode configured to integrally connect the second contact electrode disposed in the first level of the emission region to the first contact electrode disposed in the second level of the emission region.

33. The method according to claim 31, wherein: Forming the first contact electrode and the second contact electrode sequentially includes: forming the second contact electrode disposed in the first level of the emission region and the first contact electrode disposed in the second level of the emission region; and The first contact electrode disposed in the first level of the emission region and the second contact electrode disposed in the second level of the emission region are formed.

34. The method of claim 31 , further comprising: Checking whether there is a short circuit defect in the light emitting element; as well as In a case where it is determined that at least one of the light emitting elements is a defective light emitting element, the connection electrode connected to the first contact electrode or the second contact electrode connected to the defective light emitting element is disconnected.

35. The method of claim 31 , further comprising: Checking whether there is a short circuit defect in the light emitting element; as well as In a case where it is determined that at least one of the light emitting elements is a defective light emitting element, the first electrode or the second electrode connected to the defective light emitting element is separated from the first line or the second line.

Images