Chip design method and device

Abstract

The embodiment of the present invention discloses a chip design method and device, which relates to the field of computer technology and can effectively improve the performance of a chip after aging. The method includes: obtaining unit constraints of a pending unit in a chip, wherein the unit constraints include factory performance constraints, factory energy consumption constraints, aging performance constraints, and aging energy consumption constraints of the pending unit; according to the unit constraints, selecting a target unit in a standard cell library corresponding to the pending unit as the pending unit, wherein the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the target unit all meet the corresponding unit constraints, and the target unit is the standard unit with the lowest aging energy consumption parameter among all standard units in the standard cell library that meet the unit constraints. The present invention is applicable to chip design.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a chip design method and device. Background Art

[0002] Many electronic devices (such as high-performance servers) are often in a state of high-speed operation for a long time. The chips in the devices, such as CPU (Central Processing Unit) chips, will be affected by various device aging phenomena during long-term operation, resulting in a weakening of the device's current generation ability, which in turn affects the normal operation of the chip, resulting in the performance of the chip and the device becoming worse and worse. Summary of the invention

[0003] In view of this, the embodiments of the present invention provide a chip design method and device, a chip, an electronic device, a computer-readable storage medium, and a server, which can effectively improve the performance of the chip after aging.

[0004] In a first aspect, an embodiment of the present invention provides a chip design method, the method comprising: obtaining unit constraints of a pending unit in a chip, the unit constraints comprising a factory performance constraint, a factory energy consumption constraint, an aging performance constraint, and an aging energy consumption constraint of the pending unit; according to the unit constraints, selecting a target unit in a standard cell library corresponding to the pending unit as the pending unit, wherein the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the target unit all satisfy the corresponding unit constraints, and the target unit is a standard unit with the lowest aging energy consumption parameter among all standard cells in the standard cell library that satisfy the unit constraints.

[0005] Optionally, acquiring the unit constraint condition of the pending unit in the chip includes: determining the unit constraint condition of the pending unit according to the overall constraint condition of the chip and the circuit structure of the chip.

[0006] Optionally, selecting a target cell as the to-be-determined cell in the standard cell library corresponding to the to-be-determined cell according to the cell constraints includes: traversing all standard cells in the standard cell library corresponding to the to-be-determined cell to obtain a preliminary cell having the cell constraints corresponding to the factory performance parameters, the factory energy consumption parameters, the aging performance parameters, and the aging energy consumption parameters, respectively; and selecting a preliminary cell having the lowest aging energy consumption parameter from the preliminary cells as the to-be-determined cell.

[0007] Optionally, selecting the preliminary selected unit with the lowest aging energy consumption parameter from the preliminary selected units as the pending unit includes: when there are at least two preliminary selected units with the lowest aging energy consumption parameter, selecting the preliminary selected unit with the slowest performance decay or the fastest energy consumption decay as the pending unit.

[0008] Optionally, before selecting a target cell as the pending cell in the standard cell library corresponding to the pending cell according to the cell constraint condition, the method further includes: simulating each of the standard cells in the standard cell library to obtain the factory performance parameters, the factory energy consumption parameters, the aging performance parameters, and the aging energy consumption parameters of each of the standard cells.

[0009] In a second aspect, an embodiment of the present invention further provides a chip design device, comprising: an acquisition module, used to acquire unit constraints of a pending unit in a chip, wherein the unit constraints include factory performance constraints, factory energy consumption constraints, aging performance constraints, and aging energy consumption constraints of the pending unit; a selection module, used to select a target unit as the pending unit in a standard cell library corresponding to the pending unit according to the unit constraints, wherein the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the target unit all satisfy the corresponding unit constraints, and the target unit is the standard unit with the lowest aging energy consumption parameter among all standard cells in the standard cell library that satisfy the unit constraints.

[0010] Optionally, the acquisition module is specifically used to determine the unit constraint condition of the to-be-determined unit according to the overall constraint condition of the chip and the circuit structure of the chip.

[0011] Optionally, the selection module includes: a traversal submodule, used to traverse all standard cells in the standard cell library corresponding to the pending cell, and obtain a preliminary selected cell whose factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters all satisfy the corresponding cell constraints; and a selection submodule, used to select the preliminary selected cell with the lowest aging energy consumption parameter from the preliminary selected cells as the pending cell.

[0012] Optionally, the selection submodule is specifically used to select the preliminary selected unit with the slowest performance decay or the fastest energy consumption decay as the pending unit when there are at least two preliminary selected units with the lowest aging energy consumption parameter.

[0013] Optionally, the chip design device also includes: a simulation module, which is used to simulate each of the standard cells in the standard cell library before selecting a target cell as the pending cell in the standard cell library corresponding to the pending cell according to the cell constraint condition, so as to obtain the factory performance parameters, the factory energy consumption parameters, the aging performance parameters, and the aging energy consumption parameters of each of the standard cells.

[0014] In the third aspect, an embodiment of the present invention further provides a chip, wherein at least one standard cell is arranged in the chip, and the standard cell is selected from its corresponding preset standard cell library, and the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the standard cell all meet the cell constraints of the chip on the standard cell, and the standard cell is the standard cell with the lowest aging energy consumption parameter among all the standard cells in the preset standard cell library that meet the cell constraints; wherein the cell constraints include the factory performance constraints, factory energy consumption constraints, aging performance constraints, and aging energy consumption constraints of the standard cell.

[0015] Optionally, the chip is used to be powered by a first voltage before a preset time node, and to be powered by a second voltage after the preset time node, wherein the first voltage is less than the second voltage.

[0016] In a fourth aspect, an embodiment of the present invention further provides an electronic device, comprising: a housing, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the housing, and the processor and the memory are arranged on the circuit board; a power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute any chip design method provided by the embodiments of the present invention.

[0017] In a fifth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement any chip design method provided by an embodiment of the present invention.

[0018] In a sixth aspect, an embodiment of the present invention further provides a server, wherein the server is provided with any chip provided by the embodiment of the present invention.

[0019] The chip design method and device, chip, electronic device, computer-readable storage medium, and server provided by the embodiments of the present invention can obtain the unit constraints of the pending unit in the chip, such as the factory performance constraints, factory energy consumption constraints, aging performance constraints, aging energy consumption constraints, etc. of the pending unit, and select the target unit as the pending unit in the standard cell library corresponding to the pending unit according to the unit constraints, wherein the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the target unit all meet the corresponding unit constraints, and the target unit is the standard unit with the lowest aging energy consumption parameter among all the standard units in the standard cell library that meet the unit constraints. In this way, the influence of standard cell aging is taken into account when selecting standard cells in chip design. Under the conditions of meeting the factory constraints and aging constraints, the standard cell with the lowest aging energy consumption parameter is selected as much as possible to reserve more energy consumption growth space. In this way, when the chip is aged, the chip performance can be improved by increasing the operating voltage. At the same time, since a large energy consumption growth space has been reserved, the increase in the operating voltage will not cause the energy consumption to break through the corresponding energy consumption constraint, thereby effectively improving the performance of the chip after aging. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A flow chart of a chip design method provided by an embodiment of the present invention;

[0022] Figure 2 is a circuit schematic diagram of a chip in an embodiment of the present invention;

[0023] Figure 3 A schematic diagram of the structure of a chip design device provided by an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of the structure of a chip provided by an embodiment of the present invention;

[0025] Figure 5 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] As mentioned in the background technology, many electronic devices are often in a state of high-speed operation for a long time. The chips in the devices will be affected by various device aging phenomena during long-term operation, resulting in a weakening of the device's current generation ability, which in turn affects the normal operation of the chip, resulting in the performance of the chip and the device becoming increasingly worse.

[0029] In order to effectively deal with the performance degradation caused by device aging, the inventors found in their research that the expected aging of each device inside the chip can be taken into account when designing the chip, and the standard unit with the lowest energy consumption after aging can be selected to implement the device under the premise of meeting various design constraints, so as to reserve more room for energy consumption growth. In this way, when the chip ages, the chip performance can be improved by increasing the operating voltage, and the energy consumption will not exceed the corresponding energy consumption constraints due to being too large, thereby effectively improving the performance of the chip after aging.

[0030] In order to enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial technical effects of the embodiments of the present invention, specific embodiments are described in detail below.

[0031] In a first aspect, an embodiment of the present invention provides a chip design method, which can effectively improve the performance of a chip after aging.

[0032] like Figure 1 As shown, the chip design method provided by the embodiment of the present invention may include:

[0033] S11, obtaining unit constraints of the pending unit in the chip, wherein the unit constraints include factory performance constraints, factory energy consumption constraints, aging performance constraints, and aging energy consumption constraints of the pending unit;

[0034] Specifically, the chip may include several circuit modules and / or circuit elements that implement different logical functions. If it is necessary to manufacture physical devices that meet the preset requirements according to these logical functions, then on the basis of realizing the circuit logic function, the specific physical characteristics of each circuit module and / or circuit element, such as the threshold voltage, channel length, size, layout style, etc. of the device, must be determined. These different physical characteristics will have different effects on the performance and energy consumption of the chip. The combination of different physical characteristics can produce different device models. The pending unit in this step is the circuit module and / or circuit device that has been determined in terms of logical function, waiting to determine what its specific physical characteristics are. For example, there is an inverter at a certain position of the chip, but the inverter can specifically include multiple types, such as an inverter with a threshold voltage of 0.2V, an inverter with a threshold voltage of 0.3V, an inverter with a channel length of L1, an inverter with a channel length of L2, etc. Then the inverter is the pending unit, and it is necessary to determine what physical characteristics the pending unit needs to have.

[0035] Unit constraints are constraints on the performance and energy consumption of the pending unit. Considering the influence of aging, in one embodiment of the present invention, the unit constraints may include the factory performance constraints, factory energy consumption constraints, aging performance constraints, and aging energy consumption constraints of the pending unit. Among them, the factory performance constraints may be what kind of performance the pending unit needs to have when it leaves the factory, for example, the transmission delay is less than the preset time threshold T1, etc. The aging performance constraints may be what kind of performance the pending unit needs to have after aging (for example, 5 years later), for example, the transmission delay is less than the preset time threshold T2, etc. For the same device, the performance at the factory is generally better than the performance after aging, that is, the preset time threshold T1 is less than the preset time threshold T2. Similarly, the factory energy consumption constraint may be how much the energy consumption of the pending unit needs to be below when it leaves the factory (generally referring to a flip), for example, the energy consumption is less than W1, and the aging energy consumption constraint may be how much the energy consumption of the pending unit needs to be below after aging, for example, the energy consumption is less than W2. For the same device, the energy consumption at the factory is often higher than the energy consumption after aging, that is, W1 is less than W2.

[0036] S12. According to the unit constraint conditions, a target unit is selected from the standard unit library corresponding to the unit to be determined as the unit to be determined, wherein the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the target unit all satisfy the corresponding unit constraint conditions, and the target unit is the standard unit with the lowest aging energy consumption parameter among all the standard units in the standard unit library that satisfy the unit constraint conditions.

[0037] One of the bases for selecting the pending unit is to examine whether the performance and energy consumption of the candidate unit meet the unit constraint conditions of the pending unit in the chip design. In the embodiment of the present invention, if the candidate unit can meet the factory performance constraint, factory energy consumption constraint, aging performance constraint, and aging energy consumption constraint of the pending unit, it can be determined that the candidate unit meets the unit constraint conditions. If the candidate unit does not meet any of the factory performance constraint, factory energy consumption constraint, aging performance constraint, and aging energy consumption constraint, it cannot be considered that the candidate unit meets the unit constraint conditions.

[0038] In one embodiment of the present invention, various devices with different physical characteristics corresponding to the unit to be determined can be pre-packaged in the same standard cell library, so that when determining the unit to be determined, the target unit can be selected from the standard cell library corresponding to the unit to be determined. For example, "NAND gates" of various size characteristics can be pre-packaged in a standard cell library, and each "NAND gate" therein is called a standard cell; "OR gates" of various size characteristics can be pre-packaged in another standard cell library, and each "OR gate" therein is called a standard cell. When the unit to be determined is a "NAND gate", the target unit can be selected from the standard cell library corresponding to the "NAND gate".

[0039] In this step, a target cell can be selected as the pending cell from the standard cell library corresponding to the pending cell. When making the selection, in addition to satisfying the cell constraint conditions corresponding to the pending cell, the target cell must also be the standard cell with the lowest aging energy consumption parameter among all the standard cells in the standard cell library that satisfy the cell constraint conditions. For example, in one embodiment of the present invention, the cell constraint conditions of an inverter are: the factory transmission delay is less than t0, the factory energy consumption is lower than w0, the aging transmission delay is less than t1, and the aging energy consumption is lower than w1. In the standard cell library, the standard cells cell1, cell2, and cell5 all meet this condition, but cell2 has the lowest energy consumption, so cell2 is selected as the target cell for the inverter.

[0040] The chip design method provided by the embodiment of the present invention can obtain the unit constraints of the pending unit in the chip, such as the factory performance constraints, factory energy consumption constraints, aging performance constraints, aging energy consumption constraints, etc. of the pending unit, and select the target unit as the pending unit in the standard cell library corresponding to the pending unit according to the unit constraints, wherein the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the target unit all meet the corresponding unit constraints, and the target unit is the standard unit with the lowest aging energy consumption parameter among all the standard units in the standard cell library that meet the unit constraints. In this way, the influence of standard cell aging is taken into account when selecting standard cells in chip design. Under the condition of meeting the factory constraints and aging constraints, the standard cell with the lowest aging energy consumption parameter is selected as much as possible to reserve more energy consumption growth space. In this way, when the chip is aged, the chip performance can be improved by increasing the operating voltage. At the same time, since a large energy consumption growth space has been reserved, the increase in the operating voltage will not cause the energy consumption to break through the corresponding energy consumption constraint, thereby effectively improving the performance of the chip after aging.

[0041] Specifically, in one embodiment of the present invention, step S11 of obtaining the unit constraint conditions of the pending unit in the chip may specifically include: determining the unit constraint conditions of the pending unit according to the overall constraint conditions of the chip and the circuit structure of the chip. In chip design, there will be an overall constraint condition for the performance, power consumption, etc. of the chip, and the implementation of this overall constraint condition must be specifically implemented in each module and / or device in the chip. Therefore, the overall constraint conditions of the chip can be apportioned according to the specific structure of the circuit in the chip to obtain the unit constraint conditions that each module and / or device needs to meet. Among them, the power consumption constraint conditions in the overall constraint conditions can specifically correspond to the energy consumption constraint conditions for each flip (or conversion) of each module and / or device.

[0042] In one embodiment of the present invention, the overall constraint conditions may include the overall factory performance constraint conditions, the overall factory energy consumption constraint conditions, the overall aging performance constraint conditions, and the overall aging energy consumption constraint conditions. When the constraint conditions are apportioned, each overall constraint condition can be apportioned separately. Optionally, for chips containing the same circuit modules and / or devices, the overall constraint conditions can be evenly apportioned. For example, in a chip, including 10 identical NAND gates, each NAND gate can share 1 / 10 of the total factory delay, 1 / 10 of the total factory energy consumption, 1 / 10 of the total aging delay, and 1 / 10 of the total aging energy consumption. Optionally, for chips containing different circuit modules and / or devices, the unit constraints corresponding to each pending unit can be roughly estimated based on the layout and routing of the circuit and the frequency of flipping of each circuit module and / or device.

[0043] After the cell constraint conditions of the pending cell are obtained, a target cell can be selected as the pending cell in the standard cell library corresponding to the pending cell according to the cell constraint conditions in step S12.

[0044] In order to facilitate the comparison of each standard cell in the standard cell library with the cell constraint condition, optionally, in one embodiment of the present invention, before selecting the target cell as the to-be-determined cell in the standard cell library corresponding to the to-be-determined cell according to the cell constraint condition in step S12, the chip design method provided by the embodiment of the present invention may also include: simulating each of the standard cells in the standard cell library to obtain the factory performance parameters, the factory energy consumption parameters, the aging performance parameters, and the aging energy consumption parameters of each of the standard cells. The simulation operation may be performed by dedicated simulation software according to the specific physical characteristics and manufacturing process of each standard cell.

[0045] In a specific implementation, step S12 selects a target cell as the to-be-determined cell in the standard cell library corresponding to the to-be-determined cell according to the cell constraint condition, and specifically may include: traversing all standard cells in the standard cell library corresponding to the to-be-determined cell, and obtaining a preliminary selected cell whose factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters all satisfy the corresponding cell constraint conditions; and selecting a preliminary selected cell with the lowest aging energy consumption parameter from the preliminary selected cells as the to-be-determined cell. That is to say, in an embodiment of the present invention, each standard cell in the standard cell library may be screened according to the cell constraint condition, and a preliminary selected cell satisfying the cell constraint condition may be found, and then a standard cell with the lowest aging energy consumption parameter may be selected from the preliminary selected cells as the to-be-determined cell. Optionally, depending on the constraint condition and the specific situation of the standard cell, the obtained preliminary selected cells may be either multiple or one.

[0046] Of course, in other embodiments of the present invention, other methods may be used to find the target unit. For example, the preliminary unit screening may not be performed, but the standard unit that meets the unit constraint condition and has the lowest aging energy consumption parameter may be directly selected.

[0047] Since there are many standard cells with different physical characteristics in the standard cell library, when selecting the pending cells, there may be two or more preliminary selected cells with the same and lowest aging energy consumption parameters. In order to further improve the performance of the chip after aging, in one embodiment of the present invention, selecting the preliminary selected cell with the lowest aging energy consumption parameter from the preliminary selected cells as the pending cell can specifically include: when there are at least two preliminary selected cells with the lowest aging energy consumption parameter, selecting the preliminary selected cell with the slowest performance decay or the fastest energy consumption decay as the pending cell. Among them, if the performance decay rate is slow, it means that the performance decay of the standard cell is not large after aging, and a small voltage increase is required to improve the performance after aging; if the energy consumption decay is fast, it means that the energy consumption of the standard cell decreases rapidly after aging, so that more energy consumption growth space can be provided to accommodate the energy consumption increase caused by voltage increase. For example, the aging energy consumption parameters of the three preliminary selected cells cell17, cell9, and cell8 are the same, and they are all the lowest values ​​among all standard cells that meet the cell constraint conditions. If the performance decay rate of cell17 is 10%, the performance decay rate of cell9 is 15%, and the performance decay rate of cell8 is 12%, then cell17 is selected as the pending cell. If the energy consumption decay rate of cell17 is 12%, the energy consumption decay rate of cell9 is 8%, and the energy consumption decay rate of cell8 is 15%, then cell8 is selected as the pending cell.

[0048] Optionally, in one embodiment of the present invention, the performance decay rate can be calculated based on the difference between the aging performance parameters and the factory performance parameters divided by the factory performance parameters, and the energy consumption decay rate can be calculated based on the difference between the aging energy consumption parameters and the factory energy consumption parameters divided by the factory energy consumption parameters.

[0049] In order to compare each standard cell in the standard cell library with the cell constraint conditions, in one embodiment of the present invention, before selecting the target cell as the to-be-determined cell in the standard cell library corresponding to the to-be-determined cell according to the cell constraint conditions in step S12, the chip design method provided by the embodiment of the present invention may also include: simulating each standard cell in the standard cell library to obtain the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of each standard cell. The simulation operation may be performed through dedicated simulation software according to the specific physical characteristics and manufacturing process of each standard cell.

[0050] The chip design method provided by the embodiment of the present invention is described in detail below through specific examples.

[0051] like Figure 2As shown, in one embodiment of the present invention, the chip includes 5 dual-input NAND gates NAND2. In the standard cell library, both type 1 NAND2 and type 2 NAND2 meet various cell constraints of NAND2. Table 1 shows the performance and energy consumption parameters of type 1 NAND2 after 5 years of aging, and Table 2 shows the performance and energy consumption parameters of type 2 NAND2 after 5 years of aging.

[0052] By comparing the data in Table 1 and Table 2, it is found that the speed of type2 NAND2 is slower than that of type1 and the energy consumption is lower. Since type1 itself is not friendly to anti-aging, the performance decay rate of type1 is (72.39-61.12) / 61.12=18.4%. At the same time, the performance decay rate of type2 is (73.17-65.4) / 65.4=11.88%. The aging performance parameter path delay of the two is basically the same. However, the energy consumption of type2 after aging is (2.05-1.81) / 2.05=11.7% less than that of type1 after aging. In other words, the performance of type2 circuit after aging is equivalent to that of type1 circuit, but the energy consumption is lower, so type2 has more room for performance improvement.

[0053] Table 1 Performance and energy consumption comparison of type 1 NAND2 before and after aging under 0.9V voltage drive

[0054] Path delay (picoseconds) <![CDATA[Conversion energy consumption (e -14 J)]]> Fresh 61.12 2.113 Aging (after 5 years) 72.39 2.05

[0055] Table 2 Performance and energy consumption comparison of type 2 NAND2 before and after aging under 0.9V voltage drive

[0056] Path delay (picoseconds) <![CDATA[Conversion energy consumption (e -14 J)]]> Fresh 65.4 1.83 Aging (after 5 years) 73.17 1.81

[0057] Assumptions Figure 2 The energy consumption constraint of each transition of the NAND gate after 5 years of aging is less than 2.05e -14 J, then for type 1 circuit, there is no room for additional energy consumption. However, for type 2 circuit, there is still (2.05-1.81)e -14 J=0.24e -14 The energy utilization space of J can accommodate the additional energy consumption caused by voltage increase.

[0058] Specifically, Table 3 shows the data of using energy space by increasing the power supply voltage to improve performance after type 2 aging. When the voltage increases from 0.9V to 0.95V, the energy constraint is basically met. At this time, the aging performance parameter path delay of type 2 is 3.8% faster than that of type 1 (i.e. (69.6-73.17) / 73.17=-3.8%).

[0059] Table 3 Effect of voltage increase on performance and energy consumption of type 2 NAND2 after aging

[0060] Path delay (picoseconds) <![CDATA[Conversion energy consumption (e -14 J)]]> 0.925V 71.28 1.92 0.95V 69.6 2.04 0.975 68.1 2.16

[0061] Table 4 Aging performance and energy consumption information of each standard cell in the standard cell library

[0062]

[0063] It can be seen that by reasonably selecting the type of standard cell stdcell, the standard cell can meet the timing requirements of factory (fresh) and aging (age), while minimizing the energy consumption of factory and aging, thereby exchanging for room for performance improvement. In this way, by reasonably utilizing the positive margin (slack) of the timing in the circuit to reselect high-reliability and low-energy logic cells, and then ensuring that the factory and aging timings are met (slack>0), the energy consumption after aging is the lowest, thereby reserving a large energy consumption growth space. In this way, when the chip is aged, the chip performance can be improved by increasing the operating voltage. At the same time, since a large energy consumption growth space has been reserved, the increase in the operating voltage will not cause the energy consumption to exceed the corresponding energy consumption constraint conditions, thereby effectively improving the performance of the chip after aging.

[0064] Exemplarily, the performance and energy consumption information of the device after aging can be shown in Table 4. Optionally, the data in Table 4 can be obtained by simulation or experimental statistics. In one embodiment of the present invention, the purpose of meeting the aging timing can be achieved by reasonably selecting low-energy consumption devices in Table 4, while meeting the purpose of reducing energy consumption after aging.

[0065] Correspondingly, in a second aspect, an embodiment of the present invention further provides a chip design device that can effectively improve the performance of a chip after aging.

[0066] like Figure 3 As shown, the chip design device provided by the embodiment of the present invention may include:

[0067] An acquisition module 31 is used to acquire unit constraints of the pending unit in the chip, wherein the unit constraints include factory performance constraints, factory energy consumption constraints, aging performance constraints, and aging energy consumption constraints of the pending unit;

[0068] The selection module 32 is used to select a target cell as the to-be-determined cell in the standard cell library corresponding to the to-be-determined cell according to the cell constraint condition, wherein the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the target cell all satisfy the corresponding cell constraint conditions, and the target cell is the standard cell with the lowest aging energy consumption parameter among all the standard cells in the standard cell library that satisfy the cell constraint conditions.

[0069] The chip design device provided by the embodiment of the present invention can obtain the unit constraints of the pending unit in the chip, such as the factory performance constraints, factory energy consumption constraints, aging performance constraints, aging energy consumption constraints, etc. of the pending unit, and select the target unit as the pending unit in the standard cell library corresponding to the pending unit according to the unit constraints, wherein the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the target unit all meet the corresponding unit constraints, and the target unit is the standard unit with the lowest aging energy consumption parameter among all the standard units in the standard cell library that meet the unit constraints. In this way, the influence of standard cell aging is taken into account when selecting standard cells in chip design. Under the condition of meeting the factory constraints and aging constraints, the standard cell with the lowest aging energy consumption parameter is selected as much as possible to reserve more energy consumption growth space. In this way, when the chip is aged, the chip performance can be improved by increasing the operating voltage. At the same time, since a large energy consumption growth space has been reserved, the increase in the operating voltage will not cause the energy consumption to break through the corresponding energy consumption constraint, thereby effectively improving the performance of the chip after aging.

[0070] Optionally, the acquisition module 31 may be specifically configured to determine the unit constraint of the to-be-determined unit according to the overall constraint of the chip and the circuit structure of the chip.

[0071] Optionally, the selection module 32 may include:

[0072] A traversal submodule, used for traversing all standard cells in the standard cell library corresponding to the undetermined cell, and obtaining a preliminary selected cell whose factory performance parameter, factory energy consumption parameter, aging performance parameter, and aging energy consumption parameter all satisfy the corresponding cell constraint conditions;

[0073] A selection submodule is used to select a preliminary selected unit with the lowest aging energy consumption parameter from the preliminary selected units as the pending unit.

[0074] Optionally, the selection submodule is specifically used to select the preliminary selected unit with the slowest performance decay or the fastest energy consumption decay as the pending unit when there are at least two preliminary selected units with the lowest aging energy consumption parameter.

[0075] Optionally, the chip design device provided by an embodiment of the present invention may further include: a simulation module, for simulating each of the standard cells in the standard cell library before selecting a target cell as the pending cell in the standard cell library corresponding to the pending cell according to the cell constraint condition, so as to obtain the factory performance parameters, the factory energy consumption parameters, the aging performance parameters, and the aging energy consumption parameters of each of the standard cells.

[0076] Correspondingly, in a third aspect, an embodiment of the present invention further provides a chip that can effectively improve the performance of the chip after aging.

[0077] like Figure 4 As shown, an embodiment of the present invention provides a chip 4, in which at least one standard cell 41 is arranged, and the standard cell 41 is selected from its corresponding preset standard cell library, and the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the standard cell 41 all meet the cell constraints of the chip on the standard cell, and the standard cell 41 is the standard cell with the lowest aging energy consumption parameter among all the standard cells in the preset standard cell library that meet the cell constraints; wherein the cell constraints include the factory performance constraints, factory energy consumption constraints, aging performance constraints, and aging energy consumption constraints of the standard cell 41.

[0078] The chip provided by the embodiment of the present invention can select a suitable standard cell in the standard cell library according to the cell constraints of the chip 4 on the standard cell 41 (such as factory performance constraints, factory energy consumption constraints, aging performance constraints, aging energy consumption constraints, etc.), and the factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the selected standard cells all meet the corresponding unit constraints, and the selected standard cell is the standard cell with the lowest aging energy consumption parameter among all the standard cells that meet the unit constraints in the standard cell library. In this way, the influence of standard cell aging is taken into account when selecting standard cells in chip design. Under the conditions of meeting the factory constraints and aging constraints, the standard cell with the lowest aging energy consumption parameter is selected as much as possible to reserve more energy consumption growth space. When the chip is aged, the chip performance can be improved by increasing the operating voltage. At the same time, since a large energy consumption growth space has been reserved, the increase in the operating voltage will not cause the energy consumption to break through the corresponding energy consumption constraints, thereby effectively improving the performance of the chip after aging.

[0079] Optionally, the chip 4 can be used to use a first voltage to supply power before a preset time node, and a second voltage to supply power after a preset time node, wherein the first voltage is less than the second voltage. The specific preset time node, the first voltage, and the second voltage can be determined according to the aging of the standard cell 41 in the chip 4, as long as the chip performance can be improved by increasing the operating voltage, and the increase in the operating voltage does not cause the energy consumption to exceed the corresponding energy consumption constraint.

[0080] Optionally, the chip provided in the embodiments of the present invention can be a processor chip, such as a CPU, a GPU (Graphics Processing Unit), etc., or other general or special chips, such as a single-chip microcomputer, an FPGA (Field-Programmable Gate Array), a decoder, etc.

[0081] Fourthly, Figure 5 As shown, an embodiment of the present invention further provides an electronic device, comprising: a housing 100, a processor 110, a memory 120, a circuit board 130 and a power supply circuit 140, wherein the circuit board 130 is arranged inside the space enclosed by the housing 100, and the processor 110 and the memory 120 are arranged on the circuit board 130; the power supply circuit 140 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 120 is used to store executable program code; the processor 110 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 120, so as to execute any one of the chip design methods provided in the aforementioned embodiments.

[0082] The specific execution process of the above steps by the processor 110 and the steps further performed by the processor 110 by running the executable program code can be found in the description of the above embodiments, which will not be repeated here.

[0083] In the fifth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement any chip design method provided by an embodiment of the present invention, thereby also achieving corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0084] In a sixth aspect, an embodiment of the present invention further provides a server, in which any one of the chips provided in the aforementioned embodiments is provided, so that the corresponding beneficial technical effects can also be achieved, which have been described in detail above and will not be repeated here.

[0085] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0086] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0087] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0088] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0089] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0090] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip design method, characterized in that: The method comprises: Obtain unit constraints of the pending unit in the chip, wherein the unit constraints include factory performance constraints, factory energy consumption constraints, aging performance constraints, and aging energy consumption constraints of the pending unit; wherein the factory performance constraint is that the transmission delay of the pending unit when it leaves the factory is less than a preset time threshold T1, the aging performance constraint is that the transmission delay of the pending unit after aging is less than a preset time threshold T2, and the preset time threshold T1 is less than the preset time threshold T2, the factory energy consumption constraint is that the energy consumption of the pending unit when it leaves the factory is less than W1, and the aging energy consumption constraint is that the energy consumption of the pending unit after aging is less than W2, and W1 is less than W2; According to the cell constraint, a target cell is selected in the standard cell library corresponding to the to-be-determined cell as the to-be-determined cell, wherein the factory performance parameter, factory energy consumption parameter, aging performance parameter, and aging energy consumption parameter of the target cell all satisfy the corresponding cell constraint, and the target cell is the standard cell with the lowest aging energy consumption parameter among all the standard cells in the standard cell library that satisfy the cell constraint, so that the chip is powered by a first voltage before a preset time node and is powered by a second voltage after the preset time node, wherein the first voltage is less than the second voltage; The step of selecting a target cell as the to-be-determined cell in the standard cell library corresponding to the to-be-determined cell according to the cell constraint condition comprises: traversing all standard cells in the standard cell library corresponding to the to-be-determined cell to obtain a preliminary selection cell of the cell constraint condition corresponding to the factory performance parameter, the factory energy consumption parameter, the aging performance parameter, and the aging energy consumption parameter respectively; selecting a preliminary selection cell with the lowest aging energy consumption parameter from the preliminary selection cells as the to-be-determined cell; wherein, when the preliminary selection cells with the lowest aging energy consumption parameter include at least two, selecting a preliminary selection cell with the slowest performance decay or the fastest energy consumption decay as the to-be-determined cell; the performance decay rate is calculated according to the difference between the aging performance parameter and the factory performance parameter divided by the factory performance parameter, and the energy consumption decay rate is calculated according to the difference between the aging energy consumption parameter and the factory energy consumption parameter divided by the factory energy consumption parameter.

2. The method according to claim 1, characterized in that The obtaining of the cell constraint conditions of the pending cells in the chip includes: The unit constraint condition of the pending unit is determined according to the overall constraint condition of the chip and the circuit structure of the chip.

3. The method according to any one of claims 1, characterized in that Before selecting a target cell in a standard cell library corresponding to the undetermined cell as the undetermined cell according to the cell constraint condition, the method further comprises: Each of the standard cells in the standard cell library is simulated to obtain the factory performance parameters, the factory energy consumption parameters, the aging performance parameters, and the aging energy consumption parameters of each of the standard cells.

4. A chip design device, characterized in that: The device comprises: An acquisition module is used to acquire unit constraints of the pending unit in the chip, wherein the unit constraints include the factory performance constraint, factory energy consumption constraint, aging performance constraint, and aging energy consumption constraint of the pending unit; wherein the factory performance constraint is that the transmission delay of the pending unit when it leaves the factory is less than a preset time threshold T1, the aging performance constraint is that the transmission delay of the pending unit after aging is less than a preset time threshold T2, and the preset time threshold T1 is less than the preset time threshold T2, the factory energy consumption constraint is that the energy consumption of the pending unit when it leaves the factory is less than W1, and the aging energy consumption constraint is that the energy consumption of the pending unit after aging is less than W2, and W1 is less than W2; A selection module is used to select a target cell in the standard cell library corresponding to the to-be-determined cell as the to-be-determined cell according to the cell constraint condition, wherein the factory performance parameter, factory energy consumption parameter, aging performance parameter, and aging energy consumption parameter of the target cell all meet the corresponding cell constraint condition, and the target cell is the standard cell with the lowest aging energy consumption parameter among all the standard cells in the standard cell library that meet the cell constraint condition, so that the chip is powered by a first voltage before a preset time node and is powered by a second voltage after the preset time node, wherein the first voltage is less than the second voltage; The selection module includes: a traversal submodule, which is used to traverse all standard cells in the standard cell library corresponding to the pending cell, and obtain the preliminary selected cells of the cell constraints corresponding to the factory performance parameters, the factory energy consumption parameters, the aging performance parameters, and the aging energy consumption parameters respectively; select the preliminary selected cell with the lowest aging energy consumption parameter from the preliminary selected cells as the pending cell; wherein, when the preliminary selected cells with the lowest aging energy consumption parameter include at least two, select the preliminary selected cell with the slowest performance decay or the fastest energy consumption decay as the pending cell; the performance decay rate is calculated according to the difference between the aging performance parameter and the factory performance parameter divided by the factory performance parameter, and the energy consumption decay rate is calculated according to the difference between the aging energy consumption parameter and the factory energy consumption parameter divided by the factory energy consumption parameter.

5. The device according to claim 4, characterized in that The acquisition module is specifically used to determine the unit constraint condition of the to-be-determined unit according to the overall constraint condition of the chip and the circuit structure of the chip.

6. The device according to claim 4, characterized in that Also includes: A simulation module is used to simulate each of the standard cells in the standard cell library before selecting a target cell as the pending cell in the standard cell library corresponding to the pending cell according to the cell constraint condition, so as to obtain the factory performance parameters, the factory energy consumption parameters, the aging performance parameters, and the aging energy consumption parameters of each of the standard cells.

7. A chip, wherein at least one standard cell is provided in the chip, wherein the standard cell is selected from a corresponding preset standard cell library, wherein: The factory performance parameters, factory energy consumption parameters, aging performance parameters, and aging energy consumption parameters of the standard cell all meet the cell constraints of the chip on the standard cell, and the standard cell is the standard cell with the lowest aging energy consumption parameter among all the standard cells in the preset standard cell library that meet the cell constraints, so that the chip is powered by a first voltage before a preset time node and by a second voltage after a preset time node, wherein the first voltage is less than the second voltage; wherein the cell constraints include the factory performance constraints, factory energy consumption constraints, aging performance constraints, and aging energy consumption constraints of the standard cell; the factory performance constraint is that the transmission delay of the to-be-determined cell when leaving the factory is less than A preset time threshold T1, an aging performance constraint that the transmission delay of the pending unit after aging is less than the preset time threshold T2, the preset time threshold T1 is less than the preset time threshold T2, the factory energy consumption constraint that the energy consumption of the pending unit when leaving the factory is less than W1, and the aging energy consumption constraint that the energy consumption of the pending unit after aging is less than W2, and W1 is less than W2; wherein, when the standard unit with the lowest aging energy consumption parameter includes at least two, the standard unit with the slowest performance decay or the fastest energy consumption decay is selected as the pending unit; the performance decay rate is calculated based on the difference between the aging performance parameter and the factory performance parameter divided by the factory performance parameter, and the energy consumption decay rate is calculated based on the difference between the aging energy consumption parameter and the factory energy consumption parameter divided by the factory energy consumption parameter.

8. An electronic device, characterized in that: include: A shell, a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is placed inside the space enclosed by the shell, and the processor and the memory are arranged on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs the program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the chip design method described in any one of claims 1 to 3.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the chip design method according to any one of claims 1 to 3.

10. A server, characterized in that: The server is provided with the chip according to claim 7.

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