System and method for program verification of a memory system

Abstract

The present invention provides a method for memory programming verification, the method comprising performing a write operation on a memory cell of a memory device. The method also comprises identifying a memory string associated with a corresponding memory cell of the memory cell. The method also comprises identifying a first memory string of the memory string. The method also comprises disabling a portion of write verification for the first memory string. The method also comprises enabling the portion of write verification for other memory strings of the memory string. The method also comprises performing at least the portion of a write verification operation on the memory string for which write verification has been enabled.

Description

Technical Field

[0001] The present disclosure relates to memory systems, and in particular to systems and methods for program-verifying memory systems. Background Art

[0002] A non-volatile memory system is a type of memory that retains stored information without the need for an external power source. Examples of non-volatile memory systems include flash memory, such as NAND flash or NOR flash. The NAND flash structure typically arranges multiple memory cell transistors (e.g., floating gate transistors or charge trapping transistors) in series with two select gates (e.g., drain side select gate and source side select gate) and between the two select gates. The memory cell transistors and select gates in series may be referred to as a NAND string. In order to reduce the cost per bit, the size of the NAND flash memory may be reduced.

[0003] Non-volatile memory is widely used in various electronic devices and stand-alone memory devices. For example, non-volatile memory may be present in laptop computers, digital audio players, digital cameras, smart phones, video games, scientific instruments, industrial robots, medical electronic devices, solid-state drives, USB drives, memory cards, etc. Non-volatile memory can be programmed / reprogrammed and erased electrically. In addition, data programmed into such non-volatile memory during the execution of the programming operation can be verified by performing a verification operation using a read verification voltage. Typically, the verification operation equalizes the channel potentials of the non-volatile memory. Summary of the invention

[0004] The present disclosure generally relates to memory management systems and methods.

[0005] One aspect of the disclosed embodiments includes a method for memory programming verification. The method includes performing a write operation on a memory cell of a memory device. The method also includes identifying a memory string associated with a corresponding memory cell of the memory cell. The method also includes identifying a first memory string of the memory string. The method also includes disabling a portion of write verification for the first memory string. The method also includes enabling the portion of write verification for other memory strings of the memory string. The method also includes performing at least the portion of a write verification operation on the memory string for which write verification has been enabled.

[0006] Another aspect of the disclosed embodiments includes a controller including a bus interface and a processor. The bus interface communicates with at least one memory block of a memory device. The processor is configured to: perform a write operation on a memory cell of at least one memory block; identify a memory string associated with a corresponding memory cell of the memory cell; identify a first memory string of the memory strings; disable a portion of write verification for the first memory string; enable the portion of write verification for other memory strings of the memory strings; and perform at least the portion of the write verification operation on the memory string for which write verification has been enabled.

[0007] Another aspect of the disclosed embodiments includes a method for memory programming verification. The method includes performing a write operation on a memory cell of a memory device. The method also includes identifying a memory string associated with a corresponding memory cell of the memory cell. The method also includes identifying a first memory string of the memory string, the first memory string including a memory string in the memory string to be first programmed during the execution of the write operation. The method also includes skipping the execution of a portion of the write verification operation on the first memory string in response to the completion of the execution of the write operation on the first memory string. The method also includes performing at least the portion of the write verification operation on the corresponding subsequently programmed memory string of the memory string in response to the completion of the execution of the write operation on the subsequently programmed memory string.

[0008] These and other aspects of the present disclosure are disclosed in the following detailed description of the embodiments, the appended claims and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It is emphasized that, according to convention, the various features of the drawings are not drawn to scale. On the contrary, the sizes of the various features are arbitrarily enlarged or reduced for clarity.

[0010] Figure 1A to Figure 1B A block diagram of an exemplary non-volatile memory system in accordance with the principles of the present disclosure is shown generally.

[0011] Figure 2A A block diagram generally illustrates exemplary components of a controller in accordance with the principles of the present disclosure.

[0012] Figure 2B A block diagram generally illustrates exemplary components of a non-volatile memory storage system in accordance with the principles of the present disclosure.

[0013] Figure 3 A memory block in accordance with the principles of the present disclosure is shown generally.

[0014] Figure 4A and Figure 4BA memory string verify voltage diagram in accordance with the principles of the present disclosure is generally shown.

[0015] Figure 5 is a flow chart illustrating a memory program verification method according to the principles of the present disclosure.

[0016] Figure 6 is a flow chart illustrating an alternative memory program verification method according to the principles of the present disclosure.

[0017] Figure 7 is a flow chart illustrating an alternative memory program verification method according to the principles of the present disclosure.

[0018] Figure 8 is a flow chart illustrating an alternative memory program verification method according to the principles of the present disclosure. DETAILED DESCRIPTION

[0019] The following discussion relates to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used as limiting the scope of the present disclosure, including the claims. In addition, it will be appreciated by those skilled in the art that the following description has broad application, and the discussion of any embodiment is intended only as an example of that embodiment and is not intended to imply that the scope of the present disclosure (including the claims) is limited to that embodiment.

[0020] As described, a non-volatile memory system is a type of memory that retains stored information without the need for an external power source. Examples of non-volatile memory systems include flash memory, such as NAND flash or NOR flash. The NAND flash structure typically arranges a plurality of memory cell transistors (e.g., floating gate transistors or charge trapping transistors) in series with two select gates (e.g., a drain side select gate and a source side select gate) and between the two select gates. The memory cell transistors and select gates in series may be referred to as a NAND string. In order to reduce the cost per bit, the size of the NAND flash memory may be reduced.

[0021] Non-volatile memory is widely used in various electronic devices and stand-alone memory devices. For example, non-volatile memory can be found in laptop computers, digital audio players, digital cameras, smart phones, video games, scientific instruments, industrial robots, medical electronics, solid-state drives, USB drives, memory cards, etc. Non-volatile memory can be programmed / reprogrammed and erased electrically.

[0022] During the execution of a programming operation (e.g., a write operation), data is written (e.g., stored) to memory cells of a nonvolatile memory. After the data is written to the memory cells, the data in the memory cells may be verified. For example, a controller associated with the nonvolatile memory may perform a programming or write verification operation, which may include applying a read verification voltage to a memory string including programmed memory cells and one or more other write verification operations or steps. The application of the read verification voltage may generate a verification voltage (e.g., causing a verification voltage spike) in the corresponding memory string. This may equalize the channel potential of the nonvolatile memory regardless of the state of the various memory cells of the nonvolatile memory, thereby eliminating the need for source side injection.

[0023] The execution of the portion of the verification operation including applying the read verification voltage may extend the entire programming operation for a relatively long time. For example, a typical programming cycle may be about 20 microseconds, and the portion of the verification operation may increase by about 10 microseconds for each programming cycle after the corresponding programming cycle. In addition, for non-volatile memories including multi-level cells, three-level cells, four-level cells, etc., the time to perform the portion of the verification operation may increase.

[0024] In addition to the time required to perform a programming operation (e.g., the time used to program during each programming cycle and to perform a verification operation), the time parameters of the verification operation may require special attention when tuning. For example, if the ramp-down time is insufficient, a relatively low state verification voltage level may be higher than expected. This may result in over-programming and voltage widening of the corresponding memory cell.

[0025] Typically, to account for the amount of time added from a verify operation to a programming operation, a verify operation may be disabled for a non-volatile memory. For example, during the execution of a programming operation, the controller does not perform a verify operation (e.g., does not apply a read verify voltage and does not verify the data programmed to the memory cell). However, this may not change other voltage biases or other related clocks (e.g., referred to as R2 and R3).

[0026] Therefore, systems and methods, such as those described herein, that are configured to reduce programming operation times when performing verification operations may be desirable. In some embodiments, the systems and methods described herein may be configured to perform a fast verification operation to improve write performance by skipping the application of a read verification voltage on a first memory string (e.g., Str0 or any other suitable memory string) that has been programmed during the execution of a programming operation. Figure 4A and Figure 4B The simplified waveform diagram of the verification operation in two cases is shown as a whole: Str0 (eg, the first memory string programmed during the programming operation), as shown in FIG. Figure 4Aand subsequent or other memory strings that have been programmed during execution of a programming operation, such as Figure 4B exemplified as a whole.

[0027] In some embodiments, the systems and methods described herein may be configured to perform write operations on memory cells of a memory device. The systems and methods described herein may be configured to identify a memory string associated with a corresponding memory cell of a memory cell. The systems and methods described herein may be configured to identify a first memory string of a memory string. The systems and methods described herein may be configured to disable a portion of write verification for a first memory string. The systems and methods described herein may be configured to enable write verification for the portion of other memory strings of a memory string. The systems and methods described herein may be configured to perform at least the portion of a write verification operation on a memory string for which write verification has been enabled.

[0028] In some embodiments, the systems and methods described herein may be configured to perform a write operation on a memory cell of a memory device. The systems and methods described herein may be configured to identify a memory string associated with a corresponding memory cell of a memory cell. The systems and methods described herein may be configured to identify a first memory string of a memory string, the first memory string including a memory string in a memory string to be first programmed during the execution of a write operation. The systems and methods described herein may be configured to skip the execution of a portion of a write verification operation on the first memory string in response to the completion of the execution of a write operation on a subsequently programmed memory string. The systems and methods described herein may be configured to perform that portion of a write verification operation on a corresponding subsequently programmed memory string of the memory string in response to the completion of the execution of a write operation on a subsequently programmed memory string.

[0029] In some embodiments, the systems and methods described herein can be configured to reduce or eliminate programming clocks (e.g., referred to as R1, R2, and R3, and overall in Figure 4A and Figure 4B ). The systems and methods described herein may be configured to replace the programming clock with a relatively shorter clock (e.g., referred to as R1) of the first memory string during the execution of a verification operation (e.g., saving approximately 10 microseconds for each programming lookup performed during the execution of a programming operation). The systems and methods described herein may be configured to provide fast verification operations for non-volatile memories, including single-level cells (SLCs), multi-level cells (MLCs), three-level cells (TLCs), four-level cells (QLCs), etc.

[0030] Figure 1AA block diagram of an exemplary system architecture 100 including non-volatile memory is shown. Specifically, the exemplary system architecture 100 includes a storage system 102 (e.g., which may be referred to as a memory system), a controller 104, and a host 106. In various embodiments, the host 106 may include any device or system that utilizes the storage system 102. In some embodiments, various aspects of the controller 104 may be implemented by the host 106, or the host 106 may include its own controller (e.g., a processor) configured to execute instructions stored in the storage system 102, and the host 106 may also access data stored in the storage system 102.

[0031] Examples of host 106 include computing devices such as desktop computers, rack-mounted servers, laptop computers, smart phones, tablet computers, or other suitable computing devices. Host 106 may also include systems and devices such as gaming systems, digital phones, digital cameras (e.g., digital still cameras and digital movie cameras), portable media players, digital photo frames, remote controllers, TV sticks, smart TVs, etc. In addition, system architecture 100 may be implemented in memory cards such as secure digital (SD) cards or micro secure digital (micro-SD) cards. In some embodiments, system architecture 100 is embedded in a host, for example, as a solid state disk (SSD) drive installed in a laptop computer.

[0032] In embodiments where the system architecture 100 is implemented within a memory card, the host 106 may include a built-in socket for one or more types of memory cards or flash drives (e.g., a universal serial bus (USB) port or a memory card slot). Additionally or alternatively, the host 106 may include an adapter into which a memory card may be inserted. The foregoing examples of hosts are not meant to be limiting examples. Rather, the host 106 may include any type of device, system, or apparatus that accesses the storage system 102.

[0033] exist Figure 1A In the embodiment of the present invention, the storage system 102 includes a memory controller and a driver (e.g., controller 104), as further described below, however, in some embodiments of the storage system 102, the storage system 102 may include only a memory unit that is instead controlled by software executed by a controller on a host 106 (e.g., a processor of a computing device controls the storage system 102, including its error handling). In addition, although Figure 1A The storage system 102 is shown separate from the host 106, but in some embodiments, the storage system 102 is embedded with the host 106, where the memory, controller, and drivers are formed on a single integrated circuit chip.

[0034] The host 106 may communicate with the storage system 102 using a bus 112 that implements any known or later developed communication protocol that enables the storage system 102 and the host 106 to communicate. The communication protocol may include a Secure Digital (SD) protocol, a Memory Stick (MS) protocol, a USB protocol, an Advanced Microcontroller Bus Architecture (AMBA), or other suitable communication protocols.

[0035] In various embodiments, the controller 104 acts as an interface between the host 106 and the storage system 102. The host 106 can communicate with the controller 104 via a bus interface associated with the bus 112. The controller 104 may include a single circuit component, a processing circuit (e.g., logic gates and switches), a processor, a microprocessor, a microcontroller with control software, or a field programmable gate array (FPGA). In addition, the exemplary controller 104 includes a computer-readable medium storing a computer-readable program code (e.g., software or firmware) that can be executed by the processor. In some embodiments, the controller 104 is a flash memory controller. In some embodiments, the controller 104 is a processor executed within the host 106.

[0036] Still reference Figure 1A According to some embodiments, the controller 104 acts as an interface between the host 106 and the storage system 102 and manages data stored on the storage system 102. For example, the host 106 can access data stored in the storage system 102 by providing a logical address to the controller 104 via a bus interface associated with the bus 112, and the controller 104 converts the logical address to a physical address. The controller 104 can access the data and / or specific storage location associated with the physical address and facilitate the transfer of data between the storage system 102 and the host 106. In some embodiments where the storage system 102 includes flash memory, the controller 104 formats the flash memory to ensure that the memory functions properly, marks bad flash memory cells, and allocates spare cells for future failed cells or for holding firmware to operate a flash memory controller (e.g., the controller 104).

[0037] Thus, controller 104 performs various memory management functions such as wear leveling (e.g., distributing write operations to extend the life of memory blocks), garbage collection (e.g., moving valid data pages to new blocks and erasing previously used blocks), and error detection and correction (e.g., read error handling).

[0038] Still reference Figure 1A, the memory system 102 includes a non-volatile memory (NVM) block 110, which may include a plurality of memory die 110-1 through 110-N. In some embodiments, the NVM block 110 defines a physical set of memory die, such as the memory die 110-1 through 110-N. In other embodiments, the NVM block 110 defines a logical set of memory die, where the NVM block 110 includes memory die from several physically different sets of memory die. Figure 1A The manner in which NVM block 110 is defined in is not meant to be limiting.

[0039] Each memory die, such as memory die 110-1, includes a nonvolatile memory cell, such as a NAND flash memory cell, a NOR flash memory cell, or other suitable memory cell. Because the memory cells are nonvolatile, the memory cells in the memory system 102 retain data even if there is an interruption in the power supplied to the memory cells and / or the memory system 102. Therefore, the memory system 102 can be easily transported, and the memory system 102 can be used in memory cards and other storage devices that are not always connected to a power source.

[0040] In various embodiments, the memory cells in the memory die 110 are solid-state memory cells (e.g., flash memory) and are one-time programmable, a few-time programmable, or many-time programmable. In addition, the memory cells in the memory die 110 may include single-level cells (SLC), multi-level cells (MLC), or triple-level cells (TLC). In some embodiments, the memory cells are manufactured in a planar manner (e.g., 2D NAND (NOT-AND) flash memory) or in a stacked or layered manner (e.g., 3D NAND flash memory). That is, a planar flash memory includes a single layer of memory cells, while a stacked flash memory includes memory cells stacked vertically in multiple layers (e.g., referred to as a planar).

[0041] In some embodiments and as Figure 1AAs shown, the controller 104 and the NVM block 110 are communicatively coupled via an interface 114 that implements any known or later developed communication protocol. In an embodiment where the storage system 102 is a flash memory, the interface 114 is a flash memory interface, such as switching mode 200, 400, 800, or a common flash memory interface (CFI). In various embodiments, the interface 114 can be implemented by a number of channels (e.g., physical connections) provided between the controller 104 and the individual memory tube cores 110-1 to 110-N. In addition, the number of channels on which the interface 114 is established varies based on the capabilities of the controller 104. In addition, a single channel can be configured to communicatively couple more than one memory tube core. The depiction of a single interface 114 is not meant to be restrictive. Instead, a single interface represents an exemplary interface that can be used between components, and one or more interfaces can be used to communicatively couple the same components.

[0042] Figure 1B 1 shows a block diagram of a system architecture 100 according to the principles of the present disclosure. The system architecture 100 can be implemented as part of a larger system architecture. Figure 1B As shown, the system architecture 150 includes a storage module 156, which further includes a number of storage systems 102. In the exemplary system architecture 150, the storage module 156 is communicatively coupled to the host 106 through a storage controller 152. In particular, the interface 154 between the host 106 and the storage module 156 includes a bus interface that implements any known or later developed communication protocol, such as a Serial Advanced Technology Attachment (SATA) or Peripheral Component Interface Express (PCIe) interface. In some embodiments, the storage module 156 is an SSD (e.g., in a laptop or tablet).

[0043] Some specific implementations of the system architecture 100 include a hierarchical storage system. The hierarchical storage system may include multiple storage controllers 152, each of which controls a corresponding storage system 102. In addition, multiple hosts 106 can each access the hierarchical storage system. The host 106 can access the memory within the hierarchical storage system via a bus interface that implements any known or later developed communication protocol, including Non-Volatile Memory Express (NVMe) or Fibre Channel over Ethernet (FCoE) interfaces. The hierarchical storage system can be implemented as a rack-mounted storage system that can be accessed by multiple host computers (e.g., a data center).

[0044] The interface 154 may be implemented by a number of channels (e.g., physical connections) provided between the storage controller 152 and the storage modules 156. In some embodiments, the number of channels on which the interface 154 is established varies based on the capabilities of the storage controller 152. The depiction of a single interface is not meant to be limiting, and the single interface represents an exemplary interface that may be used between components, where one or more interfaces may be used to communicatively couple various components.

[0045] Figure 2A 1 is a block diagram 200 of a storage system 102 according to the principles of the present disclosure. The block diagram 200 of the storage system 102 includes the previously described Figure 1A 1, such as controller 104 and NVM memory block 110. Additional components that may be present within storage system 102 include random access memory (RAM) 230, read only memory (ROM) 232, and other components 234. In some embodiments, ROM 232 stores system boot code.

[0046] Although RAM 230 and ROM 232 are shown as separate modules within storage system 102, the illustrated architecture is not meant to be limiting. For example, RAM 230 and ROM 232 may be located within controller 104. In some embodiments, portions of RAM 230 or ROM 232 are located outside controller 104 and within controller 104, respectively. In other embodiments, controller 104, RAM 230, and ROM 232 may be located on separate semiconductor dies. In various embodiments, other components 234 include external electrical interfaces, external RAM, resistors, capacitors, logic gates, or other components that interface with controller 104.

[0047] In some embodiments, the controller 104 includes a module 202 that interfaces with the host 106, a module 204 that interfaces with the NVM memory block 110, and various other modules, which will be further described below. The modules within the controller (e.g., modules 202 and 204) are communicatively coupled to each other via a bus 206.

[0048] The following discussion of the various modules depicted within the controller 104 is intended to be illustrative and non-limiting. For example, Figure 2A The various modules shown overall in FIG. 1 are not limited to execution within the controller 104 , and in some embodiments, one or more modules may execute external to the controller 104 .

[0049] Module 202 interfaces with host 106 and includes a host interface 208 and a physical layer interface 210, which provides an electrical interface between host 106 or a next-level storage controller and controller 104. Host interface 208 facilitates the transmission of data, control signals, and timing signals. Examples of host interface 208 include SATA, SATA Express, Serial Attached SCSI (SAS), Fibre Channel, USB, PCIe, and NVMe.

[0050] Still reference Figure 2A In various embodiments, module 204 is configured to communicate with NVM block 110 and includes an error correction code (ECC) engine 212. In some embodiments, ECC engine 212 encodes data received from host 106 and stores the encoded data in NVM block 110. When data is read out from NVM memory block 110, ECC engine 212 decodes the data and corrects errors detected within the data. To detect errors, ECC engine 212 implements various types of error checking using algorithms such as low-density parity check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, soft reads, and / or extra parity checks.

[0051] The exemplary module 204 also includes a sequencer 214 and a redundant array of independent drives (RAID) module 216. In various embodiments, the sequencer 214 generates command sequences, such as program and erase command sequences, that are transmitted to the NVM memory blocks 110. The RAID module 216 generates RAID parity and recovery of failed data. The RAID parity can be used to provide an additional level of integrity protection for data written to the NVM memory blocks 110. In some embodiments, the ECC engine 212 implements the functionality of the RAID module 216.

[0052] The exemplary module 204 also includes a memory interface 218 that provides command sequences to the NVM memory block 110 and receives status information from the NVM memory block 110. For example, the memory interface 218 implements any known or later developed communication protocol, including a double data rate (DDR) interface such as a switch mode 200, 400, or 800 interface. The module 204 also includes a flash control layer 220 that controls the overall operation of the module 204.

[0053] Still reference Figure 2A2, further modules within the controller 104 include a dummy word line (DW) pattern generation module 222, a DW error analysis module 224, and a read parameter adjustment module 226. Dummy word lines are placed on non-volatile memory dies for the purpose of analyzing and tracking the behavior and health of the corresponding non-volatile memory dies. In various embodiments, the DW pattern generation module 222 places known data patterns into the dummy word lines and tracks or periodically checks for errors by reading back data from the dummy word lines and comparing the data to the known data patterns.

[0054] In various embodiments, the read parameter adjustment module 226 adjusts parameters associated with a particular non-volatile memory die. For example and as further discussed below, the read parameter adjustment module 226 may adjust parameters associated with a particular non-volatile memory die during operation (e.g., reading or writing) to adjust or re-adjust read parameters. During the operation of re-adjusting read parameters, the read parameter adjustment module 226 adjusts the read parameters of a particular memory block, reads data from the memory block, and verifies the resulting BER. If the resulting BER is equal to or lower than the target or expected BER, the read parameter adjustment module 226 stores the read parameters of the memory block. Subsequently, the stored read parameters are used during reading any word line within the memory block. Therefore, the read parameters can be unique to the memory block.

[0055] Additional modules within the exemplary controller 104 include a buffer manager / bus controller 228 that manages, for example, buffers in the RAM 230 and controls internal bus arbitration of the bus 206 within the controller 104. Additionally or alternatively, the controller 104 may include a media management layer 236 that performs wear leveling of the NVM memory blocks 110. As previously mentioned, the various modules described with respect to the controller 104 are not meant to limit the architecture of the controller 104. For example, the physical layer interface 210, the RAID module 216, the media management layer 236, and the buffer management / bus controller 228 may be examples of optional components within the controller 104.

[0056] Furthermore, in embodiments where the storage system 102 includes flash memory, the media management layer 236 can be integrated as part of the flash management that handles flash errors and interfaces with the host 106. Specifically, the media management layer 236 can include an algorithm (e.g., firmware in a memory device) that converts write commands received from the host 106 into writes to the NVM memory blocks 110.

[0057] Figure 2B A block diagram generally illustrates various features of NVM memory block 110 within storage system 102. Since the details of controller 104 have been previously described (in Figure 2A), so in Figure 2B , the controller 104 is shown as a single block. Figure 2B The previously described RAM 230, ROM 232, and other components 234 are included to help locate the reader. Next, details within the example memory die 110-1 are discussed. Although the discussion focuses on the memory die 110-1, each feature discussed with respect to the memory die 110-1 is equally applicable to all memory dies within the NVM memory block 110.

[0058] In some embodiments, the exemplary memory die 110-1 includes control circuitry 250, read / write circuitry 252, row decoder 254, column decoder 256, and memory array 260. Memory array 260 may include a two-dimensional array or a three-dimensional array of memory cells. Read / write circuitry 252 reads and programs pages of memory within memory die 110-1 in parallel. In various embodiments, memory array 260 is accessed through word lines via row decoder 254 and through bit lines via column decoder 256.

[0059] The architecture of memory die 110-1 is not meant to be limiting, and any known architecture that can perform the function of accessing memory array 260 may be used without departing from the scope of the present disclosure. For example, in various embodiments, access to memory array 260 by various peripheral circuits may be implemented in a symmetrical manner on opposite sides of memory array 260, which will reduce the density of access lines and circuits on each side of memory array 260.

[0060] Still reference Figure 2B In various embodiments, exemplary control circuitry 250 includes power control circuitry 266, address decoder 268, and state machine 270. In some embodiments, power control circuitry 266, address decoder 268, and state machine 270 may be collectively referred to as management circuitry. Control circuitry 250 and its various management circuits are communicatively coupled to row decoder 254 and column decoder 256 via various interfaces (e.g., interfaces 262 and 264). In various embodiments, control circuitry 250 performs various operations on memory array 260, including reading or writing memory cells.

[0061] The power control circuit 266 controls the power and voltages provided to the word lines and bit lines during operation of the memory array 260. The address decoder 268 provides an address interface that converts addresses provided by the host 106 between addresses used by the row decoder 254 and the column decoder 256. The exemplary address decoder 268 converts addresses provided by the host 106 into addresses that are understood and compatible with the format used by the row decoder 254 and the column decoder 256. The state machine 270 provides chip-level control of memory operations.

[0062] Thus, the storage system 102 includes various components, including a controller 104 and an NVM memory block 110, the details of which are described above. Figure 1A , Figure 1B , Figure 2A and Figure 2B A discussion of the exemplary architecture of the exemplary memory array 260 and, in particular, methods that may be performed to improve read performance in the memory system 102 will now be discussed.

[0063] Figure 3 The memory array 260 is further described. The memory array 260 is divided into a number of memory blocks 302. In flash memory, a memory block is defined as an erase unit. That is, each memory block 302 includes a plurality of memory cells that are erased together or as a block. In some embodiments, the memory array 260 may be divided into any number of blocks, for example, the memory array 260 includes 1024 blocks. In addition or alternatively, each of the memory blocks 302 may be conceptually divided into a plurality of pages defined as programming units. In some embodiments, a page of data may be stored in a row of memory cells. Each page may include user data and overhead data, wherein the overhead data includes a CC calculated using the user data. In some embodiments, the memory blocks 302-1 to 302-N may include solid-state NAND memory blocks.

[0064] Each memory block 302 (e.g., memory block 302-1) includes a plurality of bit lines 304, word lines 306, and select lines 308. Each bit line (e.g., bit line 304-1) is connected to a number of memory cells connected in series. More specifically, in an embodiment where each memory cell is a floating gate transistor, the floating gate transistors are connected in series to form a NAND string 310 (e.g., shown within the dashed box). Although Figure 3 Four memory cells are shown in FIG. 304 , but the number of memory cells within a NAND string is not meant to be limiting. For example, 16, 32, 64, 128, or any other number of memory cells may be connected in a NAND string. Each respective bit line 304 is coupled to a respective NAND string within block 302.

[0065] Still reference Figure 3, a method of reading data stored in a particular memory cell (e.g., memory cell 316) includes applying a voltage to a select line 308 of block 302, which in turn is coupled to a corresponding NAND string within block 302, including NAND string 310 having memory cell 316. The voltage applied to select line 308 is greater than the threshold voltage of select transistors 312 and 314. Select transistor 312 is controlled by a select gate drain line (SGD) 308-1, and select transistor 314 is controlled by a select gate source line (SGS) 308-2. In addition, to read the data in memory cell 316, all other memory cells or unselected memory cells in NAND string 310 are turned on (e.g., conduct current regardless of whether they are programmed or erased). Unselected memory cells have a read pass voltage (e.g., a read parameter) applied to their corresponding word lines that turns on the unselected memory cells.

[0066] During an exemplary read operation, various read compare levels (e.g., voltages) are applied to word line 306-2 to determine the value stored in memory cell 316. In some embodiments, the conduction current of memory cell 316 is measured to determine the value stored in memory cell 316. The method of accessing each memory cell and the number of memory cells accessed during reading or writing vary. For example, all bit lines of memory block 302-1 may be programmed or read at the same time. In various embodiments, memory cells along a shared word line may be programmed at the same time (e.g., concurrently). In other embodiments, the bit lines may be divided into even bit lines and odd bit lines. In an odd / even bit line architecture, memory cells along a shared word line and connected to an odd bit line are programmed simultaneously, while memory cells along a shared word line and connected to an even bit line are programmed at different times.

[0067] Each time data is written to a memory block, the data is processed by the ECC engine 212, which includes encoding the data (e.g., using a particular error correction code) and storing the encoded data in the memory block. When data is read back from the memory block, the data is processed by the ECC engine 212, which includes decoding the data, correcting errors (e.g., tracked as BER), and returning the data to the user (via the controller 104). In some embodiments, the amount of time it takes the ECC engine 212 to return the data to the controller 104 is defined as the throughput time.

[0068] In some embodiments, the controller 104 performs a data merge operation on the memory array 260. The controller 104 selects a source block from the memory blocks 302-1 to 302-N of the memory array 260 for merging or compression. For example, the controller 104 may select the memory block 302-1 as the source block for merging or compression. In the exemplary embodiments described herein, the memory block 302-1 may be referred to as the source block 302-1. The source block 302-1 may include a plurality of memory fragments, such as 16 memory fragments or any suitable number of memory fragments. The memory fragments may include data written by the host 106 during the host write operation. The memory fragments may belong to respective logical groups and may be dispersed or chaotic in the source block 302-1, so that the memory fragments associated with the same logical group may not be sequentially stored or organized in the source block 302-1. Additionally or alternatively, while some memory segments include data written by the host 106 during a host write operation, other memory segments dispersed throughout the source block 302-1 may be blank (e.g., erased by the host 106 or controller 104 or not yet written by the host 106).

[0069] In some embodiments, the memory system 102 may include one or more charge pumps that generate voltages used by the controller 104 to perform operations such as erase operations, program operations, write operations, read operations, etc. on one or more memory cells of the memory blocks 302-1 to 302-N. The charge pump may increase or decrease a power supply voltage and provide voltage pulses to the memory cells (e.g., using the increased or decreased voltage). For example, the charge pump may double the voltage from the power supply voltage, triple the voltage from the power supply voltage, halve the voltage from the power supply voltage, or increase or decrease the voltage from the power supply voltage to any suitable factor of the power supply voltage to generate voltage pulses at the voltage required to perform the memory cell operation.

[0070] In some embodiments, the charge pump is connected to one or more capacitors. For example, the charge pump may be connected to one or more capacitors in parallel or in series. In some embodiments, the charge pump may be connected to some capacitors in parallel and to some capacitors in series. During the first pulse of the charge pump operation, the charge pump may charge one or more capacitors using the supply voltage (e.g., to bring the capacitor to the same voltage as the supply voltage). The charge pump may include or be connected to a suitable switching device.

[0071] The charge pump may use a switching device to reconfigure the connection between the charge pump and one or more capacitors, which may change the way in which the one or more capacitors are connected to the charge pump (e.g., from series to parallel, from parallel to series, or a combination thereof). During the second pulse of the charge pump, the charge pump may supply a voltage from a voltage source to one or more capacitors (e.g., the capacitors are charged to the voltage of the voltage source), which may double the voltage at the one or more capacitors. It should be understood that the charge pump may be connected to any number of capacitors in any suitable manner, and may use a supply voltage and a switching device to charge the capacitors to any suitable voltage. In addition or alternatively, the charge pump may use any number of pulses to charge the capacitors. The controller 104 may use the voltage stored in the capacitors by the charge pump to program the memory cells.

[0072] In some embodiments, the controller 104 may be configured to reduce the programming operation time while performing a verification operation during the execution of the programming operation. For example, as described, the controller 104 may program or write data to the memory cells of the memory system 102. The controller 104 may program the memory cells in a plurality of memory cells (such as memory cells 316) of a memory block (such as memory block 302). As described, the memory block 302 may include one or more memory strings 310. Each memory string 310 corresponds to a plurality of memory cells of the memory cell 316. As described, the memory cell 316 may include a single-level cell (e.g., each memory cell 316 has one bit), a multi-level cell (e.g., each memory cell 316 has two bits), a three-level cell (e.g., each memory cell 316 has three bits), a four-level cell (e.g., each memory cell 316 has four bits), or any other suitable type of memory cell.

[0073] During the execution of the programming operation, the controller 104 may program the memory cells 316 of the corresponding memory string 310, which may be referred to as a programming cycle. To improve the performance of the memory system 102, after each programming cycle, the controller 104 may perform a fast verification operation as described. For example, the controller 104 may perform a programming or write verification operation on the memory string 310 after the corresponding programming cycle is completed.

[0074] In some embodiments, during the execution of a programming operation, the controller 104 may identify a first memory string 310. The first memory string 310 may include a memory string of the memory strings 310 that is programmed first (e.g., before another memory string 310) during the execution of a programming operation. The controller 104 may be configured to skip the execution of a portion of a verification operation for the first memory string 310. As described, the portion of the verification operation may include applying a read verification voltage. During the execution of a verification operation, the controller 104 may skip applying a read verification voltage to the first memory string 310 while continuing to execute other portions or steps of the verification operation for the first memory string 310.

[0075] The controller 104 may disable verification for the portion of the first memory string 310. For example, the controller 104 may set a flag indicating that program (e.g., write) verification is disabled for the portion of the first memory string 310. Additionally or alternatively, the controller 104 may set one or more bits in the first memory string 310 to a value indicating that verification is disabled for the portion of the first memory string 310.

[0076] In some embodiments, the controller 104 may receive an instruction to skip the portion of the verification operation for the first memory string 310. For example, the controller 104 may receive an instruction from the host 106 or any suitable source instructing the controller 104 to skip the portion of the verification operation for the first memory string 310 after the programming cycle corresponding to the first memory string 310 is completed. It should be understood that although only limited examples are described herein, the controller 104 may disable the portion of the verification operation for the first memory string 310 in any suitable manner other than as described herein, receive an instruction from any suitable source other than as described herein to skip the execution of the portion of the verification operation for the first memory string 310, receive an instruction from any suitable source other than as described herein instructing the controller 104 to disable the portion of the verification operation for the first memory string 310, and / or determine to skip or disable the portion of the verification operation for the first memory string 310 in any suitable manner.

[0077] In some embodiments, during the execution of a programming operation, the controller 104 may identify other (e.g., subsequent) memory strings 310. The other memory strings 310 may include memory strings 310 that are programmed after the first memory string 310 during the execution of the programming operation. The controller 104 may be configured to perform a verification operation on the other memory strings 310, including the portion of the verification operation. The controller 104 may enable the portion of the verification for the other memory strings 310 (e.g., enable normal verification). For example, the controller 104 may set a flag indicating that programming (e.g., writing) verification is enabled for the other memory strings 310. In addition or alternatively, the controller 104 may set one or more bits in the corresponding memory strings of the other memory strings 310 to a value indicating that verification is enabled for the other memory strings 310.

[0078] In some embodiments, the controller 104 can set one or more bits for the second memory string 310. The second memory string 310 can include a memory string of the memory strings 310 that is programmed immediately after or subsequently to the first memory string 310 during execution of a programming operation. In response to determining that the one or more bits of the second memory string 310 indicate that verification is enabled for the other memory strings 310, the controller 104 can perform a verification operation on the other memory strings 310, including the portion of the verification operation.

[0079] In some embodiments, the controller 104 may receive an instruction to perform a verification operation on the other memory strings 310. For example, the controller 104 may receive an instruction from the host 106 or any suitable source instructing the controller 104 to perform a verification operation on the other memory strings 310 after the programming cycle of the corresponding memory strings of the other memory strings 310 is completed. It should be understood that although only limited examples are described herein, the controller 104 may enable verification operations on the other memory strings 310 in any suitable manner other than as described herein, receive instructions from any suitable source other than as described herein to perform verification operations on the other memory strings 310, receive instructions from any suitable source other than as described herein instructing the controller 104 to enable verification operations on the other memory strings 310, and / or determine to perform verification operations on the other memory strings 310 in any suitable manner.

[0080] The controller 104 may be configured to perform the portion of the program (e.g., write) verification on the other memory strings 310 (e.g., skipping the first memory string 310). For example, the controller 104 may apply a read verification voltage to a corresponding memory string in the other memory strings 310 after completing the corresponding programming loop. The controller 104 may use the read verification voltage to verify that the desired data (e.g., data programmed or written during the execution of the programming operation) is stored in the corresponding memory cell 316.

[0081] In some embodiments, during the execution of a programming operation, the controller 104 can be configured to skip the execution of a portion of a verification operation for all memory strings 310. As described, the portion of the verification operation can include applying a read verification voltage. During the execution of a verification operation, the controller 104 can skip applying a read verification voltage to a first memory string 310 and any subsequent memory strings 310 while continuing to execute other portions or steps of the verification operation for the first memory string 310 and all subsequent memory strings 310.

[0082] The controller 104 may disable the portion of verification for each of the memory strings 310. For example, the controller 104 may set a flag indicating that program (e.g., write) verification is disabled for the portion of the memory string 310. Additionally or alternatively, the controller 104 may set one or more bits of each of the memory strings 310 to a value indicating that verification is disabled for the portion of the memory string 310.

[0083] In some embodiments, the controller 104 may receive an instruction to skip the portion of the verification operation for the memory string 310. For example, the controller 104 may receive an instruction from the host 106 or any suitable source instructing the controller 104 to skip the portion of the verification operation for the corresponding memory string 310 after the programming cycle corresponding to the corresponding memory string 310 is completed. In some embodiments, the controller 104 may receive an instruction to skip the portion of the verification operation for all memory strings 310. It should be understood that although only limited examples are described herein, the controller 104 may disable the portion of the verification operation for the memory string 310 in any suitable manner other than as described herein, receive instructions from any suitable source other than as described herein to skip the execution of the portion of the verification operation for the memory string 310, receive instructions from any suitable source other than as described herein instructing the controller 104 to disable the portion of the verification operation for the memory string 310, and / or determine to skip or disable the portion of the verification operation for the memory string 310 in any suitable manner. Additionally or alternatively, controller 104 may be configured to skip the portion of the verify operation for any suitable subset of memory strings 31 other than those described herein.

[0084] In some embodiments, the controller 104 may perform the methods described herein. However, the methods described herein being performed by the controller 104 is not meant to be limiting, and any type of software executed on the controller may perform the methods described herein without departing from the scope of the present disclosure. For example, a controller such as a processor executing software within the host 106 or firmware within the storage system 102 (e.g., stored on the ROM 232 or NVM memory block 110) may perform the methods described herein.

[0085] Figure 5is a flow chart illustrating a memory programming verification method 500 according to the principles of the present disclosure. At 502, the method 500 performs a write operation. For example, the controller 104 performs a programming (e.g., writing) operation on the memory cells 316 of the memory block 302 or any suitable memory block or memory device of the memory system 102.

[0086] At 504, the method 500 identifies a memory string. For example, the controller 104 may identify a memory string 310 associated with a corresponding memory cell 316. The controller 104 may identify the memory string 310 to be programmed during execution of a programming operation. Additionally or alternatively, the controller 104 may receive instructions from the host 106 or other suitable source to identify the memory string 310 (e.g., and corresponding memory cell 316) to be programmed during execution of a programming operation.

[0087] At 506, the method 500 identifies a first memory string of the memory strings. For example, the controller 104 identifies a first memory string 310 of the memory strings 310. The first memory string 310 may include a memory string 310 that is programmed first during execution of a programming operation.

[0088] At 508, the method 500 disables at least a portion of write verification for the first memory string. For example, as described, the controller 104 can disable at least a portion of verification for the first memory string 310. For example, the controller 104 prohibits applying a read verification voltage to the first memory string. At 510, the method 500 enables the portion of write verification for other memory strings. For example, as described, the controller 104 enables verification for other memory strings 310.

[0089] At 512, the method 500 performs write verification. For example, the controller 104 performs a verification operation on the memory string 310. The controller 104 performs the portion of write verification on the memory string 310 for which write verification is enabled. Conversely, the controller 104 does not perform the portion of write verification on the memory string 310 for which write verification is disabled (e.g., the first memory string 310). For example, the controller 104 does not apply a read verification voltage to the first memory string 310, but applies a read verification voltage to other memory strings 310 (e.g., the memory string 310 for which write verification is enabled). The controller 104 uses the read verification voltage to verify that the desired data is programmed (e.g., written or stored) to the corresponding memory cell 316.

[0090] Figure 66 is a flow chart illustrating an alternative memory programming verification method 600 according to the principles of the present disclosure. At 602, the method 600 performs a write operation. For example, the controller 104 performs a programming (e.g., writing) operation on the memory cell 316 of the memory block 302 or any suitable memory block or memory device of the memory system 102.

[0091] At 604, the method 600 identifies a memory string. For example, the controller 104 may identify a memory string 310 associated with a corresponding memory cell 316. The controller 104 may identify the memory string 310 to be programmed during execution of a programming operation. Additionally or alternatively, the controller 104 may receive instructions from the host 106 or other suitable source to identify the memory string 310 (e.g., and corresponding memory cell 316) to be programmed during execution of a programming operation.

[0092] At 606, the method 600 identifies a first memory string of the memory strings. For example, the controller 104 identifies a first memory string 310 of the memory strings 310. The first memory string 310 may include a memory string 310 that is programmed first during execution of a programming operation.

[0093] At 608, the method 600 skips performing at least a portion of write verification on the first memory string after the write operation is completed. For example, the controller 104 determines that a programming cycle corresponding to the programming operation of the first memory string 310 is completed. In response to determining that the programming cycle (e.g., programming of the first memory string 310) is completed, the controller 104 skips performing the portion of the verification operation on the first memory string 310 (e.g., the controller 104 skips applying a read verification voltage to the first memory string 310). The controller 104 may perform other steps or portions of the verification operation on the first memory string 310.

[0094] At 612, the method 600 performs write verification on subsequent memory strings. For example, the controller 104 determines that the programming cycle for the corresponding memory string 310 of the other memory strings 310 is complete. The controller 104 performs a verification operation on the corresponding memory string 310. The controller 104 applies a read verification voltage to the corresponding memory string 310 and verifies all other verification steps or portions of the operation. The controller 104 uses the read verification voltage to verify that the desired data is programmed (e.g., written or stored) to the corresponding memory cell 316 of the corresponding memory string 310. The controller 104 continues to perform verification operations on other memory strings 310 (e.g., memory strings 310 that were programmed after the first memory string 310 during the execution of the programming operation) after completing the corresponding programming cycle.

[0095] Figure 77 is a flow chart illustrating an alternative memory programming verification method 700 according to the principles of the present disclosure. At 702, the method 700 performs a write operation. For example, the controller 104 performs a programming (e.g., writing) operation on the memory cell 316 of the memory block 302 or any suitable memory block or memory device of the memory system 102.

[0096] At 704, the method 700 identifies a memory string. For example, the controller 104 may identify a memory string 310 associated with a corresponding memory cell 316. The controller 104 may identify the memory string 310 to be programmed during execution of a programming operation. Additionally or alternatively, the controller 104 may receive instructions from the host 106 or other suitable source to identify the memory string 310 (e.g., and corresponding memory cell 316) to be programmed during execution of a programming operation.

[0097] At 706, the method 700 disables a portion of write verification for the memory string. For example, the controller 104 may receive an instruction not to perform the portion of the verification operation on the memory string 310. The controller 104 may disable at least a portion of verification for the memory string 310. For example, the controller 104 prohibits applying a read verification voltage to the memory string 310.

[0098] At 712 , the method 700 performs a write verify. For example, the controller 104 performs a verify operation on the memory string 310 , thereby skipping that portion of the verify operation. For example, the controller 104 may not apply a read voltage verify voltage to the memory string 310 .

[0099] Figure 8 8 is a flow chart illustrating an alternative memory programming verification method 800 according to the principles of the present disclosure. At 802, the method 800 performs a write operation. For example, the controller 104 performs a programming (e.g., writing) operation on the memory cell 316 of the memory block 302 or any suitable memory block or memory device of the memory system 102.

[0100] At 804, the method 800 identifies a memory string. For example, the controller 104 may identify a memory string 310 associated with a corresponding memory cell 316. The controller 104 may identify the memory string 310 to be programmed during execution of a programming operation. Additionally or alternatively, the controller 104 may receive instructions from the host 106 or other suitable source to identify the memory string 310 (e.g., and corresponding memory cell 316) to be programmed during execution of a programming operation.

[0101] At 806, the method 800 skips the execution of at least a portion of the write verification of the memory string after the write operation is completed. For example, the controller 104 determines that the programming loop corresponding to the programming operation of the first memory string 310 is completed. In response to determining that the programming loop (e.g., programming of the first memory string 310) is completed, the controller 104 skips the execution of the portion of the verification operation of the first memory string 310 (e.g., the controller 104 skips applying the read verification voltage to the first memory string 310). For other memory strings 310, the controller 104 continues to determine that the corresponding programming loop corresponding to the programming operation of the corresponding memory string 310 has been completed. The controller 104 skips the portion of the verification operation of the other memory strings 310.

[0102] At 808 , the method 800 performs the remaining write verify operations on the memory string. For example, the controller 104 may perform other steps or portions of the verify operations on the memory string 310 .

[0103] In some embodiments, a method for memory programming verification includes performing a write operation on a memory cell of a memory device. The method also includes identifying a memory string associated with a corresponding memory cell of the memory cell. The method also includes identifying a first memory string of the memory string. The method also includes disabling write verification for the first memory string. The method also includes enabling write verification for other memory strings of the memory string. The method also includes performing a write verification operation on the memory string for which write verification has been enabled.

[0104] In some embodiments, the first memory string includes a memory string that is first programmed during the execution of a write operation. In some embodiments, performing a write verification operation includes applying a verification voltage (e.g., causing a verification voltage spike) to a memory string that has enabled write verification. In some embodiments, performing a write verification operation includes equalizing the channel potentials of the memory device. In some embodiments, the memory device includes a single-level cell memory device. In some embodiments, the memory device includes a multi-level cell memory device. In some embodiments, the memory device includes a three-level cell memory device. In some embodiments, the memory device includes a four-level cell memory device.

[0105] In some embodiments, the controller includes a bus interface and a processor. The bus interface communicates with at least one memory block of the memory device. The processor is configured to: perform a write operation on a memory cell of the at least one memory block; identify a memory string associated with a corresponding memory cell of the memory cell; identify a first memory string of the memory strings; disable write verification for the first memory string; enable write verification for other memory strings of the memory strings; and perform a write verification operation on the memory string for which write verification has been enabled.

[0106] In some embodiments, the first memory string comprises a memory string that is first programmed during the execution of a write operation. In some embodiments, the instructions further cause the processor to perform a write verify operation by applying a verify voltage (e.g., causing a verify voltage spike) to the memory string for which write verify is enabled. In some embodiments, the memory cell comprises one bit. In some embodiments, the memory cell comprises two bits. In some embodiments, the memory cell comprises three bits. In some embodiments, the memory cell comprises four bits.

[0107] In some embodiments, a method for memory programming verification includes performing a write operation on a memory cell of a memory device. The method also includes identifying a memory string associated with a corresponding memory cell of the memory cell. The method also includes identifying a first memory string of the memory string, the first memory string including a memory string in the memory string to be first programmed during the execution of the write operation. The method also includes skipping the execution of the write verification operation on the first memory string in response to the completion of the execution of the write operation on the first memory string. The method also includes performing a write verification operation on a corresponding subsequently programmed memory string of the memory string in response to the completion of the execution of the write operation on the subsequently programmed memory string.

[0108] In some embodiments, the memory device comprises a single level cell memory device. In some embodiments, the memory device comprises a multi-level cell memory device. In some embodiments, the memory device comprises a three-level cell memory device. In some embodiments, the memory device comprises a four-level cell memory device.

[0109] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. It is intended that the following claims be interpreted as covering all such variations and modifications. In the above specification and claims, the terms "including" and "comprising" are used in an open-ended manner and are therefore understood to mean "including but not limited to...". In addition, the terms "couple" or "couples" are intended to mean an indirect connection or a direct connection. Therefore, if a first device is coupled to a second device, the connection may be made by a direct connection or by an indirect connection via other devices and connections.

[0110] The word "example" is used herein to indicate use as an example, instance or illustration. Any aspect or design described herein as an "example" is not necessarily to be understood as being more preferred or more advantageous than other aspects or designs. On the contrary, the use of the word "example" is intended to present concepts in a specific way. As used in this application, the term "or" is intended to represent an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified, or clearly indicated from the context, "X includes A or B" is intended to represent any natural arrangement. That is, if X includes A; then X includes B; or X includes A and B, then "X includes A or B" is satisfied under any of the aforementioned examples. In addition, the articles "one" ("a" and "an") used in this application and the appended claims are generally understood to mean "one or more", unless otherwise specified or clearly indicated from the context as a singular form. In addition, unless so described, the use of the term "specific implementation" or "a specific implementation" throughout the text is not intended to represent the same embodiment or specific implementation.

[0111] The specific implementation of the systems, algorithms, methods, instructions, etc. described herein can be implemented in hardware, software, or any combination thereof. The hardware may include, for example, a computer, an intellectual property (IP) core, an application specific integrated circuit (ASIC), a programmable logic array, an optical processor, a programmable logic controller, microcode, a microcontroller, a server, a microprocessor, a digital signal processor, or any other suitable circuit. In the claims, the term "processor" should be understood to cover any of the foregoing hardware, either individually or in combination. The terms "signal" and "data" are used interchangeably.

[0112] As used herein, the term "module" may include a packaged functional hardware unit designed to be used with other components, an instruction set that can be executed by a controller (e.g., a processor that executes software or firmware), a processing circuit configured to perform a specific function, and an independent set of hardware or software components that interface with a large system. For example, a module may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a circuit, a digital logic circuit, an analog circuit, a discrete circuit, a gate, and other types of hardware or a combination thereof. In other embodiments, a module may include a memory that stores instructions that can be executed by a controller to implement module features. In some embodiments, the controller 104 is implemented in a host 106, which may be configured with hardware and / or firmware to perform the various functions described herein.

[0113] “Controller” shall mean a single circuit component, an application specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a processor with control software, a field programmable gate array (FPGA), or a combination thereof.

[0114] Furthermore, in one aspect, for example, the systems described herein may be implemented using a general purpose computer or general purpose processor with a computer program that, when executed, performs any of the corresponding methods, algorithms and / or instructions described herein. Additionally or alternatively, for example, a dedicated computer / processor may be utilized that may include other hardware for executing any of the methods, algorithms or instructions described herein.

[0115] In addition, all or part of the specific implementation of the present disclosure may take the form of a computer program product accessible from, for example, a computer usable or computer readable medium. A computer usable or computer readable medium may be, for example, any device that can tangibly contain, store, communicate, or transmit a program for use by or in connection with any processor. The medium may be, for example, an electronic, magnetic, optical, electromagnetic, or semiconductor device. Other suitable media are also provided.

[0116] The above embodiments, specific implementations and aspects have been described to facilitate understanding of the present invention and are not intended to limit the present invention. On the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which scope is given the broadest interpretation to cover all such modifications and equivalent structures permitted by law.

Claims

1. A method for memory programming verification, the method comprising: performing a write operation on a memory cell of a memory device; identifying a memory string associated with a corresponding one of the memory cells; identifying a first memory string of the memory strings; disabling a portion of write verification for the first memory string, the portion of the write verification causing a verify voltage spike; enabling the portion of the write verify on other ones of the memory strings, wherein the other memory strings include memory strings that are programmed after the first memory string during execution of a programming operation; as well as At least the portion of the write verify operation is performed on the portion of memory strings for which the write verify is enabled. 2 . The method of claim 1 , wherein the first memory string comprises a memory string that is first programmed during performance of the write operation.

3. The method of claim 1 , wherein performing at least the portion of the write verify operation comprises: applying a verification voltage to the portion of the memory string in which the write verification has been enabled; as well as Applying the verification voltage to the first memory string is skipped. 4 . The method of claim 1 , wherein performing the portion of the write verify operation comprises equalizing channel potentials of the memory devices.

5. The method of claim 1, wherein the memory device comprises a single level cell memory device.

6. The method of claim 1, wherein the memory device comprises a multi-level cell memory device.

7. The method of claim 1, wherein the memory device comprises a three-level cell memory device.

8. The method of claim 1, wherein the memory device comprises a four level cell memory device.

9. A controller comprising: a bus interface in communication with at least one memory block of a memory device; and A processor, the processor being configured to: performing a write operation on memory cells of the at least one memory block; identifying a memory string associated with a corresponding one of the memory cells; identifying a first memory string of the memory strings; disabling a portion of write verification for the first memory string, the portion of the write verification causing a verify voltage spike; enabling the portion of the write verify on other ones of the memory strings, wherein the other memory strings include memory strings that are programmed after the first memory string during execution of a programming operation; as well as At least the portion of the write verify operation is performed on the portion of memory strings for which the write verify is enabled. 10 . The controller of claim 9 , wherein the first memory string comprises a memory string that is first programmed during performance of the write operation.

11. The controller of claim 9, wherein the processor is further configured to perform at least the portion of the write verification operation by: applying a verification voltage to the portion of the memory string in which the write verification has been enabled; and Applying the verification voltage to the first memory string is skipped.

12. The controller of claim 9, wherein the memory cell comprises one bit.

13. The controller of claim 9, wherein the memory cell comprises two bits.

14. The controller of claim 9, wherein the memory cell comprises three bits.

15. The controller of claim 9, wherein the memory cell comprises four bits.

16. A method for memory programming verification, the method comprising: performing a write operation on a memory cell of a memory device; identifying a memory string associated with a corresponding one of the memory cells; identifying a first memory string of the memory strings, the first memory string comprising a memory string among the memory strings to be programmed first during performance of the write operation; responsive to completion of execution of the write operation to the first memory string, skipping execution of a portion of a write verify operation to the first memory string, the portion of the write verify causing a verify voltage spike; as well as Responsive to completion of performance of the write operation on subsequently programmed memory strings, at least the portion of the write verify operation is performed on corresponding subsequently programmed ones of the memory strings.

17. The method of claim 16, wherein the memory device comprises a single level cell memory device.

18. The method of claim 16, wherein the memory device comprises a multi-level cell memory device.

19. The method of claim 16, wherein the memory device comprises a three-level cell memory device.

20. The method of claim 16, wherein the memory device comprises a four level cell memory device.

Images