Capacitive device

Abstract

The invention relates to a capacitive device (10) comprising: a metallic layer (20); a network of nanotubes or nanowires bundles (40) extending from the face of the metallic layer; a capacitive stack (50) covering the metallic layer (20) and the nanotube bundles (40) in a coherent manner, said stack comprising an upper conductive layer (51) and a separation layer (52), the device comprising a capacitive zone (ZC) which is the zone of the upper conductive layer (51) enclosing the nanotube bundles (40) and the separation layer (52), and a lower contact zone (ZCI) which is the zone of the capacitive stack (50) allowing the free ends to be exposed, and is the zone of the separation layer (52) enclosing the upper conductive layer (51).

Description

Technical Field

[0001] This invention relates to the field of nanostructures and methods for their fabrication. In particular, this invention relates to the application of nanotubes, especially carbon nanotubes, in capacitive devices.

[0002] In this regard, the present invention relates to a high-density capacitive device comprising capacitive stacks covering a nanotube network in a conforming manner. The configuration and / or layout of the device disclosed in this invention make the device more compact compared to known devices in the prior art. The proposed configuration also simplifies the method of manufacturing the capacitive device and enables the maintenance of the nanotube integrity. Background Technology

[0003] Currently, high-density capacitors are being developed extensively. In particular, these developments include stacks known as capacitive stacks, which consist of two or three layers and are formed on surfaces or structures with high form factors to limit the size of the capacitor.

[0004] In this regard, nanowires or nanotubes, and more particularly carbon nanotubes with a high surface area to volume ratio, are ideal candidates for fabricating these structures with high form factors. More specifically, in reference [1] mentioned at the end of the specification, the authors proposed forming carbon nanotube bundles that are perpendicular to the support surface and extend in a matrix configuration.

[0005] A set of process steps can then be performed to obtain a capacitive device. These steps may include, for example, performing the formation of capacitive stacks on a network of nanotube bundles using atomic layer deposition (ALD) technology; performing electrode formation and / or etching steps. However, the configuration or arrangement of the capacitive device currently under consideration cannot maintain the integrity of the nanotube bundle during the execution of the fabrication method.

[0006] In addition, the method for manufacturing nanotube bundles described in reference [1] specifically requires the following steps:

[0007] a0) Provides a silicon substrate, the main surface of which is covered by a silicon dioxide layer, which is formed, for example, by plasma-enhanced vapor deposition;

[0008] b0) Form the lower electrode, which is formed, for example, using titanium and / or copper evaporation techniques;

[0009] c0) Forms through holes in the lower electrode, the through holes being arranged in a matrix;

[0010] d0) Carbon nanotube bundles are formed according to the conditions described in reference [2] cited at the end of the specification, with each bundle starting from a through-hole.

[0011] However, the method for manufacturing this carbon nanotube bundle is unsatisfactory.

[0012] In fact, forming a through-hole requires the use of a hard mask.

[0013] Furthermore, to a certain extent, it is necessary to form closely spaced small openings, which cannot be formed using standard photolithography techniques. Therefore, etching or electron beam lithography must be used. However, the speed and cost of this technology are incompatible with the requirements of the microelectronics industry.

[0014] Therefore, one object of the present invention is to disclose a capacitive device having an arrangement that enables a manufacturing method for protecting the integrity of nanotube bundles.

[0015] Another object of the present invention is to disclose a capacitive device, the method of which is easier to perform than methods known in the prior art. Summary of the Invention

[0016] The object of the present invention is achieved at least in part by a capacitive device comprising:

[0017] - A metal layer having two main surfaces, referred to as the front and back sides respectively;

[0018] - A network of nanotubes or nanowire bundles that extends from the front side and from the base toward the free end in a manner substantially perpendicular to the front side;

[0019] - A continuous capacitive stack, which uniformly covers a metal layer and nanotubes or nanowire bundles from its base to its free end, the stack comprising an upper conductive layer and an insulating layer that isolates the upper conductive layer from each nanotube bundle and the metal layer.

[0020] The device includes a capacitive region and a lower contact region.

[0021] In the capacitive region, the upper conductive layer encloses the nanotubes or nanowire bundles and the isolation layer, while in the lower contact region, the capacitive stack first allows the free ends to be exposed, and then the isolation layer encloses the upper conductive layer.

[0022] According to one embodiment, the device includes an upper electrode covering a capacitive region for electrical contact with an upper conductive layer.

[0023] According to one embodiment, the device includes a lower electrode covering the lower contact region to electrically contact the free end of a nanotube or nanowire bundle in the lower contact region.

[0024] According to one embodiment, the capacitive stack further includes a lower conductive layer inserted between the isolation layer and the nanotube or nanowire bundle, the lower conductive layer enclosing the isolation layer in the lower contact region.

[0025] According to one embodiment, the lower electrode is also in electrical contact with the lower conductive layer.

[0026] According to one embodiment, the lower conductive layer comprises titanium nitride.

[0027] According to one embodiment, the upper conductive layer comprises titanium nitride.

[0028] According to one embodiment, the insulating layer comprises aluminum oxide.

[0029] According to one embodiment, the device further includes a neutral region inserted between the capacitive region and the lower contact region, wherein a lower isolation layer is inserted between the metal layer and the nanotube or nanowire bundle in the neutral region.

[0030] According to one embodiment, the neutral region is covered by at least one enclosure layer made of insulating material.

[0031] According to one embodiment, the encapsulation layer of at least one layer includes a silicon oxide layer and a silicon nitride layer.

[0032] According to one embodiment, the length of the nanotube or nanowire bundle is between 2 μm and 40 μm, and preferably, the length of the nanotube or nanowire bundle is between 2 μm and 12 μm.

[0033] According to one embodiment, the metal layer is supported on a support substrate by one of its faces opposite to the front side of the metal layer, and advantageously, a dielectric layer is inserted between the support substrate and the metal layer.

[0034] The present invention also relates to a method for manufacturing a capacitive device according to the invention, the method comprising the following steps:

[0035] a) An anodizing step of a metal layer having a first thickness E1, starting from the front side of the metal layer and passing through a second thickness less than the first thickness, to form an oxide layer;

[0036] b) Selective etching of the oxide layer formed in step a);

[0037] d) Growth steps of nanotube or nanowire networks

[0038] Step a) is performed such that the exposed surface of the metal layer after step b) has a texture formed by a network of cavities having an average depth P and an average lateral dimension D, the average depth P and the average lateral dimension D being adjusted such that each nanotube bundle originates in a cavity, extends from the cavity, and extends from the base toward the free end in a manner substantially perpendicular to the metal layer.

[0039] e) The step of defining the capacitive region includes forming a stack of a first dielectric layer and a second dielectric layer covering a network of nanotube bundles, and forming a first via in the stack, the first via defining a contact region.

[0040] f) A step of forming a continuous capacitive stack, wherein the continuous capacitive stack is uniformly covered from its base to its free end with a metal layer and nanotubes or nanowire bundles, the stack comprising an upper conductive layer and an isolation layer that isolates the upper conductive layer from each nanotube bundle and the metal layer.

[0041] The upper conductive layer encloses the nanotubes or nanowire bundles and the isolation layer within the capacitive region; while in the lower contact region, which is different from the capacitive region, the capacitive stack allows the free ends to be exposed, and the isolation layer encloses the upper conductive layer. Attached Figure Description

[0042] Other features and advantages will become clear in the following description of a capacitive device according to the invention, given as a non-limiting example, with reference to the accompanying drawings:

[0043] Figure 1 This is a schematic diagram of a capacitive device in a cross-sectional plane perpendicular to the front side of the metal layer according to the present invention;

[0044] Figure 2 A schematic diagram showing details of the capacitive stack at the nanotube bundle is provided.

[0045] Figure 3 This is a schematic diagram of a metal layer supported on a supporting substrate;

[0046] Figure 4 The anodizing steps of the metal layer according to the present invention are shown;

[0047] Figure 5 The etching steps for the oxide layer formed during the anodizing step according to the present invention are shown;

[0048] Figure 6 The image is obtained using a scanning electron microscope, which allows observation of the texture of the exposed surface of the conductive material layer after the etching step b) of the oxide layer according to the present invention;

[0049] Figure 7The steps for defining a capacitive region, a neutral region, and a lower contact region according to the present invention are illustrated;

[0050] Figure 8 The steps for forming a network of nanotube bundles according to the present invention are shown;

[0051] Figure 9 These are images obtained using a scanning electron microscope, which are used to observe carbon nanotube bundles, each of which originates in a disk and extends substantially perpendicular to the conductive material layer.

[0052] Figure 10 The encapsulation step d) of the nanotube bundle network according to the present invention is shown;

[0053] Figure 11 The coating of the protected portion of the nanotube bundle by the first dielectric layer formed during step d) is shown;

[0054] Figure 12 The following step (e) illustrates the exposure of the contact area to the external environment according to the present invention;

[0055] Figure 13 The following step f) illustrates the formation step of the capacitive stack according to the present invention;

[0056] Figure 14 The arrangement of capacitive stacks at the free ends of nanotube bundles in the capacitive and neutral regions is shown.

[0057] Figure 15 The tilted cross-section of the nanotube bundle after the formation of the capacitive stack is shown, with positions A, B, C, and D showing different heights;

[0058] Figure 16A , Figure 16B , Figure 16C and Figure 16D It is obtained by scanning electron microscopy. Figure 15 Images obtained at locations A, B, C, and D as shown;

[0059] Figure 17 Step g) of forming the upper electrode according to the present invention is shown;

[0060] Figure 18 The following step (h) illustrates the exposure of the lower contact area to the external environment according to the present invention;

[0061] Figure 19 The steps for forming the lower electrode according to the present invention are shown;

[0062] Figure 20 The diagram illustrates contact at the upper and lower electrodes according to the invention.

[0063] Figure 21 This is a graphical representation of the average lateral dimension (vertical axis, in nm) of the disc or cavity as a function of the applied potential U (horizontal axis, in V) during the anodizing step of the aluminum layer, in the presence of phosphoric acid ("point A"), sulfuric acid ("point B"), oxalic acid ("point C"), or selenic acid ("point D"). Detailed Implementation

[0064] The present invention relates to a capacitive device having a capacitive stack of nanotube bundles, particularly carbon nanotube bundles, deposited in a consistent manner onto a network of nanotube bundles. In this respect, the nanotube bundles extend from the front side of a metal layer and extend from the base toward the free end in a manner substantially perpendicular to said front side.

[0065] The continuous capacitive stack includes an upper conductive layer and an isolation layer that isolates the upper conductive layer from each nanotube bundle and metal layer.

[0066] The arrangement of capacitive stacks can define a capacitive region and a lower contact region within the capacitive device. Specifically, the capacitive region is the area where the upper conductive layer encloses the nanotube bundle and the isolation layer, while the lower contact region is firstly the area where the free ends of the capacitive stack are exposed, and secondly the area where the isolation layer encloses the upper conductive layer.

[0067] Figure 1 An example of a capacitive device 10 according to the present invention is shown.

[0068] The capacitive device 10 has a metal layer 20, which includes a front side 21 and an opposing back side 22 that is substantially parallel to the front side 21.

[0069] The metal layer 20 may include aluminum or copper.

[0070] The thickness of the metal layer 20 can be between 0.5 μm and 3 μm.

[0071] According to one particular embodiment, the back side of the metal layer 20 can be supported on the support substrate 30. Advantageously, the dielectric layer 31 can be inserted between the support substrate 30 and the metal layer 20.

[0072] The capacitive device according to the invention also includes a network of nanotube bundles 40 extending from the front side 21 and extending from the base 41 toward the free end 42 in a manner substantially perpendicular to the front side.

[0073] The term "network" refers to a dense arrangement of nanotube bundles, specifically the spacing between them being an average distance D between 50 nm and 500 nm, advantageously between 50 nm and 300 nm, and particularly equal to 150 nm.

[0074] The term "nanotube bundle" refers to a group of nanotubes that are substantially parallel to each other and capable of interweaving.

[0075] This description only mentions nanotube bundles; however, the present invention can also be implemented using nanowires, and more particularly using nickel nanowires and silicon nanowires.

[0076] Nanotube bundles may include carbon nanotube bundles. However, the invention is not limited to this aspect, and those skilled in the art may consider any other kind capable of forming nanotube bundles.

[0077] The length of the nanotube bundles can be between 2 μm and 40 μm, and preferably between 2 μm and 12 μm.

[0078] Each nanotube bundle can originate in a cavity and form on the front side of the metal layer. In this respect, the metal layer 20 can be textured on its front side 21 by the presence of a network of cavities having an average depth P and an average lateral dimension D, from which each nanotube bundle extends. Advantageously, the average lateral dimension D is between 50 nm and 500 nm, advantageously between 50 nm and 300 nm, and particularly equal to 150 nm. Likewise, advantageously, the average depth P is between 10 nm and 20 nm.

[0079] Therefore, considering textured structures in the form of cavities allows for the envisioning of a relatively dense network of nanotube bundles, and more specifically, obtaining a ratio of the cross-sectional area of ​​the nanotube bundles to the occupied surface area on the order of approximately 0.3. In particular, this density enables the achievement of optimized capacitor configurations.

[0080] The capacitive device 10 according to the invention further includes a capacitive stack 50. The capacitive stack 50 is continuous and covers the metal layer 20 and the nanotube bundle 40 in a consistent manner from its base 41 to its free end 42.

[0081] In other words, the capacitive stack 50 at least partially fills the space between the nanotube bundles. More specifically, the capacitive stack 50 covers the metal layer 20 (between the nanotube bundles) and the sides of the nanotube bundles.

[0082] The capacitive stack 50 includes an upper conductive layer 51 and an isolation layer 52, which insulates the upper conductive layer from each nanotube bundle 40 and the metal layer 20.

[0083] The isolation layer 52 may include aluminum oxide (Al2O3).

[0084] The upper conductive layer 51 may include titanium nitride (TiN).

[0085] Device 10 includes a capacitive region ZC and a lower contact region ZCI.

[0086] The capacitive region ZC is the area where the upper conductive layer 51 encloses the nanotube bundle 40 and the insulating layer 52. In other words, in this capacitive region ZC, the free end 42 of the nanotube bundle 40 is covered by the upper conductive layer 51 (it should be understood that in this region, the insulating layer 52 is inserted between the nanotube bundle and the upper conductive layer 51). Figure 2 The arrangement of layers of capacitive stack 50 at the free end of nanotube bundle 40 is shown.

[0087] The capacitive device 10 may include an upper electrode 60 covering the capacitive region ZC. Therefore, the arrangement of the capacitive region ZC allows the upper electrode 60 to make direct electrical contact with the upper conductive layer 51. The upper electrode 60 may be covered by one or more layers of insulating material 66c, 66d. Contacts in the form of metal studs 61 (“Upper Bump Metallurgy” - UBM) can be formed through the layers 66c, 66d.

[0088] The lower contact area ZCI is firstly the area where the capacitive stack 50 allows the free end 42 to be exposed, and secondly the area where the insulating layer 52 encloses the conductive layer 51.

[0089] The capacitive device 10 may include a lower electrode 70 covering the lower contact region ZCI to electrically contact the free end 42 of the nanotube bundle 40 in the lower contact region ZCI. The encapsulation of the upper conductive layer 51 by the insulating layer 52 enables the upper conductive layer 51 to be electrically isolated from the lower electrode 70.

[0090] The lower electrode 70 can be covered by an insulating material layer 66d. A contact in the form of a metal stud 71 (“Upper Bump Metallurgy” – “UBM”) can be formed through the layer 66d.

[0091] According to an advantageous embodiment, the capacitive stack may include, for example, a lower conductive layer 53 made of titanium nitride, which is inserted between the insulating layer and the nanotube bundle, the lower conductive layer enclosing the insulating layer in the lower contact region. Therefore, according to this variant, the lower electrode is also capable of electrical contact with the lower conductive layer.

[0092] The capacitive device 10 may further include a neutral region ZN inserted between the capacitive region ZC and the lower contact region ZCI. In particular, the neutral region is characterized by the presence of a lower insulating layer 65, which is inserted between the metal layer 20 and the nanotube bundle 40.

[0093] Once considered, the neutral region ZN can be covered by at least one encapsulation layer 66a, 66b made of insulating material. In particular, the at least one encapsulation layer can include a silicon oxide layer 66a and a silicon nitride layer 66b covering the silicon oxide layer 66a.

[0094] Therefore, the arrangement of the described capacitive devices 10 enables the protection of the integrity of the nanotube bundle during the method of manufacturing the devices. The methods that form part of this invention are also described in the remainder of this specification.

[0095] therefore, Figures 3 to 20 An example of a method for manufacturing a capacitive device according to the present invention is shown.

[0096] Specifically, the method includes providing a metal layer 20 having a substantially parallel front side 21 and a back side 22. Figure 3 ).

[0097] The metal layer 20 may include a metal, and in particular, the metal is at least one element selected from aluminum and copper.

[0098] The metal layer 20 may have an initial thickness referred to as a first thickness E1, which is equal to or greater than 1.5 μm, and in particular, between 1.5 μm and 4 μm, for example equal to 4 μm.

[0099] The metal layer 20 can be supported on the support substrate 30, particularly on the silicon substrate, via its back surface 22.

[0100] The metal layer 20 can be formed using deposition or evaporation techniques.

[0101] A dielectric layer 31, such as a silicon oxide layer 31, can also be formed before the metal layer 20 is deposited. In other words, if considered, the dielectric layer 31 is inserted between the metal layer 20 and the supporting substrate 30.

[0102] exist Figure 4 The diagram illustrates an anodizing step a) of the method according to the invention, which forms an oxide layer 20a starting from the front side 21 of the metal layer 20 by an oxidation reaction of the metal layer 20.

[0103] The anodizing step a) can be carried out in an acid bath, particularly in an acid bath containing at least one acid selected from selenic acid, sulfuric acid, oxalic acid, and phosphoric acid. In this regard, the temperature of the acid bath can be maintained between 2°C and 3.5°C, for example, equal to 3°C.

[0104] During the anodizing step a), the metal layer 20 is consumed by oxidation starting from the front side 21, with a second thickness E2 less than the first thickness E1, thereby forming an oxide layer 20a. Advantageously, the second thickness E2 is between 0.5 μm and 3 μm, for example, 1 μm.

[0105] Since the anodizing of metals, especially aluminum, is known to those skilled in the art and is described in more detail in reference [3] cited at the end of this specification, this step will not be described in detail in the remainder of this specification.

[0106] The anodizing step a) is followed by a liquid etching step b), which can selectively etch the oxide layer 20a formed in step a).

[0107] "Selective etching" refers to the etching of the oxide layer 20a facing the metal layer 20 preferentially. In this regard, if the metal layer 20 is made of aluminum, the formed oxide layer containing aluminum oxide can be selectively etched using phosphoric acid or even a phosphate buffer.

[0108] Observation using a scanning electron microscope ( Figure 6 This allows the inventors to observe the texture of the exposed surface of the metal layer 20 at the end of step b). The texturing of this exposed surface specifically results in the presence of the disc-shaped features 29 or the cavity 29.

[0109] A "disc" or "cavity" refers to a depression present on an exposed surface, having an average depth P and an average lateral dimension D.

[0110] Specifically, the average lateral dimension D is the size of the opening of the disc.

[0111] In particular, the adjustment of these two parameters P and D depends on the conditions applied during the anodizing step a) and the properties of the metal layer 20.

[0112] Those skilled in the art know how to adjust anodizing conditions to obtain well-defined P and D values, and therefore will not describe them in detail in this patent application.

[0113] in this regard, Figure 21 This is a graphical representation of the average lateral dimension D as a function of the applied anodic oxidation potential for different types of electrolytes. The figure clearly shows that, depending on the applied anodic oxidation conditions, D can be any value between 30 nm and 550 nm.

[0114] The method according to the invention may further include the step of defining the capacitive region ZC, the lower contact region ZCI, and possibly the neutral region ZN (c). Figure 7 ).

[0115] Specifically, step c) may include the following sub-steps:

[0116] c1) is a sub-step that ensures consistent deposition of the lower isolation layer;

[0117] c2) aims to keep the lower isolation layer only in the photolithography / etching steps in the neutral region ZN.

[0118] In this regard, step c1) may include forming a lower insulating layer, for example, made of aluminum oxide, using atomic layer deposition (ALD) technology or by anodizing the aluminum layer. This technology enables the formation of a relatively uniform layer on the supported surface, thereby optimally reproducing the texture applied by the surface of the metal layer 30, particularly the arrangement of the cavities 29.

[0119] The thickness of the lower isolation layer 65 can be, for example, between 10 nm and 100 nm.

[0120] Then, following step c) is step d) of growing the nanotube bundle 40. Figure 8 Nanotube bundles 40 are formed using standard techniques.

[0121] In particular, carbon nanotube bundles can be formed by DC-PECVD or DCVD at a temperature of 400 °C using different precursors and catalysts. In this regard, the conditions for carbon nanotube growth are described in references [4], [5], [6] and [7] cited at the end of this specification.

[0122] The average length L of the nanotube bundle can be between 2 μm and 40 μm, and advantageously between 2 μm and 12 μm.

[0123] Figure 9 This is an observation of nanotube bundles obtained using the method according to the invention, obtained using a scanning electron microscope. The image clearly shows nanotube bundles 40 arranged in a mesh pattern along a direction substantially perpendicular to the metal layer 20, and that the nanotube bundles 40 originate in cavities 29. Based on this observation, the inventors found that cavities 29 help determine the formation orientation of the nanotube bundles.

[0124] Therefore, according to the present invention, the average depth P and the average lateral dimension D are adjusted such that each nanotube bundle 40 originates in the cavity 29 and extends in a direction substantially perpendicular to the metal layer 20.

[0125] Advantageously, step a) can be performed under certain conditions to obtain an average lateral dimension D between 50 nm and 500 nm, advantageously between 50 nm and 300 nm, and in particular equal to 150 nm.

[0126] Advantageously, step a) can still be performed under certain conditions to obtain an average depth P between 10 nm and 150 nm.

[0127] After step d), the free end of the nanotube bundle 40 can be directly subjected to plasma treatment step d1) to adjust the extension length of the nanotube bundle.

[0128] The method according to the invention further includes step e) of enclosing the network.

[0129] In particular, Figure 10 The enclosure steps shown include forming a first dielectric layer 66a, followed by forming a second dielectric layer 66b covering the network (and more specifically, covering the free ends of the nanotube bundle).

[0130] The first dielectric layer 66a may include TEOS, and the thickness of the first dielectric layer may be between 100nm and 1000nm, for example, equal to 500nm.

[0131] The first dielectric layer 66a, during its deposition (albeit inconsistently), coats a portion of each nanotube bundle extending from the free end 42 of the nanotube bundle 40, referred to as the protected portion 40b. Figure 11 Specifically, a first dielectric layer 66a can be formed such that the length of this portion does not exceed 100 nm. Therefore, it can be understood that the length of this portion is much shorter than the total length of the nanotube bundle 40.

[0132] The particularly advantageous nature of this aspect will become more apparent in the remainder of this specification.

[0133] A second dielectric layer 66b is formed over the first dielectric layer 66a. The second dielectric layer may include silicon nitride, and the thickness of the second dielectric layer may be between 100 nm and 500 nm.

[0134] The method according to the invention includes the step of exposing the capacitive region ZC to the external environment (e)( Figure 12 ).

[0135] Specifically, step e) includes defining a first pattern 67 in the second dielectric layer 66b, such that the layer forms a hard mask. It is understood that the first pattern 67 is simply a via formed in the second dielectric layer 66b. Specifically, the first pattern 67 defines a capacitive region ZC.

[0136] The formation of the first pattern 67 may include photolithography and etching steps, as well as a stripping step for removing the photosensitive resin.

[0137] Step e) also includes etching, particularly dry etching, by etching the first dielectric layer 66a through a hard mask formed by the second dielectric layer 66b, thereby forming a first opening 67a consistent with the first pattern 67, thus exposing the capacitor region ZC to the external environment.

[0138] Then, following step e), step f) is performed, using atomic layer deposition to form a capacitive stack 50. Figure 13This deposition technique, particularly a uniform deposition technique, deposits the stack between the nanotube bundles, and more specifically, deposits the stack in the neutral region and the lower contact region still covered by the first and second dielectric layers.

[0139] Therefore, step f) sequentially includes forming a lower conductive layer 53 (this layer can be disregarded for structures obtained using conductive materials), an isolation layer 52, and an upper conductive layer 51.

[0140] Understandably, after the consistent deposition step f), the capacitive stack covers the metal layer between the nanotube bundles 40, but also covers these nanotube bundles from the base to the free end.

[0141] In this regard, to verify the consistency of the capacitive stacks on the nanotube bundles, the inventors have used scanning electron microscopy to... Figure 15 Nanotube bundles were observed at different locations A, B, C, and D, as shown. Figure 16A , Figure 16B , Figure 16C and Figure 16D The results observed using scanning electron microscopy are presented. These figures confirm the possibility of forming capacitive stacks 50 on the nanotube bundles 40 in a consistent manner.

[0142] The second dielectric layer 66b, which was not protected during the deposition, was also covered by the capacitive stack 50.

[0143] Equally important, in the lower contact region ZCI and the neutral region ZN, the protected portion 40b of the nanotube bundle is not covered by the capacitive stack 50. More specifically, in these two regions, the insulating layer 52 and the lower conductive layer 53 (if considered) enclose the upper conductive layer 51.

[0144] therefore, Figure 14 The arrangement of the capacitor stack 50, formed by the upper conductive layer 51, the insulating layer 52, and the lower conductive layer 53, is shown. Therefore, as this... Figure 14 As shown, in the capacitive region ZC, the capacitive stack 50 completely coats the nanotube bundles (especially the free ends). On the other hand, in the neutral region ZN (and the same effect in the lower contact region ZCI), the protected portion is not covered by the capacitive stack 50. More specifically, in this region, the upper conductive layer 51 is completely enclosed by the insulating layer 52 and the lower conductive layer 51.

[0145] The arrangement described below enables electrical contact to be made in the upper conductive layer 51 and the lower conductive layer 53, respectively, without exposing the nanotube bundle 40 to process steps that could damage them.

[0146] Therefore, the method according to the invention includes forming an upper electrode 60 covering the capacitive region ZC during step g). The upper electrode 60 is capable of slightly covering layers 66a and 66b in the neutral region ZN. The formation of the upper electrode 60 is known to those skilled in the art and will not be described in further detail. Step g) may also include peeling off the capacitive stack covering the second dielectric layer 66b after forming the upper electrode 60. However, it should be understood that the portion of the capacitive stack covered by the upper electrode 60 is retained.

[0147] Figure 18 The steps (h) designed to expose the lower contact area ZCI to the external environment are shown.

[0148] Specifically, step h) includes the following steps:

[0149] h1) Form a third dielectric layer 66c covering the top electrode and the second dielectric layer 66b;

[0150] h2) A second pattern 68 is defined in the second dielectric layer 66b and the third dielectric layer, such that the latter forms a hard mask. It is understood that the second pattern 68 is simply a via formed in the second dielectric layer 66b and the third dielectric layer. Specifically, the second pattern 68 defines the lower contact region ZCI.

[0151] The formation of the second pattern 68 may include photolithography and etching steps, as well as a stripping step for removing the photosensitive resin.

[0152] Step h) also includes an etching sub-step h3), specifically dry etching, in which the first dielectric layer 66a is etched by a hard mask formed by the second dielectric layer 66b and the third dielectric layer, thereby forming a second opening 68a consistent with the second pattern 68, thus exposing the lower contact region ZCI to the external environment.

[0153] Then, after step h), the lower electrode 70 is formed following a similar process to that used to form the upper electrode 60. Figure 19 ).

[0154] Finally, by forming a passivation layer 66d, the method of manufacturing the capacitive device is terminated, and the passivation layer is opened at the two contact points, thereby providing an electrical path from the upper electrode 60 to the lower electrode 70.

[0155] Specifically, the contact points are metal studs 61 and 71 (“Upper Bump Metallurgy” (UBM)).

[0156] References

[0157] [1]A.M.Saleem et al.,“Fully solid-state integrated capacitors basedon carbon nanofibers and dielectrics with specific capacitances higher than200nF / mm 2 ”,IEEE 69th electronic Components and Technology conference,pages1870-1876,2019;

[0158] [2]A.M.Saleem et al.,“Low temperature and cost-effective growth ofvertically aligned carbon nanofibers using spin-coated polymer-stabilizedpalladium nanocatalyst”,Sci.Technol.Adv.Mater.,vol.16,No.1,page 015007,2015;

[0159] [3]Kikuchi Tatsuya et al.,“Porous Aluminium Oxide formed by Anodizingin Various Electrolyte Species”,Current Nanoscience,11(5),560-571,2015;

[0160] [4]J.Dijon et al.,“How to switch from a tip to base growth mechanismin carbon nanotube growth by catalytic chemical vapour deposition”,Carbon,Vol.48,Issue 13,pages 3953-3963,2010;

[0161] [5]S.Liatard et al.,“Vertically-aligned carbon nanotubes on aluminumas a light-weight positive electrode for lithium-polysulfide batteries”,Chem.Commun.,51,7749,2015;

[0162] [6]US 10370759;

[0163] [7]R.Ramos et al.,《Nanocarbon interconnects combining vertical CNTinterconnects and horizontal graphene lines》,IEEE International Interconnecttechnology conference / Advanced Metallization Conference,23-26 May 2016.

Claims

1. A capacitive device (10), comprising: - A metal layer (20) having two main surfaces, which are referred to as the front side (21) and the back side (22), respectively. - A network of nanotube bundles or nanowire bundles (40) extending from the front side (21) and extending from the base (41) toward the free end (42) in a manner substantially perpendicular to the front side; - A continuous capacitive stack (50) that covers the metal layer (20) and the nanotube bundles or nanowire bundles (40) in a consistent manner from the base (41) to the free end (42), the stack comprising an upper conductive layer (51) and an isolation layer (52) that isolates the upper conductive layer (51) from each of the nanotube bundles or nanowire bundles and the metal layer (20). The device includes a capacitive region (ZC) and a lower contact region (ZCI). In the capacitive region (ZC), the upper conductive layer (51) encloses the nanotube bundle or nanowire bundle (40) and the isolation layer (52); while in the lower contact region (ZCI), the capacitive stack (50) allows the free end to be exposed, and the isolation layer (52) encloses the upper conductive layer (51).

2. The apparatus according to claim 1, wherein, The device includes an upper electrode (60) covering the capacitive region (ZC) for electrical contact with the upper conductive layer (51).

3. The apparatus according to claim 1 or 2, wherein, The device includes a lower electrode (70) covering the lower contact region (ZCI) to electrically contact the free end of the nanotube bundle or nanowire bundle (40) in the lower contact region (ZCI).

4. The apparatus according to claim 1 or 2, wherein, The capacitive stack (50) further includes a lower conductive layer (53) inserted between the isolation layer (52) and the nanotube bundle or nanowire bundle (40), the lower conductive layer (53) enclosing the isolation layer (52) in the lower contact region (ZCI).

5. The apparatus according to claim 3, wherein, The capacitive stack (50) further includes a lower conductive layer (53) inserted between the isolation layer (52) and the nanotube bundle or nanowire bundle (40), the lower conductive layer (53) enclosing the isolation layer (52) in the lower contact region (ZCI), and the lower electrode (70) also making electrical contact with the lower conductive layer (53).

6. The apparatus according to claim 4, wherein, The lower conductive layer (53) comprises titanium nitride.

7. The apparatus according to claim 1 or 2, wherein, The upper conductive layer (51) includes titanium nitride.

8. The apparatus according to claim 1 or 2, wherein, The insulating layer comprises aluminum oxide.

9. The apparatus according to claim 1 or 2, wherein, The device further includes a neutral region (ZN) inserted between the capacitive region (ZC) and the lower contact region (ZCI), and in the neutral region, a lower isolation layer (65) is inserted between the metal layer (20) and the nanotube bundle or nanowire bundle (40).

10. The apparatus according to claim 9, wherein, The neutral region (ZN) is covered by at least one enclosure layer (66a, 66b) made of an insulating material.

11. The apparatus according to claim 10, wherein, The at least one encapsulation layer (66a, 66b) comprises a silicon oxide layer and a silicon nitride layer.

12. The apparatus according to claim 1 or 2, wherein, The length of the nanotube bundle or nanowire bundle (40) is between 2 μm and 40 μm.

13. The apparatus according to claim 1 or 2, wherein, The metal layer (20) is an aluminum layer with a thickness between 0.5 μm and 3 μm, and has a texture on the front side (21) of the metal layer, the texture being formed by a network of cavities having an average depth P and an average lateral dimension D, each of the nanotube bundles or nanowire bundles extending from the cavity.

14. The apparatus according to claim 13, wherein, The average lateral dimension D is between 50 nm and 500 nm.

15. The apparatus according to claim 13, wherein, The average depth P is between 10 nm and 150 nm.

16. The apparatus according to claim 1 or 2, wherein, The nanotube bundle or nanowire bundle (40) is a carbon nanotube bundle or carbon nanowire bundle.

17. The capacitive device according to claim 1 or 2, wherein, The metal layer (20) is supported on the support base (30) by one of the faces of the metal layer opposite to the front face (21).

18. The capacitive device according to claim 12, wherein, The length of the nanotube bundle or nanowire bundle (40) is between 2 μm and 12 μm.

19. The capacitive device according to claim 14, wherein, The average lateral dimension D is between 50 nm and 300 nm.

20. The capacitive device according to claim 19, wherein, The average lateral dimension D is equal to 150 nm.

21. The capacitive device according to claim 17, wherein, A dielectric layer (31) is inserted between the support substrate (30) and the metal layer (20).

22. A method of manufacturing a capacitive device according to any one of claims 1 to 21, the method comprising the following steps: a) An anodizing step of a metal layer (20) having a first thickness E1, starting from the front side (21) of the metal layer (20) and passing through a second thickness E2 less than the first thickness, to form an oxide layer; b) An etching step for the oxide layer formed in step a); d) The growth step of the network (40) of the nanotube bundle or nanowire bundle; Step a) is performed such that the exposed surface of the metal layer (20) after step b) has a texture formed by a network of cavities having an average depth P and an average lateral dimension D, the average depth P and the average lateral dimension D being adjusted such that each nanotube bundle or nanowire bundle originates in a cavity, extends from the cavity and from the base (41) toward the free end (42) in a manner substantially perpendicular to the metal layer; e) The step of defining the capacitive region (ZC) includes forming a stack of a first dielectric layer and a second dielectric layer covering the network of nanotube bundles or nanowire bundles, and forming a first via in the stack, the first via defining a contact region. f) The step of forming the continuous capacitive stack (50), wherein the continuous capacitive stack covers the metal layer (20) and the nanotube bundle or nanowire bundle (40) in a consistent manner from the base (41) to the free end 42, the stack comprising the upper conductive layer (51) and the isolation layer (52), the isolation layer isolating the upper conductive layer (51) from each nanotube bundle or nanowire bundle and the metal layer (20). The upper conductive layer (51) encloses the nanotube bundle or nanowire bundle (40) and the isolation layer (52) in the capacitive region (ZC); while in the lower contact region (ZCI), which is different from the capacitive region (ZC), the capacitive stack (50) allows the free end to be exposed, and the isolation layer (52) encloses the upper conductive layer (51). g) Form an upper electrode (60) in the capacitive region (ZC). h) A lower electrode (70) is formed in the lower contact region (ZCI).

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