Adjustable branch prediction method and microprocessor

Abstract

This application relates to adjustable branch prediction methods and microprocessors. In one embodiment, a microprocessor includes prediction logic including a branch predictor including a set of multiple-set associative tables, each table corresponding to a different length branch pattern history, and control logic configured to provide an adjustable write policy for the prediction logic.

Description

Technical Field

[0001] This invention generally relates to microprocessors, and more specifically to branch prediction in microprocessors. Background Technology

[0002] Microprocessors today operate using a pipelined processing scheme, where programming instructions are broken down into steps that execute concurrently across multiple stages of the pipeline. Instructions typically (e.g., 10-20% of the programming code) consist of branch instructions or simple branches, including unconditional branches (e.g., branches that are always taken) and conditional branches (e.g., branches that are taken or not taken based on an evaluation of a specified condition). Until the condition is computed and the conditional jump passes through the execution stage in the instruction pipeline, it is often uncertain whether the conditional jump will be taken or not, which can lead to delays in fetching the next instruction. Branch predictors have been developed to attempt to guess at the front end of the pipeline which direction (take or not take) the conditional branch will go and to which target address, thus improving the instruction flow throughout the pipeline.

[0003] A common branch predictor used in microprocessors is called a Branch Target Address Cache (BTAC). A BTAC includes hardware logic that may include a global history pattern of past branch instruction behavior to predict the target address of a fetched branch instruction. Generally, a branch predictor for a BTAC may include multiple predictor tables used in conjunction with multiple, often alphabetically associated, multi-set cache memories or edges (such as edge A and edge B in the case of two cache memories in a BTAC). Each edge may include multiple paths (e.g., 2-way, 4-way, etc.). Information for some example BTAC arrays can be found in U.S. Patent Nos. 8,832,418 and 7,707,397. For a given cache fetch (e.g., a sixteen (16)-byte fetch of a cache line in an instruction cache), there may be more than a single branch instruction. For a BTAC with edges A and B, and a cache fetch including two branch instructions, information for those two branch instructions (e.g., target address, direction, etc.) can be found in edges A and B, respectively.

[0004] For conditional branch prediction, BTAC can use a Tag Geometry (TAGE) predictor, which comprises multiple tables, each containing a global branch history pattern of varying lengths. Extensive academic work exists on TAGE predictors, and specifically on recommended actions (e.g., write strategies or allocations) to take when updating table-based erroneous predictions. However, because some microprocessors use hardware implementations of TAGE predictors, the recommendations that claim to improve performance are not easily implemented after a given tape-out. Summary of the Invention

[0005] In one embodiment, a microprocessor includes: prediction logic including a branch predictor, the branch predictor including at least a first side and a second side, the first side and the second side each including a set of multiset association tables, each table in the set of multiset association tables corresponding to a branch pattern history of different lengths; and control logic configured to provide an adjustable write strategy for the prediction logic.

[0006] Other systems, methods, features, and advantages of the present invention will be apparent or become apparent to those skilled in the art upon examination of the following drawings and detailed description. All such additional systems, methods, features, and advantages are intended to be included within this specification, the scope of the invention, and protected by the appended claims. Attached Figure Description

[0007] The various aspects of the invention can be better understood by referring to the following accompanying drawings. The components in the drawings are not necessarily drawn to scale; rather, the focus is on clearly illustrating the principles of the invention. Furthermore, in the drawings, the same reference numerals denote corresponding parts in multiple views.

[0008] Figure 1A This is a block diagram of an example branch unit pipeline for a microprocessor that implements an embodiment of an adjustable branch prediction system.

[0009] Figure 1B It is shown Figure 1A The diagram shows an example front end of a branch unit pipeline.

[0010] Figure 2A This is a schematic diagram illustrating an example of an adjustable branch prediction system.

[0011] Figure 2B It is shown in Figure 2A A schematic diagram of an embodiment of example control logic used in an adjustable branch prediction system.

[0012] Figure 2C It is shown in Figure 2A A schematic diagram of an example pseudo-random generator used in an adjustable branch prediction system.

[0013] Figure 3 This is a flowchart illustrating an example of an adjustable branch prediction method.

[0014] Figure 4 This is a flowchart illustrating another example of an adjustable branch prediction method. Detailed Implementation

[0015] Certain embodiments of an adjustable branch prediction system and method are disclosed, configured to provide an adjustable write strategy for prediction logic used in a branch prediction pipeline of a microprocessor. In one embodiment, the adjustable branch prediction system includes a programmable feature control register that can be configured by microcode (e.g., adjustable via patch code) to enable the selection of one of multiple write strategies for multiple prediction tables even after the microprocessor chip has been tapered. Therefore, consistent with recent research on allocation schemes, the allocation scheme for each of the multiple write strategies for mispredictions can be customized for the specific hardware implementation of the microprocessor's branch predictor and / or for the specific application the microprocessor is intended for.

[0016] Furthermore, software is frequently used to study branch prediction schemes (such as TAGE), where adjustments are more easily implemented. In hardware implementations of branch prediction, changes, especially after tape-out, can be costly. Conversely, some embodiments of adjustable branch prediction systems enable microcode-driven adjustments to the predictor table's write strategy, thus achieving greater flexibility in hardware-based branch prediction.

[0017] Having summarized certain features of the adjustable branch prediction system of the present invention, reference will now be made in detail to the description of the adjustable branch prediction system as illustrated in the accompanying drawings. While the adjustable branch prediction system will be described in conjunction with these drawings, it is not intended to limit it to the one or more embodiments disclosed herein. That is, while the invention permits modifications and alternatives, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein in a manner sufficient for those skilled in the art to understand. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to the specific forms disclosed. Rather, the invention will cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. As used throughout this application, the word “may” is used in a permissive sense (i.e., implying potential) rather than a mandatory sense (i.e., implying necessity). Similarly, the word “comprising” means including, but not limited to, the specific embodiments disclosed herein.

[0018] Various units, modules, circuits, logic, or other components can be described as being "configured" to perform one or more tasks. In this context, "configured" is a broad description of a structure, which generally means "having a circuit or other physical structure" that performs or is capable of performing one or more tasks during operation. A circuit can be a special-purpose circuit or a more general-purpose processing circuit operating under the control of coded instructions. That is, in describing certain aspects or features of various implementations of the invention, terms such as "unit," "module," "circuit," "logic," and "component" may be used herein. Those skilled in the art will understand that the corresponding features are implemented using circuits, whether those circuits are special-purpose circuits or more general-purpose circuits operating under the control of microcoded instructions.

[0019] Furthermore, a unit / module / circuit / logic / component can be configured to perform a task even when that unit / module / circuit / logic / component is not currently in operation. The description of a unit / module / circuit / logic / component configured to perform one or more tasks is not explicitly intended to functionally limit that unit / module / circuit / logic / component. Those skilled in the art will understand that the specific structure or interconnection of circuit elements will generally be determined by the compiler of a design automation tool (such as a register-transfer language (RTL) compiler). An RTL compiler operates on scripts that are very similar to assembly language code to compile the scripts into a form for the layout or fabrication of the final circuit.

[0020] That is, more advanced software tools are used to design integrated circuits (such as the integrated circuits of this invention) to model the desired functional operation of the circuit. As is well known, "Electronic Design Automation" (or EDA) is a category of software tools used to design electronic systems (such as integrated circuits). EDA tools are also used to program design functions into field-programmable gate arrays (FPGAs). Hardware description languages ​​(HDLs) such as Verilog and Very High Speed ​​Integrated Circuits (VHDL) are used to create high-level representations of the circuits from which low-level representations and the final actual wiring can be derived. In practice, since modern semiconductor chips can have billions of components, EDA tools are considered essential for their design. In practice, circuit designers use programming languages ​​such as C / C++ to specify operational functions. EDA software tools translate this specified function into RTL. The hardware description language (e.g., Verilog) then translates the RTL into a discrete gate netlist. This netlist defines the actual circuit produced, for example, by a foundry. In practice, these tools are well-known and understood for their role and use in facilitating the design process of electronic and digital systems, and therefore need not be described further herein.

[0021] Figure 1AAn embodiment of an exemplary branch unit pipeline of a microprocessor 10 is shown. It should be understood that, for brevity and ease of explanation and illustration, certain known components of the microprocessor 10 are omitted herein. As is known, pipelined architectures provide multiple instructions that overlap during execution, where each stage is called a pipeline level. The blocks shown in the branch unit pipeline can each be implemented according to one or more levels, which are shown on the left side of the blocks and, in the depicted embodiment, are represented by the uppercase letters C, I, B, U, L, M, F, G, W, X, E, S, W, Y, and Z, which proceed sequentially from top to bottom and are redirected (as indicated by arrows). Those skilled in the art will understand that... Figure 1A The number and / or arrangement of stages depicted herein are merely illustrative of one exemplary embodiment, and in some embodiments, different numbers and / or arrangements of stages may be implemented, and are therefore contemplated within the scope of the invention. Those skilled in the art will also understand that the blocks provide a general description of the functionality of the branch pipeline, and for brevity, associated logic or circuitry known to those skilled in the art has been omitted herein. For example, those skilled in the art will understand that, as is known, each stage of a pipeline can be separated by a clock pipeline register or latch. As another example, although Figure 1A Although not explicitly shown, those skilled in the art should understand that operations at the front end involve data exchange or interaction with the instruction cache.

[0022] The instruction cache is a random access memory device within a microprocessor. The microprocessor loads and / or pre-fetches (e.g., from DRAM via a bus interface unit) instructions of an ISA machine language program (such as x86 ISA machine language instructions) that have recently been fetched from a larger cache (e.g., L2 cache, L3 cache) or system memory and are executed by the microprocessor during the execution of the ISA machine language program. The ISA defines an instruction address register that holds the memory address of the next ISA instruction to be executed (defined by the x86 ISA as the instruction pointer (IP), but sometimes called the program counter (PC)). The microprocessor updates the contents of the instruction address register as it runs the machine language program to control program flow. To subsequently fetch ISA instructions faster from the instruction cache rather than from system memory based on the contents of the instruction address register during the next execution of the machine language program, the ISA instructions are cached such that the register holds the memory addresses of the ISA instructions present in the instruction cache. Specifically, the instruction cache is accessed based on the memory address held in the instruction address register (e.g., IP), rather than exclusively based on the memory address specified by a load or store instruction. Therefore, a dedicated data cache that stores ISA instructions as data (such as those that may reside in the hardware portion of a system employing a software translator) and is accessed exclusively based on load / store addresses rather than through instruction address register values ​​is not an instruction cache. Furthermore, for the purposes of this invention, a unified cache that caches both instructions and data (i.e., based on both instruction address register values ​​and load / store addresses, rather than exclusively based on load / store address access) is intended to be included in the definition of an instruction cache.

[0023] Special attention Figure 1A The microprocessor 10 includes a branch unit pipeline, wherein the microprocessor 10 comprises a pipelined microprocessor, and in one embodiment, the instruction set of the pipelined microprocessor is substantially compliant with the x86 architecture instruction set. As will be appreciated by those skilled in the art from the description provided herein, the present invention can be implemented in a variety of different circuit structures and architectures, and Figure 1AThe architecture shown is just one of many suitable architectures. An exemplary microprocessor 10 includes a fast predictor 12, a branch target address cache (BTAC) 14, an instruction byte queue (XIB) 16, a branch decoder 18, a formatted instruction queue (FIQ) / circular queue 20, an instruction translator 22, a register alias table (RAT) / reservation station (RS) 24, functional units (e.g., integer units, floating-point units, etc.) 26, and a branch table update 28. The boxes of the various reference numerals in the microprocessor 10 correspond to logic implemented on corresponding multiple stages C, I, B, U, L, M, F, G, W, X, E, S, W, Y, and Z, where the pipelined architecture enables different instruction sets at each stage. In one embodiment, four or more instructions can be executed at each stage, where control signals mark each stage along the pipeline. The stages associated with the fast predictor 12, BTAC 14, and XIB 16 relate to the instruction cache (I cache, Figure 1A Access (not shown in the image).

[0024] The fast predictor 12 includes a single-cycle branch predictor that provides single-cycle prediction (e.g., taking one cycle to generate the target address, provided at level I in one embodiment). In one embodiment, the fast predictor 12 includes a table (also referred to herein as an array or target array) storing the branch target addresses of previously executed branch instructions, which performs branch prediction when the stored branch instructions are subsequently encountered. In one embodiment, the table includes 128 entries, but in some embodiments other sizes (e.g., 64 entries, 32 entries, etc.) may be used. The table is organized as an n-way (e.g., n is an integer greater than 1) set-associative cache. Generally, an n-way set-associative cache is also referred to herein as a multi-set-associative cache. In one embodiment, each entry stores eight (8) 3-bit counters and the current local branch mode, which are selected by the 3-bit local branch mode. The fast predictor 12 also includes a conditional branch predictor that is accessed in parallel with the table and provides take / not take direction for conditional branches. The fast predictor also includes a return stack that can provide targets instead of the table. In one embodiment, the return stack comprises four (4) entries and provides a target for the return instruction. Note that the specifications listed above are for illustrative purposes only, and some embodiments may be implemented under different specifications, and are therefore contemplated within the scope of the invention. The fast predictor 12 is configured to deliver the predicted branch target immediately (within a single cycle) without employing branch penalties. In some embodiments, the fast predictor 12 may operate according to other specifications of its prediction mechanism and / or table configuration, or in some embodiments, the fast predictor 12 may be omitted. Most branches are correctly predicted by the fast predictor 12. In some embodiments, where the fast predictor 12 provides a branch prediction that differs from the branch prediction of BTAC 14 (e.g., different in direction and / or target) based on the same acquired branch instruction, BTAC 14 utilizes the branch prediction information provided by BTAC 14 (e.g., direction, target address, branch prediction type) to rewrite the branch prediction of the fast predictor 12 and update the fast predictor table within a set of levels of BTAC 14 (e.g., at level U).

[0025] Level I and / or Level B correspond to access to various tables in the branch unit pipeline (including I cache, tag array, translation back buffer (TLB) array, BTAC array, return stack array, etc.), (e.g., tag-based) direction or path given by multiplexing, and read instructions.

[0026] BTAC 14 maintains information related to previously executed branch instructions used to predict the target address, direction, and type during subsequent execution. BTAC 14 includes one or more tables much larger than the tables of the fast predictor 12. In one embodiment, BTAC 14 includes a 4k-entry, m-way set association table (also referred to herein as an array or target array), where m is an integer greater than 1. Similar to an n-way set association table, an m-way set association table may also be referred to herein as a multi-set association table. Each entry in BTAC 14 includes a valid bit, a branch target address prediction, a direction prediction, and a branch type. The branch type specifies whether the branch instruction is a call / return, an indirect branch, a conditional relative branch, or an unconditional relative branch. In one embodiment, BTAC 14 includes a conditional relative branch predictor (or simply a conditional branch predictor) with multiple entries (e.g., 12k) of a tag geometry (TAGE)-based conditional branch predictor, multiple tables, multiple bits (e.g., 3 bits), a take / not take (T / NT) counter, and a multi-bit global branch history, or in conjunction with these. In other words, as is known, TAGE conditional branch predictors include a label table with a geometrically increasing branch history length. As another example, indirect prediction includes a multi-entry (e.g., 1.5k) TAGE predictor, and table entries are used for static indirect branching. In one embodiment, two TAGE conditional branch predictors are used, one for edge A in the predictor array and one for edge B in the predictor array. TAGE conditional branch predictors can be part of BTAC or used in conjunction with BTAC 14.

[0027] In one embodiment, BTAC 14 includes or collaborates with a second type of conditional branch predictor (e.g., a gshare predictor associated with an edge C of the predictor array) that has lower complexity than the TAGE conditional branch predictor. The gshare conditional branch predictor may be part of or used in conjunction with BTAC 14. The gshare conditional branch predictor comprises a complexity between that of the fast predictor 12 and the TAGE conditional branch predictor (e.g., approximately 1 / 10 the size of the TAGE conditional branch predictor). In one embodiment, the gshare conditional branch predictor includes a single table (e.g., an m-bit global history register comprising the branch patterns of the last m executed branch instructions, where m is typically 10-12 bits, but not limited to that number). The gshare conditional branch predictor uses the global branch history and the location (e.g., IP) of the branch instruction to create an index (via an XOR logical operation) into a table of counters (e.g., a 2-bit counter), where the result of the index is a prediction for the current branch. Since TAGE and gshare type conditional branch predictors are known in the art, further description thereof is omitted here for brevity. Furthermore, although edges A, B, and C are emphasized here, fewer or additional edges may be used in some embodiments. Note that other types of prediction mechanisms may be used in some embodiments, including correlation-based prediction mechanisms, conditional branch predictors using a combination of global and local branch histories, etc. For each portion of a cache line of the instruction cache or each fetch unit (e.g., 16 bytes), BTAC 14 may maintain three entries (e.g., edges A, B, and C, although fewer edges may be used in some embodiments to store prediction information for fewer branch instructions), which may hold prediction information for up to three branch instructions that may exist in a portion of the cache line. BTAC 14 includes operation through a set of levels (e.g., level I, level B, and level U). In practice, the level U of the branch instruction is used as the level C of the target (e.g., the arrow from level B to level C reflects the branch instruction at level B, and the next clock is the level C of the target, or here also the cache address), resulting in a two-clock delay for BTAC prediction.

[0028] BTAC 14 features a two-clock taken penalty, which also reveals the benefit of fast branch prediction (without taken penalty) provided by the fast predictor 12 by immediately guiding the new cache address as the target. In one embodiment, BTAC 14 is larger than the fast predictor 12 and has a more sophisticated branch prediction mechanism, configured (e.g., always) to rewrite the branch prediction of the fast predictor 12 when inconsistencies exist in the branch predictions (e.g., the branch prediction determined by BTAC 14 differs from the take decision and / or branch target address determined by the fast predictor 12). In some embodiments, BTAC 14 is configured to update the fast predictor 12 during one of the BTAC levels (e.g., level U) by writing branch prediction information to a table in the fast predictor 12 (and also to a table in BTAC 14). In some embodiments, updates to BTAC 14 are delayed until the branch is executed or retired, wherein updates to BTAC 14 involve writing to the predictor table of BTAC 14. In one embodiment, the update involves target information updates and / or counter updates. The update involves writing incorrectly predicted conditional branch information to one of edges A, B, or C. In some embodiments, the update is performed according to one of several selectable writing strategies for edges A and B corresponding to the respective TAGE conditional branch predictors. However, the update to the fast predictor 12 does not wait that long and occurs during the BTAC level. Note that branches not in the fast predictor 12 are written to the fast predictor 12 two cycles later at the time corresponding to the BTAC level (e.g., during the BTAC level).

[0029] XIB 16 is an entry queue where each entry holds 16 bytes of data from the instruction cache. For example, the cached data from XIB 16 is only a stream of instruction bytes in 16-byte blocks, and given that instructions have variable lengths, it is unknown where a given x86 instruction begins or ends within the stream or within a given block. XIB 16 includes known logic for determining and marking the start and end bytes of each instruction within the stream, thereby breaking the byte stream into a stream of x86 instructions, which is provided to and stored in the FIQ / circular queue 20 for processing by the rest of the microprocessor pipeline. At the L (length) level, XIB 16 determines the instruction length. In one embodiment, the pre-decoder ( Figure 1AThe branch decoder (not shown) is implemented at level U and is configured to detect potential branch instructions and mark them in a queue for each instruction byte. Note that at this level, there is ambiguity regarding whether a given byte is the start of an instruction. If the byte is the opcode byte of a branch instruction determined later (level M), the instruction is identified as a branch instruction. For example, branch decoder 18 includes instruction multiplexing (not shown) for multiplexing instructions in multiplexing or level M, where branch instructions are identified. Note that additional information regarding branch decoding can be found in U.S. Patent 8,473,726, the full text of which is incorporated herein by reference to the extent consistent with this invention.

[0030] In stage F, these instructions are formatted as described above. In one embodiment, the formatting instructions include instructions that substantially conform to the x86 architecture instruction set. Furthermore, in stage M, it is determined whether a given instruction (possibly pre-marked by the pre-decoder) is indeed a branch. For example, in the event of a miss at fast predictor 12 or BTAC 14 (e.g., at initial startup), branch decoder 18 (e.g., instruction multiplexing) determines that the current instruction is a branch, writes to the BOT, and redirects the cache address to the new target and updates the table in the front end of microprocessor 10 in stage G. In effect, when a miss occurs at fast predictor 12 or BTAC 14, branch decoder 18 provides branch prediction, where the branch instruction is redirected to the target in stage C. In some cases, such as when there are more than a finite or predetermined maximum number of branches for each fetch at BTAC 14 (e.g., more than three branches for each 16-byte fetch), branch prediction for additional branches is delayed until decoding time.

[0031] FIQ / Circular Queue 20 receives and buffers formatting instructions until they can be translated into microinstructions. FIQ / Circular Queue 20 also provides preliminary decoding and fast looping functionality (e.g., on a BTAC loop branch, the circular queue is activated and the loop instructions are repeatedly sent), the latter indicated by the arrow on the right side of box 20.

[0032] The W class offers an optional additional timing clock.

[0033] At level X, instruction translator 22 (in level X or translation level) translates the formatted instructions stored in FIQ / circular queue 20 into microinstructions.

[0034] Instructions are provided to Register Alias ​​Table / Reservation Table (RAT / RS) 24 in program order. The RAT function of RAT / RS 24 maintains and generates dependency information for each instruction. The RAT function of RAT / RS 24 renames the source and destination of instructions to internal registers and dispatches instructions to reservations in RAT / RS 24, which (possibly out of program order) issue instructions to function unit 26. Function or execution unit 26, including integer units, executes branch instructions at E (execution) level. Execution unit, branch unit, and integer unit are terms used interchangeably herein. In one embodiment, execution unit 26 (e.g., two execution units) executes two branches in a single clock cycle. Execution unit 26 also indicates whether BTAC 14 has correctly predicted the branch instruction.

[0035] In one embodiment, the result of execution is provided to a reordering cache (not shown), which includes information related to the instructions that have been executed. It is well known that reordering caches maintain the original program order of instructions after they are issued and allow serialization of results during exit stages. In one embodiment, some of the information in the reordering cache may be stored elsewhere in the pipeline, such as at decoder 18. The information stored in the reordering cache may include branch information, such as the type of branch, branch pattern, target, tables used in prediction, and cache replacement policy information (e.g., Least Recently Used or LRU).

[0036] Branch table update 28 includes S, W, Y, and Z levels and is configured to update various tables (e.g., BTAC, TAGE) at the front end with information related to the fully decoded and executed branch instructions (e.g., the final result of the branch) (e.g., at the S level). At the S, W, Y, and Z levels, updates may involve table reads, target address writes, and counter increments or decrements, which may involve some latency. In one embodiment, branch table update 28 provides an indication of error prediction for a given conditional branch instruction and the edge (e.g., A, B, or C) that caches that conditional branch instruction.

[0037] Now for reference Figure 1B And continue to refer to Figure 1A , showing in response to Figure 1AThe microprocessor 10 shown illustrates an example fast predictor 12 and other exemplary sources used at the front end 30 of a branch unit pipeline. The front end 30 includes an fetch unit 32 (e.g., including multiplexing and clock registers), a translation back buffer (TLB) 34, an instruction cache (I cache data) 36, I cache tags 38 (or a tag array), a BTAC 14, and the fast predictor 12. The fetch unit 32 receives multiple cache instruction address sources, including sequential instruction addresses (e.g., from I level), corrected instruction addresses (e.g., from S level), decode-time instruction addresses (e.g., from G level), and addresses from the BTAC 14 and the fast predictor 12. The output of the fetch unit 32 is a cache address provided as input to the TLB 34, I cache data 36, ​​I cache tags 38, BTAC 14, and the fast predictor 12 for accessing the next instruction of the I cache data 36.

[0038] TLB 34, under the management of the memory management unit (not shown), provides virtual-to-physical page address translation as is known. That is, TLB 34 stores the physical address of the most recently used virtual address. TLB 34 receives the linear address from the segmentation unit (which translates logical addresses from the program into linear addresses) and compares a portion of that linear address with entries in TLB 34 to find a match. If a match is found, the physical address is calculated based on the TLB entry. If no match is found, a page table entry is retrieved from memory and placed into TLB 34.

[0039] I cache data 36 includes Level 1 caches containing instructions that have been fetched or pre-fetched from L2, L3, or main memory. I cache data 36 includes multiple clock registers.

[0040] I cache tag 38 includes an array of tags corresponding to instructions in I cache data 36, ​​and includes multiple clock registers for determining the match between information associated with the picked-up cache instruction (e.g., a tag or portion of a cache address) and I cache data 36 and BTAC 14.

[0041] The above text combined Figure 1ABTAC 14 is described, and it has multiple clock registers and a two (2) clock take penalty. Similarly, the fast predictor 12 described above has a zero (0) clock take penalty. For example, assume fetching along the I cache at 16 bytes per cycle, and assume a branch instruction from cache address 20 to cache address 95. Note that the address descriptions in this example imply hexadecimal representation (e.g., 0x0, 0x10, 0x20, etc.). Thus, the fetch occurs at cache address 0, cache address 10, cache address 20 (the branch instruction, but not yet resolved due to the multiple cycles of reads and multiplexing in BTAC 14, which in some embodiments are the same timing as the I cache), cache address 30 (relative clock 1), cache address 40 (relative clock 2), and then on the third clock (relative clock 3), the cache instruction fetch is redirected to cache address 95. Therefore, the branch penalty in this example comprises two clock cycles because cache addresses 30 and 40 occur after the branch. In other words, without the fast predictor 12, the branch penalty for this particular design example would always be two clock cycles. Using the smaller and faster fast predictor 12, cache address fetches (in the above example) include 0, 10, 20, and 95, with no latency to the cache address and zero penalty. As mentioned above, in some embodiments, the fast predictor 12 can be omitted.

[0042] Turning attention Figure 2A This illustrates an example embodiment of an adjustable branch prediction system 40. In one embodiment, the adjustable branch prediction system 40 includes a BTAC 14 having or coupled to a conditional branch prediction table 42, a branch table update 28, and control logic 44, which includes write policy adjustment logic 46, a pseudo-random generator (PRG) 48, and cache entry replacement logic 50, and / or cooperates with these. Note that for brevity, other parts of the pipeline are omitted here, but it should be understood that the pipeline, as described above, is... Figure 1A-1BIt functions as described. In some embodiments, fewer or additional components may be considered to include the adjustable branch prediction system 40 and / or control logic 44. In one embodiment, the branch prediction table 42 (or simply the table) includes a first edge (A), a second edge (B), and a third edge (C), but in some embodiments, a different number of edges may be used. The first edge A and the second edge B each include a set of multi-set association tables corresponding to a corresponding first conditional branch predictor (or more specifically, the TAGE conditional branch predictor, one for edge A and one for edge B). The third edge includes a single table containing a single conditional branch predictor (e.g., the gshare conditional branch predictor), but in some embodiments, the third edge may be omitted or associated with different conditional branch predictors and / or multiple tables. Multiple tables T0-TN are in the corresponding edges A and B, where N is an integer greater than one, and typically five (or actually more if path counting is used) in different complexity global branch patterns. Those skilled in the art will understand that both BTAC 14 and the conditional branch predictors (TAGE, gshare) have multi-edge arrays (each with edges A, B, and C). For example, if the branch exists in edge B of BTAC 14, then the branch also exists in edge B of the conditional predictor. Figure 2A As shown, edges A and B in prediction table 42 each have separate TAGE condition predictors, and edge C has a gshare condition branch predictor. Note that references to prediction logic here include prediction tables (including their specific structure and / or layout, read and write strategies, and prediction algorithms or methods).

[0043] like Figure 2A As shown, branch table update 28 provides information to control logic 44, including whether a given conditional branch instruction was mispredicted and where the violating (mispredicted) conditional branch instruction is cached (e.g., which edge, which path). Control logic 44 collaborates with write policy adjustment logic 46, PRG 48, and cache entry replacement logic 50 to write branch instruction information to edge A, B, or C. For example, for the TAGE conditional branch predictor, (see below in conjunction with...) Figure 2B(Further described) Write policy adjustment logic 46 controls the selection of the write policy for error prediction, wherein the allocation of the table may be partly based on the allocation percentage value of the table provided by the pseudo-random generator 48. Cache entry replacement logic 50 includes an array utilizing one of a plurality of known cache entry replacement schemes. For example, in one embodiment, the Least Recently Used (LRU) replacement algorithm is used. When control logic 44 updates (writes) table 42 (e.g., selecting between edge A or edge B), cache entry replacement logic 50 controls an address multiplexer (not shown) to select the update address. Cache entry replacement logic 50 stores replacement information for each of edges A, B, and C. Thus, cache entry replacement logic 50 is a global resource shared among the edges of table 42. In one embodiment, the replacement information includes bits indicating which edge and which path of each edge is least recently used, which are used by control logic 44 for writing to table 42. Control logic 44 also controls updates to the LRU array of cache entry replacement logic 50.

[0044] Continue to refer to Figure 2A Pay attention to the situation Figure 2B This illustrates an embodiment of the strategy adjustment logic 46. Those skilled in the art should understand from this invention that... Figure 2BThe example shown is illustrative, and in some embodiments, different circuitry may be used to perform similar functionality. Strategy adjustment logic 46 includes a fuse library 52, a patch memory (e.g., a patch read-only memory or patch ROM) 54, a microcode memory (e.g., a microcode ROM) 56, a programmable feature control register (FCR) 58, and a multiplexer selector 60. Typically, FCR 58 selects one of several write strategies, which allows microcode-driven adjustments to the TAGE predictor via patch ROM 54 (and even after tape-out). Patch ROM 54 includes privileged code (e.g., authorized or supervised). Fuse library 52 includes multiple (e.g., hundreds, thousands, etc.) physical fuses that selectively blow or break upon receiving an overcurrent signal from an entity (e.g., a chip design manufacturer, chip maker, etc.). Microcode ROM 56 is configured to read from fuse library 52 and set the registers of FCR 58 accordingly. Fuse library 52 and microcode ROM 56 incorporate known technologies, and therefore, for brevity, further description thereof is omitted here. Patch ROM 54 includes microcode for replacing portions of the microcode in microcode ROM 56. This replacement allows instructions to be processed differently. For the purposes of FCR 58, default values ​​for various logic functions can be initially set (e.g., during tape-out). Patch ROM 54 can replace portions of microcode ROM 56, which in turn selectively reads one or a combination of fuses from fuse library 52 to adjust FCR 58 to modify or adjust default values, and in this embodiment, to indicate a change in the TAGE conditional branch predictor write strategy. Thus, through the implementation of strategy adjustment logic 46, default values ​​can be set and reset (e.g., adjusted) during chip fabrication and runtime (e.g., when the chip is started in a test environment).

[0045] By various bit settings, the output of FCR 58 can be modified to reflect the functionality of several different logical functions in microprocessor 10 (e.g., circular queue detection, indirect table write strategy, etc.). In this embodiment, two bits are used to control the selection of four different write strategies by multiplexer selection 60 (e.g., using RTL settings). In other words, one of the allocation schemes associated with each of the four different write strategies is selected during error prediction, where the allocation is for the next higher table or some mixture of tables. In one embodiment, Table 1 shows four different write strategies based on five (5) TAGE tables T0-T4. It should be understood that in some embodiments, the actions for error prediction, the number of write strategies, and / or the proportional allocation of each table may vary:

[0046] Table 1

[0047] Write strategy Actions against incorrect predictions WP0 Always assigned to the next higher table WP1 Distribute across multiple tables: 50% (T1, T3), 25% (T2, T4) WP2 Assigned to the next table (75%) and the "next + 1" table (25%). WP3 Assign to the next table (50%), the "next + 1" table (25%), and the "next + 2" table (25%).

[0048] Note that table complexity increases from T0 to T4. As an example, if WP0 is chosen and the incorrect prediction comes from table T0, the allocation for the update is always to the next higher table (e.g., T1). Cache entry replacement logic 50 determines whether the allocation is to edge A or edge B. Note that the reference to the term allocation (or similarly, "to allocate", etc.) refers to the selection of the prediction table to be placed into the prediction and the entries in that table. For example, if a branch only has an entry in T0 of the TAGE conditional branch predictor and it is incorrectly predicted, the allocation is to a new entry in the next higher table (such as T1) (assuming write policy 0 or WP0). Higher tables contain longer branch patterns and are more accurate on average, but not every branch can be allocated to a higher table due to space constraints. Furthermore, in some embodiments, entries in table 0 (T0) are maintained (where counters are updated to reflect the branch direction). Note that the number of tables is an illustration of an example embodiment, and other numbers may be used in some embodiments.

[0049] The implementation of a write strategy that uses percentage allocation to each table (e.g., WP1-WP3) relies on a pseudo-random generator 48. Figure 2CAn example of a pseudo-random generator 48 is shown. That is, pseudo-random generator 48 is used after a write strategy has been selected. For example, suppose that the 2-bit value generated by the FCR causes the multiplexer selector 60 to select write strategy 2 (WP2, where the allocation is to the next table 75% of the time and to the "next + 1" table 25% of the time). Pseudo-random generator 48 is used to pseudo-randomly create 75% of the signals. Note that the logic that makes up pseudo-random generator 48 provides better results than using only a simple counter (which, for example, makes 3 out of 4 states start to signal 75% of the time), because a simple counter may be tuned to a certain branch and always signals in one way or another. In one embodiment, pseudo-random generator 48 includes a linear feedback shift register (LFSR) 62, processing logic 64, and a feature control register (FCR) 66. In one embodiment, LFSR 62 includes seven (7) bits fed to processing logic 64, which in one embodiment includes an inverter. Note that the use of seven bits is merely illustrative, and in some embodiments, registers of other sizes may be used. In practice, LFSR 62 and processing logic 64 produce each possible value for the 7 bits (e.g., cycling through all 2^7 states in a pseudo-random order, except for all zeros). A portion of the bits (e.g., a 5-bit sample, but not limited to) is provided to FCR 66, which selects the desired percentage value in a pseudo-random manner. In one embodiment, FCR 66 is (e.g., via physical or software / microcode tuning) programmable.

[0050] Based on the above description, those skilled in the art should understand that an adjustable branch prediction method (using...) Figure 3 Method 68 (represented and implemented by control logic 44 in one embodiment) includes: replacing microcode with a patch (70); reading the fuse library with the microcode from the patch (72); setting bits of a feature control register based on the read (74); using the set bits to implement multiplexing selection of one of a plurality of write strategies involving one or more prediction tables (76); and writing one or more prediction tables according to the selected write strategy based on the error prediction (78).

[0051] Adjustable branch prediction system 40 has been described. Figure 2A-2C ) and method 68 ( Figure 3 In some embodiments of ), it should be understood that an embodiment of the branch prediction method (represented as ) can be adjusted. Figure 4Method 80 is implemented in a microprocessor having prediction logic including a predictor comprising a set of multi-set association tables, each corresponding to a branch pattern history of different lengths. Adjustable branch prediction method 80 includes: receiving a write policy control signal (82); and selecting one of a plurality of selectable write policies for the prediction logic based on the write policy control signal (84).

[0052] Any processing description or box in the flowchart should be understood as representing a module, segment, logic, or part of code (which includes one or more executable instructions for implementing a particular logical function or step in the process), and alternative implementations are included within the scope of the embodiments, wherein, as those skilled in the art will understand, functions may be performed in a different order than shown or discussed (including substantially concurrent execution or execution in a different order), depending on the functions involved.

[0053] While the invention has been shown and described in detail in the accompanying drawings and the foregoing description, such showing and description should be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and implemented by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.

[0054] Note that different combinations of the disclosed embodiments may be used, therefore referring to an embodiment or one embodiment does not imply that features from that embodiment are excluded from being used with features from other embodiments. In the claims, the word "comprising" does not exclude other elements or steps.

Claims

1. A microprocessor, comprising: The prediction logic includes a branch predictor, which includes a set of multi-set association tables, each of which corresponds to a branch pattern history of different lengths. as well as Control logic, configured to provide an adjustable write strategy for the prediction logic. The control logic includes a feature control register and multiplexing selection logic. The multiplexing selection logic is configured to select one of multiple write strategies based on the bit settings of the feature control register.

2. The microprocessor of claim 1, wherein, The control logic is configured to implement the adjustable write strategy after tape-out.

3. The microprocessor of claim 1, wherein, The adjustable write strategy includes an allocation scheme selected from multiple allocation schemes involving one or more tables in the set of multi-set association tables.

4. The microprocessor of claim 3, wherein, The conditional branch predictions made by the prediction logic based on the selected allocation scheme are based on erroneous predictions.

5. The microprocessor of claim 3, wherein, The control logic includes a pseudo-random generator, which is configured to implement the allocation scheme based on a percentage allocation to each multi-set association table.

6. The microprocessor of claim 1, wherein, The control logic includes a fuse library and a microcode memory, the microcode memory being configured to read the fuse library and, based on the read, provide changes to the bit settings of the feature control register.

7. The microprocessor of claim 6, wherein, The fuse library includes multiple fuse settings that can be individually selected via privileged microcode.

8. The microprocessor of claim 7, wherein, The control logic also includes a patch memory configured to replace a selected portion of the privileged microcode.

9. The microprocessor of claim 1, wherein, The branch predictor includes the TAGE conditional branch predictor.

10. An adjustable branch prediction method implemented in a microprocessor, the microprocessor having prediction logic including a branch predictor, the branch predictor including a set of multi-set association tables, each table in the set of multi-set association tables corresponding to a branch pattern history of different lengths, the adjustable branch prediction method comprising: Receive write policy control signals; as well as Based on the write strategy control signal, the prediction logic selects one of a plurality of selectable write strategies. This also includes selecting one of multiple write strategies based on bit settings in the feature control register.

11. The adjustable branch prediction method of claim 10, wherein, The receiving and selection are performed after the tape-out.

12. The adjustable branch prediction method of claim 10 further includes implementing an allocation scheme corresponding to the selected write strategy in the write strategy, the allocation scheme relating to one or more tables in the set of multi-set association tables.

13. The adjustable branch prediction method according to claim 12 further includes performing conditional branch prediction based on the selected allocation scheme, using error prediction as a basis.

14. The adjustable branch prediction method according to claim 12 further includes implementing the allocation scheme based on a percentage allocation of pseudo-randomly generated values ​​for each multi-set association table.

15. The adjustable branch prediction method of claim 10 further includes reading the fuse group and providing a change in the bit settings of the feature control register based on the reading.

16. The adjustable branch prediction method of claim 15, further comprising selecting one or more fuse settings of a plurality of fuse settings via privileged microcode.

17. The adjustable branch prediction method of claim 16, further comprising replacing a selected portion of the privileged microcode with code from a patch memory.

18. The adjustable branch prediction method of claim 10, wherein, The branch predictor comprises a TAGE conditional branch predictor.

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