Semiconductor device and method for forming the same

Abstract

A semiconductor device including a backside via with an enlarged backside portion and a method for forming the same are disclosed. In an embodiment, a device includes: a first transistor structure in a first device layer; a frontside interconnect structure on the front side of the first device layer; a first dielectric layer on the back side of the first device layer; a first contact extending through the first dielectric layer to a source / drain region of the first transistor structure; and a backside interconnect structure on the back side of the first dielectric layer and the first contact, the first contact including a first portion having a first tapered sidewall and a second portion having a second tapered sidewall, the width of the first tapered sidewall narrowing in a direction toward the second tapered sidewall, and the width of the second tapered sidewall widening in a direction toward the backside interconnect structure. Embodiments of the present application provide a semiconductor device and a method for forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be solved. Summary of the invention

[0004] In some embodiments, a device includes: a first transistor structure in a first device layer; a front interconnect structure on the front side of the first device layer; a first dielectric layer on the back side of the first device layer; a first contact extending through the first dielectric layer to a source / drain region of the first transistor structure; and a back interconnect structure on the back sides of the first dielectric layer and the first contact, wherein the first contact includes a first portion having a first tapered sidewall and a second portion having a second tapered sidewall, wherein a width of the first tapered sidewall narrows in a direction toward the second tapered sidewall, and wherein a width of the second tapered sidewall widens in a direction toward the back interconnect structure.

[0005] In some embodiments, a device includes: a first substrate; a first device layer, above the first substrate, the first device layer including a first transistor structure; a first dielectric layer, on the back side of the first device layer; a first back side via, electrically coupled to a first source / drain region of the first transistor structure, the first back side via extending through the first substrate and the first dielectric layer, the first back side via having a first width in the first substrate and a second width in the first dielectric layer, the second width being greater than the first width; and a first interconnect structure, above the first dielectric layer and the first back side via, the first interconnect structure including a power rail electrically coupled to the first source / drain region through the first back side via.

[0006] In some embodiments, a method includes: forming a first transistor on a first substrate; exposing a first epitaxial material, wherein exposing the first epitaxial material includes thinning a back side of the first substrate; epitaxially growing a second epitaxial material over the first epitaxial material; and replacing the second epitaxial material and the first epitaxial material with a back side via, wherein the back side via is electrically coupled to a source / drain region of the first transistor.

[0007] Embodiments of the present application provide a semiconductor device including a backside via and a method for forming the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] When with Figure 1 When read together, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the sizes of various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 An example of a nanostructured field effect transistor (nanoFET) according to some embodiments is shown in a three-dimensional view.

[0010] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Figure 8C , Fig. 9A , Fig. 9B , Fig. 9C , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.13A , Fig. 13B , Fig. 13C , Fig.14A , Fig. 14B , Fig. 14C , Fig.15A , Fig. 15B , Fig. 15C , Fig.16A , Fig. 16B , Fig. 16C , Fig.17A , Fig. 17B , Fig. 17C , Fig.18A , Fig.18B , Fig.18C , Fig.19A , Fig.19B , Fig.19C , Fig. 20A , Fig. 20B , Fig. 20C , Fig.21A , Fig. 21B , Fig. 21C , Fig.22A , Fig. 22B , Fig. 22C , Fig.23A , Fig. 23B , Fig.23C , Fig.24A , Fig. 24B , Fig.24C , Fig.24D , Fig.24E , Fig.24F , Figure 24G , Fig.25A , Fig.25B , Fig.25C , Fig.26A , Fig.26B , Fig.26C , Fig.26D Fig.27A , Fig.27B , Fig.27C , Fig.27D , Fig.28A , Fig.28B , Fig.28C , Fig.29A , Fig.29B , Fig.29C , Fig. 30A , Fig. 30B and Fig. 30C are cross-sectional and top-down views of intermediate stages of nanoFET fabrication in some embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different parts of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component is in direct contact with the second component, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component is not in direct contact with the second component. In addition, the present invention may repeat reference numbers and / or characters in multiple instances. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] Various embodiments provide a method for forming a backside via in a semiconductor device and a semiconductor device including the backside via. The method includes etching a substrate adjacent to a gate structure to form a first recess, forming a first epitaxial material in the first recess, forming a second epitaxial material above the first epitaxial material, and forming an epitaxial source / drain region above the second epitaxial material. The first epitaxial material may be formed of silicon germanium having an atomic germanium concentration of about 20% to about 60%, and the second epitaxial material may be formed of silicon germanium having an atomic germanium concentration of about 0% to about 20%. The substrate is thinned to expose the first epitaxial material, and a third epitaxial material is grown above the first epitaxial material. The third epitaxial material may be formed of silicon germanium having an atomic germanium concentration of about 20% to about 60%. A dielectric material is filled that surrounds at least a portion of the third epitaxial material, and the third epitaxial material, the first epitaxial material, and the second epitaxial material are removed to form a second recess exposing the epitaxial source / drain region, and a backside via is formed in the second recess. Forming the third epitaxial material over the first epitaxial material allows for the formation of a larger backside via, increases the bonding area of ​​a subsequently formed backside via in the dielectric material, reduces the resistance of the backside via, reduces device RC time delay, and improves device performance.

[0014] Some embodiments discussed herein are described in the context of IC dies including nanoFETs. However, various embodiments may be applied to IC dies including other types of transistors (e.g., fin field effect transistors (FinFETs), planar transistors, etc.) instead of or in combination with nanoFETs.

[0015] Figure 1An example of a nanoFET (e.g., a nanowire FET, a nanosheet FET, etc.) according to some embodiments is shown in a three-dimensional view. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, etc.) above a fin 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 is used as a channel region of the nanoFET. The nanostructure 55 may include a p-type nanostructure, an n-type nanostructure, or a combination thereof. A shallow trench isolation (STI) region 68 is arranged between adjacent fins 66, which may protrude above or between adjacent STI regions 68. Although the STI region 68 is described / illustrated as being separated from the substrate 50, as used herein, the term "substrate" may refer to a separate semiconductor substrate or a combination of a semiconductor substrate and an STI region. In addition, although the bottom of the fin 66 is shown as a single material continuous with the substrate 50, the bottom of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this article, the fin 66 refers to a portion extending between adjacent STI regions 68.

[0016] The gate dielectric layer 100 is over the top surface of the fin 66 and along the top surface, sidewalls and bottom surface of the nanostructure 55. The gate electrode 102 is over the gate dielectric layer 100. The first epitaxial source / drain region 92 and the second epitaxial region 95 are arranged on the fin 66 on opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0017] Figure 1 Reference cross sections used in subsequent figures are further illustrated. Cross section AA' is along the longitudinal axis of gate electrode 102 and in a direction, for example, perpendicular to the direction of current flow between first epitaxial source / drain region 92 or second epitaxial source / drain region 95 of a nanoFET. Cross section BB' is parallel to cross section AA' and extends through first epitaxial source / drain region 92 or second epitaxial source / drain region 95 of a plurality of nanoFETs. Cross section CC' is perpendicular to cross section AA' and parallel to the longitudinal axis of fin 66 of nanoFET and in a direction of current flow between, for example, drain / drain region 92 or second epitaxial source / drain region 95 of a nanoFET. For clarity, subsequent figures refer to these reference cross sections.

[0018] Some embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices such as planar FETs or fin field effect transistors (FinFETs).

[0019] Figures 2 to 30C is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figures 2 to 5 、6A、 Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A Fig.29A and Fig. 30A Show Figure 1 Reference section AA' is shown. Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig.12D , 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.24E , Fig.25B , Fig.26B , Fig.27B , Fig.28B , Fig.29B and Fig. 30B Show Figure 1 Reference section BB' is shown. Figure 7C , Figure 8C , Fig. 9C , Fig. 10C , Fig. 11C , Fig.11D , 12C , Fig.12E , Fig. 13C , Fig. 14C , Fig. 15C , Fig. 16C , Fig. 17C , Fig.18C , Fig.19C , Fig. 20C , Fig. 21C , Fig. 22C , Fig.23C , Fig.24C , Fig.24F , Fig.25C , Fig.26C , Fig.26D , Fig.27C , Fig.27D , Fig.28C , Fig.29C and Fig. 30C Show Figure 1 Reference section CC' shown. Fig.24D and 24G A top-down view is shown.

[0020] exist Figure 2 In the embodiment of the present invention, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is arranged on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenic phosphide; or combinations thereof.

[0021] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an NMOS transistor (e.g., an n-type nano FET), and the p-type region 50P can be used to form a p-type device such as a PMOS transistor (e.g., a p-type nano FET). The n-type region 50N can be physically separated from the p-type region 50P (as shown by the separator 20), and the device components discussed (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, the n-type region 50N and the p-type region 50P discussed can be provided.

[0022] In addition Figure 2In the embodiment of the present invention, a multilayer stack 64 is formed over a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layers 53). For illustration purposes and as discussed in more detail below, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 will be patterned to form a channel region of a nanoFET in the n-type region 50N and the p-type region 50P. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of a nanoFET in the n-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of a nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in the n-type region 50N, and the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nanoFET in both the n-type region 50N and the p-type region 50P.

[0023] For illustrative purposes, the multilayer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nanoFET, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nanoFET, such as silicon, silicon carbon, etc. For illustrative purposes, the multilayer stack 64 is shown as having a bottommost semiconductor layer suitable for a p-type nanoFET. In some embodiments, the multilayer stack 64 may be formed so that the bottommost layer is a semiconductor layer suitable for an n-type nanoFET.

[0024] The first semiconductor material and the second semiconductor material can be materials with high etching selectivity to each other. In this way, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in an embodiment in which the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

[0025] Reference now Figure 3 According to some embodiments, the fin 66 is formed in the substrate 50 and the nanostructure 55 is formed in the multilayer stack 64. In some embodiments, the nanostructure 55 and the fin 66 can be formed in the multilayer stack 64 and the substrate 50, respectively, by etching grooves in the multilayer stack 64 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. Forming the nanostructure 55 by etching the multilayer stack 64 can further define the first nanostructure 52A to 52C (collectively referred to as the first nanostructure 52) from the first semiconductor layer 51, and define the second nanostructure 54A to 54C (collectively referred to as the second nanostructure 54) from the second semiconductor layer 53. The first nanostructure 52 and the second nanostructure 54 can be collectively referred to as the nanostructure 55.

[0026] The fins 66 and nanostructures 55 may be patterned by any suitable method. For example, the fins 66 and nanostructures 55 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography with a self-aligned process, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that which can otherwise be obtained using a single direct photolithography method. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 66.

[0027] For illustrative purposes, Figure 3The fins 66 in the n-type region 50N and the fins 66 in the p-type region 50P are shown as having substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be greater or less than the width of the fins 66 in the p-type region 50P. In addition, although each fin 66 and nanostructure 55 is shown as having a uniform width throughout, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or nanostructures 55 increases continuously in a direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have different widths and be trapezoidal.

[0028] exist Figure 4 In the embodiment, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, the fin 66 and the nanostructure 55 and between adjacent fins 66. The insulating material can be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the embodiment shown, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In an embodiment, the insulating material is formed so that excess insulating material covers the nanostructure 55. Although the insulating material is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 50\fin 66 and the nanostructure 55. Thereafter, a filling material such as the above-mentioned filling material may be formed over the liner.

[0029] A removal process is then applied to the insulating material to remove excess insulating material above the nanostructures 55. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be utilized. The planarization process exposes the nanostructures 55 such that after the planarization process is completed, the top surface of the nanostructures 55 is flush with the top surface of the insulating material.

[0030] The insulating material is then recessed to form STI regions 68. The insulating material is recessed so that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. In addition, the top surface of the STI region 68 may have a flat surface, a convex surface, a concave surface (such as a recess), or a combination thereof as shown. The top surface of the STI region 68 may be formed to be flat, convex, and / or concave by appropriate etching. The STI region 68 may be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of the fin 66 and the nanostructure 55. For example, oxide removal using an acid such as dilute hydrofluoric acid (dHF) may be used.

[0031] Above about Figures 2 to 4 The process described is merely one example of how to form the fin 66 and the nanostructure 55. In some embodiments, the fin 66 and / or the nanostructure 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed above the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. The epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or the nanostructure 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may eliminate previous and / or subsequent implants, although in situ and implant doping may be used together.

[0032] In addition, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are shown and discussed herein as including the same material in the p-type region 50P and the n-type region 50N. As such, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be different materials, or may be formed in a different order in the p-type region 50P and the n-type region 50N.

[0033] In addition Figure 4In the embodiment having different well types, a photoresist or other mask (not shown separately) may be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, a photoresist may be formed over the fin 66 and the STI region 68 in the n-type region 50N and the p-type region 50P. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed by using a spin coating technique, and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist may be used as a mask to substantially prevent the n-type impurity from being implanted into the n-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted in the region, with a concentration between about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist is removed, such as by an acceptable ashing process.

[0034] After or before implanting the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, an n-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the p-type impurity from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, etc., implanted in the region, and its concentration is between about 10 13 Atom / cm 3 to about 10 14 Atom / cm 3 After implantation, the photoresist may be removed, such as by an acceptable ashing process.

[0035] After implantation of n-type region 50N and p-type region 50P, annealing may be performed to repair implantation damage and activate implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be in-situ doped during growth, which may eliminate implantation, although in-situ and implantation doping may be used together.

[0036] exist Figure 5In the embodiment of the present invention, a pseudo dielectric layer 70 is formed on the fin 66 and / or the nanostructure 55. The pseudo dielectric layer 70 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to an acceptable technique. A pseudo gate layer 72 is formed above the pseudo dielectric layer 70, and a mask layer 74 is formed above the pseudo gate layer 72. The pseudo gate layer 72 may be deposited above the pseudo dielectric layer 70 and then planarized, such as by CMP. The mask layer 74 may be deposited above the pseudo gate layer 72. The pseudo gate layer 72 may be a conductive or non-conductive material and may be selected from a group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The pseudo gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. The pseudo gate layer 72 may be made of other materials having high etching selectivity from etching of the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed on the n-type region 50N and the p-type region 50P. It should be noted that the dummy dielectric layer 70 is shown to cover only the fin 66 and the nanostructure 55 for illustrative purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0037] Figures 6A to 20C Various additional steps in the fabrication of embodiment devices are shown. Figures 6A to 20C Components in the n-type region 50N or the p-type region 50P are shown. FIG. 6A to FIG. 6C In the embodiment, acceptable photolithography and etching techniques can be used to pattern the mask layer 74 (see Figure 5 ) to form a mask 78. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form a dummy gate 76 and a dummy gate dielectric 71, respectively. The dummy gate 76 covers each channel region of the fin 66. The pattern of the mask 78 can be used to physically separate each of the dummy gates 76 from the adjacent dummy gates 76. The dummy gates 76 can also have a length direction that is substantially perpendicular to the length direction of the corresponding fin 66.

[0038] exist 7A to 7C in FIG. 6A to FIG. 6C A first spacer layer 80 and a second spacer layer 82 are formed over the structure shown. The first spacer layer 80 and the second spacer layer 82 are then patterned to act as spacers for forming self-aligned source / drain regions. 7A to 7C, a first spacer 80 is formed on the top surface of the STI region 68; on the top surface and sidewalls of the fin 66, the nanostructure 55, and the mask 78; and on the sidewalls of the dummy gate 76 and the dummy gate dielectric 71. A second spacer 82 is deposited over the first spacer 80. The first spacer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, etc. using a technique such as thermal oxidation, or may be deposited by CVD, ALD, etc. The second spacer 82 may be formed of a material having a different etch rate than the material of the first spacer 80, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may be deposited by CVD, ALD, etc.

[0039] After forming the first spacer layer 80 and before forming the second spacer layer 82, implantation for lightly doped source / drain (LDD) regions (not shown separately) may be performed. In embodiments with different device types, similar to the above in Figure 4 In the implantation discussed in the above, a mask such as a photoresist may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type (e.g., p-type) of impurities may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type (e.g., n-type) of impurities may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a doping ratio between about 1×10 15 Atom / cm 3 About 1x10 19 Atom / cm 3 Annealing can be used to repair implantation damage and activate implanted impurities.

[0040] exist FIG. 8A to FIG. 8C, the first spacer 80 and the second spacer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source and drain regions, and to protect the sidewalls of the fin 66 and / or the nanostructure 55 during subsequent processing. The first spacer 80 and the second spacer 82 can be etched using a suitable etching process such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc. In some embodiments, the material of the second spacer 82 has a different etching rate than the material of the first spacer 80, so that the first spacer 80 can be used as an etch stop layer when patterning the second spacer 82, and the second spacer 82 can be used as a mask when patterning the first spacer 80. For example, the second spacer 82 can be etched using an anisotropic etching process, wherein the first spacer 80 is used as an etch stop layer, and wherein the remaining portion of the second spacer 82 forms the second spacer 83, such as Figure 8B Thereafter, the second spacer layer 83 acts as a mask while etching the exposed portion of the first spacer layer 80, thereby forming Figure 8B and Figure 8C The first spacer layer 81 is shown.

[0041] like Figure 8B As shown, the first spacer layer 81 and the second spacer layer 83 are arranged on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8C As shown, in some embodiments, the second spacer 82 can be removed from above the first spacer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, the dummy gate 76, and the dummy gate dielectric 60. In other embodiments, a portion of the second spacer 82 can remain above the first spacer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

[0042] Note that the above disclosure generally describes the process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacer layer 81 may be patterned before the second spacer layer 82 is deposited), additional spacers may be formed and removed, etc. In addition, n-type and p-type devices may be formed using different structures and steps.

[0043] exist 9A to 9CIn some embodiments, first recesses 86 and second recesses 87 are formed in fin 66, nanostructure 55, and substrate 50. Epitaxial source / drain regions will be subsequently formed in first recesses 86, and epitaxial material and epitaxial source / drain regions will be subsequently formed in second recesses 87. First recesses 86 and second recesses 87 may extend through first nanostructure 52 and second nanostructure 54, and into substrate 50. Fig. 9B As shown, the top surface of STI region 58 may be flush with the bottom surface of first recess 86. In various embodiments, fin 66 may be etched such that the bottom surface of first recess 86 is disposed below the top surface of STI region 68 or the like.

[0044] like Fig. 9B and Fig. 9C As shown, the bottom surface of the second recess 87 may be arranged below the bottom surface of the first recess 86 and the top surface of the STI region 68. The first recess 86 and the second recess 87 may be formed by etching the fin 66, the nanostructure 55 and the substrate 50 using an anisotropic etching process such as RIE, NBE, etc. During the etching process for forming the first recess 86 and the second recess 87, the first spacer 81, the second spacer 83 and the mask 78 mask portions of the fin 66, the nanostructure 55 and the substrate 50. Each layer of the nanostructure 55 and / or the fin 66 may be etched using a single etching process or multiple etching processes. After the first recess 86 and the second recess 87 reach a desired depth, a timed etching process may be used to stop etching. The second recess 87 may be etched by the same process as etching the first recess 86 and an additional etching process before or after etching the first recess 86. In some embodiments, while performing the additional etching process for the second recess 87, the area corresponding to the first recess 86 may be masked. The second recess 87 may have a depth D1 ranging from about 40 nm to about 100 nm below the bottom surface of the first nanostructure 52A. The depth of the second recess 87 may be selected to control the depth of the subsequently formed backside via (such as described below). FIG. 27A to FIG. 27C The second recess 87 may have a W1 ranging from about 10 nm to about 30 nm. Fig. 9C As shown, the second recess 87 may have tapered sidewalls that gradually narrow as the second recess 87 extends into the substrate 50 .

[0045] exist FIG. 10A to FIG. 10C In the embodiment, the portion of the sidewall of the layer of the multilayer stack 64 formed of the first semiconductor material (eg, the first nanostructure 52) exposed by the first recess 86 and the second recess 87 is etched to form a sidewall recess 88. Fig. 10CThe sidewalls of the first nanostructure 52 adjacent to the sidewall recess 88 are shown as straight, but the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etching process such as a wet etch. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process such as tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch the sidewalls of the first nanostructure 52.

[0046] exist FIG. 11A to FIG. 11D In the embodiment, the first inner spacer 90 is formed in the side wall groove 88. FIG. 10A to FIG. 10C An inner spacer layer (not shown separately) is deposited over the structure shown to form a first inner spacer 90. The first inner spacer 90 serves as an isolation member between the subsequently formed source / drain region and the gate structure. As will be discussed in more detail below, epitaxial source / drain regions and epitaxial materials will be formed in the first recess 86 and the second recess 87, and the first nanostructure 52 will be replaced with a corresponding gate structure.

[0047] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, etc. The inner spacer layer may include a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched to form a first inner spacer 90. Although the outer sidewalls of the first inner spacer 90 are shown flush with the sidewalls of the second nanostructure 54, the outer sidewalls of the first inner spacer 90 may extend beyond the sidewalls of the second nanostructure 54 or be recessed from the sidewalls.

[0048] Moreover, despite Fig. 11C The outer side wall of the first inner spacer 90 is straight, but the outer side wall of the first inner spacer 90 may be concave or convex. As an example, Fig.11D The following embodiment is shown, in which the sidewalls of the first nanostructure 52 are recessed, the outer sidewalls of the first inner spacer 90 are recessed, and the first inner spacer 90 is recessed from the sidewalls of the second nanostructure 54. The inner spacer layer can be etched by an anisotropic etching process such as RIE, NBE, etc. The first inner spacer 90 can be used to prevent subsequent etching processes (such as etching processes for forming gate structures) from affecting the subsequently formed source / drain regions (for example, as described below with respect to FIG. 12A to FIG. 12E The damage of the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 is discussed.

[0049] exist FIG. 12A to FIG. 12EIn the second recess 87, a first epitaxial material 91 and a second epitaxial material 93 are formed, a first epitaxial source / drain region 92 is formed in the first recess 86, and a second epitaxial source / drain region 95 is formed in the second recess 87. In some embodiments, the first epitaxial material 91 and the second epitaxial material 93 may be sacrificial materials that are subsequently removed to form a backside via (such as described below with reference to FIG. 27A to FIG. 27C The back through hole 130 discussed above). FIG. 12B to FIG. 12E As shown, the top surface of the second epitaxial material 93 can be disposed above the bottom surface of the first recess 86. However, in some embodiments, the top surface of the second epitaxial material 93 can be disposed flush with or below the bottom surface of the first recess 86.

[0050] The first epitaxial material 91 and the second epitaxial material 93 may be formed in the second recess 87 by masking the first recess 86. The first epitaxial material 91 and the second epitaxial material 93 may be epitaxially grown in the second recess 87 using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. The first epitaxial material 91 and the second epitaxial material 93 may include any acceptable material, such as silicon germanium, etc. The first epitaxial material 91 and the second epitaxial material 93 may be formed by first epitaxial source / drain region 92, second epitaxial source / drain region 95, substrate 50, and dielectric layer (e.g., such as described below). FIG. 25A to FIG. 25C The STI region 68 and the second dielectric layer 125 discussed above are formed of a material having a high etch selectivity. In this way, the first epitaxial material 91 and the second epitaxial material 93 can be removed and replaced with a backside via without significantly removing the first epitaxial source / drain region 92, the second epitaxial source / drain region 95, the substrate 50, and the dielectric layer.

[0051] In some embodiments, the second epitaxial material 93 may be formed of a material having a lower germanium concentration than the material of the first epitaxial material 91. For example, the germanium atomic concentration in the second epitaxial material 93 may be in a range of about 0% to about 20%, while the germanium atomic concentration in the first epitaxial material 91 may be in a range of about 20% to about 60%. The material having a higher germanium concentration may be etched at a higher rate than the material having a lower germanium concentration. Forming the second epitaxial material 93 of a material having a lower germanium concentration and the first epitaxial material 91 of a material having a higher germanium concentration allows the first epitaxial material 91 to be etched at a high etch rate and the second epitaxial material 93 to be etched at a lower etch rate, thereby protecting the epitaxial source / drain regions during a subsequent etching process for removing the first epitaxial material 91 and the second epitaxial material 93 (hereinafter referred to as the etching process). FIG. 26A to FIG. 26DDiscussion). In some embodiments, forming the first epitaxial material 91 separated from the subsequently formed first epitaxial source / drain region 92 of a material having a higher germanium concentration provides efficiency benefits due to a high etch rate. Forming the second epitaxial material 93 adjacent to the first epitaxial source / drain region of a material having a lower germanium concentration provides higher etching accuracy due to a lower etch rate. Providing the first epitaxial material 91 and the second epitaxial material 93 simultaneously allows for rapid removal of the first epitaxial material 91 and the second epitaxial material 93 while also preventing damage to the first epitaxial source / drain region 92.

[0052] The first epitaxial material 91 may have a thickness T4 ranging from about 40 nm to about 100 nm, the second epitaxial material 93 may have a thickness T5 ranging from about 10 nm to about 40 nm, and the ratio of the thickness T4 to the thickness T5 may be about 2 to about 5. The thickness of the first epitaxial material 91 and the second epitaxial material 93 may be selected to control the thickness of the backside vias (such as those described below) formed later. FIG. 27A to FIG. 27C In addition, the relative thickness of the first epitaxial material 91 and the second epitaxial material 93 can be selected to be within the above range to provide a sufficient thickness of the second epitaxial material 93 to control the etching of the first epitaxial material 91 and the second epitaxial material 93 and protect the first epitaxial source / drain region 92, while maximizing the etching rate of the first epitaxial material 91 and the second epitaxial material 93.

[0053] The first epitaxial material 91 and the second epitaxial material 93 may have a combined height equal to the depth D1. For example, the first epitaxial material 91 and the second epitaxial material 93 may have a combined height ranging from about 40 nm to about 100 nm. The combined height of the first epitaxial material 91 and the second epitaxial material 93 may be selected to control the depth of a subsequently formed backside via (such as described below with reference to FIG. FIG. 27A to FIG. 27C The first epitaxial material 91 and the second epitaxial material 93 may have a width equal to the width W1. For example, the first epitaxial material 91 and the second epitaxial material 93 may have a width ranging from about 10 nm to about 30 nm. Fig. 9C As shown, the first epitaxial material 91 and the second epitaxial material 93 may have tapered sidewalls that gradually narrow as the first epitaxial material 91 and the second epitaxial material 93 extend into the substrate 50 .

[0054] Then, a first epitaxial source / drain region 92 is formed in the first recess 86 and over the second epitaxial material 93, and a second epitaxial source / drain region 95 is formed in the second recess 87. In some embodiments, the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may exert stress on the second nanostructure 54 to improve performance. Fig. 12CAs shown, a first epitaxial source / drain region 92 is formed in the first recess 86, and a second epitaxial source / drain region 95 is formed in the second recess 87, so that each dummy gate 76 is arranged between a corresponding adjacent pair of first epitaxial source / drain region 92 / second epitaxial source / drain region 95. In some embodiments, a first spacer 81 is used to separate the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 from the dummy gate 76, and a first inner spacer 90 is used to separate the first epitaxial source / drain region 92 from the second epitaxial source / drain region 95 and the nanostructure 55 by an appropriate lateral distance so that the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 are not short-circuited with a subsequently formed gate of the resulting nanoFET. FIG. 12B to FIG. 12E As shown, the bottom surface of the first epitaxial source / drain region 92 may be arranged above the bottom surface of the second epitaxial source / drain region 95. In some embodiments, the bottom surface of the first epitaxial source / drain region 92 may be arranged to be flush with or below the bottom surface of the second epitaxial source / drain region 95.

[0055] The first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 in the n-type region 50N (e.g., NMOS region) can be formed by masking the p-type region 50P (e.g., PMOS region). Then, the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 are epitaxially grown in the first groove 86 and the second groove 87 in the n-type region 50N, respectively. The first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may include any acceptable material suitable for n-type nanoFETs. For example, if the second nanostructure 54 is silicon, the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may include a material that applies tensile strain on the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may have a surface protruding from the corresponding upper surface of the nanostructure 55, and may have a small facet.

[0056] Furthermore, the first epitaxial source / drain region 92 in the n-type region 50N may include a material having a high etch selectivity to the materials of the first epitaxial material 91 and the second epitaxial material 93. For example, the first epitaxial source / drain region 92 may have a lower germanium concentration than the first epitaxial material 91 and the second epitaxial material 93, so that the first epitaxial material 91 and the second epitaxial material 93 may be removed without significantly removing the first epitaxial source / drain region 92.

[0057] The first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 in the p-type region 50P (e.g., a PMOS region) can be formed by masking the n-type region 50N (e.g., an NMOS region). Then, the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 are epitaxially grown in the first groove 86 and the second groove 87 in the p-type region 50P, respectively. The first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may include any acceptable material suitable for a p-type nanoFET. For example, if the first nanostructure 52 is silicon germanium, the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may include a material that applies compressive strain on the first nanostructure 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may also have a surface protruding from the corresponding surface of the multilayer stack 56, and may have a small facet.

[0058] In addition, the first epitaxial source / drain region 92 in the p-type region 50P may include a material having a high etching selectivity to the materials of the first epitaxial material 91 and the second epitaxial material 93. For example, the first epitaxial source / drain region 92 may have a lower germanium concentration than the first epitaxial material 91 and the second epitaxial material 93. In some embodiments, the concentration of germanium atoms in the first epitaxial source / drain region 92 may be in a range of about 15% to about 50%. In some embodiments, a portion of the first epitaxial source / drain region 92 adjacent to the second epitaxial material 93 (such as the first semiconductor material layer 92A discussed in further detail below) may have a lower germanium concentration, and the remaining portion of the first epitaxial source / drain region 92 may have a higher germanium concentration. For example, a portion of the first epitaxial source / drain region 92 adjacent to the second epitaxial material 93 may have a germanium atomic concentration of about 10% to about 30%, while the remaining portion of the first epitaxial source / drain region 92 has a germanium atomic concentration ranging from about 15% to about 50%. As such, the first epitaxial material 91 and the second epitaxial material 93 may be removed without significantly removing the first epitaxial source / drain region 92 .

[0059] Similar to the process for forming lightly doped source / drain regions discussed previously, dopants may be implanted into the first epitaxial source / drain region 92, the second epitaxial source / drain region 95, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 to form the source / drain region, followed by annealing. The source / drain region may have a dopant between about 1×10 19 Atom / cm 3 With about 1x10 21 Atom / cm 3The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities discussed previously. In some embodiments, the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may be in-situ doped during growth.

[0060] Due to the epitaxial process used to form the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 in the n-type region 50N and the p-type region 50P, the upper surfaces of the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 have facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets result in the merging of adjacent first epitaxial source / drain region 92 and second epitaxial source / drain region 95 of the same nano-FET, such as Fig. 12B In other embodiments, as shown in Fig.12D As shown, after the epitaxial process is completed, the adjacent first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 remain separated. Fig. 12B and Fig.12D In the illustrated embodiment, the first spacer layer 81 can be formed on the top surface of the STI region 68, thereby preventing epitaxial growth. In some other embodiments, the first spacer layer 81 can cover a portion of the sidewalls of the nanostructure 55, thereby further preventing epitaxial growth. In some other embodiments, the spacer etch used to form the first spacer layer 81 can be adjusted to remove the spacer material to allow the epitaxial growth area to extend to the surface of the STI region 58.

[0061] The first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may include one or more semiconductor material layers. For example, the first epitaxial source / drain region 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. The second epitaxial source / drain region 95 may include a first semiconductor material layer 95A, a second semiconductor material layer 95B, and a third semiconductor material layer 95C. The first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may use the semiconductor material layers discussed. Each of the first semiconductor material layer 92A / 95A, the second semiconductor material layer 92B / 95B, and the third semiconductor material layer 92C / 95C may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 92A / 95A may have a dopant concentration less than the second semiconductor material layer 92B / 95B and greater than the third semiconductor material layer 92C / 95C. In some embodiments, the first semiconductor material layer 92A may have a lower germanium concentration than the second semiconductor material layer 92B and the third semiconductor material layer 92C so as to provide good etching selectivity between the first semiconductor material layer 92A and the first epitaxial material 91 and the second epitaxial material 93. In embodiments where the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 include three semiconductor material layers, the first semiconductor material layer 92A / 95A may be deposited, the second semiconductor material layer 92B / 95B may be deposited over the first semiconductor material layer 92A / 95A, and the third semiconductor material layer 92C / 95C may be deposited over the second semiconductor material layer 92B / 95B.

[0062] Fig.12E The following embodiment is shown, in which the sidewall of the first nanostructure 52 is recessed, the outer sidewall of the first inner spacer 90 is recessed, and the first inner spacer 90 is recessed from the sidewall of the second nanostructure 54. Fig.12E As shown, the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 may be formed to contact the first inner spacer 90 and may extend through the sidewalls of the second nanostructure 54 .

[0063] exist FIG. 13A to FIG. 13C In the embodiment, a first interlayer dielectric (ILD) 96 is deposited on FIG. 12A to FIG. 12C. The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the first epitaxial source / drain region 92, the second epitaxial source / drain region 95, the mask 78, and the first spacer layer 81. The CESL 94 may include a dielectric material having an etching rate different from that of the material of the first ILD 96 above, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0064] exist FIG. 14A to FIG. 14C In the process, a planarization process such as CMP may be performed to make the top surface of the first ILD 96 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, and the portion of the first spacer 81 along the sidewall of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within process variations. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 may be retained, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacer 81.

[0065] exist FIG. 15A to FIG. 15C In the embodiment of the present invention, the dummy gate 76 and the mask 78 (if present) are removed in one or more etching steps so that a third recess 98 is formed. The portion of the dummy gate dielectric 60 in the third recess 98 is also removed. In some embodiments, the dummy gate 76 and the dummy gate dielectric 60 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 76 at a faster rate than the first ILD 96 or the first spacer 81. Each of the third recesses 98 exposes and / or covers a portion of the nanostructure 55, which is used as a channel region in a subsequently completed nanoFET. The portion of the nanostructure 55 used as a channel region is arranged between adjacent pairs of the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95. During the removal, the dummy gate dielectric 60 may be used as an etch stop layer when etching the dummy gate 76. The dummy gate dielectric 60 may then be removed after the dummy gate 76 is removed.

[0066] exist FIG. 16A to FIG. 16C, the first nanostructure 52 is removed to extend the third recess 98. The first nanostructure 52 may be removed by performing an isotropic etching process such as wet etching using an etchant that is selective to the material of the first nanostructure 52, while the second nanostructure 54, the substrate 50, and the STI region 58 remain relatively unetched compared to the first nanostructure 52. In an embodiment where the first nanostructure 52 includes, for example, SiGe and the second nanostructures 54A to 54C include, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) may be used to remove the first nanostructure 52.

[0067] exist 17A to 17C , a gate dielectric layer 100 and a gate electrode 102 are formed for replacing the gate. The gate dielectric layer 100 is conformally deposited in the third recess 98. The gate dielectric layer 100 may be formed on the top surface and sidewalls of the substrate 50 and the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 may also be deposited on the top surfaces of the first ILD 96, the CESL 94, the first spacer 81, and the STI region 68, and on the sidewalls of the first spacer 81 and the first inner spacer 90.

[0068] According to some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, etc., or combinations thereof. For example, in some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a k value greater than about 7.0 and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The formation method of the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0069] The gate electrodes 102 are deposited over the gate dielectric layers 100 and fill the remaining portions of the third recesses 98. The gate electrodes 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Fig.17A Hezhi Fig. 17C A single layer gate electrode 102 is shown in FIG. 1 , but the gate electrode 102 may include any number of liner layers, work function tuning layers, and filler materials discussed. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 and between the second nanostructures 54A and the substrate 50.

[0070] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 may occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region may be formed by a different process, such that the gate dielectric layer 100 may be a different material and / or have a different number of layers, and / or the gate electrode 102 in each region may be formed by a different process, such that the gate electrode 102 may be a different material and / or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate regions.

[0071] After filling the third recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layer 100 and the material of the gate electrode 102 that are above the top surface of the first ILD 96. The gate electrode 102 and the remaining portions of the material of the gate dielectric layer 100 thus form a replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 may be collectively referred to as a "gate structure."

[0072] exist 18A to 18C In the embodiment, the gate structure (including the gate dielectric layer 100 and the corresponding gate electrode 102 thereon) is recessed so that a groove is formed directly above the gate structure and between the opposite portions of the first spacer layer 81. A gate mask 104 including one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, etc.) is filled in the groove, and then a planarization process is performed to remove the excess portion of the dielectric material extending above the first ILD 96. The gate contact (such as the gate electrode 102 to be referred to below) formed subsequently Figures 20A to 20C The gate contact 114 discussed here penetrates the gate mask 104 and contacts the top surface of the recessed gate electrode 102 .

[0073] like 18A to 18C As further shown, the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD, PECVD, etc.

[0074] exist FIG. 19A to FIG. 19C, the second ILD 106, the first ILD 96, the CESL 94, and the gate mask 104 are etched to form a fourth recess 108, which exposes the first epitaxial source / drain region 92, the second epitaxial source / drain region 95, and / or the gate structure. The fourth recess 108 may be formed by etching using an anisotropic etching process such as RIE, NBE, etc. In some embodiments, the fourth recess 108 may be etched through the second ILD 106 and the first ILD 96 using a first etching process; however, the fourth recess may be etched through the gate mask 104 using a second etching process; and then the fourth recess may be etched through the CESL 94 using a third etching process. A mask such as a photoresist may be formed over the second ILD 106 and patterned to mask portions of the second ILD 106 from the first etching process and the second etching process. In some embodiments, the etching process may over-etch, and therefore, the fourth recess 108 extends into the first epitaxial source / drain region 92, the second epitaxial source / drain region 95, and / or the gate structure, and the bottom of the fourth recess 108 may be flush with the first epitaxial source / drain region 92, the second epitaxial source / drain region 95, and / or the gate structure (e.g., at the same level as the substrate 50 or at the same distance therefrom) or lower (e.g., closer to the substrate 50). Although Fig.19C The fourth recess 108 is shown exposing the first epitaxial source / drain region 92, the second epitaxial source / drain region 95, and the gate structure with the same cross-section, but in various embodiments, the first epitaxial source / drain region 92, the second epitaxial source / drain region 95, and the gate structure may be exposed at different cross-sections, thereby reducing the risk of shorting subsequently formed contacts.

[0075] After forming the fourth recess 108, a first silicide region 110 is formed over the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95. In some embodiments, a silicide or germanide region (such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof) is formed over the exposed portions of the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 by first depositing a metal (not shown separately) that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium) of the underlying first epitaxial source / drain region 92 and the second epitaxial source / drain region 95, and then performing a thermal annealing process to form the first silicide region 110. The unreacted portion of the deposited metal is then removed, for example, by an etching process. Although the first silicide region 110 is referred to as a silicide region, the first silicide region 110 may also be a germanide region or a silicon germanide region (e.g., a region including silicide and germanide). In an embodiment, the first silicide region 110 includes TiSi and has a thickness ranging from about 2 nm to about 10 nm.

[0076] exist FIG. 20A to FIG. 20C , source / drain contacts 112 and gate contacts 114 (also referred to as contact plugs) are formed in the fourth recess 108. The source / drain contacts 112 and the gate contacts 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the source / drain contacts 112 and the gate contacts 114 each include a barrier layer and a conductive material, and each is electrically coupled to the underlying conductive component (e.g., the gate electrode 102 and / or the first electrode silicide region 110). The gate contact 114 is electrically coupled to the gate electrode 102, and the source / drain contact 112 is electrically coupled to the first epitaxial source / drain region 92 and the second epitaxial source / drain region 95 through the first silicide region 110. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106. The first epitaxial source / drain region 92, the second epitaxial source / drain region 95, the second nanostructure 54, and the gate structure (including the gate dielectric layer 100 and the gate electrode 102) may be collectively referred to as a transistor structure 109. The transistor structure 109 may be formed in a device layer, wherein a first interconnect structure (such as described below with respect to the gate electrode) is formed over its front surface. FIG. 21A to FIG. 21C The front interconnect structure 120 discussed above) and a second interconnect structure (such as the one discussed below) is formed over the back side thereof. FIG. 29A to FIG. 29C Although the device layer is described as having nanoFETs, other embodiments may include device layers having different types of transistors (eg, planar FETs, finFETs, thin film transistors (TFTs), etc.).

[0077] although FIG. 20A to FIG. 20C Source / drain contacts 112 are shown extending to each of the first epitaxial source / drain regions 92 and the second epitaxial source / drain regions 95, but source / drain contacts 112 may be omitted from some of the first epitaxial source / drain regions 92. For example, as explained in more detail below, conductive features (e.g., backside vias or power rails) may be subsequently attached through the backside of one or more first epitaxial source / drain regions 92. For these particular first epitaxial source / drain regions 92, source / drain contacts 112 may be omitted or may not be electrically connected to any above conductive lines (such as those described below with reference to the FIG. 10B ). FIG. 21A to FIG. 21C 122 as discussed above).

[0078] FIG. 21A to FIG. 30C An intermediate step of forming a front side interconnect structure and a back side interconnect structure on transistor structure 109 is shown. The front side interconnect structure and the back side interconnect structure may each include conductive features electrically connected to a nano-FET formed on substrate 50. Fig.21A, Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A , Fig.29A and Fig. 30A Show Figure 1 Reference section AA' is shown. Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.24E , Fig.25B , Fig.26B , Fig.27B , Fig.28B , Fig.29B and Fig. 30B Show Figure 1 Reference section BB' is shown. Fig. 21C , Fig. 22C , Fig.23C , Fig.24C , Fig.24F , Fig.25C , Fig.26C , Fig.26D , 27C , Fig.27D , 28C , Fig.29C and Fig. 30C Show Figure 1 Reference section CC' shown. Fig.24D and 24G A top-down view is shown. FIG. 21A to FIG. 30C The processing steps described in the foregoing can be applied to the n-type region 50N and the p-type region 50P. As described above, backside conductive features (e.g., backside vias, power rails, etc.) can be connected to one or more first epitaxial source / drain regions 92. As such, the source / drain contacts 112 can be optionally omitted from the first epitaxial source / drain regions 92.

[0079] exist FIG. 21A to FIG. 21C , a front side interconnect structure 120 is formed on the second ILD 106. The front side interconnect structure 120 may be referred to as a front side interconnect structure because it is formed on the front side of the transistor structure 109 (eg, the side of the transistor structure 109 on which active devices are formed).

[0080] The front-side interconnect structure 120 may include one or more layers of first conductive features 122 formed in one or more stacked first dielectric layers 124. Each of the stacked first dielectric layers 124 may include a dielectric material such as a low-k dielectric material, an ultra-low-k (ELK) dielectric material, etc. The first dielectric layer 124 may be deposited using a suitable process such as CVD, ALD, PVD, PECVD, etc.

[0081] The first conductive component 122 may include conductive lines and conductive vias interconnecting the conductive line layers. The conductive vias may extend through the corresponding first dielectric layers in the first dielectric layers 124 to provide vertical connections between the layers of conductive lines. The first conductive component 122 may be formed by any acceptable process, such as a damascene process, a dual damascene process, etc.

[0082] In some embodiments, the first conductive component 122 may be formed using a damascene process, wherein a combination of photolithography and etching techniques is used to pattern the corresponding first dielectric layer 124 to form a groove corresponding to the desired pattern of the first conductive component 122. An optional diffusion barrier layer and / or an optional adhesion layer may be deposited, and then the groove may be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, and the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, and the like. In an embodiment, the first conductive component 122 may be formed by depositing a seed layer of copper or a copper alloy and filling the groove by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from the surface of the corresponding first dielectric layer 124, and to planarize the surfaces of the first dielectric layer 124 and the first conductive component 122 for subsequent processing.

[0083] FIG. 21A to FIG. 21C Five layers of first conductive features 122 and first dielectric layers 124 are shown in the front interconnect structure 120. However, it should be understood that the front interconnect structure 120 may include any number of first conductive features 122 arranged in any number of first dielectric layers 124. The front interconnect structure 120 may be electrically connected to the gate contact 114 and the source / drain contacts 112 to form a functional circuit. In some embodiments, the functional circuit formed by the front interconnect structure 120 may include a logic circuit, a memory circuit, an image sensor circuit, etc.

[0084] exist FIG. 22A to FIG. 22C In the embodiment, the first carrier substrate 150 is bonded to the top surface of the front-side interconnect structure 120 by a first bonding layer 152A and a second bonding layer 152B (collectively referred to as bonding layers 152). The first carrier substrate 150 may be a glass carrier substrate, a ceramic carrier substrate, a wafer (e.g., a silicon wafer), etc. The first carrier substrate 150 may provide structural support during subsequent processing steps and in the completed device.

[0085] In various embodiments, the first carrier substrate 150 may be bonded to the front side interconnect structure 120 using a suitable technique such as dielectric inter-bonding. The dielectric inter-bonding may include depositing a first bonding layer 152A on the front side interconnect structure 120. In some embodiments, the first bonding layer 152A includes silicon oxide (e.g., high density plasma (HDP) oxide, etc.) deposited by CVD, ALD, PVD, etc. The second bonding layer 152B may similarly be an oxide layer formed on the surface of the first carrier substrate 150 before bonding using, for example, CVD, ALD, PVD, thermal oxidation, etc. Other suitable materials may be used for the first bonding layer 152A and the second bonding layer 152B.

[0086] The dielectric inter-bonding process may also include applying surface treatment to one or more of the first bonding layer 152A and the second bonding layer 152B. The surface treatment may include plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water, etc.) that can be applied to one or more bonding layers 152. Then, the first carrier substrate 150 is aligned with the front interconnect structure 120, and the two are pressed together to start the pre-bonding of the first carrier substrate 150 to the front interconnect structure 120. The pre-bonding can be performed at room temperature (e.g., about 21°C to about 25°C). After the pre-bonding, an annealing process can be applied by, for example, heating the front interconnect structure 120 and the first carrier substrate 150 to a temperature of about 170°C.

[0087] In addition FIG. 22A to FIG. 22C In the embodiment, after bonding the first carrier substrate 150 to the front-side interconnect structure 120, the device can be flipped so that the back side of the transistor structure 109 faces upward. The back side of the transistor structure 109 can refer to the side opposite to the front side of the transistor structure 109 on which active devices are formed.

[0088] exist FIG. 23A to FIG. 23C In the embodiment, a thinning process may be applied to the back side of the substrate 50. The thinning process may include a planarization process (e.g., mechanical grinding, CMP, etc.), an etch-back process, a combination thereof, etc. In some embodiments, the thinning process may include a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), etc., which can thin the substrate 50 by an etching process that is selective to the material of the substrate 50 (e.g., etching the material of the substrate 50 at a faster rate than the material of the STI region 68 and the first epitaxial material 91). FIG. 23A to FIG. 23CAs shown, after thinning the substrate 50, the back side of the STI region 68 and the first epitaxial material 91 and portions of the sidewalls of the STI region 68 and the first epitaxial material 91 may be exposed. After the thinning process, portions of the substrate 50 may remain above the gate structure (e.g., the gate electrode 102 and the gate dielectric layer 100) and the nanostructure 55. The thickness T1 of the substrate 50 above the gate structure may be about 30 nm to about 90 nm. In some embodiments, the substrate 50 may be completely removed. Fig.23C As shown, the back side of the first epitaxial material 91 may be disposed above the back side of the substrate 50 at a height H1 ranging from about 5 nm to about 35 nm.

[0089] exist FIG. 24A to FIG. 24G In the embodiment, the third epitaxial material 126 is formed over the exposed back side of the first epitaxial material 91. In some embodiments, the third epitaxial material 126 may be a sacrificial material that is subsequently removed to form a back side via (such as described below with reference to FIG. 27A to FIG. 27C The third epitaxial material 126 may be epitaxially grown over the first epitaxial material 91 using processes such as CVD, ALD, VPE, MBE, etc. The third epitaxial material 126 may include any acceptable material, such as silicon germanium, etc. The third epitaxial material 126 may be formed by a substrate 50 and a dielectric layer (e.g., such as described below). FIG. 25A to FIG. 25C The STI region 68 and the second dielectric layer 125 are formed of a material having a high etch selectivity. In this way, the third epitaxial material 126 can be removed and replaced with a backside via without significantly removing the substrate 50 and the dielectric layer.

[0090] In some embodiments, similar to the first epitaxial material 91, the third epitaxial material 126 may be formed of a material having a high germanium concentration. For example, the concentration of germanium atoms in the third epitaxial material 126 may be in a range of about 20% to about 60%. A material having a higher germanium concentration may be etched at a higher rate than a material having a lower germanium concentration (e.g., the second epitaxial material 93). Forming the third epitaxial material 126 from a material having a higher germanium concentration allows for a subsequent etching process (hereinafter referred to as the etching process) for removing the third epitaxial material 126, the first epitaxial material 91, and the second epitaxial material 93. FIG. 26A to FIG. 26D The third epitaxial material 126 is etched at a high etch rate during the etching process.

[0091] In some embodiments, an optional dielectric mask 127 may be formed over the exposed surfaces of the substrate 50 and the fins 66 before forming the third epitaxial material 126 so as to prevent the third epitaxial material 126 from being formed along the surfaces of the substrate 50 and the fins 66. The dielectric mask 127 may include an oxide (e.g., silicon oxide, etc.), a nitride (e.g., silicon nitride, etc.), a combination thereof, etc. The dielectric mask 127 may be deposited by CVD, ALD, etc. and may be etched back so that the sidewalls and backside surfaces of the first epitaxial material 91 are exposed. The dielectric mask 127 may be removed after forming the third epitaxial material 126.

[0092] In some embodiments, the third epitaxial material 126 may be formed by alternating deposition and etch-back processes. The deposition process may include CVD, ALD, VPE, MBE, combinations thereof, and the like. The deposition process may include precursors, such as germanium-containing precursors (e.g., germanium (GeH4)), silicon-containing precursors (e.g., silane (SiH4)), combinations thereof, and the like. The deposition process may also include a carrier gas, such as hydrogen (H2), nitrogen (N2), combinations thereof, and the like. The ratio of the precursor flow rate to the carrier gas flow rate may be tuned to ensure that the third epitaxial material 126 is selectively grown over the first epitaxial material 91, rather than along the surface of the STI region 68, the dielectric mask 127, and / or the substrate 50. The ratio of the germanium-containing precursor flow rate to the silicon-containing precursor flow rate may also be used to control the composition of the third epitaxial material 126.

[0093] The etch-back process may include a precursor, such as hydrogen chloride (HCl), silane (SiH4), a combination thereof, and the like. The etch-back process may also include a carrier gas, such as hydrogen (H2), nitrogen (N2), a combination thereof, and the like. In embodiments where the etch-back process includes hydrogen chloride and silane, the silane may passivate portions of the third epitaxial material 126, while the hydrogen chloride attacks and etches the unpassivated portions of the third epitaxial material 126. In this manner, the etch-back process may be used to control the shape of the third epitaxial material 126. In some embodiments, a sidewall portion of the third epitaxial material 126 may be passivated while the backside of the third epitaxial material 126 is etched. This process may be used to increase the critical dimension (e.g., width) of the third epitaxial material 126, which reduces device resistance without requiring a greater height of the third epitaxial material 126.

[0094] like FIG. 24B to FIG. 24D As shown, the third epitaxial material 126 may have an octagonal shape or a hammerhead shape in the cross-sectional view and the top view. FIG. 24E to FIG. 24GAs shown, the third epitaxial material 126 may have a hexagonal shape or a hammerhead shape in the cross-sectional view and the top view. The third epitaxial material 126 may have a thickness T2 ranging from about 5 nm to about 30 nm above the back side of the first epitaxial material. The third epitaxial material 126 may have a W2 ranging from about 20 nm to about 70 nm. The shape and size of the third epitaxial material 126 may be controlled to control the size and shape of the back side vias subsequently formed, which may replace the first epitaxial material 91, the second epitaxial material 93, and the third epitaxial material 126.

[0095] exist FIG. 25A to FIG. 25C In the embodiment of the present invention, a second dielectric layer 125 is deposited on the back side of the device. FIG. 25A to FIG. 25C As shown, the second dielectric layer 125 may be deposited over the substrate 50 and the STI region 68. In some embodiments, the second dielectric layer 125 may also be deposited over the third epitaxial material 126 and may be etched back so that a portion of the third epitaxial material 126 protrudes from the second dielectric layer 125. The second dielectric layer 125 may be deposited by a process such as CVD, ALD, etc. The second dielectric layer 125 may physically contact the sidewalls of the third epitaxial material 126, the sidewalls of the first epitaxial material 91, the sidewalls and backside of the STI region 68, and the backside of the substrate 50. The second dielectric layer 125 may include a material such as silicon oxide, but any suitable material may be utilized, such as a low dielectric constant (low-k) material having a k value of less than about 3.5. The second dielectric layer 125 may have a thickness T3 of from about 15 nm to about 30 nm over the backside of the substrate 50. Controlling the thickness of the second dielectric layer 125 may be used to control the length of a backside via that subsequently extends through the second dielectric layer 125.

[0096] exist FIG. 26A to FIG. 26D, the third epitaxial material 126, the first epitaxial material 91, and the second epitaxial material 93 are removed to form a fifth recess 128, and a second silicide region 129 is formed in the fifth recess 128. The third epitaxial material 126, the first epitaxial material 91, and the second epitaxial material 93 can be removed by a suitable etching process, which can be an isotropic etching process, such as a wet etching process. The etching process can have a high etching selectivity to the materials of the third epitaxial material 126, the first epitaxial material 91, and the second epitaxial material 93. In this way, the third epitaxial material 126, the first epitaxial material 91, and the second epitaxial material 93 can be removed without significantly removing the materials of the second dielectric layer 125, the STI region 68, the substrate 50, or the first epitaxial source / drain region 92. As previously discussed, the second epitaxial material 93 may be formed of a material having a lower germanium concentration so that the etching rate of the second epitaxial material 93 is lower in order to protect the first epitaxial source / drain region 92 from over-etching during the etching process for removing the third epitaxial material 126, the first epitaxial material 91, and the second epitaxial material 93. The fifth recess 128 may expose the sidewalls of the second dielectric layer 125, the sidewalls of the STI region 68, and the back surface of the first epitaxial source / drain region 92.

[0097] like Fig.26C As shown, the fifth groove 128 may be hammer-shaped in a cross-sectional view, wherein the first portion 128A has a tapered profile whose width continuously decreases in a direction from the front surface of the substrate 50 toward the back surface of the substrate 50; the second portion 128B has a tapered profile whose width continuously decreases in a direction from the back surface of the second dielectric layer 125 toward the back surface of the substrate 50; and the third portion 128C has a vertical sidewall. The first portion 128A may taper from a width W3 to a width W4, and have a height H2 from about 20 nm to about 50 nm. The width W3 may be in a range of about 15 nm to about 30 nm, the width W4 may be in a range of about 10 nm to about 30 nm, and the ratio of the width W3 to the width W4 may be in a range of about 1 to about 1.8. The second portion 128B may taper from a width W5 to a width W4, and have a height H3 from about 2 nm to about 10 nm. The width W5 may be in the range of about 20 nm to about 70 nm, and the ratio of the width W5 to the width W4 may be in the range of about 1 to about 1.8. The third portion 128C may have a width W5 and a height H4 ranging from about 5 nm to about 20 nm. In some embodiments, the ratio of the width W5 to the average width of the first portion 128A may be from about 2 to about 7. Forming the fifth groove 128 including the second portion 128B and the third portion 128C increases the contact area of ​​the backside via formed subsequently, which reduces the contact resistance and improves the RC time delay.

[0098] exist Fig.26D, the fifth groove 128 can be widened by an additional suitable etching process, which can be an isotropic etching process, such as a wet etching process. The additional etching process can have a high etching selectivity to the material of the second dielectric layer 125 and the substrate 50. In this way, the material of the second dielectric layer 125 and the substrate 50 can be removed without significantly removing the material of the first epitaxial source / drain region 92. After the additional etching process, the first portion 128A can taper from width W6 to width W7. Width W6 can be in the range of about 17nm to about 32nm, width W7 can be in the range of about 12nm to about 32nm, and the ratio of width W6 to width W7 can be in the range of about 1 to about 1.8. The second portion 128B can taper from width W8 to width W7. Width W8 can be in the range of about 20nm to about 70nm, and the ratio of width W8 to width W7 can be in the range of about 1.1 to about 1.8. The third portion 128C can have a width W8. Performing an additional etching process to widen the fifth groove 128 further increases the contact area of ​​a subsequently formed backside via, which further reduces contact resistance and improves RC time delay.

[0099] A second silicide region 129 may then be formed in the fifth recess 128 on the back side of the first epitaxial source / drain region 92. The second silicide region 129 may be similar to the one described above with respect to FIG. 19A to FIG. 19C The first silicide region 110 is described. For example, the second silicide region 129 may be formed of similar materials and using similar processes as the first silicide region 110.

[0100] exist FIG. 27A to FIG. 27D , a backside via 130 is formed in the fifth recess 128. The backside via 130 may extend through the second dielectric layer 125 and may be electrically coupled to the first epitaxial source / drain region 92 through the second silicide region 129. The backside vias 130 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filling material. For example, in some embodiments, the backside vias 130 each include a barrier layer and a conductive material, and each is electrically coupled to an underlying conductive component (e.g., the second silicide region 129). The backside via 130 is electrically coupled to the first epitaxial source / drain region 92 through the second silicide region 129. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc.

[0101] like FIG. 27B to FIG. 27D As shown, the back through hole 130 may have a hammer shape, wherein the back portion of the back through hole 130 has an octagonal shape. The back through hole 130 may have a Fig.27C Widths W4 to W6 as shown or Fig.27DWidths W7 to W9 are shown. By epitaxially growing the third epitaxial material 126 over the first epitaxial material 91, the width of the back portion of the backside via 130 is increased, which reduces the contact resistance of the backside via 130, reduces the RC time delay, and improves device performance.

[0102] exist FIG. 28A to FIG. 28C In the process, the backside via 130 is planarized and the second conductive line 134 and the third dielectric layer 132 are formed. A planarization process such as CMP may be performed to make the backside surface of the backside via 130 flush with the backside surface of the second dielectric layer 125. After the planarization process, the backside via 130 may have a height H5 ranging from about 30 nm to about 80 nm. Then, the second conductive line 134 and the third dielectric layer 132 may be formed over the backside via 130 and the second dielectric layer 125. The third dielectric layer 132 may be similar to the second ILD 106. For example, the third dielectric layer 132 may be formed of the same or similar material as the second ILD 106.

[0103] The second conductive line 134 is formed in the third dielectric layer 132. For example, using a combination of photolithography and etching processes, forming the second conductive line 134 may include patterning a groove in the third dielectric layer 132. The pattern of the groove in the third dielectric layer 132 may correspond to the pattern of the second conductive line 134. The second conductive line 134 is then formed by depositing a conductive material in the groove. In some embodiments, the second conductive line 134 includes a metal layer, which may be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the second conductive line 134 includes copper, aluminum, cobalt, tungsten, titanium, tantalum, ruthenium, etc. Before filling the groove with the conductive material, an optional diffusion barrier layer and / or an optional adhesion layer may be deposited. Suitable materials for the barrier layer / adhesion layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, etc. The second conductive line 134 may be formed using, for example, CVD, ALD, PVD, electroplating, etc. The second conductive line 134 is electrically coupled to the first epitaxial source / drain region 92 through the backside via 130 and the second silicide region 129. A planarization process (eg, CMP, grinding, etch-back, etc.) may be performed to remove excess portions of the second conductive line 134 formed over the third dielectric layer 132.

[0104] In some embodiments, the second conductive line 134 is a backside power rail, which is a conductive line that electrically connects the first epitaxial source / drain region 92 to a reference voltage, a power supply voltage, etc. By placing the power rail on the backside of the resulting semiconductor die rather than on the front side of the semiconductor die, advantages can be achieved. For example, the gate density of the nanoFET and / or the interconnect density of the front side interconnect structure 120 can be increased. In addition, the back side of the semiconductor die can accommodate a wider power rail, thereby reducing resistance and improving the efficiency of power delivery to the nanoFET. For example, the width of the second conductive line 134 can be at least twice the width of the first level conductive line (e.g., the first conductive component 122 and / or the first conductive line 118) of the front side interconnect structure 120.

[0105] exist FIG. 29A to FIG. 29C , the remaining portion of the backside interconnect structure 136 is formed over the third dielectric layer 132 and the second conductive line 134. The backside interconnect structure 136 may be referred to as a backside interconnect structure because it is formed on the backside of the transistor structure 109 (e.g., the side of the transistor structure 109 opposite to the side of the transistor structure 109 on which the active devices are formed). The backside interconnect structure 136 may include the second dielectric layer 125, the third dielectric layer 132, the backside via 130, and the second conductive line 134. Fig.29C As shown, the back side via 130 may include a first tapered sidewall that narrows in a direction toward the back side interconnect structure 136, a second tapered sidewall that extends from the first tapered sidewall and widens in a direction toward the back side interconnect structure 136, and a third vertical sidewall that extends from the second tapered sidewall and is perpendicular to the main surface of the substrate 50.

[0106] The remainder of the backside interconnect structure 136 may include materials and may be fabricated using the same techniques as described above with respect to FIG. 21A to FIG. 21C The backside interconnect structure 136 may be formed by processes that are the same or similar to those used for the frontside interconnect structure 120 discussed above. In particular, the backside interconnect structure 136 may include a stack of second conductive features 140 formed in the fourth dielectric layer 138. The second conductive features 140 may include wiring (e.g., wiring between subsequently formed contact pads and external connectors). The second conductive features 140 may be further patterned to include one or more embedded passive devices, such as resistors, capacitors, inductors, etc. The embedded passive devices may be integrated with the second conductive lines 134 (e.g., power rails) to provide circuits (e.g., power circuits) on the backside of the nanoFET.

[0107] exist FIG. 30A to FIG. 30C, a passivation layer 144, a UBM 146, and an external connector 148 are formed over the backside interconnect structure 136. The passivation layer 144 may include a polymer such as PBO, polyimide, BCB, etc. Alternatively, the passivation layer 144 may include a non-organic dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, etc. The passivation layer 144 may be deposited by, for example, CVD, PVD, ALD.

[0108] A UBM 146 is formed through the passivation layer 144 to the second conductive component 140 in the backside interconnect structure 136, and an external connector 148 is formed on the UBM 146. The UBM 146 may include one or more layers of copper, nickel, gold, etc. formed by an electroplating process, etc. An external connector 148 (e.g., a solder ball) is formed on the UBM 146. Forming the external connector 148 may include placing a solder ball on an exposed portion of the UBM 146 and reflowing the solder ball. In some embodiments, forming the external connector 148 includes performing an electroplating step to form a solder area above the topmost second conductive component 140, and then reflowing the solder area. The UBM 146 and the external connector 148 may be used to provide input / output connections to other electrical components, such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, etc. The UBM 146 and the external connector 148 may also be referred to as backside input / output pads, which may provide signals, power supply voltages, and / or ground connections to the above-mentioned nanoFETs.

[0109] Embodiments can achieve advantages. For example, forming a backside via including an enlarged backside portion provides a larger contact area for the backside via and reduces contact resistance in the backside via. This, in turn, can reduce RC time delay and improve device performance.

[0110] According to an embodiment, a device includes: a first transistor structure in a first device layer; a front interconnect structure on the front side of the first device layer; a first dielectric layer on the back side of the first device layer; a first contact extending through the first dielectric layer to a source / drain region of the first transistor structure; and a back interconnect structure on the back sides of the first dielectric layer and the first contact, the first contact including a first portion having a first tapered sidewall and a second portion having a second tapered sidewall, the width of the first tapered sidewall narrowing in a direction toward the second tapered sidewall, and the width of the second tapered sidewall widening in a direction toward the back interconnect structure. In an embodiment, the first contact also includes a third portion having a vertical sidewall. In an embodiment, the third portion extends from a surface of the first contact facing the back interconnect structure to the second portion, the second portion extends from the third portion to the first portion, and the first portion extends from the second portion to a surface of the first contact facing the first device layer. In an embodiment, the ratio of the width of the third portion to the average width of the first portion is 2 to 7. In an embodiment, the first transistor structure includes a gate structure, a semiconductor substrate extends between the gate structure and the first dielectric layer, the semiconductor substrate surrounds the first tapered sidewall, and the first dielectric layer surrounds the second tapered sidewall. In an embodiment, a surface of the first contact facing the backside interconnect structure and a surface of the first dielectric layer facing the backside interconnect structure are flush with each other. In an embodiment, the device further includes a power rail electrically coupled to the first contact, the first contact being electrically coupled to the source / drain region through a silicide region.

[0111] According to another embodiment, a device includes: a first substrate; a first device layer, above the first substrate, the first device layer including a first transistor structure; a first dielectric layer, on a back side of the first device layer; a first back side via, electrically coupled to a first source / drain region of the first transistor structure, the first back side via extending through the first substrate and the first dielectric layer, the first back side via having a first width in the first substrate and a second width in the first dielectric layer, the second width being greater than the first width; and a first interconnect structure, above the first dielectric layer and the first back side via, the first interconnect structure including a power rail electrically coupled to the first source / drain region through the first back side via. In an embodiment, a portion of the first back side via extending through the first dielectric layer includes a tapered sidewall having a width that widens in a direction toward the first interconnect structure. In an embodiment, a portion of the first back side via extending through the first substrate includes a tapered sidewall having a width that narrows in a direction toward the first interconnect structure. In an embodiment, a portion of the first back side via extending through the first dielectric layer includes a straight sidewall having a constant width. In an embodiment, the width of the tapered sidewall is 10 nm to 30 nm, and the constant width of the straight sidewall is 20 nm to 70 nm. In an embodiment, a ratio of the second width to the first width is 2 to 7.

[0112] According to yet another embodiment, a method includes: forming a first transistor on a first substrate; exposing a first epitaxial material, exposing the first epitaxial material including thinning the back side of the first substrate; epitaxially growing a second epitaxial material over the first epitaxial material; and replacing the second epitaxial material and the first epitaxial material with a back side via, the back side via being electrically coupled to a source / drain region of the first transistor. In an embodiment, the first epitaxial material and the second epitaxial material each include silicon germanium having a germanium atomic concentration of 20% to 60%. In an embodiment, the method further includes: etching a first recess in the first substrate; forming the first epitaxial material in the first recess; forming a third epitaxial material over the first epitaxial material; and forming the source / drain region over the third epitaxial material, the source / drain region filling a remaining portion of the first recess. In an embodiment, the first epitaxial material, the second epitaxial material, and the third epitaxial material include silicon germanium, the third epitaxial material having a lower germanium atomic concentration than the first epitaxial material and the second epitaxial material. In an embodiment, the first epitaxial material and the second epitaxial material each have a germanium atomic concentration of 20% to 60%, and the third epitaxial material has a germanium atomic concentration of 0% to 20%. In an embodiment, the second epitaxial material grows into an octagon in a cross-sectional view. In an embodiment, the method further includes forming a dielectric layer over the first substrate, the dielectric layer surrounding a first portion of the second epitaxial material, and a second portion of the second epitaxial material is exposed.

[0113] In some embodiments, a device includes: a first transistor structure in a first device layer; a front interconnect structure on the front side of the first device layer; a first dielectric layer on the back side of the first device layer; a first contact extending through the first dielectric layer to a source / drain region of the first transistor structure; and a backside interconnect structure on the back side of the first dielectric layer and the first contact, wherein the first contact includes a first portion having a first tapered sidewall and a second portion having a second tapered sidewall, wherein the width of the first tapered sidewall narrows in a direction toward the second tapered sidewall, and wherein the width of the second tapered sidewall widens in a direction toward the backside interconnect structure. In some embodiments, the first contact also includes a third portion having a vertical sidewall. In some embodiments, the third portion extends from a surface of the first contact facing the backside interconnect structure to the second portion, wherein the second portion extends from the third portion to the first portion, and wherein the first portion extends from the second portion to a surface of the first contact facing the first device layer. In some embodiments, the ratio of the width of the third portion to the average width of the first portion is 2 to 7. In some embodiments, the first transistor structure includes a gate structure, wherein a semiconductor substrate extends between the gate structure and the first dielectric layer, wherein the semiconductor substrate surrounds the first tapered sidewall, and wherein the first dielectric layer surrounds the second tapered sidewall. In some embodiments, a surface of the first contact facing the backside interconnect structure and a surface of the first dielectric layer facing the backside interconnect structure are flush with each other. In some embodiments, a power rail electrically coupled to the first contact is further included, wherein the first contact is electrically coupled to the source / drain region through a silicide region.

[0114] In some embodiments, a device includes: a first substrate; a first device layer, over the first substrate, the first device layer including a first transistor structure; a first dielectric layer, on a back side of the first device layer; a first back side via, electrically coupled to a first source / drain region of the first transistor structure, the first back side via extending through the first substrate and the first dielectric layer, the first back side via having a first width in the first substrate and a second width in the first dielectric layer, the second width being greater than the first width; and a first interconnect structure, over the first dielectric layer and the first back side via, the first interconnect structure including a power rail electrically coupled to the first source / drain region through the first back side via. In some embodiments, a portion of the first back side via extending through the first dielectric layer includes a tapered sidewall having a width that widens in a direction toward the first interconnect structure. In some embodiments, a portion of the first back side via extending through the first substrate includes a tapered sidewall having a width that narrows in a direction toward the first interconnect structure. In some embodiments, a portion of the first back side via extending through the first dielectric layer includes a straight sidewall having a constant width. In some embodiments, the width of the tapered sidewall is 10 nm to 30 nm, and wherein the constant width of the straight sidewall is 20 nm to 70 nm. In some embodiments, the ratio of the second width to the first width is 2 to 7.

[0115] In some embodiments, a method includes: forming a first transistor on a first substrate; exposing a first epitaxial material, wherein exposing the first epitaxial material includes thinning the back side of the first substrate; epitaxially growing a second epitaxial material over the first epitaxial material; and replacing the second epitaxial material and the first epitaxial material with a backside via, wherein the backside via is electrically coupled to a source / drain region of the first transistor. In some embodiments, the first epitaxial material and the second epitaxial material each include silicon germanium having a germanium atomic concentration of 20% to 60%. In some embodiments, it also includes: etching a first recess in the first substrate; forming the first epitaxial material in the first recess; forming a third epitaxial material over the first epitaxial material; and forming the source / drain region over the third epitaxial material, wherein the source / drain region fills a remaining portion of the first recess. In some embodiments, the first epitaxial material, the second epitaxial material, and the third epitaxial material include silicon germanium, wherein the third epitaxial material has a lower germanium atomic concentration than the first epitaxial material and the second epitaxial material. In some embodiments, the first epitaxial material and the second epitaxial material each have a germanium atomic concentration of 20% to 60%, and wherein the third epitaxial material has a germanium atomic concentration of 0% to 20%. In some embodiments, the second epitaxial material grows into an octagon in a cross-sectional view. In some embodiments, a dielectric layer is formed above the first substrate, the dielectric layer surrounds a first portion of the second epitaxial material, wherein a second portion of the second epitaxial material is exposed.

[0116] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a first transistor structure, in a first device layer, wherein the first device layer includes a first semiconductor substrate; a front-side interconnect structure on the front side of the first device layer; a first dielectric layer on a back side of the first device layer; a first contact extending through the first dielectric layer and the first semiconductor substrate to a source / drain region of the first transistor structure, wherein the first contact comprises a first continuous layer in physical contact with a sidewall of the first semiconductor substrate and a sidewall of the first dielectric layer; and A backside interconnect structure on the backside of the first dielectric layer and the first contact, wherein the first contact includes a first portion having a first tapered sidewall and a second portion having a second tapered sidewall, wherein a width of the first tapered sidewall narrows in a direction toward the second tapered sidewall, and wherein a width of the second tapered sidewall widens in a direction toward the backside interconnect structure.

2. The semiconductor device according to claim 1, wherein The first contact also includes a third portion having a vertical sidewall.

3. The semiconductor device according to claim 2, wherein: The third portion extends from a surface of the first contact facing the backside interconnect structure to the second portion, wherein the second portion extends from the third portion to the first portion, and wherein the first portion extends from the second portion to a surface of the first contact facing the first device layer.

4. The semiconductor device according to claim 2, wherein: A ratio of a width of the third portion to an average width of the first portion is 2 to 7.

5. The semiconductor device according to claim 1, wherein The first transistor structure includes a gate structure, wherein a first semiconductor substrate extends between the gate structure and the first dielectric layer, wherein the first semiconductor substrate surrounds the first tapered sidewall, and wherein the first dielectric layer surrounds the second tapered sidewall.

6. The semiconductor device according to claim 1, wherein A surface of the first contact facing the backside interconnect structure and a surface of the first dielectric layer facing the backside interconnect structure are flush with each other.

7. The semiconductor device of claim 1 , further comprising a power rail electrically coupled to the first contact, wherein: The first contact is electrically coupled to the source / drain region through a silicide region.

8. A semiconductor device comprising: a first substrate; a first device layer, above the first substrate, the first device layer comprising a first transistor structure; a first dielectric layer on a back side of the first device layer; a first backside via electrically coupled to a first source / drain region of the first transistor structure, the first backside via extending through the first substrate and the first dielectric layer, the first backside via having a first width in the first substrate and a second width in the first dielectric layer, the second width being greater than the first width, wherein the first backside via comprises a first continuous layer, wherein the first continuous layer is in physical contact with sidewalls of the first substrate and sidewalls of the first dielectric layer; and A first interconnect structure is over the first dielectric layer and the first backside via, the first interconnect structure including a power rail electrically coupled to the first source / drain region through the first backside via.

9. The semiconductor device according to claim 8, wherein: A portion of the first backside via extending through the first dielectric layer includes a tapered sidewall having a width that widens in a direction toward the first interconnect structure.

10. The semiconductor device according to claim 8, wherein A portion of the first backside via extending through the first substrate includes a tapered sidewall having a width that narrows in a direction toward the first interconnect structure.

11. The semiconductor device according to claim 10, wherein: The portion of the first backside via extending through the first dielectric layer includes a straight sidewall having a constant width.

12. The semiconductor device according to claim 11, wherein The width of the tapered sidewall is 10 nm to 30 nm, and wherein the constant width of the straight sidewall is 20 nm to 70 nm.

13. The semiconductor device according to claim 8, wherein: A ratio of the second width to the first width is 2 to 7.

14. A method of forming a semiconductor device, comprising: forming a first transistor on a first substrate; exposing a first epitaxial material, wherein exposing the first epitaxial material comprises thinning a back side of the first substrate; epitaxially growing a second epitaxial material over the first epitaxial material; and The second epitaxial material and the first epitaxial material are replaced with backside vias electrically coupled to source / drain regions of the first transistor.

15. The method according to claim 14, wherein: The first epitaxial material and the second epitaxial material each include silicon germanium having a germanium atomic concentration of 20% to 60%.

16. The method according to claim 14, further comprising: etching a first groove in the first substrate; forming the first epitaxial material in the first recess; forming a third epitaxial material over the first epitaxial material; as well as The source / drain region is formed above the third epitaxial material, and the source / drain region fills a remaining portion of the first groove.

17. The method according to claim 16, wherein: The first epitaxial material, the second epitaxial material, and the third epitaxial material include silicon germanium, wherein the third epitaxial material has a lower concentration of germanium atoms than the first epitaxial material and the second epitaxial material.

18. The method according to claim 17, wherein: The first epitaxial material and the second epitaxial material each have a germanium atomic concentration of 20% to 60%, and wherein the third epitaxial material has a germanium atomic concentration of 0% to 20%.

19. The method according to claim 14, wherein: The second epitaxial material grows into an octagon in a cross-sectional view.

20. The method of claim 14, further comprising forming a dielectric layer over the first substrate, the dielectric layer surrounding a first portion of the second epitaxial material, wherein A second portion of the second epitaxial material is exposed.

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