Semiconductor device and method for forming the same

Abstract

In one embodiment, a semiconductor device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source / drain region, including: a main layer in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper facet surface and a lower facet surface, the upper facet surface and the lower facet surface are respectively raised from the corresponding surfaces of the first fin and the second fin; a semiconductor contact etch stop layer (CESL) contacting the upper facet surface and the lower facet surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material. Embodiments of the present invention also relate to methods of forming semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of forming the same. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of materials on a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other issues arise that should be addressed. Summary of the invention

[0004] According to one aspect of an embodiment of the present invention, a method for forming a semiconductor device is provided, comprising: depositing an interlayer dielectric (ILD) layer on an epitaxial source / drain region, the epitaxial source / drain region comprising a main layer, a semiconductor contact etch stop layer (CESL) on the main layer, and a dummy layer on the semiconductor CESL; exposing a first portion of the dummy layer through the ILD layer; removing the first portion of the dummy layer through a first etching process to expose a second portion of the semiconductor CESL, the first etching process etching the dummy layer at a greater rate than the semiconductor CESL; removing the second portion of the semiconductor CESL to expose a third portion of the main layer; and forming a first source / drain contact on the third portion of the main layer.

[0005] According to another aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source / drain region, comprising: a main layer located in the first fin and the second fin, the main layer comprising a first semiconductor material, the main layer having an upper facet surface and a lower facet surface, the upper facet surface and the lower facet surface being respectively raised from corresponding surfaces of the first fin and the second fin; and a semiconductor contact etch stop layer (CESL) contacting the upper facet surface and the lower facet surface of the main layer, the semiconductor CESL comprising a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

[0006] According to another aspect of an embodiment of the present invention, a semiconductor device is provided, comprising: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source / drain region comprising: a main layer located in the first fin and the second fin, the main layer comprising a doped semiconductor material; a first contact etch stop layer (CESL) located on the main layer, the first CESL comprising an undoped semiconductor material; and a termination layer located on the first CESL, the termination layer comprising a doped semiconductor material; a second CESL located on the termination layer, the second CESL comprising a dielectric material; an interlayer dielectric (ILD) layer located on the second CESL; and a source / drain contact extending through the ILD layer, the second CESL, the termination layer and the first CESL, the source / drain contact contacting the main layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 An example of a FinFET according to some embodiments is shown in a three-dimensional view.

[0009] Figure 2 and Figure 3 is a three-dimensional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0010] FIG. 4A to FIG. 12B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments.

[0011] FIG. 13A to FIG. 16B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments.

[0012] FIG. 17A to FIG. 21B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments.

[0013] FIG. 22A to FIG. 25B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0016] According to some embodiments, a multi-layer epitaxial source / drain region is grown with an intermediate epitaxial layer that can be used as a semiconductor contact etch stop layer (CESL) during subsequent processing. The semiconductor CESL can be used to protect the underlying epitaxial layer and control etching losses during subsequent source / drain contact formation. Therefore, the performance of the resulting FinFET can be improved by increasing the contact area of ​​the source / drain contacts and by reducing etching losses of the epitaxial source / drain regions.

[0017] Figure 1 An example of a simplified fin field effect transistor (FinFET) is shown in a three-dimensional view according to some embodiments. For clarity, certain other components of the FinFET (described below) are omitted. The FinFETs shown can be electrically connected or coupled in a manner such as to operate as one transistor or multiple transistors (e.g., two transistors).

[0018] The FinFET includes a fin 52 extending from a substrate 50. A shallow trench isolation (STI) region 56 is disposed above the substrate 50, and the fin 52 protrudes above and between adjacent STI regions 56. Although the STI regions 56 are described, as used herein, the term "substrate" is shown as being used to refer only to a semiconductor substrate or a semiconductor substrate including an isolation region. In addition, although the fin 52 is shown as a single continuous material of the substrate 50, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this article, the fin 52 refers to a portion extending between adjacent STI regions 56.

[0019] The gate dielectric 82 is along the sidewalls and above the top surface of the fin 52, and the gate electrode 84 is above the gate dielectric 82. The source / drain region 70 is disposed on the opposite side of the fin 52 relative to the gate dielectric 82. The gate spacer 66 separates the source / drain region 70 from the gate dielectric 82 and the gate electrode 84. One or more interlayer dielectric (ILD) layers (not shown, discussed further below) are disposed between the gate dielectric 82 and the gate 84. The source / drain region 70 and the gate electrode 84 form contacts to the source / drain region 70 and the gate electrode 84 through the ILD layer (not shown, discussed further below). In embodiments where multiple transistors are formed, the source / drain region 70 can be shared between the individual transistors. In embodiments where a transistor is formed from multiple fins 52, adjacent source / drain regions 70 can be electrically connected, such as by epitaxially growing the source / drain regions 70 together, or by coupling the source / drain regions 70 with the same source / drain contact.

[0020] Figure 1 Several reference cross sections are further shown. Cross section AA is along the longitudinal axis of the fin 52 and in the direction of current flow, for example, between the source / drain regions 70 of the FinFET. Cross section BB is perpendicular to cross section AA and extends through the source / drain regions 70 of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0021] Figure 2 and Figure 33D view of an intermediate stage in the fabrication of a FinFET according to some embodiments. A substrate 50 is processed to form a FinFET. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type impurities) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0022] The substrate 50 has a region 50N and a region 50P. The region 50N can be used to form an n-type device, such as an NMOS transistor, such as an n-type FinFET. The region 50P can be used to form a p-type device, such as a PMOS transistor, such as a p-type FinFET. The region 50N can be physically separated from the region 50P, and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the region 50N and the region 50P.

[0023] exist Figure 2 In the embodiment of the present invention, fins 52 are formed to extend from substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 may be formed in substrate 50 by etching trenches in substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching may be anisotropic.

[0024] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single direct photolithography method. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

[0025] STI regions 56 are formed above substrate 50 and between adjacent fins 52. As an example of forming STI regions 56, an insulating material is formed above the intermediate structure. The insulating material may be an oxide, nitride, or the like, such as silicon oxide, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., deposition of a material based on chemical vapor deposition (CVD) in a remote plasma system, and post-curing to convert it into another material, such as an oxide), or the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In one embodiment, the insulating material is formed so that excess insulating material covers the fins 52. Some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. Thereafter, a filling material such as the above-mentioned filling material may be formed on the liner. A removal process is applied to the insulating material to remove excess insulating material above the fins 52. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), an etch back process, a combination thereof, etc. The planarization process exposes the fin 52 so that after the planarization process is completed, the top surface of the fin 52 and the insulating material are flat. The insulating material is then recessed, and the remaining portion of the insulating material forms the STI region 56. The insulating material is recessed so that the upper portion of the fin 52 in the region 50N and the region 50P protrudes from between the adjacent STI regions 56. The recessed exposed portion of the fin 52 extends above the top surface of the STI region 56. The exposed portion of the fin 52 includes a region that will become a channel region.

[0026] In addition, the top surface of STI region 56 can have a flat surface, a convex surface, a concave surface (e.g., recessed) or a combination thereof as shown. The top surface of STI region 56 can be formed to be flat, convex and / or concave by appropriate etching. STI region 56 can be recessed using an acceptable etching process, such as an etching process that is selective to the material of the insulating material (e.g., etching the material of the insulating material at a faster rate than the material of fin 52). For example, the chemical oxide can be removed by an appropriate etching process using an acid such as dilute hydrofluoric acid (dHF).

[0027] The above process is only one example of how the fin 52 is formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure can be epitaxially grown in the groove, and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. In addition, in some embodiments, a heteroepitaxial structure can be used for the fin 52. For example, after the insulating material of the STI region 56 is planarized with the fin 52, the fin 52 can be recessed, and the material is different from the fin 52 epitaxially grown above the recessed fin 52. In such an embodiment, the fin 52 includes a recessed material and an epitaxially grown material arranged above the recessed material. In another embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and a groove can be etched through the dielectric layer. Then a heteroepitaxial structure can be epitaxially grown in the groove using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments, homoepitaxial or heteroepitaxial structures may be doped in situ during the growth process if the material is epitaxially grown, which may eliminate both before and after implantation, although in situ doping and implantation doping may be used together.

[0028] In addition, it may be advantageous to epitaxially grow a different material in region 50N (eg, NMOS region) than in region 50P (eg, PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon germanium (SiGe). 1-x , where x can be in the range of 0 to 1), silicon carbide, pure germanium or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0029] In addition, appropriate wells (not shown) may be formed in fin 52 and / or substrate 50. In some embodiments, a P-well may be formed in region 50N, and an N-well may be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.

[0030] In embodiments with different well types, a photoresist or other mask (not shown) may be used to implement different implantation steps for region 50N and region 50P. For example, a photoresist may be formed over fin 52 and STI region 56 in region 50N. The photoresist is patterned to expose region 50P of substrate 50, such as a PMOS region. The photoresist may be formed using a spin coating technique and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P, and the photoresist may be used as a mask to substantially prevent n-type impurities from being implanted into region 50N, such as an NMOS region. The n-type impurity may be phosphorus, arsenic, antimony, etc., implanted into the region at a concentration equal to or less than 10 18 cm -3 , for example about 10 17 cm -3 to about 10 18 cm -3 After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0031] After implanting region 50P, a photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist may be formed by using a spin coating technique and may be patterned using an acceptable photolithography technique. Once the photoresist is patterned, a p-type impurity implantation may be performed in region 50N, and the photoresist may be used as a mask to substantially prevent the p-type impurity from being implanted into region 50P, such as a PMOS region. The p-type impurity may be boron, BF2, indium, etc., implanted into the region, with a concentration equal to or less than 10 18 cm -3 , for example about 10 17 cm -3 to about 10 18 cm -3 After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

[0032] After implanting regions 50N and 50P, an anneal may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the grown material of the epitaxial fins may be doped in situ during growth, which may eliminate implantation, although in situ and implantation doping may be used together.

[0033] exist Figure 3 In the embodiment, a dummy gate dielectric 60 is formed over the fin 52, and a dummy gate electrode 62 is formed over the dummy gate dielectric 60. The dummy gate dielectric 60 and the dummy gate electrode 62 may be collectively referred to as a dummy gate stack. The dummy gate stack extends along the sidewalls and top surface of the fin 52.

[0034] As an example of forming a pseudo gate dielectric 60 and a pseudo gate electrode 62, a pseudo dielectric layer is formed on the fin 52. The pseudo dielectric layer may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to an acceptable technique. A pseudo gate layer is formed above the pseudo dielectric layer, and a mask layer is formed above the pseudo gate layer. The pseudo gate layer may be deposited above the pseudo dielectric layer and then planarized, for example, by CMP. The mask layer may be deposited on the pseudo gate layer. The pseudo gate layer may be a conductive or non-conductive material, such as amorphous silicon, polysilicon, polySiGe, metal nitride, metal silicide, metal oxide, metal, etc. The pseudo gate layer may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art and used to deposit conductive materials. The pseudo gate layer may be made of other materials having high etching selectivity to etching of the STI region 56. The mask layer may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer and a single mask layer are formed across region 50N and region 50P. In some embodiments, the dummy dielectric layer may be deposited so that the dummy dielectric layer covers the STI region 56 extending between the dummy gate layer and the STI region 56. The mask layer is then patterned using acceptable photolithography and etching techniques to form a mask 64. The pattern of mask 64 is then transferred to the dummy gate layer by acceptable etching techniques to form a dummy gate electrode 62. The pattern of mask 64 is further transferred to the dummy dielectric layer to form a dummy gate dielectric 60. The dummy gate electrode 62 covers each channel region 58 of the fin 52 (see FIG. 2 ). Figure 4A The dummy gate electrode 62 may also have a length direction substantially perpendicular to the length direction of each fin 52 (within process limitations).

[0035] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices such as planar FETs.

[0036] FIG. 4A to FIG. 12B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A and Fig. 12A It is along Figure 1 Reference section AA in FIG. 1 shows a cross-sectional view, except that only one source / drain region 70 is shown. Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B and Fig. 12B is along Figure 1 Reference section BB in FIG. 5 shows a cross-sectional view, except that only two fins 52 are shown.

[0037] exist Figure 4A and Figure 4B In the embodiment of the present invention, a gate spacer 66 is formed on the exposed surface of the pseudo gate electrode 62, the mask 64 and / or the fin 52. The gate spacer 66 can be formed by conformally depositing one or more layers of insulating material, and then etching the insulating material. The insulating material of the gate spacer 66 can be silicon nitride, silicon carbonitride, silicon carbon nitride oxide, a combination thereof, and the like, and can be formed by a conformal deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and the like. In some embodiments, the gate spacer 66 is formed by one or more silicon oxycarbon nitride layers (such as two silicon oxycarbon nitride layers). Once formed, the insulating material can be etched by, for example, wet etching to form the gate spacer 66. The etching of the gate spacer 66 can be anisotropic. After etching, the gate spacer 66 can have curved sidewalls (as shown) or can have straight sidewalls (not shown).

[0038] Prior to or during the formation of gate spacers 66, implantation for lightly doped source / drain (LDD) regions 68 may be performed. In embodiments having different device types, similar to the implantation discussed, a mask such as a photoresist may be formed over region 50N while exposing region 50P, and an appropriate type (e.g., p-type) impurity may be implanted into exposed fins 52 in region 50P. The mask may then be removed. Subsequently, a mask such as a photoresist may be formed over region 50P while exposing region 50N, and an appropriate type (e.g., n-type) impurity may be implanted into exposed fins 52 in region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source / drain regions may have a thickness of approximately 10 15 cm -3 to about 10 16 cm -3 Annealing can be used to activate the implanted impurities.

[0039] Then, epitaxial source / drain regions 70 are formed in the fin 52. The epitaxial source / drain regions 70 are formed in the fin 52 so that each dummy gate electrode 62 is disposed between pairs of adjacent epitaxial source / drain regions 70 of the epitaxial source / drain regions. The epitaxial source / drain regions 70 extend into the LDD regions 68 and may also penetrate the LDD regions 68. In some embodiments, gate spacers 66 are used to offset the epitaxial source / drain regions 70 from the dummy gate electrodes 62 by an appropriate lateral distance through the dummy gate electrodes so that the epitaxial source / drain regions 70 do not short-circuit the gates of the subsequently formed FinFETs. The epitaxial source / drain regions 70 may be formed to apply stress in the respective channel regions 58, thereby improving performance.

[0040] The epitaxial source / drain regions 70 in the region 50N (e.g., NMOS region) may be formed by masking the region 50P, such as a PMOS region, and etching the source / drain regions of the fin 52 in the region 50N. A recess 52R is thereby formed in the fin 52. The epitaxial source / drain regions 70 in the region 50N are then epitaxially grown in the recess 52R. The epitaxial source / drain regions 70 in the region 50N may have faceted surfaces that are elevated from the respective surfaces of the fin 52 (discussed further below).

[0041] The epitaxial source / drain regions 70 in the region 50P (e.g., the PMOS region) can be formed by masking the region 50N, such as the NMOS region, and etching the source / drain regions of the fin 52 in the region 50P. Thus, a recess 52R is formed in the fin 52. Then, the epitaxial source / drain regions 70 in the region 50P are epitaxially grown in the recess 52R. The epitaxial source / drain regions 70 in the region 50P can also have faceted surfaces that are elevated from the corresponding surfaces of the fin 52 (discussed further below).

[0042] Each epitaxial source / drain region 70 includes functional layers 70A and 70B, semiconductor CESL 70C, dummy layer 70D and (optionally) termination layer 70E, each of which is a semiconductor material layer grown by an acceptable epitaxial growth process. Functional layers 70A and 70B are formed of materials suitable for the desired FinFET and are doped. Portions of semiconductor CESL 70C and dummy layer 70D will be removed during subsequent processes so that subsequently formed source / drain contacts can extend deeply into epitaxial source / drain region 70 and contact functional layer 70B. Termination layer 70E is a highly doped layer that protects epitaxial source / drain region 70 from oxidation during subsequent processes. Each of these layers will be discussed further below.

[0043] Functional layers 70A and 70B are formed of any acceptable doped semiconductor material, such as suitable for n-type or p-type FinFETs. For example, if the fins 52 in region 50N are silicon, the functional layers 70A and 70B in region 50N may include materials that apply tensile strain in the channel region 58, such as silicon, phosphorus-doped silicon (e.g., silicon phosphide), silicon carbide, phosphorus-doped silicon carbide, etc. Similarly, if the fins 52 in region 50P are silicon, the functional layers 70A and 70B in region 50P may include materials that apply compressive strain in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, etc. The functional layers 70A and 70B are in-situ doped with n-type and / or p-type impurities during growth to form source / drain regions. The n-type and / or p-type impurities used for the source / drain regions may be any of the impurities previously discussed. The functional layers 70A and 70B may be graded or non-graded, and each functional layer 70A and 70B may include multiple sub-layers, for example, 2-4 sub-layers.

[0044] Functional layer 70A grows along the sidewalls of recess 52R, and functional layer 70B grows on functional layer 70A. Functional layer 70A may also be referred to as a liner layer, and functional layer 70B may also be referred to as a main layer. Functional layer 70A may be grown to a low dopant concentration and a small thickness, which may promote adhesion to fin 52. For example, functional layer 70A may have a thickness of less than about 10 19 cm -3 The functional layer 70B is grown with a high dopant concentration and a large thickness to provide sufficient majority carriers for the resulting FinFET. For example, the functional layer 70B may have a dopant concentration of about 10 nm to about 18 nm. 19 cm -3 to about 10 21 cm -3 % to about 30 atomic %, and a thickness in the range of about 35 atomic % to about 70 atomic %. In embodiments where functional layers 70A and 70B include silicon germanium, functional layer 70A may have a lower germanium concentration than functional layer 70B, which may also promote adhesion to fin 52. For example, functional layer 70A may have a germanium concentration in the range of about 15 atomic % to about 30 atomic %, and functional layer 70B may have a germanium concentration in the range of about 35 atomic % to about 70 atomic %.

[0045] Although two functional layers 70A and 70B are shown in each epitaxial source / drain region 70, it should be understood that the epitaxial source / drain region 70 may include any number of functional layers. For example, more than two functional layers may be included in each epitaxial source / drain region 70. Likewise, the liner layer may be omitted, and only one functional layer (e.g., a main layer) may be included in each epitaxial source / drain region 70.

[0046] The semiconductor CESL 70C and the dummy layer 70D will be partially removed in subsequent processing and may not be doped. During the subsequent contact etching process, the semiconductor CESL 70C and the dummy layer 70D will be etched to form a recess in the epitaxial source / drain region 70. The semiconductor CESL 70C and the dummy layer 70D may be formed of different materials, and may be formed of the following materials: a material different from the functional layers 70A and 70B and the termination layer 70E. With respect to the contact etching process, the semiconductor CESL 70C is formed of a material having a high etching selectivity with the material of the dummy layer 70D and the gate spacer 66. Therefore, the semiconductor CESL 70C protects the underlying epitaxial layer during the subsequent contact etching process for removing the dummy layer 70D. The semiconductor CESL 70C may be formed of an undoped semiconductor material, such as silicon, silicon nitride, silicon carbonitride, silicon oxycarbide, or silicon carbide. In some embodiments, the semiconductor CESL 70C is formed of silicon, and the dummy layer 70D is formed of silicon germanium, wherein the silicon is undoped and the silicon germanium has a high germanium concentration, for example, a germanium concentration of about 60 atomic % to about 65 atomic %. In some embodiments, the semiconductor CESL 70C is formed of silicon, and the dummy layer 70D is formed of aluminum oxide. The semiconductor CESL 70C is thick enough to provide protection for the underlying epitaxial layer. For example, the semiconductor CESL 70C may have a thickness of at least 1 nm, for example, a thickness in the range of about 1 nm to about 10 nm. The dummy layer 70D is thick enough so that when the dummy layer 70D is etched, the subsequently formed source / drain contacts may penetrate deep into the epitaxial source / drain region 70. For example, the dummy layer 70D may have a thickness in the range of about 1 nm to about 10 nm.

[0047] Termination layer 70E is formed of any suitable material, such as suitable for n-type or p-type FinFETs. Termination layer 70E can be formed of similar materials as the underlying functional layers 70A and 70B. For example, functional layers 70A and 70B and termination layer 70E in region 50N can be formed of phosphorus-doped silicon, and functional layers 70A and 70B and termination layer 70E in region 50P can be formed of boron-doped silicon germanium. Termination layer 70E is grown to a small thickness and low dopant concentration, which can help protect the underlying epitaxial layers from oxidation during subsequent contact etching processes. For example, termination layer 70E can have a thickness of up to about 10 21 cm -3 The end layer 70E may have a dopant concentration of about 100 nm and a thickness in the range of about 1 nm to about 20 nm. In embodiments where the end layer 70E includes silicon germanium, the end layer 70E may have a lower germanium concentration than the functional layer 70B. For example, the end layer 70E may have a germanium concentration of up to about 35 atomic %.

[0048] As a result of the epitaxial process used to form epitaxial source / drain regions 70 in regions 50N and 50P, the upper surfaces of the epitaxial source / drain regions have facets that extend laterally outward beyond the sidewalls of the fins 52. These facets cause some layers of adjacent epitaxial source / drain regions 70 of the same FinFET to merge. Specifically, adjacent functional layers 70B, semiconductor CESL 70C, dummy layers 70D, and termination layers 70E (when formed) merge. In the illustrated embodiment, gate spacers 66 are formed to cover portions of the sidewalls of the fins 52 that extend over the STI regions 56, thereby preventing epitaxial growth. In some other embodiments, the etch used to form the gate spacers 66 can be adjusted to remove the spacer material to allow the region of epitaxial growth to extend to the surface of the STI regions 56.

[0049] The upper surface of the functional layer 70B defines an upper basin 72U that is laterally disposed between the fins 52. A lower basin 72L is defined on the lower surface of the functional layer 70B, which is also laterally disposed between the fins 52. The lower basin 72L faces the substrate 50, while the upper basin 72U faces away from the substrate 50. A semiconductor CESL 70C, a dummy layer 70D, and an end layer 70E are formed to fill the upper basin 72U. Specifically, the semiconductor CESL 70C and the dummy layer 70D are conformally formed in the upper basin 72U, and the end layer 70E (when present) fills the remaining portion of the upper basin 72U. Some epitaxial layers may not be formed in the lower basin 72L. Specifically, the semiconductor CESL 70C, the dummy layer 70D, and the end layer 70E are not formed in the lower basin 72L.

[0050] As an example of forming an epitaxial source / drain region 70 with a termination layer 70E, multiple epitaxial growth steps and etch-back steps may be performed. Specifically, a functional layer 70A is grown on the sidewalls of the recess 52R, a functional layer 70B is grown on the functional layer 70A, a semiconductor CESL 70C is grown on the functional layer 70B, and a dummy layer 70D is grown on the semiconductor CESL. An etch-back process is then performed to flatten the top surfaces of the layers 70B, 70C, and 70D. After the etch-back process, a termination layer 70E is grown on the horizontal surfaces of the layers 70B, 70C, and 70D. The termination layer 70E may thus cover the underlying layers 70B, 70C, and 70D and may fill the upper basin 72U, so that the final top surface of the epitaxial source / drain region 70 is flat or concave.

[0051] Since the epitaxial layers are grown in the recess 52R, they are Figure 4A 52 has a conformal shape in the cross-section shown (eg, in a plane extending parallel to fin 52). However, because the surface of epitaxial source / drain regions 70 is faceted, Figure 4BIn the cross section shown (eg, in a plane extending perpendicular to the fin 52), the epitaxial layers are elevated from the respective surfaces of the fin 52. For example, the semiconductor CESL 70C and the dummy layer 70D are grown so that they are Figure 4B The cross section shown is not Figure 4A The cross section shown extends over the uppermost surface of the functional layer 70B. It should be understood that a feature that does not extend through the epitaxial layer in one cross section may still extend through the epitaxial layer in another cross section.

[0052] Then, a first ILD layer 76 is deposited over the various components. The first ILD layer 76 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD) or FCVD. The dielectric material may include silicate glass, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a dielectric CESL 74 is disposed between the first ILD layer 76 and the epitaxial source / drain regions 70, the gate spacer 66, and the mask 64. The dielectric CESL 74 may be formed of a dielectric material having an etch rate different from that of the material of the first ILD layer 76 above, such as nitride, silicon oxide, silicon oxynitride, aluminum oxide, etc., and may be formed by an appropriate deposition process.

[0053] exist Figure 5A and Figure 5B In the process, a planarization process such as CMP may be performed to make the upper surface of the first ILD layer 76 flush with the upper surface of the dummy gate electrode 62 or the mask 64. The mask 64 on the dummy gate electrode 62 and the portion of the gate spacer 66 along the sidewall of the mask 64 may also be removed. After the planarization process, the dummy gate electrode 62, the gate spacer 66, and the top surface of the first ILD layer 76 are planar. Therefore, the top surface of the dummy gate electrode 62 is exposed through the first ILD layer 76. In some embodiments, the mask 64 may be retained, in which case the planarization process makes the top surface of the first ILD layer 76 flush with the top surface of the mask 64.

[0054] exist Fig. 6A and Figure 6B In the embodiment of the present invention, the dummy gate electrode 62 and the optional dummy gate dielectric 60 are removed and replaced by a replacement gate. The replacement gate includes a gate dielectric 82 and a gate electrode 84. The replacement gate may also be referred to as a "gate stack" or a "metal gate". The replacement gate extends along the sidewalls of the channel region 58 of the fin 52.

[0055] As an example of forming a replacement gate, the dummy gate electrode 62 and the mask 64 (if present) are removed in one or more etching steps to form a recess. The portion of the dummy gate dielectric 60 in the recess may also be removed. In some embodiments (not shown), only the dummy gate electrode 62 is removed, and the dummy gate dielectric 60 is retained and exposed by the recess. For example, the dummy gate dielectric 60 can be removed from the recess in the first region of the die (e.g., the core logic region) and retained in the recess in the second region of the die (e.g., the input / output region). In some embodiments, the dummy gate electrode 62 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively removes the material of the dummy gate electrode 62 at a greater rate than the material of the first ILD layer 76 and the gate spacer 66. Specifically, the channel region 58 is exposed by the recess. Each channel region 58 is disposed between pairs of adjacent epitaxial source / drain regions 70. During removal, when etching the dummy gate electrode 62, the dummy gate dielectric 60 can be used as an etch stop layer. The dummy gate dielectric 60 may then be optionally removed after the dummy gate electrode 62 is removed. After removal, the gate dielectric 82 is conformally deposited in the recess, for example, on the top surface and sidewalls of the fin 52 and on the recess 52. The gate dielectric 82 may also be formed on the top surface of the first ILD layer 76. In some embodiments, the gate dielectric 82 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric 82 includes a high-k dielectric material, and in these embodiments, the gate dielectric 82 may have a k value greater than about 7.0 and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation method of the gate dielectric 82 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. In embodiments where a portion of the dummy gate dielectric 60 remains in the recess, the gate dielectric 82 includes the material of the dummy gate dielectric 60 (e.g., silicon oxide). The gate electrodes 84 are deposited on the gate dielectric 82, respectively, and fill the rest of the recess. The gate electrode 84 may include a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multiple layers. For example, although a single-layer gate electrode 84 is shown, each gate electrode 84 may include any number of liner layers, any number of work function adjustment layers, and fill materials. After filling the gate electrode 84, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric 82 and the material of the gate electrode 84 that are above the top surface of the first ILD layer 76. The remaining portions of the gate dielectric 82 and the material of the gate electrode 84 thus form a replacement gate for the resulting FinFET.

[0056] A gate mask 86 is then formed over the replacement gate. The replacement gate (e.g., gate dielectric 82 and gate electrode 84) may be recessed, and the recess may be filled with one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc. A planarization process may be performed to remove excess portions of the dielectric material extending over the first ILD layer 76. The gate mask 86 includes portions of the dielectric material remaining in the recess.

[0057] exist Fig. 7A and Figure 7B , portions of the first ILD layer 76 and the dielectric CESL 74 are removed to form a contact opening 90. The contact opening 90 exposes the epitaxial source / drain region 70, e.g., the termination layer 70E. An acceptable etching process that is selective to the first ILD layer 76 and does not remove the gate spacers 66 or the gate mask 86 can be performed to form the contact opening 90. Another etching process can then be performed to remove the dielectric CESL 74. In some embodiments, the removal is an anisotropic etch, and residual vertical portions of the dielectric CESL 74 remain along the gate spacers 66. In some embodiments, a small residual horizontal portion of the dielectric CESL 74 can remain along the functional layer 70B. Such a residual horizontal portion (not shown) can have a small width, e.g., less than 1 nm, and can protect the functional layer 70B (with respect to FIG. 1 ) during a subsequent etch. Fig. 8A and Figure 8B discuss).

[0058] The etching process may be performed using an etching mask 92 such as a photoresist having a pattern of contact openings 90. In this embodiment, the etching mask 92 has a pattern of slit openings. The slit openings are strips perpendicular to and overlapping the gate electrode 84 and strips parallel to and overlapping the fin 52. In this way, the fin 52 is removed. Fig. 7A All of the first ILD layer 76 in the cross section shown is removed to form contact openings 90. In other embodiments (discussed further below), the etch mask 92 may have other types of openings to form contact openings 90 of different sizes. After the etching process, the etch mask 92 may be removed, for example, by an acceptable ashing process.

[0059] exist Fig. 8A and Figure 8BIn the embodiment of the present invention, the exposed portion of the end layer 70E is removed to expose a portion of the dummy layer 70D. The exposed portion of the dummy layer 70D is then removed to expose a portion of the semiconductor CESL 70C. The contact opening 90 is thus enlarged. The removal may be performed by one or more etching steps. The etching may be any acceptable etching process that is selective to the dummy layer 70D and the end layer 70E, such as etching the material of the dummy layer 70D and the end layer 70E at a greater rate than the material of the semiconductor CESL 70C. For example, the etching rate of the material of the dummy layer 70D and the end layer 70E may be about 10 times to about 2000 times the etching rate of the material of the semiconductor CESL 70C relative to the etching process. The etching process may be anisotropic.

[0060] In embodiments where the semiconductor CESL 70C is formed of silicon and the dummy layer 70D is formed of silicon germanium, the etching process may be an anisotropic wet etching using one of several etching solutions. In some embodiments, the etching solution is a mixture of HCL, H2O2, and water. In some embodiments, the etching solution is a mixture of deionized water (DIW) and ozone, such as ozonated DIW. In some embodiments, the etching solution is a mixture of H2SO4 and H2O2. In such embodiments, the etching process may be performed for a duration of about 5 seconds to about 300 seconds.

[0061] In an embodiment where semiconductor CESL 70C is formed of silicon and dummy layer 70D is formed of aluminum oxide, the etching process may be an anisotropic wet etching performed using ammonia (NH 3 ). In such an embodiment, the etching process may be performed for a duration ranging from about 5 seconds to about 200 seconds.

[0062] exist Fig. 9A and Fig. 9B In the embodiment where the semiconductor CESL 70C is silicon, the dielectric layer 94 may be silicon oxide. Unexposed portions of the semiconductor CESL 70C, such as portions not exposed by the contact opening 90, are not oxidized. In some embodiments, the oxidation may be performed by natural oxidation, such as by exposing the structure to an oxygen-containing atmosphere. In some embodiments, the oxidation may be performed by a wet oxygen treatment process, such as by exposing the structure to ozonated deionized water or hydrogen peroxide. In some embodiments, the oxidation may be performed by a dry oxygen treatment process, such as by exposing the structure to oxygen at an elevated temperature, such as a temperature in the range of about 80° C. to about 500° C. The dry oxygen treatment process may be performed with a plasma to damage the surface of the semiconductor CESL 70C and thereby accelerate the oxidation. For example, in a dry oxygen treatment process, a plasma may be generated with argon and oxygen.

[0063] exist Fig. 10A and Fig. 10B In the process, the dielectric layer 94 is removed so that the contact opening 90 is enlarged. After removal, a portion of the functional layer 70B is exposed, and in particular, the upper basin 72U is exposed. A source / drain contact will then be formed in the upper basin 72U, allowing the source / drain contact to contact a large surface area of ​​the functional layer 70B, which can reduce the resistance of the source / drain contact. By exposing the upper basin 72U using an additional CESL (e.g., semiconductor CESL 70C), the amount of etching loss of the functional layer 70B can be reduced. The functional layer 70B has a high dopant concentration, so reducing its loss can improve the performance of the resulting FinFET. In addition, the use of timed etching can be avoided, thereby avoiding over-etching of the functional layer 70B and under-etching of the dielectric CESL 74.

[0064] The dielectric layer 94 may be removed by any acceptable oxide removal or cleaning process. In embodiments where the dielectric layer 94 is silicon oxide, the oxide removal process is a wet etch or dry etch performed with nitrogen trifluoride (NF3), ammonia (NH3), dilute hydrofluoric acid (dHF) acid, a fluorocarbon (e.g., methyl fluoride (CH3F)), tetrafluoromethane (CF4), etc.), or a combination thereof. For example, the etch may be a wet etch performed with dHF for a duration in the range of about 10 seconds to about 30 seconds. The etch does not remove unoxidized portions of the semiconductor CESL 70C. The etch is selective to the dielectric layer 94, e.g., etches the material of the dielectric layer 94 at a greater rate than the material of the functional layer 70B. For example, the etch rate of the material of the dielectric layer 94 may be about 10 times to about 2000 times the etch rate of the material of the functional layer 70B relative to the etch process.

[0065] After etching, the upper portion of the contact opening 90 (e.g., the portion extending through the dielectric CESL 74 and the first ILD layer 76) has a width W1, which may be in the range of about 8 nm and about 20 nm, and the lower portion of the contact opening 90 (e.g., the portion extending through the dummy layer 70D and extending into the epitaxial source / drain region 70) has a width W2 in the range of about 6 nm to about 19 nm. The width W1 is greater than the width W2. For example, the width W1 may be about 3 nm to about 4 nm greater than the width W2, and the ratio of W1:W2 may be in the range of about 1 to about 1.5. The widths W1 and W2 may be in the range of about 1.5 to about 2.5 nm. Fig. 10A Measured in the cross section shown, although Fig. 10B The cross section shown shows the first ILD layer 76 and the dummy layer 70D. Due to the conformal nature of epitaxy, the semiconductor CESL 70C and the dummy layer 70D (see FIGS. 4A and Figure 4B) may have a continuously decreasing width in a direction D1 extending from the top surface to the bottom surface of the epitaxial source / drain region 70. The width W2 of the epitaxial source / drain region 70 may continuously decrease along the width direction. In other words, the width W2 may continuously decrease in the direction D1.

[0066] exist Fig.11A and Fig. 11B In the embodiment of the present invention, a lower source / drain contact 98 is formed in the contact opening 90. A liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the contact opening 90. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, ruthenium, aluminum, copper, silver, gold, nickel, etc., and may be formed by deposition, plating, etc. A planarization process such as CMP may be performed to remove excess material from the top surface of the first ILD layer 76. The remaining liner and conductive material form the lower source / drain contact 98. The lower source / drain contact 98 is physically and electrically coupled to the epitaxial source / drain region 70. After formation, the upper portion of the lower source / drain contact 98 is surrounded by the dielectric CESL 74, and the middle portion of the lower source / drain contact 98 is surrounded by the termination layer 70E. The lower portion of the lower source / drain contact 98 is surrounded by the functional layer 70B. Silicide 96 may be disposed between the epitaxial source / drain region 70 and the lower source / drain contact 98. Silicide 96 may be formed by depositing a conductive material in the contact opening 90 and annealing. The conductive material may be cobalt, titanium, titanium nitride, nickel, etc. or a combination thereof. After annealing, silicide 96 may include TiSi2, CoSi2, etc. Silicide 96 may contact the sidewalls of the remaining portion of the termination layer 70E.

[0067] exist Fig. 12A and Fig. 12B , a second ILD layer 102 is deposited over the first ILD layer 76. In some embodiments, the second ILD layer 102 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD layer 102 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. An etch stop layer 100 is disposed between the second ILD layer 102 and the lower source / drain contacts 98, the gate mask 86, the gate spacer 66, and the dielectric CESL 74. The etch stop layer 100 can be formed of a dielectric material having a different etch rate from the material of the overlying second ILD layer 102, such as silicone, silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, etc., and can be formed by an appropriate deposition process.

[0068] Then form the upper source / drain contact 104 and the gate contact 106. An opening for the upper source / drain contact 104 is formed through the second ILD layer 102 and the etch stop layer 100, and an opening for the gate contact 106 is formed through the second ILD layer 102, the etch stop layer 100 and the gate mask 86. The opening can be formed using acceptable photolithography and etching techniques. A liner such as a diffusion barrier layer, an adhesion layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the top surface of the second ILD layer 102. The remaining liner and conductive material form the upper source / drain contact 104 and the gate contact 106 in the opening. The upper source / drain contact 104 is physically and electrically coupled to the lower source / drain contact 98, and the gate contact 106 is physically and electrically coupled to the gate electrode 84. The upper source / drain contact 104 and the gate contact 106 may be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each upper source / drain contact 104 and the gate contact 106 may be formed in different cross sections, which may avoid shorting of the contacts.

[0069] As described above, there may (or may not) be a region below the epitaxial source / drain region 70 (e.g., in the lower basin 72L, see Figure 4B ) forms the termination layer 70E and / or the dummy layer 70D. In some embodiments (see Fig. 12B ), the termination layer 70E is not formed below the epitaxial source / drain region 70, but the termination layer 70E is formed on the dummy layer 70D. In some embodiments (see Fig. 12A ), the termination layer 70E and the dummy layer 70D are not formed below the epitaxial source / drain region 70.

[0070] FIG. 13A to FIG. 16B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments. Fig.13A , Fig.14A , Fig.15A and Fig.16A It is along Figure 1 Reference section AA in FIG. 1 shows a cross-sectional view, except that only one source / drain region 70 is shown. Fig. 13B , Fig. 14B , Fig. 15B and Fig. 16B It is along Figure 1 Reference section BB in FIG. 5 shows a cross-sectional view, except that only two fins 52 are shown.

[0071] exist Fig.13A and Fig. 13B In the Fig. 6A and Figure 6B A similar intermediate structure is shown, except that the gate mask 86 is omitted and the planarization process (relative to the planarization process) on the first ILD layer 76 is performed. Figure 5A and Figure 5B Discussion)) is also omitted. Therefore, the dielectric CESL 74 and the first ILD layer 76 have portions disposed above the gate electrode 84. Portions of the first ILD layer 76 and the dielectric CESL 74 are removed to form the contact opening 90. The removal can be performed using an etch mask 92 by acceptable photolithography and etching techniques. In this embodiment, the etch mask 92 has a pattern of a bounded opening (e.g., an opening without a gap). The defined opening is defined on all sides by the material of the etch mask 92. In this way, after the contact opening 90 is formed, the contact opening 90 can be retained. Fig.13A Some of the first ILD layer 76 in the cross section shown. Therefore, a small width contact 98 can be formed between adjacent gate electrodes 84, thereby reducing the parasitic capacitance between the gate electrode 84 and the lower source / drain contact 98.

[0072] exist Fig.14A and Fig. 14B In the embodiment of the present invention, a contact spacer 112 is formed along the sidewall of the contact opening 90. The contact spacer 112 may be formed by conformally depositing a dielectric layer in the contact opening 90 and then etching the dielectric layer. The dielectric layer may be formed of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, etc., and may be formed by a deposition process such as CVD, ALD, etc. The etching may be anisotropic.

[0073] exist Fig.15A and Fig. 15B In the embodiment, portions of semiconductor CESL 70C, dummy layer 70D, and termination layer 70E are removed to enlarge contact opening 90. FIG. 8A to FIG. 10B The semiconductor CESL 70C, the dummy layer 70D, and the termination layer 70E are removed by etching and oxidation techniques similar to those discussed above, for example, by etching the termination layer 70E and the dummy layer 70D to expose the semiconductor CESL 70C, oxidizing the exposed portion of the semiconductor CESL 70C, and then etching the oxidized portion of the semiconductor CESL 70C. After enlarging the contact opening 90, the sidewalls of the contact spacer 112, the semiconductor CESL 70C, the dummy layer 70D, and the termination layer 70E are exposed.

[0074] After etching, the upper portion of the contact opening 90 (e.g., the portion extending through the dielectric CESL 74 and the first ILD layer 76) has a width W3, which may be in the range of about 6 nm and about 25 nm. The lower portion of the contact opening 90 (e.g., the portion extending through the dummy layer 70D and extending into the epitaxial source / drain region 70) has a width W4, which may be in the range of about 5 nm to about 24 nm. The width W4 is greater than the width W3. For example, the width W4 may be about 3 nm to about 4 nm greater than the width W3, and the ratio of W4:W3 may be in the range of about 1 to about 1.5. The width W4 may continuously decrease in the direction D1.

[0075] exist Fig.16A and Fig. 16B In the embodiment of the present invention, the lower source / drain contacts 98 and the silicide 96 are formed in the contact opening 90. The lower source / drain contacts 98 and the silicide 96 can be formed using the same method as described above with respect to Fig.11A and Fig. 11B After formation, the upper portion of the lower source / drain contact 98 is surrounded by the contact spacer 112, the middle portion of the lower source / drain contact 98 is surrounded by the termination layer 70E, and the lower portion of the lower source / drain contact 98 is surrounded by the functional layer 70B. Then, the same techniques as described above with respect to Fig. 12A and Fig. 12B Similar techniques are used to form the etch stop layer 100 , the second ILD layer 102 , the upper source / drain contacts 104 , and the gate contact 106 , except that the gate contact 106 also extends through the dielectric CESL 74 and the first ILD layer 76 .

[0076] FIG. 17A to FIG. 21B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments. Fig.17A , Fig.18A , Fig.19A , Fig. 20A and Fig.21A It is along Figure 1 Reference section AA in FIG. 1 shows a cross-sectional view, except that only one source / drain region 70 is shown. Fig. 17B , Fig.18B , Fig.19B , Fig. 20B and Fig.21B It is along Figure 1 Reference section BB in FIG. 5 shows a cross-sectional view, except that only two fins 52 are shown.

[0077] exist Fig.17A and Fig. 17B In the Fig. 6A and Figure 6BIn this embodiment, the termination layer 70E is omitted from the epitaxial source / drain region 70. Thus, the dielectric CESL 74 is formed on the semiconductor CESL 70C and the portion of the dummy layer 70D (see FIG. Fig.17A ). Portions of the first ILD layer 76 and the dielectric CESL 74 are removed to form a contact opening 90. The first ILD layer 76 and the dielectric CESL 74 may be formed using the same techniques as described above with respect to Fig. 7A and 7B The removal may be performed by techniques similar to those discussed above, such as by using an etch mask 92 having slit openings.

[0078] As an example of forming an epitaxial source / drain region 70 without an end layer 70E, multiple epitaxial growth steps and back etching steps may be performed. Specifically, a functional layer 70A is grown on the sidewalls of the recess 52R, and a functional layer 70B is grown on the functional layer 70A. A back etching process is then performed to flatten the top surface of the functional layer 70B. After the back etching process, a semiconductor CESL 70C is grown on the functional layer 70B, and a dummy layer 70D is grown on the semiconductor CESL 70C. The growth may be conformal. Another back etching process is then performed to flatten the top surfaces of the layers 70C and 70D. When the end layer 70E is omitted, the upper basin 72U may remain unfilled so that the final top surface of the epitaxial source / drain region 70 is convex.

[0079] exist Fig.18A and Fig.18B In the embodiment of the present invention, the dummy layer 70D is removed, thereby enlarging the contact opening 90. Fig. 8A and Figure 8B The dummy layer 70D is removed by an etching technique similar to the one discussed above.

[0080] exist Fig.19A and Fig.19B In the embodiment, the exposed portion of the semiconductor CESL 70C in the contact opening 90 is oxidized to form a dielectric layer 94. Fig. 9A and Fig. 9B The semiconductor CESL 70C is oxidized using techniques similar to those discussed above. As described above, the unexposed portions of the semiconductor CESL 70C are not oxidized. Furthermore, in this embodiment, some unoxidized portions of the semiconductor CESL 70C remain between the dielectric CESL 74 and the functional layer 70B.

[0081] exist Fig. 20A and Fig. 20B In the embodiment of the present invention, the dielectric layer 94 is removed so that the contact opening 90 is enlarged. Fig. 10A and Fig. 10BThe contact opening 90 is etched by a technique similar to that discussed above to remove the dielectric layer 94. As described above, etching does not remove the unoxidized portion of the semiconductor CESL 70C. After etching, the upper portion of the contact opening 90 (e.g., the portion extending through the dielectric CESL 74 and the first ILD layer 76) has a width W5, which may be in the range of about 6 nm and about 30 nm, and the lower portion of the contact opening 90 (e.g., the portion extending through the dummy layer 70D and extending into the epitaxial source / drain region 70) has a width W6 that may be in the range of about 5 nm to about 30 nm. The width W5 is greater than the width W6. For example, the width W5 may be greater than the width W6 by about 3 nm, and the ratio of W5: W6 may be in the range of about 1 to about 1.5. The width W6 may decrease continuously in the direction D1.

[0082] exist Fig.21A and Fig.21B In the embodiment of the present invention, the lower source / drain contacts 98 and the silicide 96 are formed in the contact opening 90. The lower source / drain contacts 98 and the silicide 96 can be formed using the same method as described above with respect to Fig.11A and Fig. 11B After formation, the upper portion of the lower source / drain contact 98 is surrounded by the dielectric CESL 74, the middle portion of the lower source / drain contact 98 is surrounded by the unoxidized portion of the semiconductor CESL 70C, and the lower drain contact 98 of the lower source is surrounded by the functional layer 70B. Then, the lower drain contact 98 is formed using the same techniques as described above with respect to Fig. 12A and Fig. 12B The etch stop layer 100 , the second ILD layer 102 , the upper source / drain contacts 104 , and the gate contact 106 are formed using techniques similar to those discussed above.

[0083] FIG. 22A to FIG. 25B is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some other embodiments. Fig.22A , Fig.23A , Fig.24A and Fig.25A It is along Figure 1 Reference section AA in FIG. 1 shows a cross-sectional view, except that only one source / drain region 70 is shown. Fig. 22B , Fig. 23B , Fig. 24B and Fig.25B It is along Figure 1 Reference section BB in FIG. 5 shows a cross-sectional view, except that only two fins 52 are shown.

[0084] exist Fig.22A and Fig. 22B In the Fig. 6A and Figure 6BA similar intermediate structure is shown, except that the gate mask 86 is omitted and the planarization process is performed on the first ILD layer 76 (with respect to FIG. Figure 5A and Figure 5B Thus, the dielectric CESL 74 and the first ILD layer 76 have portions disposed above the gate electrode 84. In this embodiment, the termination layer 70E is omitted from the epitaxial source / drain regions 70. The portions of the first ILD layer 76 and the dielectric CESL 74 may be formed using the same techniques as described above with respect to Fig.13A and Fig. 13B The first ILD layer 76 and the dielectric CESL 74 are removed using techniques similar to those discussed above, such as by using an etch mask 92 having restricted openings.

[0085] exist Fig.23A and Fig. 23B In the embodiment, the contact spacer 112 is formed along the sidewall of the contact opening 90. Fig.14A and Fig. 14B The contact spacers 112 are formed using techniques similar to those discussed above.

[0086] exist Fig.24A and Fig. 24B In the embodiment, portions of the semiconductor CESL 70C and the dummy layer 70D are removed to enlarge the contact opening 90. The semiconductor CESL 70C and the dummy layer 70D may be used as described above with reference to FIGS. 8A to 8B. Fig. 10B The semiconductor CESL 70C is removed by similar etching and oxidation techniques discussed above. For example, by etching the dummy layer 70D to expose the semiconductor CESL 70C, oxidizing the exposed portion of the semiconductor CESL 70C, and then etching the oxidized portion of the semiconductor CESL 70C. After the contact opening 90 is enlarged, the sidewalls of the contact spacer 112 and the semiconductor CESL 70C and the dummy layer 70D are exposed. In addition, some unoxidized portions of the semiconductor CESL 70C may remain between the dielectric CESL 74 and the functional layer 70B. After etching, the upper portion of the contact opening 90 (e.g., the portion extending through the dielectric CESL 74 and the first ILD layer 76) has a width W7, which may be in the range of about 6 nm to about 25 nm, and the lower portion of the contact opening 90 (e.g., the portion extending through the dummy layer 70D and extending into the epitaxial source / drain region 70) has a width W8 that may be in the range of about 5 nm to about 24 nm. The width W8 is greater than the width W7. For example, the width W8 may be greater than the width W7 by about 3 nm, and the ratio of W8:W7 may be in the range of about 1 to about 1.5. The width W8 may continuously decrease in the direction D1.

[0087] exist Fig.25A and Fig.25B In the embodiment of the present invention, the lower source / drain contacts 98 and the silicide 96 are formed in the contact opening 90. The lower source / drain contacts 98 and the silicide 96 can be formed using the same method as described above for the Fig.11A and Fig. 11B After formation, the upper portion of the lower source / drain contact 98 is surrounded by the contact spacer 112, the middle portion of the lower source / drain contact 98 is surrounded by the unoxidized portion of the semiconductor CESL 70C, and the lower portion of the lower source / drain contact 98 is surrounded by the functional layer 70B. Fig. 12A and Fig. 12B Similar techniques are used to form the etch stop layer 100 , the second ILD layer 102 , the upper source / drain contacts 104 , and the gate contact 106 , except that the gate contact 106 also extends through the dielectric CESL 74 and the first ILD layer 76 .

[0088] Other variations are possible. For example, in some embodiments, both the dummy layer 70D and the termination layer 70E are omitted. The semiconductor CESL 70C may thus fill the upper basin 72U, and the dielectric CESL 74 may be formed directly on the semiconductor CESL 70C.

[0089] Embodiments may achieve advantages. Forming the epitaxial source / drain region 70 to include the semiconductor CESL 70C allows the lower source / drain contact 98 to be formed to extend to the desired depth into the epitaxial source / drain region 70. Therefore, the contact area of ​​the lower source / drain contact 98 may be increased, thereby reducing the contact resistance and increasing the ION of the final FinFET. In addition, the lower source / drain contact 98 is extended into the epitaxial source / drain region 70 using the semiconductor CESL instead of a timed etch, thereby reducing the amount of material removed from the functional layer 70B. Because the functional layer 70B has a high dopant concentration, reducing the loss of the functional layer 70B may improve the performance of the resulting FinFET.

[0090] In one embodiment, a method includes: depositing an interlayer dielectric (ILD) layer on an epitaxial source / drain region, the epitaxial source / drain region including a main layer, a semiconductor contact etch stop layer (CESL) on the main layer, and a dummy layer on the semiconductor CESL; exposing a first portion of the dummy layer through the ILD layer; removing the first portion of the dummy layer by a first etching process to expose a second portion of the semiconductor CESL, the first etching process etching the dummy layer at a greater rate than the semiconductor CESL; removing the second portion of the semiconductor CESL to expose a third portion of the main layer; and forming a first source / drain contact on the third portion of the main layer.

[0091] In some embodiments of the method, the dummy layer is formed of silicon germanium, the dummy layer is formed of silicon germanium, the semiconductor CESL is formed of silicon, and the main layer is formed of phosphorus-doped silicon or boron-doped silicon germanium. And the first etching process includes: etching the silicon germanium with a mixture of H2SO4 and H2O2 for a duration of 5 seconds to 300 seconds. In some embodiments of the method, the dummy layer is formed of aluminum oxide, the semiconductor CESL is formed of silicon, the main layer is formed of phosphorus-doped silicon or boron-doped silicon germanium, and the first etching process includes: etching the aluminum oxide with ammonia (NH3) for a time in the range of 5 seconds to 200 seconds. In some embodiments of the method, removing the second portion of the semiconductor CESL includes: oxidizing the second portion of the semiconductor CESL to form a dielectric layer; and removing the dielectric layer by a second etching process, the second etching process etching the dielectric layer at a greater rate than the main layer. In some embodiments of the method, the semiconductor CESL is formed of silicon, the dielectric layer is formed of silicon oxide, and the second etching process includes: etching the silicon oxide with dilute hydrofluoric acid (dHF) for a time in the range of 10 seconds to 30 seconds. In some embodiments of the method, exposing the first portion of the dummy layer includes removing a portion of the ILD layer above the epitaxial source / drain region to form an opening, the opening being wider than the second portion of the semiconductor CESL, and further including: forming a silicide in the opening, the silicide being disposed between the first source / drain contact and the epitaxial source / drain region. In some embodiments of the method, exposing the first portion of the dummy layer includes removing a portion of the ILD layer above the epitaxial source / drain region to form an opening, the opening being narrower than the second portion of the semiconductor CESL, and further including: forming a contact spacer in the opening, the contact spacer surrounding the first source / drain contact; and forming a silicide in the opening, the silicide being disposed between the first source / drain contact and the epitaxial source / drain region. In some embodiments of the method, the epitaxial source / drain region further includes a termination layer on the dummy layer, and further includes: depositing a dielectric CESL on the termination layer, the ILD layer being deposited above the dielectric CESL; exposing a fourth portion of the termination layer through the dielectric CESL; and removing the fourth portion of the termination layer to expose the first portion of the dummy layer, and after forming the first source / drain contact, a fifth portion of the termination layer remains between the dielectric CESL and the main layer. In some embodiments, the method further includes: depositing a dielectric CESL on the dummy layer and the semiconductor CESL, the ILD layer being deposited above the dielectric CESL; and exposing the first portion of the dummy layer through the dielectric CESL, and after forming the first source / drain contact, a fourth portion of the semiconductor CESL remains between the dielectric CESL and the main layer.

[0092] In one embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source / drain region including: a main layer located in the first fin and the second fin, the main layer including a first semiconductor material, the main layer having an upper facet surface and a lower facet surface, the upper facet surface and the lower facet surface being raised from corresponding surfaces of the first fin and the second fin, respectively; and a semiconductor contact etch stop layer (CESL) contacting the upper facet surface and the lower facet surface of the main layer, the semiconductor CESL including a second semiconductor material, the second semiconductor material being different from the first semiconductor material.

[0093] In some embodiments, the device further includes: an interlayer dielectric (ILD) layer located above the epitaxial source / drain region; and a source / drain contact having a first portion and a second portion, the first portion extending through the ILD layer, the second portion extending into the epitaxial source / drain region, the first portion having a first width, the second portion having a second width, the second width being greater than the first width. In some embodiments, the device further includes: an interlayer dielectric (ILD) layer located above the epitaxial source / drain region; and a source / drain contact having a first portion and a second portion, the first portion extending through the ILD layer, the second portion extending into the epitaxial source / drain region, the first portion having a first width, the second portion having a second width, the second width being less than the first width. In some embodiments of the device, the epitaxial source / drain region further includes a dummy layer contacting the semiconductor CESL, the dummy layer including a third semiconductor material, the third semiconductor material being different from each of the first semiconductor material and the second semiconductor. In some embodiments of the device, the epitaxial source / drain region further includes a termination layer in contact with the dummy layer, the termination layer including a first semiconductor material, and further including: a dielectric CESL located above the epitaxial source / drain region, a portion of the termination layer contacting the main layer and the dielectric CESL. In some embodiments, the device further includes: a dielectric CESL located above the epitaxial source / drain region, a portion of the semiconductor CESL contacting the main layer and the dielectric CESL. In some embodiments of the device, the first semiconductor material is phosphorus-doped silicon or boron-doped silicon germanium, the second semiconductor material is silicon, and the third semiconductor material is silicon germanium. In some embodiments of the device, the first semiconductor material is phosphorus-doped silicon or boron-doped silicon germanium, the second semiconductor material is silicon, and the third semiconductor material is aluminum oxide.

[0094] In one embodiment, a device includes: a semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; an epitaxial source / drain region including: a main layer located in the first fin and the second fin, the main layer including a doped semiconductor material; a first contact etch stop layer (CESL) located on the main layer, the first CESL including an undoped semiconductor material; and a termination layer located on the first CESL, the termination layer including a doped semiconductor material; a second CESL located on the termination layer, the second CESL including a dielectric material; an interlayer dielectric (ILD) layer located on the second CESL; and source / drain contacts extending through the ILD layer, the second CESL, the termination layer and the first CESL, the source / drain contacts contacting the main layer.

[0095] In some embodiments of the device, a first portion of the source / drain contact extends through the first CESL and a second portion of the source / drain contact extends through the second CESL, the first portion being wider than the second portion. In some embodiments of the device, a first portion of the source / drain contact extends through the first CESL and a second portion of the source / drain contact extends through the second CESL, the first portion being narrower than the second portion.

[0096] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A method for forming a semiconductor device, comprising: depositing an interlayer dielectric (ILD) layer on the epitaxial source / drain region, the epitaxial source / drain region comprising a main layer, a semiconductor contact etch stop layer (CESL) on the main layer, and a dummy layer on the semiconductor contact etch stop layer, the dummy layer being formed of aluminum oxide, the semiconductor contact etch stop layer being formed of silicon, and the main layer being formed of phosphorus-doped silicon or boron-doped silicon germanium; exposing a portion of the dummy layer through the interlayer dielectric layer; removing the portion of the dummy layer by a first etching process to expose a first portion of the semiconductor contact etch stop layer, the first etching process etching the dummy layer at a greater rate than etching the semiconductor contact etch stop layer; removing the first portion of the semiconductor contact etch stop layer to expose a portion of the main layer; as well as A first source / drain contact is formed on the portion of the main layer.

2. The method according to claim 1, wherein: The first etching process comprises: The silicon germanium is etched using a mixture of H2SO4 and H2O2 for a duration of 5 seconds to 300 seconds.

3. The method according to claim 1, wherein: The first etching process comprises: Aluminum oxide is etched using ammonia (NH3) for a time ranging from 5 seconds to 200 seconds.

4. The method according to claim 1, wherein: Removing the first portion of the semiconductor contact etch stop layer includes: oxidizing the first portion of the semiconductor contact etch stop layer to form a dielectric layer; and The dielectric layer is removed by a second etching process that etches the dielectric layer at a greater rate than the primary layer.

5. The method according to claim 4, wherein: The semiconductor contact etch stop layer is formed of silicon, the dielectric layer is formed of silicon oxide, and the second etching process includes: The silicon oxide is etched using dilute hydrofluoric acid (dHF) for a time ranging from 10 seconds to 30 seconds.

6. The method according to claim 1, wherein: Exposing the portion of the dummy layer includes removing a portion of the interlayer dielectric layer above the epitaxial source / drain region to form an opening, the opening being wider than the first portion within the semiconductor contact etch stop layer, and further comprising: When forming the silicide in the opening within the region, the silicide within the region is disposed between the first source / drain contact within the region and the epitaxial source / drain region within the region.

7. The method according to claim 1, wherein: Exposing the portion of the dummy layer includes removing a portion of the interlayer dielectric layer above the epitaxial source / drain region to form an opening, the opening being narrower than the first portion of the semiconductor contact etch stop layer, and further comprising: forming a contact spacer in the opening, the contact spacer surrounding the first source / drain contact; and A silicide is formed in the opening, the silicide being disposed between the first source / drain contact and the epitaxial source / drain region.

8. The method according to claim 1, wherein: The epitaxial source / drain region also includes a termination layer on the dummy layer, and further includes: depositing a dielectric contact etch stop layer on the termination layer, an interlayer dielectric layer being deposited over the dielectric contact etch stop layer; exposing a first portion of the termination layer through the dielectric contact etch stop layer; and The first portion of the termination layer is removed to expose the portion of the dummy layer, and a second portion of the termination layer remains between the dielectric contact etch stop layer and the main layer after forming the first source / drain contacts.

9. The method according to claim 1, further comprising: depositing a dielectric contact etch stop layer on the dummy layer and the semiconductor contact etch stop layer, the interlayer dielectric layer being deposited above the dielectric contact etch stop layer; as well as The portion of the dummy layer is exposed through the dielectric contact etch stop layer, and a second portion of the semiconductor contact etch stop layer remains between the dielectric contact etch stop layer and the main layer after forming the first source / drain contacts.

10. A semiconductor device comprising: Semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; Epitaxial source / drain regions, including: a main layer located in the first fin and the second fin, the main layer comprising a first semiconductor material, the main layer having an upper facet surface and a lower facet surface, the upper facet surface and the lower facet surface being elevated from corresponding surfaces of the first fin and the second fin, respectively; a semiconductor contact etch stop layer (CESL) contacting the upper facet surface and the lower facet surface of the main layer, the semiconductor contact etch stop layer comprising a second semiconductor material different from the first semiconductor material; a dummy layer contacting the semiconductor contact etch stop layer, the dummy layer comprising a third semiconductor material different from each of the first semiconductor material and the second semiconductor material; and A termination layer is in contact with the dummy layer, and the termination layer includes the first semiconductor material.

11. The semiconductor device according to claim 10, further comprising: an interlayer dielectric (ILD) layer located above the epitaxial source / drain regions; as well as A source / drain contact has a first portion and a second portion, wherein the first portion extends through the interlayer dielectric layer, the second portion extends into the epitaxial source / drain region, the first portion has a first width, the second portion has a second width, and the second width is greater than the first width.

12. The semiconductor device according to claim 10, further comprising: an interlayer dielectric (ILD) layer located above the epitaxial source / drain regions; as well as A source / drain contact has a first portion and a second portion, wherein the first portion extends through the interlayer dielectric layer, the second portion extends into the epitaxial source / drain region, the first portion has a first width, and the second portion has a second width, the second width being smaller than the first width.

13. The semiconductor device according to claim 10, wherein: The thickness of the finishing layer is in the range of 1 nm to 20 nm.

14. The semiconductor device according to claim 10, wherein: The epitaxial source / drain region further comprises: A dielectric contact etch stop layer is located above the epitaxial source / drain region, and a portion of the termination layer contacts the main layer and the dielectric contact etch stop layer.

15. The semiconductor device according to claim 10, further comprising: A dielectric contact etch stop layer is located above the epitaxial source / drain region, and a portion of the semiconductor contact etch stop layer is in contact with the main layer and the dielectric contact etch stop layer.

16. The semiconductor device according to claim 10, wherein: The first semiconductor material is phosphorus-doped silicon or boron-doped silicon germanium, the second semiconductor material is silicon, and the third semiconductor material is silicon germanium.

17. The semiconductor device according to claim 10, wherein: The first semiconductor material is phosphorus-doped silicon or boron-doped silicon germanium, the second semiconductor material is silicon, and the third semiconductor material is aluminum oxide.

18. A semiconductor device comprising: Semiconductor substrate; a first fin extending from the semiconductor substrate; a second fin extending from the semiconductor substrate; Epitaxial source / drain regions, including: A main layer, located in the first fin and the second fin, the main layer comprising a doped semiconductor material; a first contact etch stop layer (CESL) disposed on the main layer, the first contact etch stop layer comprising an undoped semiconductor material; and a termination layer, located on the first contact etch stop layer, the termination layer comprising a doped semiconductor material; a second contact etch stop layer, located on the termination layer, the second contact etch stop layer comprising a dielectric material; an interlayer dielectric (ILD) layer on the second contact etch stop layer; and A source / drain contact extends through the interlayer dielectric layer, the second contact etch stop layer, the termination layer, and the first contact etch stop layer, the source / drain contact contacts the main layer.

19. The semiconductor device according to claim 18, wherein: A first portion of the source / drain contact extends through the first contact etch stop layer, and a second portion of the source / drain contact extends through the second contact etch stop layer, the first portion being wider than the second portion.

20. The semiconductor device according to claim 18, wherein A first portion of the source / drain contact extends through the first contact etch stop layer, and a second portion of the source / drain contact extends through the second contact etch stop layer, the first portion being narrower than the second portion.

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