Semiconductor structure and method for forming the same

Abstract

The semiconductor structure includes: a first interposer; a second interposer laterally adjacent to the first interposer, wherein the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and to a first side of the second interposer, wherein the first side of the first interposer and the first side of the second interposer face the first die. Embodiments of the present application also relate to methods of forming the semiconductor structure.

Description

Technical Field

[0001] The present invention generally relates to semiconductor packages and semiconductor structures and methods of forming the same, and in a specific embodiment, to chip-on-wafer-on-substrate (CoWoS) packages and methods for forming the CoWoS packages. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) In most cases, the increase in integration density comes from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

[0003] As the demand for shrinking electronic devices grows, there has been a demand for smaller and more creative semiconductor die packaging technologies. An example of such a packaging system is a stacked package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. Another example is a chip on wafer on substrate (CoWoS) structure, in which a semiconductor chip is attached to a wafer (e.g., an interposer) to form a chip on wafer (CoW) structure. Then, the CoW structure is attached to a substrate (e.g., a printed circuit board) to form a CoWoS structure. These and other advanced packaging technologies can produce semiconductor devices with enhanced functionality and a small footprint. Summary of the invention

[0004] Some embodiments of the present application provide a semiconductor structure, including: a first interposer; a second interposer laterally adjacent to the first interposer, wherein the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and to a first side of the second interposer, wherein the first side of the first interposer and the first side of the second interposer face the first die.

[0005] Other embodiments of the present application provide a semiconductor structure, including: a redistribution structure; a first interposer located on the redistribution structure; a second interposer located on the redistribution structure and laterally adjacent to the first interposer, wherein the second interposer is spaced apart from the first interposer; and a first die located above the first interposer and above the second interposer, wherein a first die connector of the first die is bonded to a first conductive bump of the first interposer, and a second die connector of the first die is bonded to a second conductive bump of the second interposer.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor structure, the method comprising: placing a first interposer to be laterally adjacent to a second interposer; embedding the first interposer and the second interposer in a first molding material; and bonding a first die to the first interposer and the second interposer, wherein a first die connector of the first die is bonded to a first conductive bump at a first side of the first interposer, and a second die connector of the first die is bonded to a second conductive bump at a first side of the second interposer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present invention and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, in which:

[0008] Figures 1 to 4 , Figure 5A and Figure 5B Various views of a chip-on-wafer (CoW) device at various stages of fabrication in an embodiment are shown;

[0009] Figure 6 shows a cross-sectional view of a chip-on-wafer-on-substrate (CoWoS) device in an embodiment;

[0010] Figure 7 shows a cross-sectional view of a CoWoS device in another embodiment;

[0011] Figure 8 and Fig. 9 shows a cross-sectional view of a CoW device at various stages of fabrication in an embodiment;

[0012] Fig.10 shows a cross-sectional view of a CoWoS device in an embodiment;

[0013] Figures 11 to 17 illustrates various exemplary cross-sectional views of a front side portion of an interposer in some embodiments;

[0014] Fig.18 and Fig.19 illustrates various exemplary cross-sectional views of a backside portion of an interposer in some embodiments; and

[0015] Fig. 20 is a flow chart of a method for forming a semiconductor structure in some embodiments. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0017] Moreover, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Throughout the description herein, unless otherwise described, the same reference numerals in different figures refer to the same or similar components formed by the same or similar processes using the same or similar materials.

[0018] In some embodiments, a CoW device includes a plurality of dies attached to a first interposer and a second interposer. The second interposer is spaced apart from the first interposer and is placed side by side with the first interposer. The first interposer and the second interposer are embedded in a first molding material. A redistribution structure may be formed along a back side of the first interposer and along a back side of the second interposer. A first die among the plurality of dies is bonded to a front side of the first interposer and a front side of the second interposer. A second die among the plurality of dies is bonded only to a front side of the second interposer. The CoW device is then bonded to a substrate to form a CoWoS device. The disclosed embodiments allow multiple dies to be integrated in a CoW device using multiple smaller interposers instead of a single large interposer. Smaller interposers avoid or reduce warping of the interposer. Additional benefits include: easier bonding of the interposer to the substrate during formation of the CoWoS device; less stress in the CoWoS structure; and reduced risk of cracks or delamination of the interposer and / or substrate.

[0019] Figures 1 to 4 , Figure 5A and Figure 5B Various views of a chip-on-wafer (CoW) device 150 are shown at various stages of fabrication in an embodiment. Throughout the discussion herein, a CoW device may also be referred to as a CoW package, and a CoWoS device may also be referred to as a CoWoS package.

[0020] Reference now Figure 1, the first interposer 100A and the second interposer 100B are attached to a support 50, which may be, for example, a belt supported by a frame. In some embodiments, the support 50 is a carrier. In subsequent processing, the support 50 is removed from the final product. The first interposer 100A is placed laterally adjacent to (e.g., side by side with) the second interposer 100B, with a gap G between them. In other words, the first interposer 100A is spaced apart from the second interposer 100B. The first interposer 100A and the second interposer 100B may be collectively referred to as an interposer 100.

[0021] In some embodiments, each interposer 100 (eg, 100A or 100B) includes a substrate 101, a front-side dielectric layer 103, a back-side dielectric layer 105, and a conductive path 107 (eg, a through-substrate via (TSV)). Figure 1 In the example of FIG. 1 , each interposer also has a plurality of conductive bumps 109 on its front side. In the illustrated embodiment, the conductive bumps 109 are electrically coupled to the conductive paths 107. The conductive bumps 109 may be, for example, copper pillars.

[0022] exist Figure 1 In the example of FIG. 1 , each of the interposers 100 has a molding material 117 formed around the conductive bumps 109 on the front side thereof, and the interposers 100 are attached to the support 50 by the molding material 117. The molding material 117 may be connected to each of the interposers 100 such that the sidewalls of the molding material 117 are aligned with the corresponding sidewalls of the interposers 100. As examples, the molding material 117 may include epoxy resin, organic polymer, polymer with or without the addition of a silicon dioxide or glass-based filler, or other materials.

[0023] After the interposer 100 is attached to the support 50, a molding material 104 is formed to fill the gap G between the interposers 100. The molding material 104 may include the same material as the molding material 117, so the details are not repeated. Next, a polishing process, such as chemical mechanical polishing (CMP), may be performed to remove excess portions of the molding material 104 from the upper surface of the backside dielectric layer 105, so that the molding material 104 and the backside dielectric layer 105 have coplanar upper surfaces. In the illustrated embodiment, the molding material 104 and the molding material 117 are formed of the same material and are therefore illustrated as a continuous volume of the molding material 117 in subsequent figures.

[0024] In the illustrated embodiment, the substrate 101 of each of the interposers 100 is a silicon substrate, but other suitable substrates such as glass, ceramic, etc. may also be used. The conductive path 107 may be a TSV or any other suitable conductive path. In the discussion below, the conductive path 107 may be referred to as a TSV or a TSV conductor, with the understanding that any suitable conductive path may be used. In an embodiment where the conductive path 107 is a TSV, the TSV 107 may be formed by first forming the TSV conductor 107 partially through the substrate 101, and then thinning the substrate 101 to expose the TSV 107. In other embodiments, the TSV 107 extends through the substrate 101 when initially formed, and thinning the substrate 101 is not required. The TSV conductor 107 may be formed by applying a suitable photoresist to the substrate 101 and developing it, and then etching the substrate 101 to generate a TSV opening (which is later filled as discussed below).

[0025] Once the opening for the TSV conductor 107 is formed, it can be lined with, for example, a liner ( Figure 1 Not shown separately), barrier layer (in Figure 1 The liner 108 is formed by a process such as chemical vapor deposition, oxidation, physical vapor deposition, atomic layer deposition, etc., and a conductive material fills the opening for the TSV conductor 107. In an embodiment, the liner may be a dielectric material such as silicon nitride, silicon oxide, dielectric polymer, a combination of these, etc., formed by a process such as chemical vapor deposition, oxidation, physical vapor deposition, atomic layer deposition, etc.

[0026] The barrier layer may include a conductive material such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, etc. may alternatively be utilized. The barrier layer may be formed using a CVD process such as plasma enhanced CVD (PECVD). However, other alternative processes such as sputtering or metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD) may alternatively be used. The barrier layer may be formed so as to conform to the shape of the underlying opening for the TSV conductor 107.

[0027] The conductive material may include copper, although other suitable materials may alternatively be utilized, such as aluminum, tungsten, alloys, doped polysilicon, combinations thereof, etc. The conductive material may be formed by depositing a seed layer and then electroplating copper on the seed layer, filling and overfilling the openings for the TSV conductors 107. Once the openings for the TSV conductors 107 are filled, excess barrier layer and excess conductive material outside of the openings for the TSV conductors 107 may be removed by a polishing process such as chemical mechanical polishing (CMP), although any suitable removal process may be used.

[0028] Each of the front-side dielectric layer 103 and the back-side dielectric layer 105 includes a suitable dielectric material, such as silicon oxide, silicon nitride, a low-k dielectric (such as carbon-doped oxide), an ultra-low-k dielectric (such as porous carbon-doped silicon dioxide), a combination thereof, etc. In some embodiments, the dielectric material used for the front-side dielectric layer 103 (or the back-side dielectric layer 105) includes a polymer material, such as low-temperature polyimide (PI), polybenzoxazole (PBO), a combination thereof, etc. Any suitable formation method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), can be used to form the front-side dielectric layer 103 or the back-side dielectric layer 105. It should be noted that the materials used for the front-side dielectric layer 103 and the back-side dielectric layer 105 are independently selected and, therefore, may be the same or may be different. In the illustrated embodiment, the frontside dielectric layer 103 and the backside dielectric layer 105 are connected to the substrate 101 such that the sidewalls of the frontside dielectric layer 103 (and the sidewalls of the backside dielectric layer 105 ) are aligned with corresponding sidewalls of the substrate 101 .

[0029] exist Figure 1 In the example of FIG. 1 , the first interposer 100A and the second interposer 100B have the same height T, measured between the outer surface of the front-side dielectric layer 103 and the outer surface of the back-side dielectric layer 105. In addition, the conductive bumps 109 may also have the same height.

[0030] Next, in Figure 2 In the embodiment, a redistribution structure 110 is formed on the backside dielectric layer 105 of the first interposer 100A and the backside dielectric layer 105 of the second interposer 100B. The redistribution structure 110 is electrically coupled to the TSV 107 of the first interposer 100A and the TSV 107 of the second interposer 100B. Figure 2 In the embodiment, the redistribution structure 110 extends continuously from the first interposer 100A to the second interposer 100B, and the sidewalls of the redistribution structure 110 are aligned with the corresponding sidewalls of the interposers 100A / 100B. A conductive connector 115 (e.g., a controlled collapse chip connection bump (C4 bump), a copper pillar, etc.) electrically coupled to the redistribution structure 110 is formed over the redistribution structure 110. A solder region 116 may optionally be formed on the conductive connector 115 or as part of the conductive connector 115.

[0031] Figure 2 The redistribution structure 110 in the embodiment includes conductive features, such as conductive lines 113 formed in the dielectric layer 111. In some embodiments, the redistribution structure 110 includes one or more layers of conductive lines 113 and vias ( Figure 2). In some embodiments, the one or more dielectric layers 111 are formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 111 is formed of a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; etc. The one or more dielectric layers 111 can be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, etc., or a combination thereof.

[0032] In some embodiments, the conductive features of the redistribution structure 110 are formed of a suitable conductive material, such as copper, titanium, tungsten, aluminum, etc. The conductive features can be formed by, for example, forming openings in the dielectric layer 111 to expose the underlying conductive features (e.g., TSV 107), forming a seed layer over the dielectric layer 111 and in the openings, forming a patterned photoresist having a design pattern over the seed layer, plating (e.g., electroplating or chemical plating) a conductive material in the design pattern and over the seed layer, and removing portions of the photoresist and the seed layer where the conductive material is not formed. Figure 2 In the example of FIG. 1 , the conductive line 113A of the redistribution structure 110 continuously extends from the first interposer 100A to the second interposer 100B.

[0033] Figure 2 The redistribution structure 110 in the first interposer 100A extends continuously from the first interposer 100A to the second interposer 100B. In other embodiments, the first redistribution structure and the second redistribution structure (spaced apart (e.g., separated) from the first redistribution structure) are formed along the back side of the first interposer 100A and the back side of the second interposer 100B, respectively. The first redistribution structure and the substrate 101 of the first interposer 100A are co-terminal, and the second redistribution structure and the substrate 101 of the second interposer 100B are co-terminal. In some embodiments, the redistribution structure 110 is not formed, and a conductive connector 115 electrically coupled to the TSV 107 is formed on the backside dielectric layer 105.

[0034] Next, in Figure 3 middle, Figure 2 The structure in the molded product (e.g., the interposer 100 having the redistribution structure 110) is released from the support 50, flipped over, and attached to the support 52. The support 52 may be the same as or similar to the support 50. A planarization process such as CMP may be performed to recess the molding material 117 so that the conductive bumps 109 are exposed at the upper surface of the molding material 117.

[0035] Next, in Figure 4In the embodiment of the present invention, a dielectric layer 119, such as a polymer layer (e.g., a polyimide layer), is formed over the molding material 117. The dielectric layer 119 can be formed using the same or similar formation process as the front-side dielectric layer 103, so the details are not repeated. Next, an opening is formed in the dielectric layer 119 using a suitable method such as photolithography and patterning, and a conductive bump 121, such as a microbump or a copper bump, is formed in the opening to be electrically coupled to the corresponding conductive bump 109. The conductive bump 121 or the combination of the conductive bump 121 and the corresponding underlying conductive bump 109 can be referred to as a conductive bump of the corresponding interposer 100 (e.g., 100A or 100B). A solder region 123 can be optionally formed over the conductive bump 121.

[0036] Next, in Figure 5A In the embodiment of the present invention, dies 131 (e.g., 131A or 131B) and 133 are bonded to conductive bumps 121. Each of dies 131 / 133 (also referred to as semiconductor dies, integrated circuit (IC) dies) includes a substrate, electronic components (e.g., transistors, resistors, capacitors, or inductors) formed in / on the substrate, and interconnect structures that connect the electronic components to form functional circuits. In addition, each of dies 131 / 133 has a die connector 132 that is electrically coupled to the functional circuit of the die and provides electrical connections between the die and external components (e.g., another die or a printed circuit board).

[0037] In some embodiments, die 131 and die 133 are the same type of die. In other embodiments, die 131 and die 133 are different types of die. For example, die 131 may be a logic die, and die 133 may be a memory die, such as a high bandwidth memory (HBM) die.

[0038] like Figure 5A As shown, the die 131A overlaps both the first interposer 100A and the second interposer 100B. In other words, a first portion of the die 131A is disposed within the lateral extent of the first interposer 100A, and a second portion of the die 131A is disposed within the lateral extent of the second interposer 100B. Therefore, some of the die connectors 132 of the die 131A are bonded to the conductive bumps 121 of the first interposer 100A, and some of the die connectors 132 of the die 131A are bonded to the conductive bumps 121 of the second interposer 100B. Figure 5A Also shown is a die 131B disposed within the lateral extent of the second interposer 100B, with all die connections 132 of the die 131B bonded to the conductive bumps 121 of the second interposer 100B. In addition, a die 133 is bonded to the corresponding conductive bumps 121 and disposed within the lateral extent of the corresponding interposer 100 (e.g., 100A or 100B).

[0039] In some embodiments, the die 131 / 133 is bonded to the interposer 100 by a reflow process, so that the solder region 134 on the top of the die connector 132 melts and combines with the corresponding solder region 123 of the interposer 100 to form a solder joint between the die connector 132 and the conductive bump 121. In other embodiments, the die 131 / 133 is bonded to the interposer 100 by a direct bonding process. For example, in an exemplary direct bonding process, no solder region is formed on the die connector 132 or on the conductive bump 121, and the conductive bump 121 (e.g., copper pillar) is directly bonded to the die connector 132 (e.g., copper pillar) by, for example, copper diffusion through heat and / or pressure in the direct bonding process.

[0040] After bonding the die 131 / 133, an underfill material 125 is formed between the dielectric layer 119 and the die 131 / 133. The underfill material 125 may also fill or partially fill the gap between adjacent die 131 / 133. Exemplary materials for the underfill material 125 include, but are not limited to, polymers and other suitable non-conductive materials. The underfill material 125 may be dispensed in the gap between the dielectric layer 119 and the die 131 / 133 using, for example, a needle or a jet dispenser. A curing process may be performed to cure the underfill material 125. The underfill material 125 forms a fillet around the edge (e.g., sidewall) of the die 131 / 133, such as Figure 5A In the illustrated embodiment, it should be noted that due to gravity, the width of the bottom fill material 125 (along the Figure 5A 100A / 100B) increases as the bottom fill material 125 extends from the lower surface of the tube core 131 / 133 toward the interposer 100A / 100B.

[0041] After forming the underfill material 125, a molding material 129 is formed around the die 131 / 133 so that the die 131 / 133 is embedded in the molding material 129. The material and forming method of the molding material 129 may be the same as or similar to the material and forming method of the molding material 117, and thus the details are not repeated. Figure 5A In the example of FIG. 1 , sidewalls of molding material 129 are aligned with corresponding sidewalls of interposer 100 and with corresponding sidewalls of molding material 117 . Figure 5A The structure shown in , excluding the support 52 , is referred to as a chip-on-wafer (CoW) structure, and the device formed is referred to as a CoW device 150 .

[0042] Figure 5B A top view of a CoW device 150 is shown. Figure 5A Corresponding to the Figure 5B The cross-sectional view of section AA in. Figure 5B, the boundary (eg, sidewall) of the molding material 129 is shown. The boundary of the molding material 129 overlaps with the corresponding sidewall of the first interposer 100A and the corresponding sidewall of the second interposer 100B (see FIG. Figure 4 ). Figure 5B The dashed line 145 in FIG. 1 shows the location of the gap G between the interposers 100A and 100B. Therefore, the area within the boundary of the molding material 129 (e.g., on the left side of the dashed line 145) represents the location of the first interposer 100A, and the area on the right side of the dashed line 145 represents the location of the second interposer 100B.

[0043] exist Figure 5B In the example of , a plurality of dies (e.g., 131A, 131B, 131C) are disposed within a bonding boundary defined by interposers 100 (e.g., 100A and 100B). A first portion of die 131A is disposed within the boundary of the first interposer 100A (e.g., to the left of dashed line 145), and a second portion of die 131A is disposed within the boundary of the second interposer 100B (e.g., to the right of dashed line 145). Die 131B is completely disposed within the boundary of the second interposer 100B. Figure 5B Also shown is die 131C, which is not in section AA and therefore not shown in FIG. Figure 5A Shown in.

[0044] Figure 6 FIG. 2 shows a cross-sectional view of a chip-on-wafer-on-substrate (CoWoS) device 200 in an embodiment. Figure 5A The CoW device 150 in the CoWoS device 200 is attached (e.g., bonded) to the substrate 135 to form the CoWoS device 200. In some embodiments, the substrate 135 is a multi-layer circuit board. For example, the substrate 135 may include one or more dielectric layers 146 formed of bismaleimide triazine (BT) resin, FR-4 (a composite material composed of woven glass fiber cloth and a flame-retardant epoxy resin adhesive), ceramic, glass, plastic, tape, film, or other supporting materials. The substrate 135 may include conductive components (e.g., wires 141 and vias 143) formed in / on the substrate 135. As shown in FIG. Figure 6 As shown, substrate 135 has conductive pads 137 formed on an upper surface of substrate 135 and on a lower surface of substrate 135, and conductive pads 137 are electrically coupled to conductive features of substrate 135. Substrate 135 may also have external connectors 139 (e.g., solder balls, copper pillars, copper pillars with solder on top) at its lower surface for electrical connection to another electronic component.

[0045] The CoW device 150 is bonded to the substrate 135. For example, a reflow process may be performed to electrically and mechanically couple the CoW device 150 to the substrate 135. In some embodiments, the solder region 116 bonds the CoW device 150 to the substrate 135.

[0046] Next, an underfill material 142 is formed between the CoW device 150 and the substrate 135. The underfill material 142 may be the same or similar to the underfill material 125 and may be formed by the same or similar formation method, so the details are not repeated. The underfill material 142 may form a rounded corner around the edge (e.g., sidewall) of the CoW device 150. It should be noted that in Figure 7 Due to gravity, the width of the bottom filling material 142 (along Figure 7 The width of the underfill material 142 (measured in the horizontal direction of the substrate 135) increases as the underfill material 142 extends toward the substrate 135. In other words, the width of the underfill material 142 and the width of the underfill material 125 increase in the same direction (eg, from the CoW device 150 toward the substrate 135).

[0047] As more and more dies (e.g., 131, 133) are integrated into the CoWoS structure to provide semiconductor devices with enhanced functionality and / or more storage capacity (e.g., memory capacity), the size of the interposer and the size of the substrate may need to be increased to accommodate the dies. Without the currently disclosed interposer design (e.g., two separated interposers 100A / 100B in a CoW device, among others), all dies 131 / 133 are bonded to a single interposer, and the size of the single interposer may become too large. Therefore, it may be difficult to keep the single interposer flat (e.g., having a flat upper surface and / or a flat lower surface). Due to its large size, warping of the single interposer may occur, which may make it difficult to bond the CoW device to the substrate 135. The warping of the interposer may also cause stress in the solder area 116, which may cause failures in the solder area 116 and may cause cracks or delamination of the interposer and / or substrate 135.

[0048] In contrast, with the currently disclosed CoWoS structure, some of the dies are bonded to the first interposer 100A and some of the dies are bonded to the second interposer 100B. Therefore, each of the interposers 100A / 100B still has a small size to avoid or reduce warping. Additional benefits include: easier bonding to the substrate 135, less stress in the CoWoS structure, and reduced risk of cracks or delamination of the interposer and / or substrate. In addition, although the interposers 100A and 100B can be designed to accommodate the CoW structure disclosed herein, the design of the dies 131 / 133 does not need to be changed for the disclosed CoW structure. In other words, the advantages described above can be achieved without any design loss to the dies 131 / 133.

[0049] Figure 7A cross-sectional view of a CoWoS device 200A in another embodiment is shown. The CoWoS device 200A is similar to Figure 6 The CoWoS device 200 is shown in FIG. 1 , but the width (eg, 100A, 100B) of the interposer 100 is reduced, so that the molding material 117 surrounds the interposer 100 . In other words, the outer sidewall 101OS of the interposer 100 is covered by the molding material 117 .

[0050] Figure 8 and Fig. 9 1 shows a cross-sectional view of a CoW device 300 at various stages of manufacture in an embodiment. Figure 8 In the embodiment of the present invention, the dies 131 (e.g., 131A, 131B) and the dies 133 are attached to the carrier 161 by, for example, an adhesive layer 163. The carrier 161 may be made of materials such as silicon, polymers, polymer composites, metal foils, ceramics, glass, epoxy glass, beryllium oxide, tapes, or other materials for structural support. In some embodiments, the adhesive layer 163 is deposited or laminated over the carrier 161. The adhesive layer 163 may be photosensitive and may be easily stripped from the carrier 161 in a subsequent carrier stripping process by, for example, irradiating ultraviolet (UV) light on the carrier 161. For example, the adhesive layer 163 may be a light-to-heat conversion (LTHC) coating.

[0051] Next, a molding material 129 is formed over the carrier 161 surrounding the die 131 / 133. After the molding material 129 is formed, a planarization process such as CMP may be performed to expose the upper surface of the die connector 132. In some embodiments, a conductive bump 121, such as a microbump, is formed over the die connector 132. Although not shown, a dielectric layer, such as a polymer layer, may be formed over the molding material 129 before the conductive bump 121 is formed, in which case the conductive bump 121 extends through the dielectric layer to be electrically coupled to the die connector 132.

[0052] Next, the first interposer 100A and the second interposer 100B are bonded to the die 131 / 133 . Figure 8 In the example of , some of the die connectors 132 of die 131B are bonded to the first interposer 100A, and other die connectors 132 of die 131B are bonded to the second interposer 100B. In contrast, all die connectors of die 131A (or die 133) are bonded to the same interposer. Figure 1 Compared with the interposer 100 (e.g., 100A, 100B) in Figure 8 The interposer 100 in FIG. 1 does not have a backside dielectric layer 105. Of course, this is only a non-limiting example. Other interposers, such as Figure 1 The interposer 100 may also be used to form Figure 8The structure in .

[0053] Next, an underfill material 125 is formed between the upper surfaces of the interposers 100 (eg, 100A and 100B) and the molding material 129. The underfill material 125 may fill or partially fill the gaps between the interposers 100. In the illustrated embodiment, due to gravity, the interposers 100 are formed along the underfill material 125. Figure 8 The width of the underfill material 125 measured in the horizontal direction in FIG. 1 increases as the underfill material 125 extends from the lower surface of the interposer 100 toward the molding material 129 .

[0054] Next, in Fig. 9 In the embodiment of the present invention, the molding material 117 is formed over the molding material 129 surrounding the interposer 100 and surrounding the underfill material 125. A planarization process such as CMP may be performed to achieve a planar upper surface between the molding material 117 and the back side of the interposer 100.

[0055] Next, a redistribution structure 110 (including a dielectric layer 111 and a conductive feature 113) electrically coupled to the interposer 100 is formed over the molding material 117. Next, a conductive connector 115 electrically coupled to the redistribution structure 110 and optionally a solder region 116 are formed over the redistribution structure 110. Next, a carrier stripping process is performed to remove the carrier 161 and the adhesive layer 163, and after the carrier stripping, Fig. 9 The structure in FIG. 1 shows a CoW device 300 .

[0056] Fig.10 4 shows a cross-sectional view of a CoWoS device 400 in an embodiment. The CoWoS device 400 is formed by, for example, reflowing the device 400 through a reflow process. Fig. 9 The conductive connection 115 of the CoW device 300 is bonded to the conductive pad 137 of the substrate 135. The substrate 135 has been described above, so the details will not be repeated here.

[0057] After the CoW device 300 is bonded to the substrate 135, an underfill material 142 is formed on the substrate 135 and around the edge of the CoW device 300. Fig.10 In the example of FIG. 1 , due to gravity, the width of the bottom filling material 142 (along Fig.10 135) increases as the bottom fill material 142 extends toward the substrate 135. It should be noted that the width of the bottom fill material 125 decreases as it extends toward the substrate 135. In other words, the width of the bottom fill material 142 increases along a first direction (e.g., downward toward the substrate 135), and the width of the bottom fill material 125 increases along an opposite second direction (e.g., upward away from the substrate 135).

[0058] Figures 11 to 17 1 shows cross-sectional views of various embodiments of a front side portion (eg, a portion at the front side) of an interposer in some embodiments. Specifically, Figures 11 to 17 Structures for different embodiments of conductive bumps at the front side of the interposer are shown. Figures 11 to 17 The conductive bump structures of the various embodiments shown in FIG. 1 may be used as the conductive bump structures in the CoW device 150 or 300 as will be readily understood by those skilled in the art.

[0059] refer to Fig.11 , Fig.11 The conductive bump structure in Figure 4 The structure of the interposer is similar to that of the interposer, but has a conductive line 124 (e.g., a copper line used as a redistribution line) formed in a dielectric layer 119 (e.g., a polyimide layer) and electrically coupled to the conductive bump 109. In other words, the dielectric layer 119 and the conductive line 124 form a redistribution structure at the front side of the interposer. In addition, a microbump 121 electrically coupled to the conductive line 124 is formed above the conductive line 124. A solder region 123 is optionally formed above the microbump 121.

[0060] Figure 12 to Figure 14 Three embodiments of conductive bump structures are shown with aluminum pads 151 (instead of conductive bumps 109) formed at the upper surface of the front-side dielectric layer 103 and electrically coupled to the TSVs 107. Fig.12 In the embodiment, a passivation layer 153 (eg, a polymer layer) is formed on the front side dielectric layer 103 , and a micro bump 121 extending through the passivation layer 153 to be electrically coupled to the aluminum pad 151 is formed over the passivation layer 153 .

[0061] exist Fig.13 In the embodiment, a passivation layer 153 (eg, a polymer layer) is formed on the front side dielectric layer 103 , and a gold bump 155 extending through the passivation layer 153 to be electrically coupled to the aluminum pad 151 is formed over the passivation layer 153 .

[0062] exist Fig.14 In the embodiment, a passivation layer 153 (e.g., a polymer layer) is formed on the front side dielectric layer 103, and a copper pillar 157 extending through the passivation layer 153 to be electrically coupled to the aluminum pad 151 is formed over the passivation layer 153. An electroless nickel electroless palladium immersion gold (ENEPIG) layer 159 is then formed over the exposed surface of the copper pillar 157.

[0063] Figures 15 to 17 1 shows three embodiments of conductive bump structures having copper pillars 109 formed in molding material 117 and electrically coupled to TSV 107, similar to Figure 6 and Figure 7 .exist Fig.15In the embodiment, micro bumps 121 are formed above the molding material 117 and on the copper pillars 109. It should be noted that no micro bumps 121 are formed here. Figure 6 The dielectric layer 119 in the microbump 121 is formed so that the sidewall of the microbump 121 is completely exposed. A solder region 123 may be formed on the microbump 121. Fig.16 In the embodiment, gold bumps 155 are formed over the molding material 117 and on the copper pillars 109. Fig.17 In the embodiment of the present invention, copper pillar 157 is formed over molding material 117 and on copper pillar 109. Then, ENEPIG layer 159 is formed over the sidewall and upper surface of copper pillar 157.

[0064] Fig.18 and Fig.19 1 shows cross-sectional views of various embodiments of a backside portion (eg, a portion at the backside) of an interposer in some embodiments. Specifically, Fig.18 and Fig.19 Different embodiment structures for conductive bumps at the backside of the interposer are shown. Fig.18 and Fig.19 The conductive bump structures of the various embodiments shown in the drawings can be used as the backside conductive bump structures in the CoW device 150 or 300 as will be readily understood by those skilled in the art. Fig.18 and Fig.19 In the embodiment, the redistribution structure 110 is not formed on the back side of the interposer 100 .

[0065] exist Fig.18 In the embodiment of the present invention, a passivation layer 118, such as a PBO layer, is formed on a backside dielectric layer 105 (e.g., a silicon nitride layer) of an interposer 100 (e.g., 100A or 100B). Next, a C4 bump 115 is formed on the passivation layer 118 to extend through the passivation layer 118 to be electrically coupled to the TSV 107. A solder region 116 may be formed on the C4 bump 115.

[0066] exist Fig.19 In the embodiment of the present invention, the backside dielectric layer 105 of the interposer 100 is a polymer layer (eg, a polyimide layer). C4 bumps extending through the backside dielectric layer 105 to electrically couple to the TSVs 107 are formed directly on the backside dielectric layer 105. Solder regions 116 may be formed on the C4 bumps 115.

[0067] Variations and modifications to the disclosed embodiments are possible and are fully intended to be included within the scope of the present invention. For example, although two separated interposers are used as an example to form a CoW device, the principles disclosed herein can be applied to embodiments using more than two separated interposers to form CoW devices and CoWoS devices. In addition, the various front-side bump structures and back-side bump structures disclosed herein can be combined in any suitable manner to form CoW devices and CoWoS devices.

[0068] Fig. 20 1 is a flow chart of a method 1000 for manufacturing a semiconductor structure according to some embodiments. It should be understood that Fig. 20 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, options, and modifications. For example, the embodiments may be added, removed, replaced, rearranged, and repeated. Fig. 20 The individual steps shown in .

[0069] refer to Fig. 20 In step 1010, a first interposer is placed laterally adjacent to a second interposer. In step 1020, the first interposer and the second interposer are embedded in a first molding material. In step 1030, a first die is bonded to the first interposer and the second interposer, wherein a first die connector of the first die is bonded to a first conductive bump at a first side of the first interposer, and a second die connector of the first die is bonded to a second conductive bump at a first side of the second interposer.

[0070] Advantages of the present invention include: Reduced warpage in interposers 100A and 100B due to reduced dimensions in each of the interposers. Additional advantages include: Less stress at the junction between the interposer and the substrate, and reduced risk of cracks or delamination. Improved device reliability, and improved semiconductor processing yield. These advantages can be achieved without redesigning the die attached to the interposer.

[0071] According to an embodiment, a semiconductor structure includes: a first interposer; a second interposer laterally adjacent to the first interposer, wherein the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and to a first side of the second interposer, wherein the first side of the first interposer and the first side of the second interposer face the first die. In an embodiment, a first portion of the first die is disposed within a lateral extent of the first interposer, and a second portion of the first die is disposed within a lateral extent of the second interposer. In an embodiment, the semiconductor structure further includes: a second die attached to a first side of the second interposer, wherein the second die is disposed within a lateral extent of the second interposer. In an embodiment, the semiconductor structure further includes: a redistribution structure located at a second side of the first interposer opposite to the first side of the first interposer, wherein the redistribution structure extends continuously from the first interposer to the second interposer. In an embodiment, a first portion of the first die has a first die connector, and a second portion of the first die has a second die connector, wherein the first die connector is bonded to a first conductive bump at a first side of the first interposer, and the second die connector is bonded to a second conductive bump at a first side of the second interposer. In an embodiment, the semiconductor structure further comprises: a first molding material, wherein the first interposer and the second interposer are embedded in the first molding material, wherein the first molding material extends along a first side of the first interposer and along a first side of the second interposer, wherein the first molding material fills a gap between the first interposer and the second interposer; an underfill material located between the first molding material and the first die; and a second molding material surrounding the first die and surrounding the underfill material. In an embodiment, the first molding material covers a first sidewall of the first interposer away from the second interposer, and the first molding material covers a second sidewall of the second interposer away from the first interposer. In an embodiment, the first molding material covers a first sidewall of the first interposer facing the second interposer and exposes a second sidewall of the first interposer away from the second interposer, wherein the first molding material covers a third sidewall of the second interposer facing the first interposer and exposes a fourth sidewall of the second interposer away from the first interposer. In an embodiment, the semiconductor structure further comprises: a first molding material surrounding the first interposer and surrounding the second interposer; an underfill material between the first interposer and the first die and between the second interposer and the first die, wherein the first molding material surrounds the underfill material, wherein the first molding material and the underfill material have coplanar surfaces; and a second molding material surrounding the first die, wherein the second molding material contacts the coplanar surfaces. In an embodiment, a width of the underfill material decreases as the underfill material extends from the coplanar surface toward the first interposer. In an embodiment, the semiconductor structure further comprises: a substrate attached to a second side of the first interposer and a second side of the second interposer.

[0072] According to an embodiment, a semiconductor structure includes: a redistribution structure; a first interposer located on the redistribution structure; a second interposer located on the redistribution structure and laterally adjacent to the first interposer, wherein the second interposer is spaced apart from the first interposer; and a first die located above the first interposer and above the second interposer, wherein a first die connector of the first die is bonded to a first conductive bump of the first interposer and a second die connector of the first die is bonded to a second conductive bump of the second interposer. In an embodiment, the redistribution structure extends continuously from the first interposer to the second interposer. In an embodiment, the redistribution structure extends beyond the lateral extent of the first interposer and beyond the lateral extent of the second interposer. In an embodiment, a first sidewall of the redistribution structure is aligned with a first sidewall of the first interposer, and a second sidewall of the redistribution structure is aligned with a second sidewall of the second interposer. In an embodiment, the semiconductor structure further includes: a bottom filling material located between the first interposer and the first tube core and between the second interposer and the first tube core; a first molding material located on the redistribution structure, wherein the first molding material surrounds the first interposer, the second interposer and the bottom filling material; and a second molding material located on the first molding material and on the bottom filling material, wherein the second molding material surrounds the first tube core, wherein the bottom filling material has a first width measured at a first interface with the first interposer and has a second width measured at a second interface with the second molding material, wherein the first width is less than the second width.

[0073] According to an embodiment, a method of forming a semiconductor structure includes: placing a first interposer to be laterally adjacent to a second interposer; embedding the first interposer and the second interposer in a first molding material; and bonding a first die to the first interposer and the second interposer, wherein a first die connector of the first die is bonded to a first conductive bump at a first side of the first interposer, and a second die connector of the first die is bonded to a second conductive bump at a first side of the second interposer. In an embodiment, the method further includes: before embedding the first interposer and the second interposer, forming a redistribution structure along a second side of the first interposer and along a second side of the second interposer. In an embodiment, the method further includes: bonding a second die to a second interposer, wherein after bonding the second die, the second die is disposed within a lateral extent of the second interposer. In an embodiment, the method further includes: after bonding the first die, bonding a substrate to a second side of the first interposer and a second side of the second interposer.

[0074] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will be apparent to those skilled in the art with reference to the specification. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A semiconductor structure comprising: First intermediary layer; a second interposer laterally adjacent to the first interposer, wherein the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and to a first side of the second interposer, wherein the first side of the first interposer and the first side of the second interposer face the first die; A first molding material surrounding the first interposer and surrounding the second interposer; an underfill material surrounded by the first molding material, wherein the first molding material and the underfill material have coplanar surfaces; and a second molding material surrounding the first die, wherein the second molding material contacts the coplanar surfaces.

2. The semiconductor structure according to claim 1, wherein: A first portion of the first die is disposed within a lateral extent of the first interposer, and a second portion of the first die is disposed within a lateral extent of the second interposer.

3. The semiconductor structure according to claim 2, further comprising: A second die is attached to the first side of the second interposer, wherein the second die is disposed within a lateral extent of the second interposer.

4. The semiconductor structure according to claim 1, further comprising: A redistribution structure is located at a second side of the first interposer opposite to the first side of the first interposer, wherein the redistribution structure continuously extends from the first interposer to the second interposer.

5. The semiconductor structure according to claim 1, wherein: A first portion of the first die has a first die connector and a second portion of the first die has a second die connector, wherein the first die connector is bonded to a first conductive bump at a first side of the first interposer and the second die connector is bonded to a second conductive bump at a first side of the second interposer.

6. The semiconductor structure according to claim 1, wherein: The first interposer and the second interposer are embedded in the first molding material, wherein the first molding material extends along a first side of the first interposer and along a first side of the second interposer, wherein the first molding material fills a gap between the first interposer and the second interposer, wherein the bottom filling material is located between the first molding material and the first tube core, and the second molding material surrounds the first tube core and surrounds the bottom filling material.

7. The semiconductor structure according to claim 6, wherein: The first molding material covers a first sidewall of the first interposer away from the second interposer, and the first molding material covers a second sidewall of the second interposer away from the first interposer.

8. The semiconductor structure according to claim 6, wherein: The first molding material covers a first sidewall of the first interposer facing the second interposer and exposes a second sidewall of the first interposer away from the second interposer, wherein the first molding material covers a third sidewall of the second interposer facing the first interposer and exposes a fourth sidewall of the second interposer away from the first interposer.

9. The semiconductor structure according to claim 1, wherein: The underfill material is located between the first interposer and the first die and between the second interposer and the first die.

10. The semiconductor structure according to claim 9, wherein: The width of the underfill material decreases as the underfill material extends from the coplanar surface toward the first interposer.

11. The semiconductor structure of claim 1 , further comprising: A substrate is attached to the second side of the first interposer and the second side of the second interposer.

12. A semiconductor structure comprising: Redistribution structure; A first interposer layer, located on the redistribution structure; a second interposer on the redistribution structure and laterally adjacent to the first interposer, wherein the second interposer is spaced apart from the first interposer; and a first die located above the first interposer and above the second interposer, wherein a first die connector of the first die is bonded to a first conductive bump of the first interposer and a second die connector of the first die is bonded to a second conductive bump of the second interposer; an underfill material between the first interposer and the first die and between the second interposer and the first die; a first molding material surrounding the underfill material; and a second molding material on the first molding material and on the underfill material, The underfill material has a first width measured at a first interface with the first interposer and has a second width measured at a second interface with the second molding material, wherein the first width is smaller than the second width.

13. The semiconductor structure according to claim 12, wherein: The redistribution structure continuously extends from the first interposer to the second interposer.

14. The semiconductor structure according to claim 12, wherein: The redistribution structure extends beyond a lateral extent of the first interposer and beyond a lateral extent of the second interposer.

15. The semiconductor structure according to claim 12, wherein: A first sidewall of the redistribution structure is aligned with a first sidewall of the first interposer, and a second sidewall of the redistribution structure is aligned with a second sidewall of the second interposer.

16. The semiconductor structure according to claim 12, wherein: The first molding material is located on the redistribution structure, wherein the first molding material surrounds the first interposer and the second interposer, and wherein the second molding material surrounds the first die.

17. A method of forming a semiconductor structure, the method comprising: placing the first interposer laterally adjacent to the second interposer; embedding the first interposer and the second interposer in a first molding material; as well as bonding a first die to the first interposer and the second interposer, wherein a first die connector of the first die is bonded to a first conductive bump at a first side of the first interposer, and a second die connector of the first die is bonded to a second conductive bump at a first side of the second interposer; Wherein, a first molding material surrounds the first interposer and surrounds the second interposer, a bottom filling material is surrounded by the first molding material, wherein the first molding material and the bottom filling material have coplanar surfaces, and a second molding material surrounds the first tube core, and the second molding material contacts the coplanar surfaces.

18. The method according to claim 17, further comprising: Before embedding the first interposer and the second interposer in the first molding material, a redistribution structure is formed along a second side of the first interposer and along a second side of the second interposer.

19. The method according to claim 18, further comprising: A second die is bonded to the second interposer, wherein after bonding the second die, the second die is disposed within a lateral extent of the second interposer.

20. The method of claim 18, further comprising: After bonding the first die, bonding a substrate to a second side of the first interposer and a second side of the second interposer.

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