Error correction code changes based on memory subsystem wear

Abstract

Data to be stored at a memory subsystem may be received. A usage characteristic of the memory subsystem may be determined. The received data may be encoded to generate a codeword having a plurality of check bits. A portion of the plurality of check bits of the generated codeword may be removed based on the usage characteristic of the memory subsystem. Furthermore, the codeword may be stored without the removed portion of the plurality of check bits.

Description

Technical Field

[0001] The present disclosure relates generally to memory subsystems, and more particularly, to changing error correction codes based on wear of the memory subsystem. Background Art

[0002] The memory subsystem may be a storage system, such as a solid-state drive (SSD) or a hard disk drive (HDD). The memory subsystem may be a memory module, such as a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile dual in-line memory module (NVDIMM). The memory subsystem may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, the host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0003] One aspect of the present application provides a method, the method comprising: receiving data at a memory subsystem; determining a usage characteristic of the memory subsystem; encoding the received data to generate a codeword having a plurality of check bits; removing a portion of the plurality of check bits of the generated codeword based on the usage characteristic of the memory subsystem by a processing device; and storing the codeword without the removed portion of the plurality of check bits.

[0004] Another aspect of the present application provides a system, the system comprising: a memory component; and a processing device operatively coupled to the memory component to perform the following operations: receiving data to be stored at the system; encoding the received data to generate a codeword having a plurality of check bits; removing a portion of the plurality of check bits from the codeword; storing the codeword without the portion of the plurality of check bits; determining that a condition associated with the system has changed; receiving subsequent data to be stored at the system; encoding the subsequent data to generate another codeword having the plurality of check bits; removing a reduced portion of the plurality of check bits from the another codeword, wherein the reduced portion of the plurality of check bits corresponds to a portion of the plurality of check bits removed that is less than the portion of the plurality of check bits of the stored codeword; and storing the another codeword without the reduced portion of the plurality of check bits.

[0005] Another aspect of the present application provides a non-transitory computer-readable medium comprising instructions, which, when executed by a processing device, causes the processing device to perform operations comprising: receiving data to be stored at a memory subsystem; determining usage characteristics of the memory subsystem; encoding the received data to generate a codeword having a plurality of check bits; removing a portion of the plurality of check bits of the generated codeword based on the usage characteristics of the memory subsystem; and storing the codeword without the removed portion of the plurality of check bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0007] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is shown.

[0008] Figure 2A Flowchart of an example method for storing codewords with multiple check bits based on usage or wear characteristics of a memory subsystem in accordance with some embodiments.

[0009] Figure 2B Flowchart of an example method for storing a codeword with multiple check bits based on a change in a condition of a memory subsystem according to some embodiments.

[0010] Figure 3A Storing multiple check bits based on different characteristics indicative of the operating life of the memory subsystem is shown in accordance with some embodiments of the present disclosure.

[0011] Figure 3B Puncturing or storing multiple parity bits based on different characteristics indicative of increased operating life of a memory subsystem according to some embodiments of the present disclosure is shown.

[0012] Figure 4 Flowchart of an example method for generating additional check bits for a codeword based on the number of bits of check data for the codeword according to some embodiments of the present disclosure.

[0013] Figure 5A Reconstruction of punctured check bits according to some embodiments of the present disclosure is shown.

[0014] Figure 5B A write path for storing codewords according to some embodiments of the present disclosure is shown.

[0015] Figure 5C A read path to generate data from a codeword according to some embodiments of the present disclosure is shown.

[0016] Figure 6A block diagram illustrating an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0017] Various aspects of the present disclosure relate to changing error correction codes based on the loss of a memory subsystem. A memory subsystem is also referred to as a "memory device" hereinafter. An example of a memory subsystem is a storage device coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input / output bus, a storage area network). Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, and hard disk drives (HDDs). Another example of a memory subsystem is a memory module coupled to a CPU via a memory bus. Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), non-volatile dual in-line memory modules (NVDIMMs), etc. A memory subsystem may be a hybrid memory / storage subsystem. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem, and may request data to be retrieved from the memory subsystem.

[0018] Conventional memory subsystems may implement error correction and error detection (i.e., error control) operations for data stored at and / or retrieved from memory components of the memory subsystem. Error control operations may encode host data using error correction codes (ECC) and store the encoded host data at the memory subsystem. For example, the host data may be encoded to produce a codeword, and the codeword may be stored at the memory subsystem. Subsequently, when the host system requests the host data, the codeword may be decoded to produce the host data. The encoding and decoding of the error control operations may be used to detect any errors that may have been caused by noise or other such impairments, which may cause the value or bit of the host data to change (e.g., from a '0' value to a '1' value or vice versa) when the host data is stored or read. The detected errors may then be corrected based on the error control operations.

[0019] The error correction codes utilized by the error control operations of the conventional memory subsystem may be designed based on the worst case scenario for data stored at the conventional memory subsystem. For example, as the use or wear of the conventional memory subsystem increases, the error rate present at the stored data may be expected to increase. Therefore, the error correction codes may be designed based on the highest error rate (present at the stored data) that may occur when the conventional memory subsystem is at the end of its working life or has a maximum amount of wear. Such error correction codes may generate a fixed amount of check bits for each data segment to be encoded and stored. The multiple check bits used may result in more bit errors in the data detected and corrected. Since the error rate of the memory subsystem at the beginning of the working life is expected to be lower than the error rate of the memory subsystem at the end of the working life, the fixed amount of check bits used may be overused when encoding data during the beginning of the working life of the conventional memory subsystem.

[0020] Aspects of the present disclosure address the above and other deficiencies by varying the error correction code based on usage or wear of the memory subsystem. For example, the code rate or the number of check bits included in a codeword may be varied over the operating life of the memory subsystem. For example, as wear or usage of the memory subsystem increases and the error rate may be expected to increase, the code rate or the number of check bits included in a codeword for host data to be encoded may increase over time.

[0021] In some embodiments, the polar encoder and polar decoder may be used for error control operations that utilize error correction codes that vary based on the wear of the memory subsystem. For example, host data may be encoded by a polar encoder at a particular moment in the working life of the memory subsystem. The resulting codeword may include a plurality of check bits, and a portion of the check bits of the resulting codeword may be stored. At a subsequent moment in the working life of the memory subsystem, subsequent host data may be received, and the same polar encoder may be used to generate another codeword with the same number of check bits, and then an increased portion of the check bits of the other codeword may be stored at the memory subsystem. Thus, the same polar encoder may be used to generate a codeword with a fixed number of check bits, and a portion of the fixed number of check bits may be stored based on the wear of the memory subsystem. As the wear of the memory subsystem increases, the number of check bits stored with the codeword may increase. In addition, a polar decoder may be used to decode the codeword to generate the resulting host data. In some embodiments, certain check bits may be reconstructed before the codeword is determined by the polar decoder, as described in further detail below.

[0022] Advantages of the present disclosure include, but are not limited to, increasing the utilization of the memory subsystem for storing host data. For example, because the size of the check data can be smaller when the memory subsystem is at the end of its working life, more host data can be stored at the memory subsystem at the beginning of its working life. In addition, because less check data can be written over the working life of the memory subsystem, the durability of the memory subsystem can also be increased because the number of check bits stored gradually increases as the memory subsystem wears out, rather than a fixed large number of check bits. For example, because less check data is written to the memory components over the working life of the memory subsystem, the wear rate of the memory subsystem can be considered to be reduced.

[0023] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is shown. The memory subsystem 110 may include media, such as memory components 112A to 112N. The memory components 112A to 112N may be volatile memory components, non-volatile memory components, or a combination thereof. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage subsystem. In general, the computing environment 100 may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0024] The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110, so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 may further utilize a non-volatile memory (NVM) express (NVMe) interface to access the memory components 112A to 112N. The physical host interface may provide an interface for transmitting control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0025] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of memory components 112A to 112N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more bits of data (e.g., a data block) used by the host system 120. Although non-volatile memory components such as NAND-type flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), or non-(NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, compared to many flash-based memories, the cross-point non-volatile memory may perform write-in-place operations, where the non-volatile memory cells may be programmed without pre-erasing the non-volatile memory cells. In addition, the memory cells of the memory components 112A to 112N may be grouped into memory pages or data blocks, which may refer to cells of a memory component used to store data.

[0026] The memory system controller 115 (hereinafter referred to as the "controller") may communicate with the memory components 112A to 112N to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory components 112A to 112N. The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for executing various programs, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0027] In general, the controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A-112N. The controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory components 112A-112N. The controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory components 112A-112N, and convert responses associated with the memory components 112A-112N into information for the host system 120.

[0028] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory components 112A-112N.

[0029] The memory subsystem 110 includes encoder and decoder components 113 that can be used to encode host data to generate codewords to be stored at the memory components 112A to 112N, and decode codewords to generate host data. In some embodiments, the controller 115 includes at least a portion of the encoder and decoder components 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, the encoder and decoder components 113 are part of the host system 120, an application, or an operating system.

[0030] The encoder and decoder component 113 may receive host data and an indication of the wear or usage of the memory subsystem 110. The host data may be encoded based on the indicated wear or usage of the memory subsystem. For example, multiple check bits of a codeword may be stored based on the wear or usage of the memory subsystem 110. Additional details regarding the operation of the encoder and decoder component 113 are described below.

[0031] Figure 2A Flowchart of an example method 200 for storing codewords with multiple check bits based on usage or wear characteristics of a memory subsystem according to some embodiments. The method 200 may be performed by processing logic that may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 is performed by Figure 1 The encoder and decoder components 113 are executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the processes can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0032] like Figure 2AAs shown in , at operation 201, processing logic receives data to be stored at a memory subsystem. For example, a host system may provide host data to be stored at the memory subsystem. At operation 202, processing logic determines a usage characteristic of the memory subsystem. The usage characteristic may be based on a write count of the memory subsystem, where the write count indicates the number of write operations that have been performed by the memory subsystem. In some embodiments, the usage characteristic may indicate an average bit error rate of data recently read from the memory subsystem or a retry rate of error correction of data recently read from the memory subsystem. The retry rate may identify the number of error correction cycles that have been performed when an error correction operation has failed. The usage characteristic may be any indication of the working life of the memory subsystem. In combination Figure 2B Describe other details of the usage characteristics. In some embodiments, the usage characteristics may indicate the operating conditions of the memory subsystem. For example, the usage characteristics may indicate the current operating temperature or other environmental conditions of the memory subsystem.

[0033] At operation 203, processing logic encodes the received data to generate a codeword having a plurality of check bits. For example, a polar encoder may be used to generate a codeword having a defined number of check bits, as described below with respect to Figure 2B Further detailed description. At operation 204, processing logic removes a portion of the plurality of check bits of the generated codeword based on the usage characteristics of the memory subsystem. For example, a specific number of check bits may be removed from the generated codeword based on the usage characteristics of the memory subsystem. As further detailed description is provided below, as the usage or wear of the memory subsystem increases, fewer check bits may be removed from the generated codeword. Therefore, as the wear or usage of the memory subsystem increases, the codeword may be stored with more check bits. At operation 205, processing logic stores the codeword without the removed portion of the plurality of check bits. Therefore, the number of check bits stored with the codeword may be based on the usage or wear of the memory subsystem. As the usage or wear of the memory subsystem changes, the number of check bits stored with the codeword may also change.

[0034] Figure 2B Flowchart of an example method 250 for storing a codeword with multiple check bits based on a change in a condition of a memory subsystem according to some embodiments of the present disclosure. The method 250 may be performed by a processing logic that may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 250 is performed by Figure 1The encoder and decoder components 113 are executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the processes can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0035] like Figure 2B , at operation 251, processing logic receives data to be stored at a memory subsystem. For example, a host system may provide data to be stored at a memory subsystem (i.e., host data). At operation 252, processing logic encodes the data to generate a codeword having a plurality of check bits. For example, an encoding operation may be performed on the data to generate a codeword having a plurality of check bits. The encoding operation may be a linear transformation of the data. For example, an encoding operation may be performed on data having a particular number of bits, and a linear transformation may be performed on the data to generate a codeword having an increased number of bits. Examples of such encoding operations include, but are not limited to, polar codes or polar encoding operations. A polar code may be a linear block error correction code that applies a matrix to data to convert the data into a codeword. The check bits of a codeword may be additional bits used to detect and correct any errors when the codeword is retrieved later. In some embodiments, the check bits may be based on or calculated by the values ​​of the bits of the data to be encoded. Thus, a codeword may include encoded data and check bits for the data.

[0036] At operation 253, processing logic stores the codeword with the reduced portion of check bits. For example, a subset (i.e., a proper subset) of the check bits generated as part of the codeword may be stored. Thus, a portion of the codeword corresponding to a portion of the encoded data and the check bits may be stored at the memory subsystem. In some embodiments, the portion of the check bits may be selected based on usage or wear characteristics or conditions of the memory subsystem. The selection of the check bits to be stored may be performed by puncturing, which refers to removing certain check bits after encoding with an error correction code (e.g., a polar code).

[0037] The check bits may be punctured or removed based on a characteristic or condition of the memory subsystem. The characteristic may indicate the wear or usage of the working life of the memory subsystem. For example, the wear may be the number of total write operations that have been performed at the memory subsystem. In some embodiments, the characteristic may indicate an average bit error rate of data recently read from the memory subsystem. In the same or alternative embodiments, the characteristic may indicate a retry rate for error correction of data recently read from the memory subsystem. The retry rate may be based on modified read operations of data that were not successfully corrected by error control operations. For example, the retry rate may identify the rate at which repeated modified read operations are used to retrieve data in response to failed error control operations. Any other characteristic that indicates the working life or operating condition of the memory subsystem may be used to puncture the check bits.

[0038] As shown at operation 254, processing logic determines that a condition of the memory subsystem has changed. The change in condition may be based on a characteristic of the memory subsystem satisfying a threshold condition. For example, the condition of the memory subsystem may be considered to have changed when the number of write operations performed by the memory subsystem exceeds a particular write count threshold or a threshold condition associated with a threshold number of write counts. In some embodiments, the condition of the memory subsystem may be considered to have changed when an average bit error rate exceeds a particular bit error rate threshold or when a retry rate of error correction exceeds a particular retry rate threshold. The condition of the memory subsystem may be considered to have changed over the working life of the memory subsystem as the number of write operations performed increases to satisfy a write threshold condition (e.g., meets or exceeds a write threshold number), the average bit error rate increases to satisfy a bit error rate threshold, and / or the retry rate of error correction increases to satisfy a retry rate threshold. Various thresholds may be considered to have been satisfied when corresponding characteristics meet or exceed corresponding thresholds.

[0039] At operation 255, processing logic receives additional data to be stored at the memory subsystem. For example, subsequent host data may be received from the host system after the condition of the memory subsystem changes. At operation 256, processing logic encodes the additional data to generate another codeword having multiple check bits. For example, polar encoding may be performed on the additional data to generate another codeword including the same number of check bits as the codeword generated before the memory subsystem condition changes. Thus, the same polar encoder may be used to generate another codeword. At operation 257, processing logic stores another codeword having an increased portion of the multiple check bits based on the change in the memory subsystem condition. For example, the another codeword may be stored with more check bits than the codeword stored before the memory subsystem condition changes. Thus, fewer check bits may be punctured or removed relative to the codeword stored before the memory subsystem condition changes. In combination Figure 3B Additional details regarding puncturing of check bits are described.

[0040] Thus, codewords may be stored with check bits based on a condition or characteristic of the memory subsystem. At a first moment in the working life of the memory subsystem, the codeword may be stored with a first number of check bits. When the condition of the memory subsystem changes, a second moment in the working life of the memory subsystem may be detected. At the second moment in the working life of the memory subsystem, the codeword may be stored with a second number of check bits that is greater than the first number of check bits stored with the codeword at the first moment in the working life of the memory subsystem.

[0041] Figure 3A The storage of multiple check bits based on different characteristics indicative of the working life of the memory subsystem according to some embodiments of the present disclosure is shown. The storage of the check bits may be performed by processing logic that may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the check bits are selected to be stored or by Figure 1 The encoder and decoder components 113 perform redundancy.

[0042] like Figure 3A As shown in , the amount of check data stored for host data can increase as the working life of the memory subsystem increases. For example, at the first part of the working life of the memory subsystem, codeword 310 can be generated by polar encoding operations to generate encoded host data 1 and multiple check bits. A portion of the multiple check bits of codeword 310 can be punctured so that check data 1 is stored in the codeword. Since check data 1 is smaller, it can be considered that more check bits from the multiple check bits are punctured. Over time, a second part of the working life of the memory subsystem can be reached. For example, a specific condition or characteristic of the memory subsystem can meet a threshold condition for the second part of the working life. Host data 2 can be received and encoded to generate encoded host data 2 and the same number of check bits. However, as shown, the portion of the multiple check bits stored with codeword 311 can increase. For example, fewer check bits can be punctured relative to the check bits of codeword 310. Therefore, the size of the check data of the codeword generated during the second part of the working life of the memory subsystem can be increased. The increased size of the check data of the codeword may result in an increased ability to correct more bit errors of the host data compared to codewords with smaller check data. Since additional errors may be expected when compared to an earlier portion of the operating life of the memory subsystem, the size of the check data may be increased by puncturing fewer check bits at a later second portion of the operating life of the memory subsystem to allow for enhanced error correction of the host data.

[0043] In addition, as the working life of the memory subsystem elapses, the condition or characteristic of the memory subsystem may satisfy another threshold condition for a subsequent third portion of the working life of the memory subsystem. Host data 3 may be received and encoded using a polar encoder to generate encoded host data 3 and the same number of check bits. However, the portion of the plurality of check bits stored with codeword 312 may increase relative to both the first portion and the second portion of the working life of the memory subsystem. As shown, the size of check data 3 may increase as the working life of the memory subsystem increases.

[0044] Figure 3B The present disclosure shows that a plurality of check bits are punctured or stored based on different characteristics indicating an increase in the working life of the memory subsystem according to some embodiments of the present disclosure. The puncturing or storage of the check bits may be performed by processing logic that may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the check bits are selected to be stored or stored by Figure 1 The encoder and decoder components 113 perform redundancy.

[0045] like Figure 3B As shown in , the number of punctured check bits can be reduced over time so that more check bits are stored with the codeword as the working life of the memory subsystem increases. For example, as shown, the polar encoder can generate a codeword with check bits 0 to N. For example, when encoding host data, 200 check bits can be generated by the polar encoder. In some embodiments, 100 of the 200 check bits can be punctured at a first moment in the working life of the memory subsystem. For example, at the initial moment of the working life, the maximum number of check bits can be punctured. As the working life of the memory subsystem increases, fewer check bits can be punctured or removed. For example, at an intermediate moment in the working life of the memory subsystem, 50 of the 200 check bits can be punctured. Subsequently, for the end of the working life of the memory subsystem, the minimum number of check bits can be punctured. For example, no check bits can be punctured.

[0046] In some embodiments, puncturing of bits may be nested between different portions of the operating life of a memory subsystem. For example, at a first time, particular bit positions of check data may be punctured such that check data at a first subset of bit positions of the check data is stored, while check data at a second subset of bit positions of the check data is not stored. At a subsequent time when the number of stored check bits increases, corresponding check data at the same first subset of bit positions may be stored along with corresponding check data at portions of the positions of the second subset of bit positions that were previously punctured. Thus, as the operating life of the memory subsystem increases, the check data at the punctured bit positions may gradually become unpunctured as the check data is stored at the memory subsystem.

[0047] Thus, the same decoder structure (e.g., the same polar decoder) may be used throughout the operating life of the memory subsystem as the code rate changes. For example, the same decoder structure or design may be used as the order in which the check bits are punctured in a nested scheme. Thus, different decoder structures or designs do not utilize different puncturing patterns (e.g., different positions or orders in which the check bits are punctured) as the code rate changes. Thus, using a nested scheme for puncturing the check bits may result in a single structure or design of the decoder, which may further result in fewer memory resources being utilized by the decoder since multiple different puncturing patterns do not need to be stored.

[0048] Figure 4 Flowchart of an example method 400 for generating additional check bits for a codeword based on the number of bits of check data for the codeword according to some embodiments of the present disclosure. The method 400 may be performed by processing logic that may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by Figure 1 The encoder and decoder components 113 are executed. Although shown in a specific order or sequence, unless otherwise specified, the order of the processes can be modified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0049] like Figure 4, at operation 410, processing logic retrieves a codeword stored at a memory subsystem. The codeword may be retrieved in response to a read operation from a host system that specifies host data that was previously encoded into the codeword. As previously described, the codeword may include a first portion corresponding to the encoded host data and a second portion corresponding to a portion of a check bit of the encoded host data. At operation 420, processing logic determines check data for the codeword. For example, a portion of the codeword that includes a check bit may be identified. In some embodiments, a predefined or specified portion of the codeword may include the encoded host data, and another specified portion may include the check data. For example, the encoded host data may be located at a defined number of bits at the beginning of the codeword. Any bits after the defined number of bits at the beginning of the codeword may be check bits for check data stored in the codeword after puncturing as previously described.

[0050] At operation 430, processing logic generates additional check bits based on the number of bits of check data for the codeword. For example, the check bits that were punctured or removed may be reconstructed or generated. In some embodiments, the number of reconstructed additional check bits may be based on the number of bits of check data for the codeword. For example, multiple additional check bits may be generated so that the number of additional check bits combined (i.e., added to) the multiple check bits of check data for the retrieved codeword matches the total number of check bits of check data originally generated for the host data corresponding to the encoded host data for the codeword. In some embodiments, the additional check bits may be generated based on other bits and the structure of the encoder used to encode the data for the codeword. For example, the values ​​of the additional check bits may be generated or reconstructed during a decoding operation by utilizing the values ​​of other bits (e.g., other bits of the codeword) and any constraints between bits utilized by the coding scheme used (e.g., polar codes). In combination Figure 5A Additional details regarding the reconstruction of the check bits are described.

[0051] like Figure 4, at operation 440, processing logic decodes the codeword with the additional check bits to produce host data. For example, a polar decoder may be used to decode the codeword with the additional check bits. For example, a combination of the additional check bits that have been punctured may be combined with check bits that have not been punctured and bits of the host data, and a decoding operation may be performed on the combination of bits and the value of the additional check bits may be reconstructed simultaneously. In some embodiments, if the combination of bits is successfully decoded, it may be assumed that the additional check bits have been accurately reconstructed. Otherwise, if the combination of bits is not successfully decoded, the additional check bits may not be correctly reconstructed. In such cases where the decoding operation is unsuccessful for the reconstructed check bits, a different value of the additional check bits may be tentatively reconstructed again, and a decoding operation may be performed with the new combination of bits. The polar decoder may decode the codeword to produce host data and corresponding check data for the host data. In addition, at operation 450, processing logic returns the host data to the host system. For example, the host data decoded from the codeword may be returned to the host system in response to a read request from the host system.

[0052] Figure 5A 1 shows a reconstruction of punctured check bits according to some embodiments of the present disclosure. The reconstruction of punctured check bits may be performed by processing logic that may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the check bits are Figure 1 The encoder and decoder components 113 are reconstructed.

[0053] like Figure 5A , odd parity data 501 may include multiple parity bits. For example, a location of parity data 501 having a '0' or a '1' may represent a value of generated parity data that is not punctured and therefore stored in a codeword as previously described. A location of parity data 501 having an 'X' may represent a bit location of generated parity data in a codeword that is punctured and therefore not stored at a memory subsystem. A codeword having parity data 501 may be retrieved, and the parity bits at the locations having the 'X' may be reconstructed during decoding by a polar decoder. For example, as shown, parity data 502 may represent parity data 501 having reconstructed punctured parity bits. The total number of bits at parity data 502 may represent the total number of bits generated for parity data by a polar encoder for corresponding host data for a codeword including parity data 501. Thus, the punctured parity bits may be reconstructed or regenerated to reflect the parity data previously generated by a polar encoder for host data.

[0054] Figure 5B1 shows a write path for storing codewords according to some embodiments of the present disclosure. The operations of the write path may be performed by processing logic that may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the operations of the write path are performed by Figure 1 The encoder and decoder components 113 are executed.

[0055] like Figure 5B , host data may be received. In some embodiments, a cyclic redundancy check (CRC) may be performed on the host data to generate data received by the polar encoder 510. The polar encoder 510 may generate a codeword including the encoded data and a plurality of check bits. A check bit puncturing operation 511 may puncture a portion of the plurality of check bits based on the characteristics of the memory subsystem as previously described. Thus, the input to the check bit puncturing operation 511 may be greater than the output of the check bit puncturing operation 511. The output of the polar encoder 510 that has been punctured may then be stored at a memory component 512 of the memory subsystem.

[0056] Figure 5C 1 shows a read path for generating data from a codeword according to some embodiments of the present disclosure. The operations of the read path may be performed by processing logic that may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the operations of the read path are performed by Figure 1 The encoder and decoder components 113 are executed.

[0057] like Figure 5C , a stored codeword with check bits (e.g., non-punctured or non-removed check bits) may be retrieved from memory component 512. A check bit reconstruction operation 521 may receive the stored codeword and may utilize information of the decoding operation of polar decoder 520 as previously described to reconstruct the punctured check bits. Thus, the input to check bit reconstruction operation 521 may be less than the output of check bit reconstruction operation 521. Subsequently, the codeword with added check bits may be decoded by polar decoder 520 to produce host data to be returned to the host system.

[0058] Figure 6 An example machine of a computer system 600 is shown in which a set of instructions may be executed for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 1) a host system 120 that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, to run the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0059] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge or a non-digital circuit system, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is shown, the term "machine" should also be construed to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0060] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618 that communicate with each other via a bus 630.

[0061] Processing device 602 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a processor that implements a combination of instruction sets. Processing device 602 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 to communicate on a network 620.

[0062] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution thereof by the computer system 600, the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0063] In one embodiment, instructions 626 include implementing instructions corresponding to encoder and decoder components (e.g., Figure 1 The machine-readable storage medium 624 is shown as a single medium in the example embodiment, but the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executed by a machine and causing the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0064] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to other skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of operations that produce a desired result. Operations are those that require physical manipulation of physical quantities. These quantities are typically, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Mainly for common reasons, it has proven to be convenient at times to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0065] It should be borne in mind, however, that all of these and similar terms should be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0066] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as but not limited to any type of disk, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical card, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus, including a floppy disk, an optical disk, a compact disc read-only memory (CD-ROM), and a magnetic optical disk.

[0067] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used with the program according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the method. The structures for various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0068] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0069] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method performed by a memory subsystem, the method comprising: receiving data at the memory subsystem; determining a usage characteristic of the memory subsystem; encoding the received data to generate a codeword having a plurality of check bits; removing, by a processing device, a portion of the plurality of check bits of the generated codeword based on the usage characteristics of the memory subsystem; as well as storing the codeword without the removed portion of the plurality of check bits, wherein the usage characteristic corresponds to a write count of the memory subsystem, and wherein removing the portion of the plurality of check bits comprises: determining whether the write count of the memory subsystem satisfies a threshold condition associated with a threshold number of write counts; as well as Removing a reduced portion of the plurality of check bits of the generated codeword in response to the write count of the memory subsystem satisfying the threshold condition associated with the threshold number of write counts, and removing an increased portion of the plurality of check bits of the generated codeword in response to the write count of the memory subsystem not satisfying the threshold condition associated with the threshold number of write counts, and wherein the reduced portion includes fewer bits than the increased portion.

2. The method of claim 1, wherein the encoding of the received data to generate the codeword having the plurality of check bits is based on a polar encoder.

3. The method of claim 1, wherein the removing the reduced portion of the plurality of check bits corresponds to the stored codeword having more check bits than the stored codeword without the increased portion of the plurality of check bits.

4. The method according to claim 1, further comprising: receiving a request for the data from a host system; retrieving the stored codeword without the removed portion of the plurality of check bits; reconstructing the removed portion of the plurality of check bits; as well as The codeword with the reconstructed parity bits is decoded.

5. The method of claim 4, wherein the decoding of the codeword with the reconstructed parity bits is based on a polar decoder.

6. A method performed by a memory subsystem, the method comprising: receiving data at the memory subsystem; determining a usage characteristic of the memory subsystem; encoding the received data to generate a codeword having a plurality of check bits; removing, by a processing device, a portion of the plurality of check bits of the generated codeword based on the usage characteristics of the memory subsystem; as well as storing the codeword without the removed portion of the plurality of check bits, wherein the usage characteristic corresponds to an operating life of the memory subsystem, and wherein removing the portion of the plurality of check bits comprises: determining whether the operating life of the memory subsystem satisfies a threshold condition; Removing a reduced portion of the plurality of check bits of the generated codeword in response to the operating lifetime of the memory subsystem satisfying the threshold condition, and removing an increased portion of the plurality of check bits of the generated codeword in response to the operating lifetime of the memory subsystem not satisfying the threshold condition, and wherein the reduced portion includes fewer bits than the increased portion.

7. A memory subsystem, the memory subsystem comprising: Memory components; as well as A processing device operatively coupled to the memory component to perform the following operations: receiving data to be stored at the memory subsystem; determining a usage characteristic of the memory subsystem; encoding the received data to generate a codeword having a plurality of check bits; removing a portion of the plurality of check bits from the codeword based on the usage characteristics of the memory subsystem; as well as storing the codeword without the removed portion of the plurality of check bits; wherein the usage characteristic corresponds to a write count of the memory subsystem, and wherein removing the portion of the plurality of check bits comprises: determining whether the write count of the memory subsystem satisfies a threshold condition associated with a threshold number of write counts; as well as Removing a reduced portion of the plurality of check bits of the generated codeword in response to the write count of the memory subsystem satisfying the threshold condition associated with the threshold number of write counts, and removing an increased portion of the plurality of check bits of the generated codeword in response to the write count of the memory subsystem not satisfying the threshold condition associated with the threshold number of write counts, and wherein the reduced portion includes fewer bits than the increased portion.

8. The memory subsystem of claim 7, wherein the encoding of the received data to produce the codeword is based on a polar encoder.

9. The memory subsystem of claim 7, wherein the processing device further performs the following operations: receiving a request for the data from a host system; retrieving the stored codeword without the portion of the plurality of check bits; reconstructing the removed portion of the plurality of check bits; as well as The codeword with the reconstructed check bits is decoded by a polar decoder.

10. A memory subsystem, the memory subsystem comprising: Memory components; as well as A processing device operatively coupled to the memory component to perform the following operations: receiving data to be stored at the memory subsystem; determining a usage characteristic of the memory subsystem; encoding the received data to generate a codeword having a plurality of check bits; removing a portion of the plurality of check bits from the codeword based on the usage characteristics of the memory subsystem; storing the codeword without the removed portion of the plurality of check bits; wherein the usage characteristic corresponds to an operating life of the memory subsystem, and wherein removing the portion of the plurality of check bits comprises: determining whether the operating life of the memory subsystem satisfies a threshold condition; Removing a reduced portion of the plurality of check bits of the generated codeword in response to the operating lifetime of the memory subsystem satisfying the threshold condition, and removing an increased portion of the plurality of check bits of the generated codeword in response to the operating lifetime of the memory subsystem not satisfying the threshold condition, and wherein the reduced portion includes fewer bits than the increased portion.

11. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving data to be stored at the memory subsystem; determining a usage characteristic of the memory subsystem; encoding the received data to generate a codeword having a plurality of check bits; removing a portion of the plurality of check bits of the generated codeword based on the usage characteristics of the memory subsystem; as well as storing the codeword without the removed portion of the plurality of check bits, wherein the usage characteristic corresponds to a write count of the memory subsystem, and wherein to remove the portion of the plurality of parity bits, the operations further comprise: determining whether the write count of the memory subsystem satisfies a threshold condition associated with a threshold number of write counts; as well as Removing a reduced portion of the plurality of check bits of the generated codeword in response to the write count of the memory subsystem satisfying the threshold condition associated with the threshold number of write counts, and removing an increased portion of the plurality of check bits of the generated codeword in response to the write count of the memory subsystem not satisfying the threshold condition associated with the threshold number of write counts, and wherein the reduced portion includes fewer bits than the increased portion.

12. The non-transitory computer-readable medium of claim 11, wherein the encoding of the received data to generate the codeword having the plurality of parity bits is based on a polar encoder.

13. The non-transitory computer-readable medium of claim 11, wherein the removing the reduced portion of the plurality of parity bits corresponds to a stored codeword having more parity bits than the stored codeword without the increased portion of the plurality of parity bits.

14. The non-transitory computer-readable medium of claim 11, wherein the operations further comprise: receiving a request for the data from a host system; retrieving the stored codeword without the removed portion of the plurality of check bits; reconstructing the removed portion of the plurality of check bits; as well as The codeword with the reconstructed parity bits is decoded.

15. The non-transitory computer-readable medium of claim 14, wherein the decoding of the codeword with the reconstructed parity bits is based on a polar decoder.

16. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving data to be stored at the memory subsystem; determining a usage characteristic of the memory subsystem; encoding the received data to generate a codeword having a plurality of check bits; removing a portion of the plurality of check bits of the generated codeword based on the usage characteristics of the memory subsystem; as well as storing the codeword without the removed portion of the plurality of check bits, wherein the usage characteristic corresponds to an operating life of the memory subsystem, and wherein removing the portion of the plurality of check bits comprises: determining whether the operating life of the memory subsystem satisfies a threshold condition; Removing a reduced portion of the plurality of check bits of the generated codeword in response to the operating lifetime of the memory subsystem satisfying the threshold condition, and removing an increased portion of the plurality of check bits of the generated codeword in response to the operating lifetime of the memory subsystem not satisfying the threshold condition, and wherein the reduced portion includes fewer bits than the increased portion.

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