Deflection measurement using combined optical and electron beam techniques

Abstract

The present invention discloses an offset metrology system for manufacturing semiconductor device wafers, comprising: an optical offset metrology tool configured to measure an offset at at least one target between two layers of semiconductor devices selected from a batch of semiconductor device wafers intended to be the same; an electron beam offset metrology tool configured to measure an offset at the at least one target between two layers of semiconductor devices selected from the batch; and a combiner operable to combine outputs of the optical offset metrology tool and the electron beam offset metrology tool to provide a combined offset metric.

Description

[0001] Cross-reference to related applications

[0002] Reference is made to U.S. Provisional Patent Application No. 62 / 806,226, filed on February 15, 2019, and entitled “NOVEL APPROACH FOR ACCURATE OVL USING COMBINE OPTICAL AND EBEAM TECHNOLOGY,” the disclosure of which is hereby incorporated by reference and the benefit of priority of which is hereby claimed.

[0003] Reference is also made to the following patents and patent applications, which are related to the subject matter of this application, the disclosures of which are hereby incorporated by reference:

[0004] U.S. patent application Ser. No. 15 / 979,336, filed May 14, 2018, entitled “OVERLAY MEASUREMENTS OF OVERLAPPING TARGET STRUCTURES BASED ON SYMMETRY OF SCANNING ELECTRON BEAM SIGNALS”;

[0005] Applicant’s U.S. Patent No. 9,093,458, entitled “DEVICE CORRELATED METROLOGY (DCM) FOR OVL WITH EMBEDDED SEM STRUCTURE OVERLAY TARGETS,” issued on July 28, 2015;

[0006] Applicant’s U.S. Patent No. 8,330,281, entitled “OVERLAYMARKS, METHODS OF OVERLAY MARK DESIGN AND METHODS OF OVERLAY MEASUREMENTS,” issued on December 11, 2012; and

[0007] Applicant's U.S. Patent No. 7,317,531, entitled “APPARATUS AND METHODS FOR DETECTING OVERLAY ERRORS USING SCATTEROMETRY,” issued on January 8, 2008. Technical Field

[0008] The present invention relates to the field of metrology, and more particularly to offset metrology processes. Background Art

[0009] Various types of devices are known for metering and offset metering processes. Summary of the Invention

[0010] The present invention seeks to provide improved offset measurement systems and methods.

[0011] Therefore, according to a preferred embodiment of the present invention, there is provided an offset metrology system for manufacturing semiconductor device wafers, comprising: an optical offset metrology tool configured to measure an offset at at least one target between two layers of semiconductor devices selected from a batch of semiconductor device wafers intended to be the same; an electron beam offset metrology tool configured to measure an offset at the at least one target between two layers of semiconductor devices selected from the batch; and a combiner operable to combine outputs of the optical offset metrology tool and the electron beam offset metrology tool to provide a combined offset metric.

[0012] Preferably, the optical offset metrology tool comprises a scatterometry metrology tool. Alternatively, the optical offset metrology tool comprises an imaging metrology tool.

[0013] According to a preferred embodiment of the present invention, the optical offset metrology tool and the electron beam offset metrology tool each measure the offset between two layers of a single semiconductor device. Alternatively, the optical offset metrology tool and the electron beam offset metrology tool each measure the offset between two layers of different semiconductor device wafers selected from the batch.

[0014] According to another preferred embodiment of the present invention, a method for manufacturing semiconductor device wafers is also provided, which includes: performing at least an initial stage of a lithography process on at least one semiconductor device wafer selected from a batch of semiconductor device wafers intended to be the same; thereafter measuring the offset of at least two layers of at least one semiconductor device wafer selected from the batch of semiconductor device wafers intended to be the same by: using an optical offset metrology tool to measure the offset at at least one target between the two layers of at least one of the at least one semiconductor device wafer selected from the batch of semiconductor device wafers intended to be the same; using an electron beam offset metrology tool to measure the offset at at least one target between the two layers of at least one of the at least one semiconductor device wafer selected from the batch of semiconductor device wafers intended to be the same; and combining the outputs of the optical offset metrology tool and the electron beam offset metrology tool to provide a combined offset metric; and using the combined offset metric to adjust the lithography process to provide an adjusted lithography process.

[0015] According to a preferred embodiment of the present invention, measuring the offset includes using the optical offset metrology tool and the electron beam offset metrology tool to measure the offset between two layers of a single semiconductor device. Alternatively, measuring the offset includes using the optical offset metrology tool and the electron beam offset metrology tool to measure the offset between two layers of different semiconductor device wafers selected from the batch.

[0016] According to a preferred embodiment of the present invention, the adjusted photolithography process includes the initial stage in the photolithography process. In addition, the method further includes performing photolithography rework using the adjusted photolithography process.

[0017] Preferably, the adjusted lithographic process comprises a phase in the lithographic process that is different from the initial phase in the lithographic process.

[0018] According to a preferred embodiment of the present invention, the method further includes performing photolithography on an additional semiconductor device having a configuration intended to be the same as that of the semiconductor device using the adjusted photolithography process.

[0019] According to a preferred embodiment of the present invention, the method further comprises utilizing the combined offset metric to adjust at least one of a measurement parameter and a result of the optical offset metrology tool. Additionally or alternatively, the method also comprises utilizing the combined offset metric to adjust at least one of a measurement parameter and a result of the electron beam offset metrology tool.

[0020] According to a preferred embodiment of the present invention, the optical offset metrology tool comprises a scatterometry metrology tool.Alternatively or additionally, the optical offset metrology tool comprises an imaging metrology tool.

[0021] Preferably, at least the initial stage of performing a photolithography process on at least one semiconductor device wafer includes: performing a photolithography process on at least one semiconductor device selected from a batch of semiconductor device wafers intended to be the same; thereafter measuring the post-photolithography offset of at least two layers of at least one semiconductor device selected from the batch of semiconductor device wafers intended to be the same; and thereafter performing an etching process on at least one semiconductor device selected from the batch of semiconductor device wafers intended to be the same.

[0022] Preferably, measuring the offset includes employing the optical offset metrology tool and the electron beam offset metrology tool to measure the offset between two layers of a single semiconductor device. Alternatively, measuring the offset includes employing the optical offset metrology tool and the electron beam offset metrology tool to measure the offset between two layers of different semiconductor device wafers selected from the batch.

[0023] According to a preferred embodiment of the present invention, the method further includes performing photolithography on an additional semiconductor device having a configuration intended to be the same as that of the semiconductor device using the adjusted photolithography process.

[0024] According to a preferred embodiment of the present invention, the optical migration metrology tool comprises a scatterometry metrology tool. Alternatively, the optical migration metrology tool comprises an imaging metrology tool.

[0025] Preferably, the method further comprises utilizing the combined offset metric to adjust at least one of a measurement parameter and a result of measuring post-lithographic offset. Additionally or alternatively, the method further comprises utilizing the combined offset metric to adjust at least one of a measurement parameter and a result of an optical offset metrology tool. Alternatively or additionally, the method further comprises utilizing the combined offset metric to adjust at least one of a measurement parameter and a result of an electron beam offset metrology tool.

[0026] According to a preferred embodiment of the present invention, measuring the post-lithography offset includes employing an optical offset metrology tool to measure the offset at at least one target between two layers selected from at least one of the at least one semiconductor device wafers of the batch of semiconductor device wafers intended to be the same. Additionally or alternatively, measuring the post-lithography offset includes employing an electron beam offset metrology tool to measure the offset at at least one target between two layers selected from at least one of the at least one semiconductor device wafers of the batch of semiconductor device wafers intended to be the same. Alternatively or additionally, measuring the post-lithography offset includes: employing a post-lithography optical offset metrology tool to measure the offset at at least one target between two layers selected from at least one of the at least one semiconductor device wafers of the batch of semiconductor device wafers intended to be the same; employing a post-lithography electron beam offset metrology tool to measure the offset at at least one target between the two layers selected from at least one of the at least one semiconductor device wafers of the batch of semiconductor device wafers intended to be the same; and combining the outputs of the post-lithography optical offset metrology tool and the post-lithography electron beam offset metrology tool to provide a combined offset metric.

[0027] According to another preferred embodiment of the present invention, there is further provided a target for use in measuring offset in the manufacture of semiconductor devices, the target comprising: a first periodic structure formed on a first layer of the semiconductor device; having a first pitch along an axis; and a second periodic structure formed on a second layer of the semiconductor device and having a second pitch along an axis parallel to the axis, the target being characterized in that it includes at least one first region that is particularly suitable for optical metrology and at least one second region separated from the at least first region that is particularly suitable for electron beam metrology.

[0028] Preferably, in at least one portion of the at least one first region, the first periodic structure exists and the second periodic structure does not exist. Additionally or alternatively, in at least one second portion of the at least one first region, the first periodic structure does not exist and the second periodic structure exists.

[0029] According to a preferred embodiment of the present invention, both the first periodic structure and the second periodic structure exist in the at least one second region.

[0030] According to a preferred embodiment of the present invention, in the at least one second region, there are a third periodic structure and a fourth periodic structure. Alternatively, in the at least one second region, there is one of the first periodic structure and the second periodic structure and there is a third periodic structure.

[0031] According to a preferred embodiment of the present invention, in the at least one second region, the first periodic structure and the second periodic structure partially overlap. Additionally or alternatively, in the at least one second region, the third periodic structure and the fourth periodic structure partially overlap.

[0032] Preferably, in the at least one second region, the one of the first periodic structure and the second periodic structure and the third periodic structure partially overlap.

[0033] According to a preferred embodiment of the present invention, different portions of the first periodic structure and the second periodic structure partially overlap to different degrees.

[0034] According to a preferred embodiment of the present invention, different portions of the third periodic structure and the fourth periodic structure partially overlap to different degrees.

[0035] According to a preferred embodiment of the present invention, different portions of the one of the first periodic structure and the second periodic structure and the third periodic structure partially overlap to different degrees.

[0036] Preferably, at least one of the first periodic structure and the second periodic structure comprises a plurality of periodic substructures. Additionally or alternatively, at least one of the third periodic structure and the fourth periodic structure comprises a plurality of periodic substructures.

[0037] According to a preferred embodiment of the present invention, in the at least one second region, the first periodic structure and the second periodic structure do not overlap.

[0038] According to a preferred embodiment of the present invention, in the at least one second region, the third periodic structure and the fourth periodic structure do not overlap. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The present invention will be more fully understood and appreciated from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0040] Figure 1A is a simplified schematic perspective illustration of a first method for manufacturing a semiconductor device wafer;

[0041] Figure 1B is with Figure 1A The enlarged circle B in the figure corresponds to the enlarged circle B, which is used for Figure 1A A simplified schematic perspective illustration of an offset metrology system for use in a method of manufacturing a semiconductor device wafer;

[0042] Figure 2A and 2B Together is an explanation Figure 1A and1B A simplified flow chart of a first method for manufacturing a semiconductor device wafer;

[0043] Figure 3A is a simplified schematic perspective illustration of a second method for manufacturing a semiconductor device wafer;

[0044] Figure 3B is with Figure 3A The enlarged circle B in the figure corresponds to the enlarged circle B, which is used for Figure 3A A simplified schematic perspective illustration of an offset metrology system for use in a method of manufacturing a semiconductor device wafer;

[0045] Figure 4A and 4B Together is an explanation Figure 3A and 3B a simplified flow chart of a second method for manufacturing a semiconductor device wafer;

[0046] Figures 5A to 5D It is a combination of display Figures 1A to 4B Simplified illustrations of four alternative embodiments of a first hybrid target used in a method for manufacturing a semiconductor device wafer;

[0047] Figures 6A to 6D It is a combination of display Figures 1A to 4B Simplified illustrations of four alternative embodiments of a second hybrid target used in a method for manufacturing a semiconductor device wafer;

[0048] Figures 7A to 7D It is a combination of display Figures 1A to 4B Simplified illustrations of four alternative embodiments of a third hybrid target for use in a method of manufacturing a semiconductor device wafer; and

[0049] Figures 8A to 8D It is a combination of display Figures 1A to 4B Simplified illustrations of four alternative embodiments of a method for fabricating a semiconductor device wafer using a fourth hybrid target. DETAILED DESCRIPTION

[0050] Reference Figure 1A , which is a simplified schematic diagram of a first method 100 for manufacturing a semiconductor device wafer. Figure 1A As seen in FIG, at least one semiconductor device wafer 102 selected from a batch of semiconductor device wafers (BSDWII) 104 intended to be the same is patterned at a first photolithography stage 110. It should be understood that although BSDWII 104 is drawn with twelve semiconductor device wafers 102, BSDWII 104 may include any number of semiconductor device wafers 102 greater than or equal to one.

[0051] After patterning at the first photolithography stage 110, the offset of at least two layers of the semiconductor device wafer 102 is optionally measured by an offset metrology system 120, and as indicated by arrow 122, the results from the measurement by the offset metrology system 120 may be sent to the first photolithography stage 110 for patterning any of additional ones of the semiconductor device wafers 102 selected from the BSDWII 104 or for re-patterning a previously patterned semiconductor device wafer 102. It should be understood that not every semiconductor device wafer 102 patterned at the first photolithography stage 110 needs to be sent to the offset metrology system 120 for offset measurement.

[0052] In a preferred embodiment of the present invention, after acceptable patterning at the first lithography stage 110, the semiconductor device wafer 102 selected from the BSDWII 104 is sent to the additional lithography stage 140 for additional patterning. It should be noted that the results from the offset metrology system 120 may also be sent to the additional lithography stage 140, as indicated by arrow 142. It should be understood that the above reference to Figure 1A Other steps, including metrology and fabrication processes, are performed on the semiconductor device wafer 102 selected from the BSDWII 104 before, between, and after the steps of the described first method 100 .

[0053] Reference Figure 1B , which is Figure 1A The enlarged circle B in the figure corresponds to the enlarged circle, Figure 1B A simplified schematic perspective illustration of an offset metrology system 120 for the first method 100 is shown, which can be seen to include both an optical offset metrology tool 144 and an e-beam offset metrology tool 146. It should be understood that the optical offset metrology tool 144 can be any suitable optical offset metrology tool, such as a scatterometry metrology tool or an imaging metrology tool.

[0054] A typical scatterometry metrology tool used as the optical offset metrology tool 144 is the ATL 1000, commercially available from KLA-Tencor Corporation of Milpitas, California, USA. TM 100. A typical imaging metrology tool used as the optical offset metrology tool 144 is the Archer ® 100, commercially available from KLA-Tencor, Inc. of Milpitas, California, USA. TM 600. A typical electron beam offset metrology tool 146 is commercially available from KLA-Tencor, Inc. of Milpitas, California, USA. TM .

[0055] It should be understood that the optical offset metrology tool 144 and the e-beam offset metrology tool 146 are operable to measure offsets of the same semiconductor device wafer 102 or different ones of the semiconductor device wafers 102 selected from the BSDWII 104. Regardless of measuring offsets of the same or different semiconductor device wafers 102, the optical offset metrology tool 144 and the e-beam offset metrology tool 146 are operable to measure offsets between the same two layers of the semiconductor device wafer 102 selected from the BSDWII 104.

[0056] It should be further understood that, in preferred embodiments of the present invention, the offset measurements performed by the optical offset metrology tool 144 and the e-beam offset metrology tool 146 typically include multiple measurements performed at multiple sites 148 on the semiconductor device wafer 102. However, in alternative embodiments of the present invention, the offset measurements performed by the optical offset metrology tool 144 and the e-beam offset metrology tool 146 may include only a single measurement or multiple measurements performed at a single site 148 on the semiconductor device wafer 102.

[0057] The offset metrology system 120 further includes a combiner 149 that combines the outputs of the optical offset metrology tool 144 and the e-beam offset metrology tool 146 to provide a combined offset metric, such as a target specific combined optical and e-beam offset metrology (TSCOEBMM) 150 , as indicated by arrows 152 and 154 .

[0058] The offset metrology system 120 can communicate the TSCOEBMM 150 to the lithography stages 110 and 140, as indicated by arrows 122 and 142, respectively, and the TSCOEBMM 150 can be used to adjust parameters of the lithography stages 110 and 140. Additionally, the TSCOEBMM 150 can be utilized in adjusting at least one of the measurement parameters and results of the optical offset metrology tool 144, as indicated by arrow 156. The TSCOEBMM 150 can also be utilized in adjusting at least one of the measurement parameters and results of the electron beam offset metrology tool 146, as indicated by arrow 158.

[0059] Reference Figure 2A and 2B , which together illustrate the first method 100 ( Figure 1A and 1B). As seen at a first step 202, at least one semiconductor device wafer 102 selected from the BSDWII 104 is patterned at a first lithography stage 110. As seen at a next step 204, after patterning at the first lithography stage 110, an optical offset metrology tool 144 of an offset metrology system 120 is utilized to measure a post-lithography optical offset at at least one target between two layers of the semiconductor device wafer 102. It should be understood that one of the at least two layers of the semiconductor device wafer 102 measured at step 204 is the layer patterned at step 202. The other of the at least two layers of the semiconductor device wafer 102 measured at step 204 can be any layer formed prior to the first method 100.

[0060] It should be understood that in preferred embodiments of the present invention, the offset measurement performed at step 204 typically includes multiple measurements performed at multiple sites 148 on the semiconductor device wafer 102. However, in alternative embodiments of the present invention, the offset measurement performed at step 204 may include only a single measurement or multiple measurements performed at a single site 148 on the semiconductor device wafer 102.

[0061] As seen at the next step 206 , after patterning at the first lithography stage 110 , the e-beam offset metrology tool 146 of the offset metrology system 120 is also utilized to measure post-lithography optical offset at at least one target between two layers of the semiconductor device wafer 102 .

[0062] It should be understood that the semiconductor device wafer 102 measured at step 206 may be the same semiconductor device wafer 102 measured at step 204 , but may also be a different semiconductor device wafer 102 selected from the BSDWII 104 .

[0063] It should be further understood that, in a preferred embodiment of the present invention, the offset measurements performed at step 206 include multiple measurements performed at multiple sites 148 on the semiconductor device wafer 102. However, in alternative embodiments of the present invention, the offset measurements performed at step 206 may include only a single measurement or multiple measurements performed at a single site 148 on the semiconductor device wafer 102. It should be noted that, regardless of the number of measurements performed or the number of sites measured, at steps 204 and 206, the offset is measured between corresponding layers of the semiconductor device wafer 102 selected from the BSDWII 104 and patterned by the first photolithography stage 110 at step 202.

[0064] After steps 204 and 206, as seen at the next step 208, the offset metrology system 120 combines the output of the optical offset metrology tool 144 at step 204 and the output of the electron beam offset metrology tool 146 at step 206 to generate a TSCOEBMM 150. The TSCOEBMM 150 may be generated using a weighted average, regression, machine learning methods, or any additional method.

[0065] For example, at step 208 , for each site 148 measured on the semiconductor device wafer 102 , the optical offset measured at step 204 and the electron beam offset measured at step 206 may be compared, and whichever measurement, either at step 204 or step 206 , that results in fewer residuals may be used as the TSCOEBMM 150 for that site 148 .

[0066] In the next step 210, the first method 100 determines whether the offset measured at steps 204 and 206 is above a first threshold. If the offset measured at steps 204 and 206 is above the first threshold, the first method 100 proceeds to the next step 212 where an adjustment based on the TSCOEBMM 150 is performed. Step 212 includes at least one of optional sub-steps 214, 216, and 218.

[0067] At optional sub-step 214, the TSCOEBMM 150 is utilized in adjusting at least one of the measurement parameters and results of the optical offset metrology tool 144. For example, measurement parameters of the optical offset metrology tool 144, such as the region of interest at which the offset is measured, the wavelength of light utilized in the offset measurement, the polarization of the light utilized in the offset measurement, the numerical aperture, the diffraction mask, and the diffraction aperture, may be adjusted so that the measurement results from the optical offset metrology tool 144 more closely match the measurement results of the electron beam offset metrology tool 146.

[0068] At optional sub-step 216, the TSCOEBMM 150 is utilized in adjusting at least one of measurement parameters and results of the e-beam offset metrology tool 146. For example, the TSCOEBMM 150 may be utilized to identify and remove outlier measurement results from the offset measurements performed by the e-beam offset metrology tool 146 at step 206.

[0069] At optional sub-step 218, the TSCOEBMM 150 is utilized in adjusting the first lithography stage 110. For example, parameters of the first lithography stage 110 may be adjusted, including rotation, scaling, and translation, among other things.

[0070] After step 212, the first method 100 continues at the next step 220 to determine whether the offset measured at steps 204 and 206 is above a second threshold. If the offset measured at steps 204 and 206 is above the second threshold, the first method 100 continues at the next step 222 to determine whether to send one or more semiconductor device wafers 102 back for rework.

[0071] If one or more semiconductor device wafers 102 are to be reworked, then the one or more semiconductor device wafers 102 are stripped and the first method 100 returns to step 202 for patterning the one or more semiconductor device wafers 102 at the adjusted first photolithography stage 110. If one or more semiconductor device wafers 102 are not to be reworked (including in particular the case where the optional sub-step 218 is not performed), then the semiconductor device wafer 102 or the entire BSDWII 104 is rejected, as seen at the next step 224.

[0072] If the offset is not above the second threshold, the first method 100 proceeds from step 220 to the next step 226. Note that when the offset measured at steps 204 and 206 is not above the first threshold, the first method 100 proceeds from step 210 to step 226, as shown in FIG. Figure 2A and 2B As seen in.

[0073] At step 226, the first method 100 determines whether the offset measured at steps 204 and 206 is above a third threshold. If the offset is above the third threshold, the first method 100 proceeds to the next step 228, where the TSCOEBMM 150 is utilized in adjusting the second lithography stage 140. For example, parameters of the second lithography stage 140 may be adjusted, including, among other things, rotation, scaling, and translation.

[0074] After step 228 or after step 226, when the offset is not above the third threshold, first method 100 proceeds to an optional next step 230 where the semiconductor device wafer or wafers 102 are patterned at the second photolithography stage 140. At a next step 232, a decision is made as to whether to process additional semiconductor device wafers 102, after which additional semiconductor device wafers 102 are fabricated at a next step 234 using at least one of the adjusted photolithography stages 110 and 140, or first method 100 ends, as seen at a next step 236.

[0075] It should be appreciated that the additional semiconductor device wafers 102 fabricated at step 234 may be fabricated using any of the first method 100 or any other suitable alternative method including the first photolithography stage 110 and optionally the optical offset metrology tool 144, the e-beam offset metrology tool 146, and the second photolithography stage 140 (which has been adapted as part of the first method 100).

[0076] For further information, please refer to the above Figure 2A and 2B Other steps, including metrology and fabrication processes, are performed on the semiconductor device wafer 102 selected from the BSDWII 104 before, between, and after the steps of the described first method 100 .

[0077] Reference Figure 3A , which is a simplified schematic diagram of a second method 300 for manufacturing a semiconductor device wafer. Figure 3A , at least one semiconductor device wafer 302 selected from a batch of semiconductor device wafers (BSDWII) 304 intended to be the same is patterned at a photolithography stage 310. It should be understood that while BSDWII 304 is drawn with twelve semiconductor device wafers 302, BSDWII 304 may include any number of semiconductor device wafers 302 greater than or equal to one.

[0078] After patterning at the photolithography stage 310, the semiconductor device wafer 302 is optionally measured by an offset metrology tool 312. The offset metrology tool 312 may be any suitable offset metrology tool, including those described above with reference to FIG. Figure 1A and 1B Described are an offset metrology system 120, an optical offset metrology tool (eg, a scatterometry metrology tool or an imaging metrology tool), and an electron beam offset metrology tool.

[0079] An exemplary scatterometry metrology tool for use as the offset metrology tool 312 is the ATL scatterometry metrology tool commercially available from KLA-Tencor, Inc. of Milpitas, California, USA. TM 100. A typical imaging metrology tool used as the offset metrology tool 312 is the Archer ® 100, commercially available from KLA-Tencor, Inc. of Milpitas, California, USA. TM 600. A typical electron beam offset metrology tool used as the offset metrology tool 312 is the eDR7xxx commercially available from KLA-Tencor, Inc. of Milpitas, California, USA. TM .

[0080] As indicated by arrow 314, the results from the measurements by the offset metrology tool 312 may be sent to the lithography stage 310 for patterning any of the additional ones of the semiconductor device wafers 302 selected from the BSDWII 304 or for re-patterning a previously patterned semiconductor device wafer 302. It should be understood that not every semiconductor device wafer 302 patterned at the lithography stage 310 needs to be sent to the offset metrology tool 312 for offset measurement.

[0081] After acceptable patterning at the photolithography stage 310, the semiconductor device wafer 302 selected from the BSDWII 304 is sent to the etch stage 316 for etching. After the etch stage 316, the semiconductor device wafer 302 is optionally measured by the offset metrology system 320, and as indicated by arrow 322, the results from the measurement by the offset metrology system 320 can be sent to the photolithography stage 310 for patterning additional ones of the semiconductor device wafers 302 selected from the BSDWII 304. The results from the offset metrology system 320 can also be sent to the offset metrology tool 312, as indicated by arrow 342. It should be understood that not every semiconductor device wafer 102 patterned at the first photolithography stage 110 needs to be sent to the offset metrology system 120 for offset measurement.

[0082] It should be understood that reference may be made to Figure 3A Other steps, including metrology and fabrication processes, are performed on the semiconductor device wafer 302 selected from the BSDWII 304 before, between, and after the steps of the described second method 300 .

[0083] Reference Figure 3B , which is Figure 1A The enlarged circle B in the figure corresponds to the enlarged circle, Figure 3B A simplified schematic diagram of an offset metrology system 320 for use in the second method 300 is shown. Figure 3B , the offset metrology system 320 includes both an optical offset metrology tool 344 and an e-beam offset metrology tool 346. It should be appreciated that the optical offset metrology tool 344 can be any suitable optical offset metrology tool, such as a scatterometry metrology tool or an imaging metrology tool.

[0084] An exemplary scatterometry metrology tool for use as the optical offset metrology tool 344 is the ATL scatterometry metrology tool commercially available from KLA-Tencor, Inc. of Milpitas, California, USA. TM 100. A typical imaging metrology tool used as the optical offset metrology tool 344 is the Archer ® 100, commercially available from KLA-Tencor, Inc. of Milpitas, California, USA. TM 600. A typical electron beam offset metrology tool 346 is commercially available from KLA-Tencor, Inc. of Milpitas, California, USA.TM .

[0085] It should be understood that the optical offset metrology tool 344 and the e-beam offset metrology tool 346 are operable to measure offsets of the same semiconductor device wafer 302 selected from the BSDWII 304 or of different ones of the semiconductor device wafers 302. Regardless of measuring offsets of the same or different semiconductor device wafers 302, the optical offset metrology tool 344 and the e-beam offset metrology tool 346 are operable to measure offsets between the same two layers of the semiconductor device wafer 302 selected from the BSDWII 304.

[0086] It should be further understood that, in a preferred embodiment of the present invention, the offset measurements performed by the optical offset metrology tool 344 and the e-beam offset metrology tool 346 typically include multiple measurements performed at multiple sites 348 on the semiconductor device wafer 302. However, in alternative embodiments of the present invention, the offset measurements performed by the optical offset metrology tool 344 and the e-beam offset metrology tool 346 may include only a single measurement or multiple measurements performed at a single site 348 on the semiconductor device wafer 302.

[0087] The offset metrology system 320 further includes a combiner 349 that combines the outputs of the optical offset metrology tool 344 and the electron beam offset metrology tool 346 to provide a combined offset metric, such as a target specific combined optical and electron beam offset metrology (TSCOEBMM) 350 , as indicated by arrows 352 and 354 .

[0088] Excursion metrology system 320 may communicate TSCOEBMM 350 to lithography stage 310 and to excursion metrology tool 312 as indicated by arrows 322 and 342 , respectively, and TSCOEBMM 150 may be used to adjust at least one of parameters of lithography stage 310 and measurement parameters and results of excursion metrology tool 312 .

[0089] Additionally, TSCOEBMM 350 may be utilized in adjusting at least one of the measurement parameters and results of optical offset metrology tool 344, as indicated by arrow 356. TSCOEBMM 350 may also be utilized in adjusting at least one of the measurement parameters and results of electron beam offset metrology tool 346, as indicated by arrow 358.

[0090] Reference Figure 4A and 4B , together with the description Figure 3A and 3BFIG2 is a simplified flow chart of a second method 300 of FIG2 . As seen at a first step 402, at least one semiconductor device wafer 302 selected from a BSDWII 304 is patterned at a photolithography stage 310. As seen at a next step 404, after patterning at the photolithography stage 310, an offset metrology tool 312 is utilized to measure a post-lithography offset between two layers of the semiconductor device wafer 302. It should be understood that one of the at least two layers of the semiconductor device wafer 302 measured at step 404 is the layer patterned at step 402. The other of the at least two layers of the semiconductor device wafer 302 measured at step 404 can be any layer formed prior to the second method 300.

[0091] It should be understood that in preferred embodiments of the present invention, the offset measurement performed at step 404 typically includes multiple measurements performed at multiple sites 348 on the semiconductor device wafer 302. However, in alternative embodiments of the present invention, the offset measurement performed at step 404 may include only a single measurement or multiple measurements performed at a single site 348 on the semiconductor device wafer 302.

[0092] As seen at the next step 406, the second method 300 determines whether the post-lithography offset measured at step 404 is above a first threshold. If the post-lithography offset measured at step 404 is above the first threshold, the second method 300 proceeds to the next step 408 where the lithography stage 310 is adjusted based on the post-lithography offset measured at step 404. For example, parameters of the lithography stage 310 may be adjusted, including rotation, scaling, and translation, among other things.

[0093] After step 408, when the offset is above the first threshold, or after step 406, when the offset is not above the first threshold, the second method 300 proceeds to the next step 410, where the semiconductor device wafer 302 is etched at the etching stage 316. It should be understood that the semiconductor device wafer 302 etched at step 316 may be the same semiconductor device wafer 302 measured at step 404, but may also be a different semiconductor device wafer 302 selected from the BSDWII 304 and patterned by the photolithography stage 310 at step 402.

[0094] As seen at the next step 412, after etching at step 410, the optical offset metrology tool 344 of the offset metrology system 320 is utilized to measure the post-etch optical offset between the two layers of the semiconductor device wafer 302. It should be appreciated that, in preferred embodiments of the present invention, the offset measurement performed at step 412 typically includes multiple measurements performed at multiple sites 348 on the semiconductor device wafer 302. However, in alternative embodiments of the present invention, the offset measurement performed at step 412 may include only a single measurement or multiple measurements performed at a single site 348 on the semiconductor device wafer 302.

[0095] As seen at the next step 414, after etching at the etch stage 316, the post-etch offset between the two layers of the semiconductor device wafer 302 is also measured by the e-beam offset metrology tool 346 of the offset metrology system 320. It should be understood that the semiconductor device wafer 302 measured at step 414 can be the same semiconductor device wafer 302 measured at step 412, but can also be a different semiconductor device wafer 302 selected from the BSDWII 104 and patterned by the photolithography stage 310 at step 402.

[0096] It should be further understood that, in a preferred embodiment of the present invention, the offset measurements performed at step 414 include multiple measurements performed at multiple sites 348 on the semiconductor device wafer 302. However, in alternative embodiments of the present invention, the offset measurements performed at step 414 may include only a single measurement or multiple measurements performed at a single site 348 on the semiconductor device wafer 302. It should be noted that regardless of the number of measurements performed or the number of sites measured, at steps 412 and 414, the offset is measured between corresponding layers of the semiconductor device wafer 302 selected from the BSDWII 304.

[0097] After steps 412 and 414, the offset metrology system 320 outputs a TSCOEBMM 350 as seen at the next step 416. It should be appreciated that the TSCOEBMM 350 is generated from measurements from both the optical offset metrology tool 344 at step 412 and the electron beam offset metrology tool 346 at step 414. The TSCOEBMM 350 may be generated using a weighted average, regression, machine learning methods, or any additional method.

[0098] For example, at step 416, for each site 348 measured on the semiconductor device wafer 302, the optical offset measured at step 412 and the electron beam offset measured at step 414 may be compared, and whichever measurement, performed at step 412 or step 414, that results in fewer residuals may be used as the TSCOEBMM 350 for that site 348.

[0099] At the next step 418, the second method 300 determines whether the offset measured at steps 412 and 414 is above a second threshold. If the offset is above the second threshold, the second method 300 proceeds to the next step 420 where an adjustment based on the TSCOEBMM 350 is performed. Step 420 includes at least one of optional sub-steps 422, 424, 426, and 428.

[0100] At optional sub-step 422, the TSCOEBMM 350 is utilized in adjusting at least one of the measurement parameters and results of the optical offset metrology tool 344. For example, measurement parameters of the optical offset metrology tool 344, such as the region of interest at which the offset is measured, the wavelength of light utilized in the offset measurement, the polarization of the light utilized in the offset measurement, the numerical aperture, the diffraction mask, and the diffraction aperture, may be adjusted so that the measurement results from the optical offset metrology tool 344 more closely match the measurement results of the electron beam offset metrology tool 346.

[0101] At optional sub-step 424, TSCOEBMM 350 is utilized in adjusting at least one of measurement parameters and results of e-beam offset metrology tool 346. For example, TSCOEBMM 350 may be utilized to identify and remove outlier measurement results from the offset measurements performed by e-beam offset metrology tool 346 at step 414.

[0102] At optional sub-step 426, the TSCOEBMM 150 is utilized in adjusting the lithography stage 310. For example, parameters of the first lithography stage 310 may be adjusted, including rotation, scaling, and translation, among other things.

[0103] At optional sub-step 428, the TSCOEBMM 150 is utilized in adjusting at least one of the measurement parameters and results of the post-lithography offset measurement performed by the offset metrology tool 312 at step 404. For example, measurement parameters of the offset metrology tool 312, such as the region of interest at which the offset is measured, the wavelength of light utilized in the offset measurement, the polarization of the light utilized in the offset measurement, the numerical aperture, the diffraction mask, and the diffraction aperture, may be adjusted. As an additional example, the TSCOEBMM 350 may be utilized to identify and remove outlier measurement results from the offset measurement performed by the offset metrology tool 312 at step 404.

[0104] Following step 420 , a decision is made as to whether to process additional semiconductor device wafers 302 as seen at the next step 430 , after which additional semiconductor device wafers 302 are fabricated at the next step 432 , or the second method 300 ends as seen at step 434 .

[0105] It should be noted that when the offset measured in steps 412 and 414 is not higher than the second threshold, the second method 300 proceeds directly from step 418 to step 430, as shown in FIG. Figure 4A and 4B As seen in.

[0106] It should be appreciated that the additional semiconductor device wafers 302 fabricated at step 432 may be fabricated using the second method 300 or any other suitable alternative method, including the photolithography stage 310 and optionally any of the offset metrology tools 312, optical offset metrology tools 344, and e-beam offset metrology tools 346 (which have been adapted as part of the second method 300).

[0107] For further information, please refer to the above Figure 4A and 4B Other steps, including metrology and fabrication processes, are performed on the semiconductor device wafer 302 selected from the BSDWII 304 before, between, and after the steps of the described second method 300 .

[0108] Reference Figures 5A to 5D , which shows a structure formed on a semiconductor device wafer 502 (e.g., semiconductor device wafer 102 ( Figures 1A to 2B ) or semiconductor device chip 302 ( Figures 3A to 4B )) are simplified illustrations of four alternative embodiments of a first mixing target 500 on two separate layers. The first mixing target 500 is used in the first method 100 and the second method 300 for fabricating a semiconductor device wafer.

[0109] like Figures 5A to 5D As seen in FIG, the first hybrid target 500 includes a first periodic structure 504 formed on a first layer 506 of a semiconductor device wafer 502 and a second periodic structure 508 formed on a second layer 509 of the semiconductor device wafer 502 .

[0110] As in Figures 5A to 5D As further seen in FIG, first hybrid target 500 includes first and second optically sensitive regions 510 and 512 and preferably a separate electron beam sensitive region 518 positioned therebetween. It will be appreciated that optically sensitive regions 510 and 512 are particularly well suited for optical metrology and electron beam sensitive region 518 is particularly well suited for electron beam metrology.

[0111] It should be understood that the first layer 506 and the second layer 509 of the semiconductor device wafer 502 may, but need not, be adjacent to each other. It should be further understood that the first optically sensitive region 510 and the second optically sensitive region 512 are operable to be imaged using a suitable imaging offset metrology tool, such as Archer Imaging, commercially available from KLA-Tencor, Inc., Milpitas, California, USA. TM600) using an imaging algorithm (such as that described in U.S. Patent No. 8,330,281, the disclosure of which is hereby incorporated by reference) to indicate an offset between the first layer 506 and the second layer 509 of the semiconductor device wafer 502.

[0112] The electron beam sensitive region 518 is operable to be used in conjunction with a suitable electron beam offset metrology tool (e.g., the eDR7xxx commercially available from KLA-Tencor, Milpitas, California, USA). TM ) using a scatterometry algorithm (such as the scatterometry algorithm described in U.S. patent application Ser. No. 15 / 979,336, filed May 14, 2018, entitled “OVERLAY MEASUREMENTS OF OVERLAPPING TARGET STRUCTURES BASED ONSYMMETRY OF SCANNING ELECTRON BEAM SIGNALS,” the disclosure of which is hereby incorporated by reference) to indicate an offset between the first layer 506 and the second layer 509 of the semiconductor device wafer 502.

[0113] On a first layer 506 of a semiconductor device wafer 502, a first photosensitive region 510 is formed as a first periodic structure 504 having a grating shown here as including lines 522 and spaces 524 with a pitch A between 600 nm and 2400 nm along an axis 530. On a second layer 509 of the semiconductor device wafer 502, a second photosensitive region 512 is formed as a second periodic structure 508 having a grating shown here as including lines 532 and spaces 534 with a pitch B between 600 nm and 2400 nm along an axis parallel to the axis 530. The widths of the lines 522 and 532 are preferably between 20% and 80% of the pitches A and B, respectively.

[0114] As in Figure 5A As seen in the embodiment illustrated in FIG, the first periodic structure 504 of the first optically sensitive region 510 and the second periodic structure 508 of the second optically sensitive region 512 partially overlap in the electron beam sensitive region 518. It should be noted that the first periodic structure 504 of the optically sensitive region 510 and the second periodic structure 508 of the optically sensitive region 512 are arranged relative to each other so that in the electron beam sensitive region 518, various pairs of lines 522 and 532 partially overlap to varying degrees. For example, in the electron beam sensitive region 518, various pairs of lines 522 and 532 may overlap to a maximum of 1 / 4. and degree.

[0115] As in Figures 5B to 5D As seen in the embodiment illustrated in FIG, the first periodic structure 504 of the first optically sensitive region 510 and the second periodic structure 508 of the second optically sensitive region 512 are not present in the electron beam sensitive region 518. Instead, on the first layer 506 of the semiconductor device wafer 502, the electron beam sensitive region 518 is formed as a third periodic structure 540 having a grating shown here as including lines 542 and spaces 544 with a pitch C between 30 nm and 600 nm and preferably between 30 nm and 200 nm along an axis parallel to the axis 530. On the second layer 509 of the semiconductor device wafer 502, the electron beam sensitive region 518 is formed as a fourth periodic structure 550 having a grating shown here as including lines 552 and spaces 554 with a pitch D between 30 nm and 600 nm and preferably between 30 nm and 200 nm along an axis parallel to the axis 530. The widths of the lines 542 and 552 are preferably between 20% and 80% of the pitches C and D, respectively. It should be noted that the third periodic structure 540 and the fourth periodic structure 550 partially overlap in the electron beam sensitive region 518 .

[0116] It should be noted that in the reference Figure 5A In the depicted embodiment, the first periodic structure 504 and the second periodic structure 508 are arranged relative to each other such that various pairs of lines 522 and 532 partially overlap to varying degrees. Figures 5B to 5D In the depicted embodiment, the third periodic structure 540 and the fourth periodic structure 550 are arranged relative to each other so that various pairs of lines 542 and 552 partially overlap to varying degrees. However, it should be understood that no relationship is required between the pitches A, B, C, and D or the widths of the lines 522, 532, 542, and 552.

[0117] It should be further noted that periodic structures 504, 508, 540, and 550 preferably include multiple periodic substructures (not shown). More specifically, lines 522, 532, 542, and 552 can be segmented, but they need not be segmented. In embodiments where lines 522, 532, 542, and 552 are segmented, each of lines 522, 532, 542, and 552 is defined by multiple sublines and subspaces between the sublines.

[0118] Reference Figures 6A to 6D , which shows a structure formed on a semiconductor device wafer 602 (e.g., semiconductor device wafer 102 ( Figures 1A to 2B ) or semiconductor device chip 302 ( Figures 3A to 4B)) are simplified illustrations of four alternative embodiments of the second mixing target 600 on two separate layers. The second mixing target 600 is used in the first method 100 and the second method 300 for manufacturing semiconductor device wafers.

[0119] like Figures 6A to 6D As seen in FIG, the second hybrid target 600 includes a first periodic structure 604 formed on a first layer 606 of a semiconductor device wafer 602 and a second periodic structure 608 formed on a second layer 609 of the semiconductor device wafer 602 .

[0120] As in Figures 6A to 6D As further seen in FIG, second hybrid target 600 includes first and second optically sensitive regions 610, 612 and preferably a separate electron beam sensitive region 618 positioned therebetween. It will be appreciated that optically sensitive regions 610 and 612 are particularly well suited for optical metrology and electron beam sensitive region 618 is particularly well suited for electron beam metrology.

[0121] It should be understood that the first layer 606 and the second layer 609 of the semiconductor device wafer 602 may, but need not, be adjacent to each other. It should be further understood that the first optically sensitive region 610 and the second optically sensitive region 612 can be operated to measure the offset of the semiconductor device wafer 602 by a suitable imaging offset metrology tool (e.g., Archer Imaging Systems, commercially available from KLA-Tencor, Inc., Milpitas, California, USA). TM 600) using an imaging algorithm (such as that described in U.S. Patent No. 8,330,281, the disclosure of which is hereby incorporated by reference) to indicate an offset between a first layer 606 and a second layer 609 of a semiconductor device wafer 602.

[0122] The electron beam sensitive region 618 is operable to be used in conjunction with a suitable electron beam offset metrology tool (e.g., the eDR7xxx commercially available from KLA-Tencor, Milpitas, California, USA). TM ) is measured using an imaging algorithm (such as the imaging algorithm described in U.S. Patent No. 9,093,458, the disclosure of which is hereby incorporated by reference) to indicate the offset between the first layer 606 and the second layer 609 of the semiconductor device wafer 602.

[0123] On a first layer 606 of a semiconductor device wafer 602, a first photosensitive region 610 is formed as a first periodic structure 604 having a grating, shown here as including lines 622 and spaces 624, with a pitch E between 600 nm and 2400 nm along an axis parallel to an axis 630. On a second layer 609 of the semiconductor device wafer 602, a second photosensitive region 612 is formed as a second periodic structure 608 having a grating, shown here as including lines 632 and spaces 634, with a pitch F between 600 nm and 2400 nm along an axis 630. The widths of the lines 622 and 632 are preferably between 20% and 80% of the pitches E and F.

[0124] As in Figure 6A As seen in the embodiment illustrated in FIG, the first periodic structure 604 of the first optically sensitive region 610 and the second periodic structure 608 of the second optically sensitive region 612 extend into the electron beam sensitive region 618. It should be noted that the first periodic structure 604 and the second periodic structure 608 are arranged relative to each other such that in the electron beam sensitive region 618, the first periodic structure 604 and the second periodic structure 608 do not overlap.

[0125] As in Figures 6B to 6D As seen in the embodiment illustrated in FIG, the first periodic structure 604 of the first optically sensitive region 610 and the second periodic structure 608 of the second optically sensitive region 612 are not present in the electron beam sensitive region 618. Instead, on the first layer 606 of the semiconductor device wafer 602, the electron beam sensitive region 618 is formed as a third periodic structure 640 having a grating shown here as including lines 642 and spaces 644 with a pitch G along an axis parallel to the axis 630 of between 100 nm and 600 nm, and preferably between 100 nm and 300 nm. On the second layer 609 of the semiconductor device wafer 602, the electron beam sensitive region 618 is formed as a fourth periodic structure 650 having a grating shown here as including lines 652 and spaces 654 with a pitch H along an axis parallel to the axis 630 of between 100 nm and 600 nm, and preferably between 100 nm and 300 nm. The width of lines 642 and 652 is preferably between 20% and 80% of pitches G and H, respectively.

[0126] It should be noted that the third periodic structure 640 and the fourth periodic structure 650 of the electron beam sensitive region 618 are arranged relative to each other so that the third periodic structure 640 and the fourth periodic structure 650 do not overlap. It should be further noted that no relationship needs to be set between the pitches E, F, G and H or the widths of the lines 622, 632, 642 and 652.

[0127] It should be further noted that periodic structures 604, 608, 640, and 650 preferably include multiple periodic substructures (not shown). More specifically, lines 622, 632, 642, and 652 can be segmented, but they need not be segmented. In embodiments where lines 622, 632, 642, and 652 are segmented, each of lines 622, 632, 642, and 652 is defined by multiple sublines and subspaces between the sublines.

[0128] Reference Figures 7A to 7D , which shows a structure formed on a semiconductor device wafer 702 (e.g., semiconductor device wafer 102 ( Figures 1A to 2B ) or semiconductor device chip 302 ( Figures 3A to 4B )) are simplified illustrations of four alternative embodiments of the third mixing target 700 on two separate layers. The third mixing target 700 is used in the first method 100 and the second method 300 for manufacturing semiconductor device wafers.

[0129] like Figures 7A to 7D As seen in FIG, the third hybrid target 700 includes a first periodic structure 704 formed on a first layer 706 of a semiconductor device wafer 702 and a second periodic structure 708 formed on a second layer 709 of the semiconductor device wafer 702 .

[0130] As in Figures 7A to 7D As further seen in FIG, third hybrid target 700 includes first and second optically sensitive regions 710, 712 and preferably a separate electron beam sensitive region 718 positioned therebetween. It will be appreciated that optically sensitive regions 710 and 712 are particularly well suited for optical metrology and electron beam sensitive region 718 is particularly well suited for electron beam metrology.

[0131] It should be understood that the first layer 706 and the second layer 709 of the semiconductor device wafer 702 may, but need not, be adjacent to each other. It should be further understood that the first optically sensitive region 710 and the second optically sensitive region 712 are operable to measure the optical properties of the semiconductor device wafer 702 using a suitable scatterometry offset metrology tool (e.g., commercially available from ATL Corporation of KLA-Tencor, Milpitas, California, USA). TM 100) indicates an offset between a first layer 706 and a second layer 709 of a semiconductor device wafer 702 using a scatterometry algorithm (such as that described in U.S. Patent No. 7,317,531, the disclosure of which is hereby incorporated by reference).

[0132] The electron beam sensitive area 718 is operable to be sensitive to the electron beam offset metrology tool (such as the eDR7xxx commercially available from KLA-Tencor, Milpitas, California, USA). TM) using a scatterometry algorithm (such as the scatterometry algorithm described in U.S. patent application Ser. No. 15 / 979,336, filed May 14, 2018, and entitled “OVERLAY MEASUREMENTS OF OVERLAPPING TARGET STRUCTURES BASED ONSYMMETRY OF SCANNING ELECTRON BEAM SIGNALS”) to indicate an offset between a first layer 706 and a second layer 709 of a semiconductor device wafer 702.

[0133] On a first layer 706 of a semiconductor device wafer 702, first and second optically sensitive regions 710 and 712 are formed as a first periodic structure 704 having a grating shown here as including lines 722 and spaces 724 with a pitch I between 400 nm and 900 nm along an axis 730. On a second layer 709 of the semiconductor device wafer 702, the first and second optically sensitive regions 710 and 712 are formed as a second periodic structure 708 having a grating shown here as including lines 732 and spaces 734 with a pitch J between 400 nm and 900 nm along the axis 730. The widths of the lines 722 and 732 are preferably between 20% and 80% of the pitches I and J, respectively.

[0134] like Figure 7A As seen in the embodiment illustrated in FIG, the second periodic structure 708 exists in the electron beam sensitive region 718. It should be understood that in reference Figure 7A In the depicted embodiment, either the first periodic structure 704 or the second periodic structure 708 is present in the electron beam sensitive region 718 .

[0135] In addition, Figure 7A In the embodiment illustrated in FIG, a third periodic structure 740 is present in the electron beam sensitive region 718. The third periodic structure 740 is shown here as a grating comprising lines 742 and spaces 744 having a pitch K between 30 nm and 600 nm, and preferably between 30 nm and 200 nm, along an axis parallel to the axis 730. It should be noted that the second periodic structure 708 and the third periodic structure 740 partially overlap in the electron beam sensitive region 718.

[0136] It should be noted that the second periodic structure 708 and the third periodic structure 740 are arranged relative to each other so that various pairs of lines 732 and 742 partially overlap to varying degrees in the electron beam sensitive region 718. For example, various pairs of lines 732 and 742 may overlap to varying degrees in the electron beam sensitive region 718. and degree.

[0137] As in Figures 7B to 7D As seen in the embodiment illustrated in FIG, the first periodic structure 704 and the second periodic structure 708 are not present in the electron beam sensitive region 718. Instead, on the first layer 706 of the semiconductor device wafer 702, the electron beam sensitive region 718 is formed with a third periodic structure 740. On the second layer 709 of the semiconductor device wafer 702, the electron beam sensitive region 718 is formed with a fourth periodic structure 750, shown here as a grating comprising lines 752 and spaces 754, having a pitch L between 30 nm and 600 nm, and preferably between 30 nm and 200 nm, along an axis parallel to the axis 730. The widths of the lines 742 and 752 are preferably between 20% and 80% of the pitches K and L, respectively. It should be noted that the third periodic structure 740 and the fourth periodic structure 750 partially overlap in the electron beam sensitive region 718.

[0138] It should be noted that in the reference Figure 7A In the depicted embodiment, the second periodic structure 708 and the third periodic structure 740 are arranged relative to each other such that various pairs of lines 722 and 742 partially overlap to varying degrees. Figures 7B to 7D In the depicted embodiment, the third periodic structure 740 and the fourth periodic structure 750 are arranged relative to each other so that various pairs of lines 742 and 752 partially overlap to varying degrees. However, it should be understood that no relationship is required between the pitches I, J, K, and L or the widths of the lines 722, 732, 742, and 752.

[0139] It should be further noted that periodic structures 704, 708, 740, and 750 preferably include multiple periodic substructures (not shown). More specifically, lines 722, 732, 742, and 752 can be segmented, but they need not be segmented. In embodiments where lines 722, 732, 742, and 752 are segmented, each of lines 722, 732, 742, and 752 is defined by multiple sublines and subspaces between the sublines.

[0140] Reference Figures 8A to 8D , which shows a structure formed on a semiconductor device wafer 802 (e.g., semiconductor device wafer 102 ( Figures 1A to 2B ) or semiconductor device chip 302 ( Figures 3A to 4B )) are simplified illustrations of four alternative embodiments of a fourth compound target 800 on two separate layers. The fourth compound target 800 is used in the first method 100 and the second method 300 for fabricating a semiconductor device wafer.

[0141] like Figures 8A to 8DAs seen in FIG, the fourth hybrid target 800 includes a first periodic structure 804 formed on a first layer 806 of a semiconductor device wafer 802 and a second periodic structure 808 formed on a second layer 809 of the semiconductor device wafer 802 .

[0142] As in Figures 8A to 8D As further seen in FIG, fourth hybrid target 800 includes first and second optically sensitive regions 810, 812 and preferably a separate electron beam sensitive region 818 positioned therebetween. It will be appreciated that optically sensitive regions 810 and 812 are particularly well suited for optical metrology and electron beam sensitive region 818 is particularly well suited for electron beam metrology.

[0143] It should be understood that the first layer 806 and the second layer 809 of the semiconductor device wafer 802 may, but need not, be adjacent to each other. It should be further understood that the first optically sensitive region 810 and the second optically sensitive region 812 are operable to measure the optical properties of the semiconductor device wafer 802 using a suitable scatterometry offset metrology tool (e.g., commercially available from ATL Corporation of KLA-Tencor, Milpitas, California, USA). TM 100) indicates an offset between a first layer 806 and a second layer 809 of a semiconductor device wafer 802 using a scatterometry algorithm (such as that described in U.S. Patent No. 7,317,531, the disclosure of which is hereby incorporated by reference).

[0144] The electron beam sensitive region 818 is operable to be used in conjunction with a suitable electron beam offset metrology tool (e.g., the eDR7xxx commercially available from KLA-Tencor, Milpitas, California, USA). TM ) is measured using an imaging algorithm (such as the imaging algorithm described in U.S. Patent No. 9,093,458, the disclosure of which is hereby incorporated by reference) to indicate the offset between the first layer 806 and the second layer 809 of the semiconductor device wafer 802.

[0145] On a first layer 806 of a semiconductor device wafer 802, a first photosensitive region 810 and a second photosensitive region are formed as a first periodic structure 804 having a grating shown here as including lines 822 and spaces 824 with a pitch M between 400 nm and 900 nm along an axis 830. On a second layer 809 of the semiconductor device wafer 802, the first photosensitive region and the second photosensitive region 812 are formed as a second periodic structure 808 having a grating shown here as including lines 832 and spaces 834 with a pitch N between 400 nm and 900 nm along the axis 830. The widths of the lines 822 and 832 are preferably between 20% and 80% of the pitches M and N, respectively.

[0146] As in Figure 8AAs seen in the embodiment illustrated in FIG, the first periodic structure 804 of the first optically sensitive region 810 and the second periodic structure 808 of the second optically sensitive region 812 extend into the electron beam sensitive region 818. It should be noted that the first periodic structure 804 and the second periodic structure 808 are arranged relative to each other such that in the electron beam sensitive region 818, the first periodic structure 804 and the second periodic structure 808 do not overlap.

[0147] As in Figures 8B to 8D As seen in the embodiment illustrated in FIG, first and second periodic structures 804, 808 are not present in electron beam sensitive region 818. Instead, on first layer 806 of semiconductor device wafer 802, electron beam sensitive region 818 is formed as a third periodic structure 840 having a grating, shown here as including lines 842 and spaces 844, with a pitch O between 100 nm and 600 nm, and preferably between 100 nm and 300 nm, along an axis parallel to axis 830. On second layer 809 of semiconductor device wafer 802, electron beam sensitive region 818 is formed as a fourth periodic structure 850 having a grating, shown here as including lines 852 and spaces 854, with a pitch P between 100 nm and 600 nm, and preferably between 100 nm and 300 nm, along an axis parallel to axis 830. The widths of lines 842 and 852 are preferably between 20% and 80% of pitch O and P, respectively.

[0148] It should be noted that the third periodic structure 840 and the fourth periodic structure 850 of the electron beam sensitive region 818 are arranged relative to each other so that the third periodic structure 840 and the fourth periodic structure 850 do not overlap. It should be further noted that no relationship needs to be set between the pitches M, N, O and P or the widths of the lines 822, 832, 842 and 852.

[0149] It should be further noted that periodic structures 804, 808, 840, and 850 preferably include multiple periodic substructures (not shown). More specifically, lines 822, 832, 842, and 852 can be segmented, but they need not be segmented. In embodiments where lines 822, 832, 842, and 852 are segmented, each of lines 822, 832, 842, and 852 is defined by multiple sublines and subspaces between the sublines.

[0150] Those skilled in the art will appreciate that the present invention is not limited to what has been particularly shown and described above. The scope of the present invention includes both combinations and subcombinations of the various features described above, as well as modifications thereof, all of which are not in the prior art.

Claims

1. An excursion metrology system for manufacturing semiconductor device wafers, comprising: an optical offset metrology tool configured to measure an offset at at least one target between two layers of a semiconductor device selected from a batch of semiconductor device wafers intended to be the same; an electron beam offset metrology tool configured to measure an offset at the at least one target between two layers of semiconductor devices selected from the batch; and A combiner is configured to combine outputs of the optical offset metrology tool and the e-beam offset metrology tool to provide a combined offset metric, wherein the outputs of the optical offset metrology tool and the e-beam offset metrology tool are measured in a same manufacturing process.

2. The system of claim 1, wherein the optical offset metrology tool comprises a scatterometry metrology tool or an imaging metrology tool.

3. The system of claim 1, wherein the optical offset metrology tool and the e-beam offset metrology tool each measure an offset between two layers of a single semiconductor device.

4. The system of claim 1, wherein the optical offset metrology tool and the e-beam offset metrology tool each measure an offset between two layers of different semiconductor device wafers each selected from the lot.

5. A method for manufacturing a semiconductor device wafer, comprising: performing at least an initial stage of a photolithography process on at least one semiconductor device wafer selected from a batch of semiconductor device wafers that are intended to be the same; Thereafter, an offset is measured of at least two layers of at least one semiconductor device wafer selected from the batch of semiconductor device wafers that is intended to be the same by: employing an optical offset metrology tool to measure an offset at at least one target between the two layers of at least one of the at least one semiconductor device wafers selected from the batch of semiconductor device wafers that are intended to be the same; employing an electron beam offset metrology tool to measure an offset at the at least one target between two layers of at least one of the at least one semiconductor device wafers selected from the batch of semiconductor device wafers that are intended to be the same; and combining outputs of the optical offset metrology tool and the e-beam offset metrology tool to provide a combined offset metric, wherein the outputs of the optical offset metrology tool and the e-beam offset metrology tool are measured during the same manufacturing process; and The combined offset metric is utilized for adjusting the lithography process to provide an adjusted lithography process.

6. The method of claim 5, wherein the measuring offset comprises employing the optical offset metrology tool and the e-beam offset metrology tool to measure an offset between two layers of a single semiconductor device.

7. The method of claim 5, wherein the measuring offset comprises employing the optical offset metrology tool and the e-beam offset metrology tool to measure an offset between two layers that are both selected from different semiconductor device wafers of the lot.

8. The method of claim 5, comprising utilizing the combined offset metric for adjusting at least one of a measurement parameter, a result of the optical offset metrology tool, or a result of the e-beam offset metrology tool.

9. The method of claim 5, wherein the optical offset metrology tool comprises a scatterometry metrology tool or an imaging metrology tool.

10. The method of claim 5, wherein performing at least an initial stage of a photolithography process on at least one semiconductor device wafer comprises: performing a photolithography process on at least one semiconductor device selected from a batch of semiconductor device wafers intended to be the same; thereafter measuring a post-lithographic offset of at least two layers of at least one semiconductor device selected from the batch of semiconductor device wafers that is intended to be the same; and Thereafter, an etching process is performed on at least one semiconductor device selected from the intended same batch of semiconductor device wafers.

11. The method of claim 10 , wherein the measuring the post-lithography offset comprises employing an optical offset metrology tool or an electron beam offset metrology tool to measure the offset at at least one target between two layers of at least one of the at least one semiconductor device wafers selected from the batch of semiconductor device wafers that are intended to be the same.

12. The method of claim 10, wherein measuring post-lithography offset comprises: employing a post-lithography optical offset metrology tool to measure an offset at at least one target between two layers of at least one of the at least one semiconductor device wafers selected from the batch of semiconductor device wafers that are intended to be the same; employing a post-lithography electron beam offset metrology tool to measure an offset at the at least one target between the two layers of at least one of the at least one semiconductor device wafers selected from the batch of semiconductor device wafers that are intended to be the same; and Outputs of the post-lithography optical offset metrology tool and the post-lithography e-beam offset metrology tool are combined to provide a combined offset metric.

13. A target for use in measuring offset in the manufacture of a semiconductor device, the target comprising: a first periodic structure formed on a first layer of a semiconductor device; having a first spacing along the axis; and a second periodic structure formed on a second layer of the semiconductor device and having a second pitch along an axis parallel to the axis, The target is characterized in that it includes at least one first region suitable for optical metrology and at least one second region separated from the at least one first region suitable for electron beam metrology. The target according to claim 13 , wherein in the at least one second region, both the first periodic structure and the second periodic structure are present.

15. The target according to claim 13, wherein in the at least one second region, a third periodic structure and a fourth periodic structure exist. 16 . The target according to claim 13 , wherein in the at least one second region, one of the first periodic structure and the second periodic structure exists and a third periodic structure exists.

17. The object of claim 13, wherein at least one of the first periodic structure and the second periodic structure comprises a plurality of periodic substructures.

18. The object of claim 15, wherein at least one of the third periodic structure and the fourth periodic structure comprises a plurality of periodic substructures.

19. The target according to claim 14, wherein in the at least one second region, the first periodic structure and the second periodic structure do not overlap.

20. The target according to claim 15, wherein in the at least one second region, the third periodic structure and the fourth periodic structure do not overlap.

Images