Integrated Circuit Metal Ion Diffusion Defect Verification

Abstract

A method for verifying that an integrated circuit chip is not susceptible to a conductive metal ion diffusion defect is disclosed. A test component is applied to the back side of the integrated circuit chip to form a test assembly. The test assembly includes a conductive metal layer for promoting diffusion of conductive metal ions and a transmission medium layer. The test assembly is heated at a thermal activation temperature. The integrated circuit chip is verified by a computer to determine whether the integrated circuit chip has a conductive metal ion diffusion defect.

Description

Background Art

[0001] In some cases, conductive metal ions, such as those containing copper (Cu), may diffuse undesirably through the layers of an integrated circuit chip, for example, from the back side of the integrated circuit chip. Such conductive metal ion diffusion may cause failure of the affected portion of the integrated circuit chip. For example, undesirable conductive metal ion diffusion may cause transistors in the integrated circuit chip to short circuit during operation. In some cases, such undesirable conductive metal ion diffusion may be the result of a manufacturing defect of the integrated circuit chip. Summary of the invention

[0002] An accelerated method for verifying that an integrated circuit chip is not susceptible to a conductive metal ion diffusion defect is disclosed. A test component is applied to the back side of the integrated circuit chip to form a test assembly. The test assembly includes a conductive metal layer for promoting diffusion of conductive metal ions and a transmission medium layer. The test assembly is heated at a thermal activation temperature. The integrated circuit chip is verified by a computer to determine whether the integrated circuit chip has a conductive metal ion diffusion defect.

[0003] This summary is provided to introduce in a simplified form a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that solve any or all of the disadvantages mentioned in any part of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A perspective view of an example integrated circuit chip is shown.

[0006] Figure 2 Cross-sectional views of various aspects of an integrated circuit chip without conductive metal ion diffusion defects are shown.

[0007] Figure 3 is a flow chart of an example method for verifying that an integrated circuit chip is not susceptible to conductive metal ion diffusion defects.

[0008] Figure 4 An example test assembly is schematically shown.

[0009] Figure 5 Example test components within a test assembly are schematically shown.

[0010] Figure 6 Another example test component within a test assembly is schematically shown.

[0011] Figure 7 Aspects of the test assembly are shown schematically.

[0012] Figure 8 Another example test assembly configured for use in a pressure-based verification method is schematically illustrated.

[0013] Fig. 9 An example test computing system is schematically shown.

[0014] Detailed Description

[0015] Figure 1 An example integrated circuit chip 100 is shown mounted to a substrate package 102. The substrate package 102 includes a plurality of contacts 104. The contacts 104 may be connected to a hardware package (such as a motherboard) to mount the integrated circuit chip 100 in a computing device for operation. Non-limiting examples of different types of integrated circuit chips include a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), and a memory unit, among others. The integrated circuit chip 100 may take any suitable form.

[0016] Figure 2 A cross-sectional view of various aspects of an exemplary integrated circuit chip is schematically shown. More specifically, different layers of the integrated circuit chip forming a transistor 200 are depicted. The transistor 200 includes a source 202, a gate 204, and a drain 206 formed on a substrate layer 208. A plurality of interconnects 210 (e.g., 210A, 210B, 210C) are electrically connected to the source 202, the gate 204, and the drain 206, respectively. The interconnects 210 include conductive metals that facilitate electrical connections between the transistor 200 and other electronic components of the integrated circuit chip. Such electrical connections allow electrical signals and power to be transmitted and distributed across the integrated circuit chip. In one example, the conductive metal is copper or includes copper.

[0017] In some cases, the conductive metal ions may diffuse undesirably through the layers of the integrated circuit chip, such as from the back side of the integrated circuit chip, and cause failure of the affected portion of the integrated circuit chip. Figure 2 As shown, multiple foreign metal ions may cause short circuits from source 202, gate 204, or drain 206 to substrate 208 or to each other. Note that the schematic examples depicted are simplified / idealized for clarity, and that conductive metal ion diffusion defects in an integrated circuit chip may take any suitable form caused by undesired migration of conductive materials.

[0018] Undesirable diffusion of conductive metal ions in an integrated circuit chip may not always be easily identified when the integrated circuit chip is manufactured. For example, although the integrated circuit chip may be susceptible to a conductive metal ion diffusion defect, the negative effects of such a defect may not appear until the integrated circuit chip has been in operation for a certain amount of time. As such, it may be difficult to detect that the integrated circuit chip is susceptible to a conductive metal ion diffusion defect before the integrated circuit chip is put into operation.

[0019] Therefore, the present specification relates to a method for verifying that an integrated circuit chip is not susceptible to conductive metal ion diffusion defects. The verification method can accelerate the diffusion of conductive metal ions in an integrated circuit chip that is susceptible to conductive metal ion diffusion defects by adopting a combination of acceleration techniques. In one example, the verification method includes applying a test component to the back side of the integrated circuit chip under test to form a test assembly. The test assembly includes a conductive metal layer and a transmission medium layer. The conductive metal layer provides an important source of conductive metal, which can be ionized during the verification method to facilitate the diffusion of conductive metal ions through the integrated circuit chip under test. The transmission medium layer can promote the diffusion of conductive metal ions through the susceptible portion of the integrated circuit chip under test. In addition, as part of the verification process, the test assembly is heated at a thermal activation temperature, which helps the conductive metal ions to be transmitted via the transmission medium between the conductive metal layer and the susceptible portion of the integrated circuit chip, thereby exposing defects in the integrated circuit chip.

[0020] In this manner, integrated circuit chips susceptible to conductive metal ion diffusion defects may be identified in a timely manner, thereby allowing for efficient verification of the integrated circuit chips before they are placed into operation in a computing device.

[0021] Figure 3 3 is a flow chart of an example method 300 for verifying that an integrated circuit chip is not susceptible to conductive metal ion diffusion defects. The verification method 300 can be performed as a screening process separate from the manufacturing process (e.g., post-manufacturing verification) of the integrated circuit chip. At 302, the method 300 can include: applying a test component to the back side of the integrated circuit chip to form a test assembly.

[0022] Figure 4An example test assembly 400 is schematically shown, which can be formed to verify that an integrated circuit chip is not susceptible to conductive metal diffusion defects. The test assembly 400 includes an integrated circuit chip 402 under test. A test component 404 is applied to the back side 406 of the integrated circuit chip 402. The test component 404 can form a layer that substantially covers the entire back side 406 of the integrated circuit chip 402. The test component 404 can include a conductive metal and a transmission medium. The conductive metal included in the test component 404 can match the conductive metal of the integrated circuit chip 402. For example, if the integrated circuit chip 402 may be susceptible to copper diffusion defects, the test component can be configured to include copper. The transmission medium can include any suitable material that is configured to be inserted between two components to enhance the thermal coupling between the two components. In particular, the transmission medium can be configured to promote the ionization of the conductive metal so that the conductive metal ions can diffuse between the test component 404 and the integrated circuit chip 402. In some examples, the transmission medium may include a thermal interface material. Non-limiting examples of thermal interface materials that may be included in test assembly 404 include thermally conductive pastes, thermal adhesives, thermally conductive pads, thermal tapes, and phase change materials.

[0023] In some implementations, the conductive metal and transmission medium of the test component 404 can be arranged in different layers. Figure 5 As shown, the test assembly 404 may include a conductive metal layer 500 applied directly to the back side 406 of the integrated circuit chip 402. In some examples, the conductive metal layer 500 may be applied to substantially the entire back side 406 of the integrated circuit chip 402. The conductive metal layer 500 may include any suitable conductive metal material. In one example, the conductive metal layer 500 includes copper. The conductive metal layer 500 may have any suitable thickness. In one example, the conductive metal layer 500 may have a thickness ranging between 0.0001-0.002 mm.

[0024] In addition, the transmission medium layer 502 can be directly applied to the conductive metal layer 500 to form the test assembly 404. In some examples, the transmission medium layer 502 can be applied to substantially the entire surface of the conductive metal layer 500. In some examples, the transmission medium layer 502 can have a surface area greater than or equal to the surface area of ​​the conductive metal layer 500. The transmission medium layer 502 can have any suitable thickness. In addition, the thickness of the transmission medium layer 502 can depend on the type of transmission medium used in the test assembly 404. The depicted example can be preferred for the verification process because the surface contact between the conductive metal layer and the back side of the integrated circuit chip can be high enough to promote the diffusion of conductive metal ions between the test assembly 404 and the integrated circuit chip 402.

[0025] Alternatively, in some examples, such as Figure 6As shown, the test assembly 404 can include a transmission medium layer 600 applied directly to the back side 406 of the integrated circuit chip 402. In some examples, the transmission medium layer 600 can be applied to substantially the entire back side 406 of the integrated circuit chip 402. In addition, a conductive metal layer 602 can be applied directly to the transmission medium layer 600 to form the test assembly 404. In some examples, the conductive metal layer 602 can be applied to substantially the entire surface of the transmission medium layer 600. In some examples, the transmission medium layer 602 can have a surface area greater than or equal to the surface area of ​​the conductive metal layer 500.

[0026] Back to Figure 4 In some implementations, the test assembly 400 can optionally include a heat sink 408. The heat sink 408 can be applied to the back side 410 of the test component 404. In particular, the heat sink 408 can be clamped on the integrated circuit chip 402 to compress the test component 404 to the back side 406 of the integrated circuit chip 402. In this way, the surface contact between the test component 404 and the integrated circuit chip 402 can be increased to better promote the diffusion of conductive metal ions between the test component 404 and the integrated circuit chip 402.

[0027] Figure 7 Various aspects of a test assembly 400 including a heat sink 408 are schematically shown. In particular, when the heat sink 408 is clamped to the integrated circuit chip 402, the heat sink 408 compresses the test assembly 404 so that the conductive metal layer 700 is pressed against the back side 406 of the integrated circuit chip 402 to increase the surface contact between the two surfaces. In addition, in some examples, the transmission medium layer 702 can be a viscous material. In some such examples, the heat sink 408 can compress the transmission medium layer 702 so that the transmission medium surrounds the perimeter of the conductive metal layer 700. Specifically, the transmission medium can be pressed around the outer edge of the conductive metal layer 700 between the back side 406 and the conductive metal layer 700. Such a spatial arrangement of different components of the test assembly 400 can further promote the ionization of the conductive metal and the diffusion of the conductive metal ions from the conductive metal layer 700 into the integrated circuit chip 402.

[0028] return Figure 3At 304, method 300 includes heating the test assembly to a thermal activation temperature. For example, the test assembly may be placed in an oven to heat the test assembly to the thermal activation temperature. The thermal activation temperature may be a temperature suitable for promoting diffusion of conductive metal ions throughout the integrated circuit chip under test. In some examples, the thermal activation temperature may be a temperature at which the transmission medium changes phase (e.g., becomes more viscous or at least partially liquefies to promote the transmission of conductive metal ions). In order to accelerate any potential diffusion of conductive metal ions throughout the integrated circuit chip under test, in some examples, the thermal activation temperature may be set so that it is greater than the operating temperature of the integrated circuit chip. This may allow diffusion to occur faster than it would during normal operation of the integrated circuit chip. For example, the thermal activation temperature may be selected from a thermal range of 100-150 degrees Celsius. In a specific example, the thermal activation temperature is 125 degrees Celsius.

[0029] In addition, in some examples, the test assembly can be heated to a thermal activation temperature for a specified duration, the thermal activation temperature being suitable for promoting diffusion of conductive metal ions throughout the integrated circuit chip under test. For example, the specified duration can be selected from a time range of 72-120 hours. In a specific example, the test assembly is heated to the thermal activation temperature for 96 hours.

[0030] In some implementations, at 306, method 300 may optionally include pressurizing the test assembly at an increased pressure relative to ambient pressure while the test assembly is heated to the thermal activation temperature. For example, the test assembly may be heated and pressurized in an autoclave or some other heated pressure chamber. In addition to being heated to further accelerate the diffusion of the conductive metal ions in the integrated circuit chip under test, the test assembly may also be pressurized. In some examples, the test assembly may be pressurized for the entire duration that the test assembly is heated. In other examples, the test assembly may be pressurized for a portion of the duration that the test assembly is heated.

[0031] In some implementations where the test assembly is pressurized, the transmission medium applied to the test components of the integrated circuit chip under test can be a liquid that forms a film on the test assembly once the test assembly is pressurized. Figure 8As shown, a conductive metal layer 802 may be applied to the back side 406 of the integrated circuit chip 402 under test to form the test assembly 400. The test assembly 400 may be placed in a pressure chamber 800 and pressurized. Pressurization may result in the formation of an adsorbed H2O layer 804 on the exposed back side 806 of the conductive metal layer 802. The adsorbed H2O layer 804 may act as a transmission medium layer, facilitating the diffusion of conductive metal ions between the conductive metal layer 802 and the integrated circuit chip 402. In the illustrated example, the conductive metal layer 802 and the adsorbed H2O layer 804 may collectively comprise the test assembly 404. It will be appreciated that any suitable adsorbent material may form a film on the conductive metal layer 802 under pressure to act as a transmission medium for the test assembly 404.

[0032] return Figure 3 In some implementations, at 308, method 300 may optionally include removing the test assembly from the integrated circuit chip under test. The test assembly may be removed after heating the test assembly to allow the integrated circuit chip to be installed in a computing device to computer verify the integrated circuit chip. In some implementations, the test assembly may be removed and a heat sink may be applied to a back side of the integrated circuit chip. Alternatively, in some implementations, the test assembly may remain connected to the integrated circuit under test during computer verification.

[0033] At 310, method 300 includes computer verification of the integrated circuit chip to determine whether the integrated circuit chip has the conductive metal ion diffusion defect. The computer verification of the tested integrated circuit chip can be performed by any suitable test computing equipment. For example, Fig. 9The test computing system 900 shown in the figure can perform computer verification of the integrated circuit chip under test. In some examples, the computer verification may include installing the integrated circuit chip in the test computing device, and determining that the integrated circuit chip has a conductive metal ion diffusion defect based on the inability of the test computing device to be powered on. In some examples, the computer verification may include installing the integrated circuit chip in the test computing device, and determining that the integrated circuit chip has a conductive metal ion diffusion defect based on the test computing device generating a rendered image with graphic artifacts. In some examples, the computer verification may include installing the integrated circuit chip in the test computing device, and determining that the integrated circuit chip has a conductive metal ion diffusion defect based on the test computing device generating another type of error. In some examples, the computer verification may include in-situ testing in a stress environment and continuous repeated testing of the integrated circuit chip. For example, the integrated circuit chip under test may be installed in the test computing device, and the test computing device may be controlled to repeatedly perform processing-intensive computing operations. In addition, it may be determined that the integrated circuit chip has a conductive metal ion diffusion defect based on the inability of the test computing device to produce the desired results or to perform computing operations. Furthermore, in some implementations, the integrated circuit chip / processor (e.g., 901, 902) may be configured with a built-in test function to perform functional testing on the chip itself without requiring an entire computing system. In some such implementations, it may be determined that the integrated circuit chip has a conductive metal ion diffusion defect based on the built-in test function in the chip / processor (901, 902) outputting expected test results, indicating that the chip is not functioning properly or that the chip / processor cannot perform self-tests properly to produce expected results.

[0034] In some implementations, the methods and processes described herein may be bound to a computing system of one or more computing devices. Specifically, such methods and processes may be implemented as computer applications or services, application programming interfaces (APIs), libraries, and / or other computer program products.

[0035] Fig. 9 A non-limiting implementation of a computing system 900 that can at least partially perform one or more of the above methods and processes is schematically shown. The computing system 900 is shown in a simplified form. The computing system 900 can be used to computer verify an integrated circuit chip 901 under test installed in the computing system 900, as described above with reference to Figure 3 The computing system 900 may take the form of one or more personal computers, server computers, tablet computers, home entertainment computers, network computing devices, gaming devices, mobile computing devices, mobile communication devices (e.g., smart phones), and / or other computing devices, as well as wearable computing devices such as smart watches and head-mounted augmented reality devices.

[0036] The computing system 900 includes a logic processor 902, a volatile memory 904, and a non-volatile storage device 906. The computing system 900 may optionally include a display subsystem 908, an input subsystem 910, a communication subsystem 912, and / or Fig. 9 Other components not shown.

[0037] Logical processor 902 includes one or more physical devices configured to execute instructions. For example, a logical processor may be configured to execute instructions that are part of one or more applications, programs, routines, libraries, objects, components, data structures, or other logical constructs. Such instructions may be implemented to perform tasks, implement data types, transform the state of one or more components, implement technical effects, or otherwise obtain desired results.

[0038] The logical processor 902 may include one or more physical processors (hardware) configured to execute software instructions. Additionally or alternatively, the logical processor 902 may include one or more hardware logic circuits or firmware devices configured to execute hardware-implemented logic or firmware instructions. Each processor of the logical processor 902 may be single-core or multi-core, and the instructions executed thereon may be configured for serial, parallel and / or distributed processing. The individual components of the logical processor 902 may be optionally distributed between two or more separate devices, which may be located remotely and / or configured for collaborative processing. Various aspects of the logical processor 902 may be virtualized and executed by a remotely accessible networked computing device configured in a cloud computing configuration. It will be understood that in such a case, these virtualization aspects are run on different physical logical processors of various different machines. In some examples, the tested integrated circuit chip 901 may be installed in the logical processor 902 to test the function of the integrated circuit chip 901 as part of the computer verification of the integrated circuit chip 901.

[0039] The non-volatile storage device 906 includes one or more physical devices configured to hold instructions executable by a logical processor to at least partially implement the methods and processes described herein. When implementing such methods and processes, the state of the non-volatile storage device 906 may be transformed—for example, to hold different data.

[0040] The non-volatile storage device 906 may include a removable and / or built-in physical device. The non-volatile storage device 1006 may include an optical memory (e.g., CD, DVD, HD-DVD, Blu-ray disc, etc.), a semiconductor memory (e.g., ROM, EPROM, EEPROM, flash memory, etc.), and / or a magnetic memory (e.g., a hard disk drive, a floppy disk drive, a tape drive, MRAM, etc.) or other mass storage device technology. The non-volatile storage device 906 may include a non-volatile, dynamic, static, read / write, read-only, sequential access, location addressable, file addressable, and / or content addressable device. It will be understood that the non-volatile storage device 906 is configured to save instructions even when power to the non-volatile storage device 906 is cut off.

[0041] The volatile memory 904 may include a physical device that includes random access memory. The volatile memory 904 is typically used by the logical processor 902 to temporarily store information during the processing of software instructions. It will be understood that when the power to the volatile memory 904 is cut off, the volatile memory 904 typically does not continue to store instructions.

[0042] Aspects of the logic processor 902, volatile memory 904, and non-volatile storage device 906 may be integrated together into one or more hardware logic components. Such hardware logic components may include, for example, field programmable gate arrays (FPGAs), program and application specific integrated circuits (PASIC / ASIC), program and application specific standard products (PSSP / ASSP), systems on chips (SOCs), and complex programmable logic devices (CPLDs).

[0043] When a display subsystem 908 is included, the display subsystem 908 can be used to present a visual representation of the data held by the non-volatile storage device 906. The visual representation can take the form of a graphical user interface (GUI). Since the methods and processes described herein change the data held by the non-volatile storage device and thus transform the state of the non-volatile storage device, the state of the display subsystem 908 can also be transformed to visually represent the changes in the underlying data. The display subsystem 908 can include one or more display devices utilizing substantially any type of technology. Such display devices can be combined with the logical processor 902, the volatile memory 904, and / or the non-volatile storage device 906 in a shared housing, or such display devices can be peripheral display devices.

[0044] When an input subsystem 910 is included, the input subsystem 910 may include or interface with one or more user input devices such as a keyboard, mouse, touch screen, or game controller. In some implementations, the input subsystem 910 may include or interface with selected natural user input (NUI) components. Such components may be integrated or peripheral, and the transduction and / or processing of input actions may be handled on or off the board. Example NUI components may include a microphone for language and / or speech recognition; infrared, color, stereoscopic display, and / or depth cameras for machine vision and / or gesture recognition; head trackers, eye trackers, accelerometers, and / or gyroscopes for motion detection and / or intent recognition; and electric field sensing components for assessing brain activity; and / or any other suitable sensor.

[0045] When the communication subsystem 912 is included, the communication subsystem 912 can be configured to communicatively couple the various computing devices described herein to each other and to other devices. The communication subsystem 912 may include wired and / or wireless communication devices compatible with one or more different communication protocols. As non-limiting examples, the communication subsystem 912 can be configured to communicate via a wireless telephone network or a wired or wireless local area network or wide area network (such as HDMI over a Wi-Fi connection). In some implementations, the communication subsystem 912 can allow the computing system 900 to send messages to other devices and / or receive messages from other devices via a network such as the Internet.

[0046] In one example, a method for verifying that an integrated circuit chip is not susceptible to a conductive metal ion diffusion defect includes: applying a test component to the back side of the integrated circuit chip to form a test assembly. The test component includes a conductive metal layer and a transmission medium layer for promoting diffusion of conductive metal ions. The method further includes: heating the test assembly at a thermal activation temperature; and computer verifying the integrated circuit chip to determine whether the integrated circuit chip has the conductive metal ion diffusion defect. In this example and / or other examples, the method may further include, when the test assembly is heated, pressurizing the test assembly at an increased pressure relative to ambient pressure. In this example and / or other examples, the transmission medium may include adsorbed H2O. In this example and / or other examples, the transmission medium may include a thermal interface material. In this example and / or other examples, the conductive metal may include copper. In this example and / or other examples, the test component may substantially cover the entire back side of the integrated circuit chip. In this example and / or other examples, the test assembly may further include a heat sink, and the heat sink may be clamped on the integrated circuit chip to compress the conductive metal layer and the transmission medium layer of the test component to the back side of the integrated circuit chip. In this example and / or other examples, the conductive metal layer may be applied to the back side of the integrated circuit chip, and the transmission medium layer may be applied to the conductive metal layer. In this example and / or other examples, the transmission medium layer may be applied to the back side of the integrated circuit chip, and the conductive metal layer may be applied to the transmission medium layer. In this example and / or other examples, the test assembly may be heated for a specified duration, which is selected from a time range of 72-120 hours. In this example and / or other examples, the thermal activation temperature may be selected from a thermal range of 100-150 degrees Celsius. In this example and / or other examples, the transmission medium layer may have a surface area greater than or equal to the surface area of ​​the conductive metal layer. In this example and / or other examples, computer verification may include installing the integrated circuit chip in a test computing device, and determining that the integrated circuit chip has a conductive metal ion diffusion defect based on the inability of the test computing device to be powered on. In this example and / or other examples, computer verification may include installing the integrated circuit chip in a test computing device, and determining that the integrated circuit chip has a conductive metal ion diffusion defect based on the test computing device generating a rendered image with graphic artifacts.

[0047] In one example, a method for verifying that an integrated circuit chip is not susceptible to a copper ion diffusion defect includes: applying a test component to the back side of the integrated circuit chip to form a test assembly. The test component includes a copper layer and a thermal interface material layer for promoting the diffusion of copper ions. The method further includes: heating the test assembly for a specified duration at a thermal activation temperature higher than the operating temperature of the integrated circuit chip; removing the test component from the integrated circuit chip; and computer verification of the integrated circuit chip to determine whether the integrated circuit chip has the copper ion diffusion defect. In this example and / or other examples, the test assembly may further include a heat sink, and the heat sink may be clamped on the integrated circuit chip to compress the copper layer and the thermal interface material layer of the test component to the back side of the integrated circuit chip. In this example and / or other examples, the copper layer may be applied to the back side of the integrated circuit chip, and the transmission medium layer may be applied to the thermal interface material layer. In this example and / or other examples, the thermal activation temperature may be selected from a thermal range of 100-150 degrees Celsius. In this example and / or other examples, the specified duration for which the test assembly is heated may be selected from a time range of 72-120 hours.

[0048] In one example, a method for verifying that an integrated circuit chip is not susceptible to a copper ion diffusion defect includes: applying a test component to a back side of an integrated circuit chip to form a test assembly. The test component includes a copper layer and a transmission medium layer for promoting diffusion of copper ions. The method further includes: heating the test assembly at a thermal activation temperature higher than an operating temperature of the integrated circuit chip for a specified duration; pressurizing the test assembly at an increased pressure relative to ambient pressure while the test assembly is heated at the thermal activation temperature; removing the test component from the integrated circuit chip; and computer verifying the integrated circuit chip to determine whether the integrated circuit chip has the copper ion diffusion defect.

[0049] It should be understood that the configurations and / or methods described herein are exemplary in nature, and these specific embodiments or examples should not be considered to have limiting significance, as many variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various actions illustrated and / or described may be performed in the illustrated and / or described order, in other orders, in parallel, or omitted. Likewise, the order of the processes described above may be changed.

[0050] The subject matter of the present disclosure includes all novel and non-obvious combinations and sub-combinations of the various processes, systems and configurations, and other features, functions, acts, and / or properties disclosed herein, as well as any and all equivalents thereof.

Claims

1. A method for verifying whether an integrated circuit chip is susceptible to a conductive metal ion diffusion defect, the method comprising: applying a test component to the back side of the integrated circuit chip to form a test assembly, wherein the test component includes a conductive metal layer and a transmission medium layer for facilitating diffusion of conductive metal ions; heating the test assembly at a heat activation temperature; as well as Computer verification of the integrated circuit chip to determine whether the integrated circuit chip has the conductive metal ion diffusion defect; Wherein the test assembly further comprises a heat sink, and wherein the heat sink is clamped on the integrated circuit chip to compress the conductive metal layer and the transmission medium layer of the test component to the back side of the integrated circuit chip.

2. The method according to claim 1, characterized in that Further including: As the test assembly is heated, the test assembly is pressurized at an increased pressure relative to ambient pressure.

3. The method according to claim 2, characterized in that The transport medium layer includes adsorbed H2O.

4. The method according to claim 1, characterized in that The transmission medium layer includes a thermal interface material.

5. The method according to claim 1, characterized in that The conductive metal layer includes copper.

6. The method according to claim 1, characterized in that The test assembly covers substantially the entire back side of the integrated circuit chip.

7. The method according to claim 1, characterized in that The transmission medium layer is applied to the back side of the integrated circuit chip, and wherein the conductive metal layer is applied to the transmission medium layer.

8. The method according to claim 1, characterized in that The test assembly is heated for a specified duration selected from a time range of 72-120 hours.

9. The method according to claim 1, characterized in that The thermal activation temperature is selected from a thermal range of 100-150 degrees Celsius.

10. The method according to claim 1, characterized in that The transmission medium layer has a surface area greater than or equal to a surface area of ​​the conductive metal layer.

11. The method according to claim 1, characterized in that The computer verification includes installing the integrated circuit chip in a test computing device and determining that the integrated circuit chip has the conductive metal ion diffusion defect based on the test computing device being unable to be powered on.

12. The method according to claim 1, characterized in that The computer verification includes installing the integrated circuit chip in a test computing device and determining that the integrated circuit chip has the conductive metal ion diffusion defect based on the test computing device generating a rendered image having a graphic artifact.

13. The method according to claim 1, characterized in that Computer verification includes performing a self-test of the integrated circuit chip and determining that the integrated circuit chip has the conductive metal ion diffusion defect based on the self-test producing expected results.

14. A method for verifying whether an integrated circuit chip is susceptible to copper ion diffusion defects, the method comprising: applying a test component to the back side of the integrated circuit chip to form a test assembly, wherein the test component includes a copper layer and a thermal interface material layer for promoting diffusion of copper ions; heating the test assembly at a thermal activation temperature greater than an operating temperature of the integrated circuit chip for a specified duration; removing the test assembly from the integrated circuit chip; as well as Computer verification of the integrated circuit chip to determine whether the integrated circuit chip has the copper ion diffusion defect; Wherein the test assembly further comprises a heat sink, and wherein the heat sink is clamped on the integrated circuit chip to compress the copper layer and the thermal interface material layer of the test component to the back side of the integrated circuit chip.

15. The method according to claim 14, characterized in that The copper layer is applied to the back side of the integrated circuit chip.

16. The method according to claim 14, characterized in that The heat activation temperature is selected from a thermal range of 100-150 degrees Celsius, and wherein the specified duration for which the test assembly is heated is selected from a time range of 72-120 hours.

17. A method for verifying whether an integrated circuit chip is susceptible to copper ion diffusion defects, the method comprising: applying a test component to the back side of the integrated circuit chip to form a test assembly, wherein the test component includes a copper layer and a transmission medium layer for facilitating diffusion of copper ions; heating the test assembly at a thermal activation temperature greater than an operating temperature of the integrated circuit chip for a specified duration; pressurizing the test assembly at an increased pressure relative to ambient pressure while the test assembly is heated to the thermal activation temperature; removing the test assembly from the integrated circuit chip; as well as Computer verification of the integrated circuit chip to determine whether the integrated circuit chip has the copper ion diffusion defect; Wherein the test assembly further comprises a heat sink, and wherein the heat sink is clamped on the integrated circuit chip to compress the copper layer and the transmission medium layer of the test component to the back side of the integrated circuit chip.

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